This commit (82de42fa14) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because the
parent clocks will only be probed after the child's ofdata_to_platdata().
To resolve this, the clock parent's register base will only be retrieved
by the child in probe() method instead of ofdata_to_platdata().
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
The card-detect GPIO and any other GPIO access currently doesn't work in
U-Boot SPL on any STM32 platform and crashes the SPL. To work around this
problem on AV96 right before release, remove the cd-gpios from DT. This
patch must be reverted right after release, once the proper fix for the
GPIO driver, "gpio: stm32: support gpio ops in SPL", is applied.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Currently the driver gets ns16550 base address in the driver
probe() routine, which may potentially break any ns16550 wrapper
driver that does additional initialization before calling
ns16550_serial_probe().
Things are complicated that we need consider ns16550 devices on
both simple-bus and PCI bus. To fix the issue we move the base
address assignment for simple-bus ns16550 device back to the
ofdata_to_platdata(), and assign base address for PCI ns16550
device in ns16550_serial_probe().
This is still not perfect. If any PCI bus based ns16550 wrapper
driver tries to access plat->base before calling probe(), it is
still subject to break.
Fixes: 720f9e1fdb ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()")
Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
USB 3 host controller may be described in ACPI to allow users alter
the properties or other features. Describe it for Intel Tangier SoC.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There is established way to provide I²C timings, or actually counters,
to the OS via ACPI. Fill them for Intel Merrifield platform.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
1. Update build steps where mainline Trusted Firmware A is used.
2. Fix BL31_BASE to the proper one according to the SoC reference
manual.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There is no need to have an assignment to NULL for XSDT pointer.
Therefore, no need to assign it when rsdt_address is not set.
Because of above changes we may decrease indentation level as well.
While here, drop unnecessary parentheses.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
To access the PHY, the MAC registers must be initialized. Call the init
function in probe() to make it so, otherwise the PHY ID readout returns
all zeroes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Commit f4dc714aaa ("arm64: Turn u-boot.bin back into an ELF file after
relocate-rela")
introduce REMAKE_ELF option to recreate u-boot.elf from u-boot ->
u-boot.bin + DT -> u-boot.elf.
The best is to ilustrate it from make V=1 output
cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin
cp u-boot-dtb.bin u-boot.bin
aarch64-linux-gnu-objcopy -I binary -B aarch64 -O elf64-littleaarch64 u-boot.bin u-boot-elf.o
aarch64-linux-gnu-ld.bfd u-boot-elf.o -o u-boot.elf --defsym="_start"=0x8000000 -Ttext=0x8000000
Last command has no explicit linker script passed that's why toolchain
internal linker script is used.
In Binutils 2.32 case it contains SIZEOF_HEADERS symbol which has changed
behavior by commit
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=64029e93683a266c38d19789e780f3748bd6a188
which result in situation that program headers has changed from
(xilinx_zynqmp_mini_defconfig)
Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000010000 0x00000000fffc0000 0x00000000fffc0000
0x0000000000018918 0x0000000000018918 RW 0x10000
to
Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000000000 0x00000000fffb0000 0x00000000fffb0000
0x0000000000028918 0x0000000000028918 RW 0x10000
Xilinx tools like XSDB or Bootgen are using program headers for loading ELF
to the right location and by above binutils change ELF is loaded to
incorrect location.
The patch is explicitly use u-boot-elf.lds (just cat now) for u-boot.elf
recreation which is called when REMAKE_ELF is setup.
By purpose u-boot-elf.lds doesn't contain OUTPUT_FORMAT/OUTPUT_ARCH to be
able to use by all archs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-By: Álvaro Fernández Rojas <noltari@gmail.com>
When generating the MAC address based on the boards serial number
the last digit was overwritten with the null termination. That way
boards with serial numbers close to each other would use the same
MAC address.
Signed-off-by: Jan-Christoph Tebbe <Jan-Christoph.Tebbe@ithinx.io>
Commit cf8dcc5d02 ("common: spl_fit: Default to IH_OS_U_BOOT if
FIT_IMAGE_TINY enabled") is not correct, it will append fdt to each loadable
image. Actually when using TINY FIT, the first loadable image is thought as
u-boot and already have fdt appended.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
The Jetson Nano Developer Kit is a Tegra X1-based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4GB
of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity. NVMe support
has also been added. Env save is at the end of QSPI (4MB-8K).
A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded
from extlinux.conf. Adjust the load addresses to fix this for now.
Using the calculated_env addresses table from T186 U-Boot is a
better fix, but it isn't working correctly on T210 U-Boot right now,
so this will do until I can fix it.
Signed-off-by: Tom Warren <twarren@nvidia.com>
This Tegra QSPI driver hadn't been brought up to date with how
DM drivers are fetching data from the FDT now, and was pulling
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
to work the same way it does in the tegra114 SPI driver, using
dev_read_ functions.
Signed-off-by: Tom Warren <twarren@nvidia.com>
When claim_bus was setting the clock, it reset the QSPI controller,
which wipes out any tap delays set by previous bootloaders (nvtboot,
CBoot for example on Nano). Instead of doing that in claim_bus, which
gets called a lot, moved clock setting to probe(), and set tap delays
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
save works reliably again.
Signed-off-by: Tom Warren <twarren@nvidia.com>
claim_bus() is passed a udevice *dev, which is the bus device's parent.
In this driver, claim_bus assumed it was the bus, which caused the
'priv' info pointer to be wrong, and periph_id was incorrect. This in
turn caused the periph clock call to assign the wrong clock (PLLM
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
working w/this errant clock, but it was moot as QSPI wasn't active
unless you probed it, and that wasn't happening until I posted a patch
to enable env save to QSPI for Nano (coming soon).
Signed-off-by: Tom Warren <twarren@nvidia.com>
According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This allows the user to set $serverip in the environment before
executing a DHCP request. If they do, U-Boot will use that IP rather
than using the IP in the DHCP response.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
U-Boot is configured to build as position independent executable. Enable
relocation of RELA section required to work with different load
addresses.
Signed-off-by: Vishruth <vishruthj@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Peter Robinson <probinson@gmail.com>
Fix VI_I2C clock source type. Will be needed by VI_I2C driver.
Also added use of INTERNAL_ID macro in two places, needed to keep
the id returned to 8 bits.
Signed-off-by: Tom Warren <twarren@nvidia.com>
T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB
tables. Remove pinmux/GPIO init tables & code from all T210-based builds
below:
p2371-2180 aka TX1
p2371-0000
e2220-1170
p2571
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.
Adds call to board_cleanup_before_linux to facilitate this.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
This adds to the DT the I2C controllers that connect to the board ID EEPROM,
etc. With this change, you can now probe all I2C devices on a TX1 board.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
The default resolution for rockchip display is 1920x1080
which failed to work on 4K HDMI out displays on rk3399.
So, mark the default resolution as 3480x2160 for rk3399
HDMI out.
This would work all the hdmi display resolutions till
4K.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Enable pre console buffer for rk3399 platform.
This would help to capture the console messages prior to
the console being initialised. Enabling this would help
to capture all the console messages on video output source
like HDMI. So we can find the full console messages of
U-Boot proper on HDMI display when enabled it for RK3399
platform boards.
Buffer address used for pre console is 0x0f200000 which is
ram base plus 240MiB. right now the Allwinner SoC is using
similar computation.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
VOP display endpoint pipeline configuration differs
between rk3288 vs rk3399.
These VOP pipeline configuration depends on how the
different display interfaces connected in sequence to
IN and OUT ports like for,
RK3288:
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_lvds: endpoint@2 {
reg = <2>;
remote-endpoint = <&lvds_in_vopb>;
};
vopb_out_mipi: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi_in_vopb>;
};
};
RK3399:
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_mipi: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_in_vopb>;
};
vopb_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopb>;
};
vopb_out_dp: endpoint@4 {
reg = <4>;
remote-endpoint = <&dp_in_vopb>;
};
};
here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399.
The rockchip vop driver often depends on this determined endpoint
number and stored in vop_mode. So based on this vop_mode the bpp
and pin polarity would configure on detected display interface.
Since, the existing driver using rk3288 vop mode settings enabling
the same will result wrong display interface configuration for rk3399.
Add the patch for fixing these vop modes for rk3399.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.
But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.
So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
This feature should not be enabled in release but can be useful for
developers who need to monitor register accesses at some specific places.
Helped me identify a bug in u-boot, by comparing the register accesses
from the u-boot driver with the ones from its linux variant.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
[jagan: use 16 bit array with tmp variable]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The sama5d2 QSPI controller memory space is limited to 128MB:
0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000.
There are nor flashes that are bigger in size than the memory size
supported by the controller: Micron MT25QL02G (256 MB).
Check if the address exceeds the MMIO window size. An improvement
would be to add support for regular SPI mode and fall back to it
when the flash memories overrun the controller's memory space.
Fixes: 24c8ff4684 ("spi: Add Atmel QuadSPI driver")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This tool always verifies the default configuration. It is useful to be
able to verify a specific one. Add a command-line flag for this and plumb
the logic through.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present bootm_host_load_images() is passed the configuration that has
been verified, but ignores it and just uses the default configuration.
This may not be the same.
Update this function to use the selected configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is currently possible to use a different configuration's signature and
thus bypass the configuration check. Make sure that the configuration node
that was hashed matches the one being checked, to catch this problem.
Also add a proper function comment to fit_config_check_sig() and make it
static.
Signed-off-by: Simon Glass <sjg@chromium.org>
This test is actually made up of five separate tests. Split them out so
that they appear as separate tests.
Unfortunately this restarts U-Boot multiple times which adds about a
second to the already-long vboot test, about 8 seconds total on my
machine. We could add a special 'teardown' test afterwards but if the
tests are executed out of order that would not work.
Changing test_vboot into a class causes it not to be discovered and makes
it different from all other tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a check to make sure that it is not possible to add a new
configuration and use the hashed nodes and hash of another configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function only returns an error message sometimes. Update it to always
return an error message if one is available. This makes it easier to see
what went wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is useful to be a little more specific about what is being checked.
Update a few messages to help with this.
Signed-off-by: Simon Glass <sjg@chromium.org>
The core and vdd PMIC buck regulators were misconfigured, which caused
instability of the board and malfunction of high-speed interfaces, like
the RGMII. Configure the PMIC correctly to repair these problems. Also,
model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9
("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{};
became pins1{};pins2{};, however the SPL extras were not updated to reflect
that change. Fix this.
This fixes booting from SD1 X9 slot on the AV96 board.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fixes: 35a54d41d9 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
This last minute pull-request is intended to fix some drivers
when used on ARC boards. The problem was introduced by
07906b3dad
What happened while doing one pretty simple improvement to make
U-Boot port more flexible and portable (by switching accessors from
assembly-written to plain C version) we implicitly added 2 problems:
1. Downgraded accessors from being volatile which signalled to
the compiler that it's now possible to do all kinds of optimizations
which may easily include merge of subsequent byte reads/writes into
word operations. Which is OK for accessing mormal memory but
breaks operation of peripherals if we access its memory-mapped regs
in such a "creative" manner.
2. As a part of assembly-written implementation we had compiler barriers
in form of the following construction 'asm volatile("" : : : "memory")',
and we dropped it in C implemntation. This in its turn enabled compiler
to mess with instruction ordering. Guess what it gives us in the end :)
So with all that we had in some corner-cases veeery funny instruction flows
generated. And in particular it broke DW SPI functionality when we were
writing large amount of data. Funny enough our tests which were writing
small amount of data still worked and only by the chance we caught that
breakage and unrolled that quite interesting loop of unexpected
problems.
The road to hell is paved with good intentions. Amen :)
We add memory barriers for __raw_readX / __raw_writeX accessors same
way as it is done for readX and writeX accessors as lots of U-boot
driver uses __raw_readX / __raw_writeX instead of proper accessor
with barrier.
It will save us from lot's of debugging in the future and it is OK
as U-Boot is not that performance oriented as real run-time
software like OS or user bare-metal app so we may afford being not
super fast as we only being executed once.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We must use compiler barriers in C-version read/write IO accessors
before and after operation (read or write) so it won't be reordered
by compiler.
Fixes commit 07906b3dad ("ARC: Switch to generic accessors")
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We must use 'volatile' in C-version read/write IO accessors
implementation to avoid merging several reads (writes) into
one read (write), or optimizing them out by compiler.
Fixes commit 07906b3dad ("ARC: Switch to generic accessors")
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
When MACB_ZYNQ is enabled there is compilation warnings
drivers/net/macb.c: In function ‘_macb_init’:
drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function);
did you mean ‘MACB_MCF’?
writel((value), (port)->regs + MACB_##reg)
^~~~~
It has been caused by changing macros name by commit below.
Fixes: 6c636514d4 ("net: macb: sync header definitions as taken from Linux")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Not all boards have the same CSB frequency, nor do every SPI slave
necessarily support running at 16.7 MHz. So implement ->set_speed;
that also allows using a smaller PM (i.e., 0) for slaves that do
support a higher speed.
Based on work by Klaus H. Sørensen.
Cc: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
There are a few problems with the current driver.
First, it unconditionally reads from dout/writes to din whether or not
those pointers are NULL. So for example a simple "sf probe" ends up
writing four bytes at address 0:
=> md.l 0x0 8
00000000: 45454545 45454545 05050505 05050505 EEEEEEEE........
00000010: 00000000 00000000 07070707 07070707 ................
=> sf probe 0
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48
SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB
=> md.l 0x0 8
00000000: ff000000 45454545 05050505 05050505 ....EEEE........
00000010: 00000000 00000000 07070707 07070707 ................
(here I've change the first debug statement to a printf, and made it
print the din/dout pointers rather than the uints they point at).
Second, as we can also see above, it always writes a full 32 bits,
even if a smaller amount was requested. So for example
=> mw.l $loadaddr 0xaabbccdd 8
=> md.l $loadaddr 8
02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................
02000010: aabbccdd aabbccdd aabbccdd aabbccdd ................
=> sf read $loadaddr 0x400 6
device 0 offset 0x400, size 0x6
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48
SF: 6 bytes @ 0x400 Read: OK
=> sf read 0x02000010 0x400 8
device 0 offset 0x400, size 0x8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64
SF: 8 bytes @ 0x400 Read: OK
=> md.l $loadaddr 8
02000000: 45454545 45450000 aabbccdd aabbccdd EEEEEE..........
02000010: 45454545 45454545 aabbccdd aabbccdd EEEEEEEE........
Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7
bytes), the last three bytes and up being the wrong ones, since the
driver does a full 32 bit read and then shifts the wrong byte out:
=> mw.l $loadaddr 0xaabbccdd 4
=> md.l $loadaddr 4
02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................
=> sf read $loadaddr 0x444 10
device 0 offset 0x444, size 0x10
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128
SF: 16 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000: 552d426f 6f742032 3031392e 30342d30 U-Boot 2019.04-0
=> mw.l $loadaddr 0xaabbccdd 4
=> sf read $loadaddr 0x444 0xb
device 0 offset 0x444, size 0xb
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88
SF: 11 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000: 552d426f 6f742032 31392e00 aabbccdd U-Boot 219......
Fix all of that by always using a character size of 8, and reject
transfers that are not a whole number of bytes. While it ends being
more work for the CPU, we're mostly bounded by the speed of the SPI
bus, and we avoid writing to the mode register in every loop.
Based on work by Klaus H. Sørensen.
Cc: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Currently, max_cs is write-only; it's just set in
mpc8xxx_spi_ofdata_to_platdata and not otherwise used.
My mpc8309 was always resetting during an "sf probe 0". It turns out
dm_gpio_set_dir_flags() was being called with garbage, since nothing
had initialized priv->gpios[0] - our device tree used "cs-gpios"
rather than "gpios", so gpio_request_list_by_name() had returned 0.
That would have been a lot easier to figure out if the chip select
index was sanity checked, so rename max_cs to cs_count, and reject a
xfer with a too large cs index.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi
chip select, SPISEL_BOOT, that is used by the boot code to boot from
flash.
This chip select will typically be used to select a SPI boot
flash. The SPISEL_BOOT signal is controlled by a single bit in the
SPI_CS register.
Implement a gpio driver for the spi chip select register. This allows a
spi driver capable of using gpios as chip select, to bind a chip select
to SPISEL_BOOT.
It may be a little odd to do this as a GPIO driver, since the signal
is neither GP or I, but it is quite convenient to present it to the
spi driver that way. The alternative it to teach mpc8xxx_spi to handle
the SPISEL_BOOT signal itself (that is how it's done in the linux
kernel, see commit 69b921acae8a)
Signed-off-by: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The driver correctly handles reading back the value of an output gpio
by reading from the shadow register for output, and from gpdat for
inputs.
Unfortunately, when setting the value of some gpio, we do a RMW cycle
on the gpdat register without taking the shadow register into account,
thus accidentally setting other output gpios (at least those whose
value cannot be read back) to 0 at the same time.
When changing a gpio from input to output, we still need to make sure
it initially has the requested value. So, the procedure is
- update the shadow register
- compute the new gpdir register
- write the bitwise and of the shadow and new gpdir register to gpdat
- write the new gpdir register
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Since some chips don't support reading back the value of output gpios
from the gpdat register, we should not do a RMW cycle (i.e., the
clrbits_be32) on the gpdat register when setting a gpio as input, as
that might accidentally change the value of some other (still
configured as output) gpio.
The extra indirection through mpc8xxx_gpio_set_in() does not help
readability, so just fold the gpdir update into
mpc8xxx_gpio_direction_input().
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
This adds the check against IH_OS_VXWORKS during FIT image load,
to allow loading FIT image for VxWorks.
Signed-off-by: Lihua Zhao <lihua.zhao@windriver.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Pull request for UEFI sub-system for efi-2020-04-rc5
This series fixes:
* UEFI Python tests CONFIG_OF_CONTROL=y.
* int to pointer cast warning for cmd/efidebug.c
* memory reservation even if fdt node is disabled
Now that the Python test is fixed reintroduce the reverted patch for
vexpress_ca9x4 to enable EFI_LOADER and define the dtb file name.
Add save_boot_params() to save reset status value from bootrom.
Bootrom will clear the status register in reset manager and stores the
reset status value in shared memory. Bootrom stores shared data at last
2KB of onchip RAM.
This function save reset status provided by bootrom to rst_mgr_status.
More information about reset status register value can be found in reset
manager register description.
When running in debugger without bootrom, r0 to r3 are random values.
So, skip save the value when r0 is not bootrom shared data address.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
With CONFIG_OF_CONTROL environment variable $fdtcontroladdr is not defined
and test_efi_grub_net() fails.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
If the DM_ETH is enabled, the board-specific ethernet registeration
should be disabled, make it so.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add code to reset the board through PMIC, by writing the required
PMIC registers in the CPU reset handler.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Configure RX and TX bus-width values to use flexspi in octal I/O mode.
If bus-widths are not specified, then single I/O mode is set by default.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Configure RX and TX bus-width values to use flexspi in octal I/O mode.
If bus-widths are not specified, then single I/O mode is set by default.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
MC_INIT and BOOT command currently access spi-nor flash memory directly.
As per spi-mem framework, flash memory access via absolute addresses is
no more possible. Use flash APIs to access memory instead of directly
using it.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CONFIG_ENV_ADDR helps in picking environment from flash before DDR init.
Define the value as 0x20500000 for lx2160ardb and lx2160aqds.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable FSPI controller support. So, flash environment can now be used.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each
connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected
on different buses, only one flash can be probed at a time.
Add fspi node properties aligned with LX2160A-RDB fspi properties.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Adjust environment kernel_addr_r from 0x96000000 to 0x92000000
to fix a bug that failed to boot kernel for ls1012afrwy with 512MiB RAM,
=> tftpboot $kernel_addr_r Image (Image size is 36 MiB)
TFTP error: trying to overwrite reserved memory...
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This patch appends othbootargs to bootargs for LS1021ATWR board.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The eMMC HS200 speed mode on Layerscape platforms has not been
supported properly. The eSDHC clock tuning has not been implemented
by now. So disable it until it is supported properly in case of
any potential issues.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add config to enable the PFE and ETH support.
Also change the pfe secure boot header address.
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable CONFIG_DM_USB to remove below compile warning:
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
With DM_USB enabled, enable CONFIG_BLK to remove this
compile warning for ls1012afrdm based targets:
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1046A
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1043A
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Move the environment variables from command head file to
ls1028ardb specific head file so that they will not mess
up with ls1028aqds board.
Also updated some variable slightly.
There is no function change by this patch.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The SDHC1_DAT4 signal could be routes to SDHC1_VS or SDHC1
adapter slot for SDHC1 usage. When SDHC1 is selected in RCW,
do not force to route it to SDHC1 adapter slot if find it
has already been configued for SDHC1_VS.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.
Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.
Fixes: 3675cb044e ("PCI: Add driver for a 'pci-host-ecam-generic' host controller")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The old load address of itb will overwrite uboots reserved memory
on ls1012afrwy with 512 MiB ram
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The correct setting for the RGMII ports on LS1046ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.
Fixes: cc1aa218f5 ("armv8/ls1046a: RGMII PHY requires internal
delay on Tx")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.
Fixes: 5a78a472f6 ("armv8/ls1043a: RGMII PHY requires internal
delay on Tx")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The RGMII modes that include internal delay were not all
properly treated in the memac code. Add support for all
RGMII delay modes.
Fixes: 111fd19e3b ("fm/mEMAC: add mEMAC frame work")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Select BOARD_LATE_INIT config so that many board works can be done
in late init stage.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Update the secure boot headers offsets of Kernel and other
firmware images for SD and XSPI boot sources used by
esbc_validate command.
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Setting fdt_high and initrd_high to 0xffffffffffffffff leads to
various difficulty to resolve bugs.
Remove them and use bootm_size instead to safely contain a kernel,
device tree and initrd for relocation.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Setting fdt_high and initrd_high to 0xffffffffffffffff leads to
various difficulty to resolve bugs.
Remove them and use bootm_size instead to safely contain a kernel,
device tree and initrd for relocation.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Program GIC LPI configuration table:
1. Redistributor PROCBASER configuration table (which
is common for all redistributors)
2. Redistributor pending table (PENDBASER), for all the
available redistributors.
Signed-off-by: Manish Tomar <manish.tomar@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Update "board_fix_fdt" with correct counter value "i".
This will fix the issue while fetching the "reg_names"
resource from fdt after fixup.
Signed-off-by: Vikas Singh <vikas.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This patch sets CONFIG_SYS_BOOTMAPSZ to the amount of memory available
to safely contain a kernel, device tree and initrd for relocation. The
way to set fdt_high as 0xffffffff to disable device tree relocation is
removed.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add IIC3 node from mainline Linux DT. This will be further updated in
subsequent DT sync, however adding this node for now is sufficient and
minimal change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The fdtdec_get_addr() does not take into account values set in #address-cells
and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit
systems. This is true for most DTs, however there are exceptions. Switch to
fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells
values into consideration, otherwise the reset controller node register
offset is incorrectly parsed.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
mmc bootbus and partconf commands are needed in order to be able to
configure booting from separate boot0/boot1 eMMC partitions.
Signed-off-by: Petr Štetiar <ynezz@true.cz>
[jagan: rebase on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
EFI was disabled in f95b8a4b5f because of the missing DTB file,
and indeed, the DTB file is required to load recent versions of GRUB
(2.04) correctly.
Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
Sub-nodes of /reserved-memory may be disabled. In this case we should not
reserve memory in the memory map.
Reported-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Fixes: fef907b2e4 ("efi_loader: create reservations after
ft_board_setup")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
On 32 bit systems fix
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
Fixes: a415d61eac ("cmd: map addresses to sysmem in efidebug memmap")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
With CONFIG_OF_CONTROL environment variable $fdtcontroladdr is not defined
and test_efi_helloworld_net() fails.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
We need to align the cache buffer to ARCH_DMA_MINALIGN in order to avoid
access errors like
CACHE: Misaligned operation at range [be0231e0, be0235e0]
seen on the MCIMX7SABRE.
Fixes: d5aee659f2 ("fs: ext4: cache extent data")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Commit 41e30dcf87 ("cmd: mmc: Make Mode: printout consistent") fixed
the layout of `mmc info` output. Reflect this change in the respective
testcase.
Also fix a typo in the documentation.
Fixes: 41e30dcf87 ("cmd: mmc: Make Mode: printout consistent")
Signed-off-by: Harald Seiler <hws@denx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently this causes failures of the platform when running the EFI
loader tests, so disable it for now.
This reverts commit af827140e5.
Signed-off-by: Tom Rini <trini@konsulko.com>
Depending on the SoC, a header of four characters is prepended to the
image. There is already a macro defining the number of characters:
RK_SPL_HDR_SIZE, so use it instead of hardcoding "4".
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Since commit 79030a4861 ("rockchip: Add Single boot image
(with binman, pad_cat)") the following boot regression is seen:
U-Boot 2020.04-rc3-00050-gd16e18ca6c-dirty (Mar 09 2020 - 11:40:07 -0300)
Model: Elgin RV1108 R1 board
DRAM: 128 MiB
initcall sequence 67fd12a0 failed at call 6000b927 (err=-22)
This happens because the above commit missed to include the
"rockchip-u-boot.dtsi" for rv1108, so include this file
like it done for other Rockchip SoC dtsi's.
Fixes: 79030a4861 ("rockchip: Add Single boot image (with binman, pad_cat)")
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Currently the following error message is seen during boot:
U-Boot 2020.01-08751-g55759ae141 (Mar 09 2020 - 14:44:52 -0300)
Model: Elgin RV1108 R1 board
DRAM: 128 MiB
APLL: 600000000 DPLL:1200000000 GPLL:1188000000
ACLK_BUS: 148500000 ACLK_PERI:148500000 HCLK_PERI:148500000 PCLK_PERI:74250000
MMC: dwmmc@30110000: 0
Loading Environment from MMC... OK
In: serial@10210000
Out: serial@10210000
Err: serial@10210000
Model: Elgin RV1108 R1 board
rockchip_dnl_key_pressed: adc_channel_single_shot fail!
....
Since the elgin-rv1108 does not use ADC to read the download
key status, select CONFIG_ROCKCHIP_BOOT_MODE_REG=0 to avoid
such error.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Since commit 8e9a8d0d0c ("rockchip: elgin-rv1108: use board_early_init_f
for per-boar init") the function that configure the board GPIOs is no
longer called since CONFIG_BOARD_EARLY_INIT_F=y is not selected.
These GPIOs do not need to be configured in such early stagem, so change it
to rk_board_late_init() and also select CONFIG_BOARD_LATE_INIT=y
to fix the regression.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to make the console pins more robust to noise, activate
the pullups and increase its drive strength.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
These boards aren't ChromeOS devices so won't have a cros-ec-keyb
input as it's the keyboard available via the ChromeOS Embedded
Controller. Update them to use a USB keyboard which would actually
be available. Also enable the usb keyboard option for those devices
that don't have it enabled already.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
EFI was disabled in f95b8a4b5f because of the missing DTB file,
and indeed, the DTB file is required to load recent versions of GRUB
(2.04) correctly.
Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
Pull request for UEFI sub-system for efi-2020-04-rc4 (5)
This series contains bug fixes for the UEFI sub-system:
* report correct variable length in GetNextVariable()
* correct copying direction if freestanding memmove()
* remove const for parameter of GetNextVariableName()
* correct function descriptions
Unit tests are added and adjusted.
'vendor' is both an input and an output parameter. So it cannot be
constant.
Fixes: 0bda81bfdc ("efi_loader: use const efi_guid_t * for variable services")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
For EFI binaries we have to provide an implementation of memmove() in
efi_freestanding.c.
Before this patch the memmove() function was copying in the wrong
direction.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
GetNextVariableName should report the length of the variable including the
final 0x0000 in bytes.
Check this in the unit test.
Increase the buffer size for variable names. 40 bytes is too short.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The runtime service GetNextVariable() returns the length of the next
variable including the closing 0x0000. This length should be in bytes.
Comparing the output of EDK2 and U-Boot shows that this is currently not
correctly implemented:
EDK2:
OsIndicationsSupported: 46
PlatformLang: 26
PlatformLangCodes: 36
U-Boot:
OsIndicationsSupported: 23
PlatformLang: 13
PlatformLangCodes: 18
Provide correct length in GetNextVariable().
Fixes: d99a87f84b ("efi_loader: implement GetNextVariableName()")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Now that those common Allwinner config symbols are defined automatically
for all boards in their Kconfig files, we can remove the now redundant
definitions from the boards' _defconfig files.
Some boards had a differing definiton for some of those symbols, it
looks like mostly to "merge races" when the symbol was introduced (new
board *_defconfig file missed the "add symbol to all files" patch).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Some config symbols are found in *almost* every _defconfig file for
Allwinner boards, because those options are actually a platform choice,
and not a per-board decision.
Some of these options are older, some have recently been added.
Move those options to be set for all Allwinner boards in their
respective Kconfig files.
The rationales are as follows:
- NR_DRAM_BANKS: All Allwinner SoC map DRAM at one contiguous region of
address space only, starting at 1 GB. So it's always one bank.
- SPL_{DOS,EFI}_PARTITION: The Allwinner SPL does only support raw MMC
accesses, we don't care about filesystems or partitions in there, so
there is no need to define those symbols at all.
- USE_PREBOOT: We start USB early when a keyboard is configured, using the
preboot env variable, so we need to set this variable.
- SYS_RELOC_GD_ENV_ADDR: We don't specify any ENV_ADDR, so need this
symbol to be set (according to 8d8ee47e03).
- SYS_USB_EVENT_POLL_VIA_INT_QUEUE: According to commit eab9433aa5,
specifying this reduces the latency of the USB keyboard handling, so
this was formerly enabled in config headers for all Allwinner boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The Pine H64 board comes with some onboard SPI flash chip, which is
perfect for loading SPL, ATF and U-Boot proper from there.
Enable the functionality in the defconfig, so that we use sunxi-fel to
transfer a bootable image to the NOR flash.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The Allwinner H6 SoC uses a quite different memory map, also changes the
clocks quite a bit. This requires some changes to the SPL SPI routine,
which hardcodes these values so far.
Using the just introduced helper functions to determine base address
and SPI controller generation, we can cover some of these differences
easily.
The clock setup is different, so requires some explicit code changes
there (reset and clock gate in one register at a different address).
Also we need to change the pinmux function to use a different set of
pins that the H6 uses for SPI0.
Eventually we can enable the H6 to use SPI booting in Kconfig.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Now that we can easily select an SoC specific SPI0 base address, adding
support for the Allwinner R40 is fairly trivial:
We set the base address, add this SoC to the ones that use PC23 and
enable it in Kconfig.
This allows booting from SPI flash on R40 boards.
Tested on a Bananapi M2 Berry with SPI flash connected to the header pins.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
So far we were using the CONFIG_SUNXI_GEN_SUN6I symbol to select between
the two SPI controller generations used on Allwinner SoCs. This is a
convenience symbol to roughly differentiate between "older" and "newer"
generation of SoCs.
The H6 SoCs is the newest SoC so far, but is sufficiently different to
not define this symbol. However it is using a SPI controller compatible
to the "new gen" SoCs.
To prepare for H6 support, we replace the check for this single symbol
with an explicit function, which can later be extended.
For now we just return CONFIG_SUNXI_GEN_SUN6I in there, so this does not
create a functional change.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
So far on all supported Allwinner SoCs we find the old generation SPI
controller always at address 0x1c05000, and the new generation one at
0x1c68000. However the Allwinner R40 SoC has a new generation SPI at
the old address, and the H6 uses a completely different address.
So split off the base address from the respective SPI registers, by
changing the #defines to just contain offsets.
The base address is provided by a function, so it can easily be extended
later when support for those SoCs materialises.
This does not change the code size (since the toolchain is clever enough
to optimise this properly), also does not bring any functional change at
this point.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Pull request for UEFI sub-system for efi-2020-04-rc4 (4)
This series fixes several bugs:
* consider the /reserved-memory node in the device tree
* consider memory reservations created in ft_board_setup()
* correct output of 'efidebug memmap' on the sandbox
* correct the definition of efi_capsule_header()
Furthermore some definitions needed for future patches are added to
header files.
Using memcpy() for some MMIO access is generally frowned upon and might
break things on some platforms. Allwinner H3, which fails to boot, being
an example here.
Moreover, fields being accessed are naturally aligned and warnings
produced by GCC have been quiesced for some time already by:
53dc8ae ("gcc-9: silence 'address-of-packed-member' warning")
That said, it should be okay to revert this commit.
This reverts commit 9bd34a69a4.
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tomasz Duszynski <tduszyns@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
See UEFI specification, section 8.5.3.
In addition, the structure, efi_capsule_header, should be "packed"
as it is a serialized binary format in a capsule file.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
This is a preparatory patch.
Those functions will be used in an implementation of UEFI firmware
management protocol as part of my capsule update patch.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Some of those values will be used in an implementation of UEFI firmware
management protocol as part of my capsule update patch.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
These flags are expected to be set in OsIndicationsSupported variable
if corresponding features are supported. See UEFI specification,
section 8.5.4.
In particular, capsule-related flags will be used in my capsule
update patch.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Fix misspelled EFI_OS_INDICATIONS_BOOT_TO_FW_UI.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Currently, bootefi only parses memory reservation block to setup
EFI reserved memory mappings. However, it doesn't parse the
reserved-memory[1] device tree node that also can contain the
reserved memory regions.
Add capability to parse reserved-memory node and update the EFI memory
mappings accordingly.
1. <U-Boot source>/doc/device-tree-bindings/reserved-memory/reserved-memory.txt]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Fix an endless loop.
The /reserved-memory node may have children without reg property. Remove
a superfluous debug statement.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Addresses in the sandbox's device tree are in the sandbox's virtual address
space. If we want to compare memory reservations in the device-tree with
the output of 'efidebug memmap', we need to convert back to this address
space.
Adjust the output of the 'efidebug memmap' command.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Some memory reservations are made in ft_board_setup(). Ensure that we
create reserved memory map entries after ft_board_setup().
The downside of this patch is that if bootefi is called multiple times with
an devicetree argument superfluous reservations for the old copies of the
device tree will exist. But that is still better than missing a reservation.
Deleting the superfluous reservations is not possible because reservations
in the memory map are rounded to page size and may be coallesced.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Few v0.1 SBI calls are being replaced by new SBI calls that follows
v0.2 calling convention.
Implement the replacement extensions and few additional new SBI
function calls that makes way for a better SBI interface in future.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
We now have SBI v0.2 which is more scalable and extendable to handle
future needs for RISC-V supervisor interfaces.
Introduce a new config and move all SBI v0.1 code under that config.
This allows to implement the new replacement SBI extensions cleanly
and remove v0.1 extensions easily in future. Currently, the config
is enabled by default. Once all M-mode software, with v0.1, is no
longer in use, this config option and all relevant code can be easily
removed.
This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407361/
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
The SBI v0.2 introduces a base extension which is backward compatible
with v0.1. Implement all helper functions and minimum required SBI
calls from v0.2 for now. All other base extension function will be
added later as per need.
As v0.2 calling convention is backward compatible with v0.1, remove
the v0.1 helper functions and just use v0.2 calling convention.
Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and
let CONFIG_SBI_IPI depend on it.
This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407363/
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
As per the new SBI specification, current SBI implementation version
is defined as 0.1 and will be removed/replaced in future. Each of the
function call in 0.1 is defined as a separate extension which makes
easier to replace them one at a time.
Rename existing implementation to reflect that. This patch is just
a preparatory patch for SBI v0.2 and doesn't introduce any functional
changes.
This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407355/
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
There is no need for S-mode U-Boot to call sbi_clear_ipi() as it
can be cleared directly from S-mode. This saves some cycles.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas@auer.io>
Currently sbi_remote_sfence_vma{,_asid} does not pass their arguments
to SBI at all, which is semantically incorrect.
This keeps in sync with Linux kernel commit:
a21344dfc6ad: fix sbi_remote_sfence_vma{,_asid}
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas@auer.io>
On some platforms/architectures the value from get_timer() can wrap.
This is particularly problematic when long-running code needs to measure
a time difference as is the case with watchdog_reset() which tries to
avoid tickling the watchdog too frequently.
Use time_after() from time.h instead of a plain > comparison to avoid
any issues with the time wrapping on a system that has been sitting in
u-boot for a long time.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Currently watchdog tries to use dev_read_u32_default to get timeout
configuration in case OF_CONTROL is enabled. However, if SPL is
built with OF_PLATDATA this has no sense as there is no device tree.
This patch fixes this issue by only use dev_read_u32_default if OF_CONTROL
is enabled but OF_PLATDATA is not.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
GCC-10 reports:
In file included from tools/common/image-fit.c:1:
include/image.h: In function ‘fit_image_get_data_and_size’:
./tools/../common/image-fit.c:1015:9: warning: ‘len’ may be used
uninitialized in this function [-Wmaybe-uninitialized]
1015 | *size = len;
| ~~~~~~^~~~~
./tools/../common/image-fit.c:996:6: note: ‘len’ was declared here
996 | int len;
| ^~~
Add the missing check of the return value of fit_image_get_data_size().
Fixes: c3c8638804 ("add FIT data-position & data-offset property support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Just cleanup help indentation to be the same for all options.
It means <tab><space><space> indentation.
OMAP3 should be indented by tabs which is also fixed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4dbc107f46 ("cmd: gpio: Correct do_gpio() return value") correctly
changed the behaviour of the gpio command to return CMD_RET_SUCCESS or
CMD_RET_FAILURE, but any existing script which expects the return value
to be the pin value is broken by this change.
Reinstate the legacy behaviour for `gpio input` only.
Fixes: 4dbc107f46 ("cmd: gpio: Correct do_gpio() return value")
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Signed-off-by: Alex Kiernan <alex.kiernan@hivehome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The commit 5fed97af20 ("Makefile: ensure DTB doesn't overflow into
initial stack") adds an extra check for stack size in BSS if
CONFIG_SYS_INIT_SP_BSS_OFFSET is enabled.
This check, however, doesn't make sense under the configuration where
control dtb won't be built in and it should be void in such cases.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Fixes: 5fed97af20 ("Makefile: ensure DTB doesn't overflow into initial stack")
Reviewed-by: Stephen Warren <swarren@nvidia.com>
All drivers seems to align now to serial_xxx maning, so, aligning
also this driver, to allow to be found easily.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
Actually, using dev->seq value before probe to deduce the current
serial port index leads to reading an invalid seq value (-1).
So, getting dev->seq at probe time.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
Pull request for UEFI sub-system for efi-2020-04-rc4 (3)
This pull request provides the hardware RNG driver for Amlogic systems needed
for the EFI_RNG_PROTOCOL.
Furthermore bug fixes are provided:
* correct an error message in the efidebug command
* correct an error in the 'efidebug rm' command
* remove an unnecessary assignment in efi_queue_event()
For all sandbox systems with DM_RNG we enable RNG_SANDBOX. So we can simply
set the default to yes.
All rng drivers depend on DM_RNG. Use a single 'if' instead of individual
dependencies. Now 'make menuconfig' shows the individual drivers neatly
indented under the DM_RNG entry.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Add the missing line feed at the error message if the variable referred to
by 'efidebug boot rm' does not exist.
Shorten the format string by using the variable name instead of the number
of the boot variable.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
There is a wrong usage of utf8_utf16_strncpy() in "boot rm" command, and
then it will end up with a failure of this command due to a wrong
value of an interim variable ("var_name16").
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Currently, if GetMemoryMap API returns EFI_BUFFER_TOO_SMALL, it doesn't
set valid values to other parameters, descriptor_size and
descriptor_version, except memory_map_size.
Some efi applications, however, may use those value; in particular,
xen uses descriptor_size to calculate a size of buffer to be allocated.
While UEFI specification is ambiguous in this point, it would be better
to address this issue proactively to maximize the compatibility with
existing efi applications.
With this patch, for example, xen.efi (and hence linux kernel) can be
started via bootefi without modification.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The binman-option BINMAN_FDT is introduced by this commit:
commit 3c10dc95bd ("binman: Add a library to access binman entries")
BINMAN_FDT being selected when BINMAN=y that resulting in mt7623
and mt7622 are unable to boot. The root cause of this issue is commit:
commit cbd2fba1ec ("arm: MediaTek: add basic support for MT7629 boards")
select BINMAN=y in all mediatek SoCs, and others mediatek SoCs not
expect to use BINMAN_FDT.
This patch remove BINMAN=y option when ARCH_MEDIATEK=y and
move this to the specify SoCs part config.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Currently when booting the kernel on i.MX8 U-Boot hangs in an
endless loop when switching off dma, connectivity or lsio power
domains during device removal. It hapens first when removing
gpio0 (gpio@5d080000) device, here its power domain device
'lsio_gpio0' is obtained for switching off power. Since the
obtained 'lsio_gpio0' device is removed afterwards, its power
domain is also switched off and here the parent power domain
device 'lsio_power_domain' is optained for switching off the
power. Thereafter, when the obtained 'lsio_power_domain' is
removed, device_remove() removes its first child 'lsio_gpio0'.
During this child removal the 'lsio_power_domain' device is
obtained again for switching and when removing it later,
the same child removal is repeated, so we are stuck in an
endless loop. Below is a snippet from dm tree on i.MX8QXP
for better illustration of the DM devices relationship:
Class Index Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
...
simple_bus 0 [ + ] generic_simple_bus |-- imx8qx-pm
power_doma 0 [ + ] imx8_power_domain | |-- lsio_power_domain
power_doma 1 [ + ] imx8_power_domain | | |-- lsio_gpio0
power_doma 2 [ + ] imx8_power_domain | | |-- lsio_gpio1
Do not remove a power domain device if it is a parent of the
currently controlled device.
Fixes: 52edfed65d ("dm: core: device: switch off power domain after device removal")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Oliver Graute <oliver.graute@gmail.com>
Reported-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Correct the dependency for STM32 ETZPC protection, linked to SOC
STM32MP identified by CONFIG_STM32MP15x and not linked to
CONFIG_TARGET_STM32MP1 (no more existing).
This patch fix an issue introduced by commit 846254888e ("stm32mp1:
split board and SOC support for STM32MP15x family").
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
This fixes the following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This fixes the following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Booting a mainline kernel in secure mode on i.MX7D causes only
one CPU to be brought up.
Change it to booting in non secure mode by default, which
allows the two CPUs to be brought up.
It does have a side effect of not probing the CAAM driver.
If CAAM driver is needed then a secure world OS such as OPTEE needs
to be used.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Instead of resetting the ethernet phy through functions in imx8mq_evk.c, let the
driver reset the phy via dts description adding a reset duration of 10 ms
following atheros 8031's datasheet recommendation.
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Convert imx6sabresd ethernet to driver model to fix the following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Uboot size is incorrect.
Uboot SPL use CONFIG_SYS_MONITOR_LEN to read uboot from NAND : 0x80000
With sama5d3_xplained_nandflash_defconfig : u-boot.bin size is ~800Ko 0xC0000
So I increased size to 1MB : 0x100000
Signed-off-by: Fabien Lehoussel <fabien.lehoussel@medianesysteme.com>
The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).
Before commit 83cfbeb0df ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.
I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.
The uid and mask bits 3:0 are now again the same as in the Linux kernel.
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
This patch adds ability to switch beetween two PHY SGMII modes.
Some hardware, for example, FPGA IP designs may use 6-wire mode
which enables differential SGMII clock to MAC.
Patch description, dt flags have been done in mainline Linux by
commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The helper is used to reset PHYs on connect and it determines the clause
to use (C22/C45) based on interface type. This fixes 'PHY reset timed out'
warnings in console for USXGMII/XFI PHYs.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 27c3f70f3b ("net: phy: Increase link up delay in
genphy_update_link()") increased the per-iteration waiting time from
1ms to 50ms, without adjusting the timeout counter. This lead to the
timeout increasing from the typical 4 seconds to over three minutes.
Adjust the timeout counter evaluation by that factor of 50 to bring the
timeout back to the intended value.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
doc/README.drivers.eth seems like a good source for understanding
U-Boot's network subsystem, but is only talking about legacy network
drivers. This is particularly sad as proper documentation would help in
porting drivers over to the driver model.
Rewrite the document to describe network drivers in the new driver model
world. Most driver callbacks/methods are almost identical in their
semantic, but recv() differs in some important details.
Also keep some parts of the original text at the end, to help
understanding old drivers. Add some hints on how to port drivers over.
This also uses the opportunity to reformat the document in reST, on the
way moving it into doc/driver-model and adding it into the structure
there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid
protocol configuration. The PHY doesn't support it, it's just used as an
alias for one of the other two protocols.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add NC-SI to the usual phy handling. This makes two notable changes:
- Somewhat similar to a fixed phy, phy_connect() will create an NC-SI
phy if CONFIG_PHY_NCSI is defined.
- An early return is added to phy_read() and phy_write() to handle a
case like the NC-SI phy which does not define a bus.
Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This introduces support for the NC-SI protocol, modelled as a phy driver
for other ethernet drivers to consume.
NC-SI (Network Controller Sideband Interface) is a protocol to manage a
sideband connection to a proper network interface, for example a BMC
(Baseboard Management Controller) sharing the NIC of the host system.
Probing and configuration occurs by communicating with the "remote" NIC
via NC-SI control frames (Ethernet header 0x88f8).
This implementation is roughly based on the upstream Linux
implementation[0], with a reduced feature set and an emphasis on getting
a link up as fast as possible rather than probing the full possible
topology of the bus.
The current phy model relies on the network being "up", sending NC-SI
command frames via net_send_packet() and receiving them from the
net_loop() loop (added in a following patch).
The ncsi-pkt.h header[1] is copied from the Linux kernel for consistent
field definitions.
[0]: https://github.com/torvalds/linux/tree/master/net/ncsi
[1]: https://github.com/torvalds/linux/blob/master/net/ncsi/ncsi-pkt.h
Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
We keep both of these jobs in sync as much as possible even when the
primary motivation is to keep Travis from exceeding the build time limit
there. With that in mind:
- Use "rk" not "rockchip" to get all Rockchip SoC platforms in one job,
rather than just all Rockchip vendor platforms.
- The NXP LX216* SoCs have their own job, exclude them from the AArch64
generic job.
- SoCFPGA SoCs have their own job, exclude them from the AArch64 generic
job.
Signed-off-by: Tom Rini <trini@konsulko.com>
Some device may enable CONFIG_CLK but not still support this clock in
CC, so better use debug() in place of dev_warn() otherwise a lot of
boards will throw useless dev_warn()s.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The current implementation in arch/arm/mach-imx/cpu.c uses non-DM
code to retrieve the core clock frequency. As the root clock is not
listed we currently get:
CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
Fix this by adding the missing entry, which results in:
CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
fdt_high value of 0xffffffff disables fdt relocation on boot. We don't
need that for Cubox-i/Hummingboard. Rely on generic code to find the
optimal fdt location at boot time.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Before DM_VIDEO conversion this board used 24bpp
display configuration, so use it again.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Currently the expansion of the console variable leads to
the following kernel command line:
console=ttyLP0,${baudrate} earlycon root=/dev/mmcblk1p2 rootwait rw
, which causes the console to not show characters after the LPUART driver
is probed as the 'baudrate' variable is not properly translated.
Fix it by splitting the console variable in two parts: one for the
ttyLP0 part and the other one for the baudrate, which matches the way
it is done on other i.MX targets.
Tested by successfully booting a mainline kernel on a i.MX8QXP MEK
board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
On the aristainetos2c boards the PMIC needs to be initialized,
because the Ethernet PHY uses a different regulator that is not
setup per hardware default. This does not influence the other
versions as this regulator isn't used there at all.
Signed-off-by: Heiko Schocher <hs@denx.de>
With CONFIG_SUPPORT_EMMC_BOOT moved to Kconfig, move it to defconfig
files.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Update the dummy clock names to use unique identifiers. Otherwise the
previous node just gets overwitten by the next one with the same name.
This fixes eMMC boot not working on J721e-evm.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
System firmware does not guarantee that clocks going out of the device
will be stable during power management configuration. There are some
DCRC errors when SPL tries to get the next stage during eMMC boot after
sysfw pm configuration.
Therefore add a config_pm_pre_callback() to switch off the eMMC clock
before power management and restart it after it is done.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The call to spl_mmc_get_uboot_raw_sector() completely ignores and
overwrites the raw_sect value passed from the caller of spl_mmc_load().
Fix this by passing raw_sect to the function and returning the same
value in the default case.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The 4 bit MMC controllers have an internal debounce for the SDCD line
with a debounce delay of 1 second. Therefore, after clocks to the IP are
enabled, software has to wait for this time before it can power on the
controller.
Add a deferred_probe() callback which polls on sdcd for a maximum of 2 seconds
before switching on power to the controller or (in the case of no card)
returning a ENOMEDIUM. This pushes the 1 second wait time to when the
card is actually needed rather than at every probe() making sure that
users who don't insert an SD card in the slot don't have to wait such a
long time.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
With the latest RIOT, there is a different otap delay value for each
speed mode. Add a new binding with every supported speed mode. Also
disable a given speed mode in the host caps if its corresponding
otap-del-sel is not present.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and
don't have any meaningful differences. Therefore, get rid of all
references to SD_LEGACY and use MMC_LEGACY to mean both of them.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add the sdhci_deferred_probe() function to register as the
deferred_probe() callback to the mmc core. It will in turn call the
deferred_probe() callback of the platform drivers as declared in the
sdhci_ops.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add a deferred_probe() API for platforms that want to do some
configurations just before starting to enumerate the device.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add a saved_clock member to struct mmc to store the previous clock speed
in the clock needs to be stopped for some time.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This header uses bd_t without including its definition.
Change it to (struct bd_info), and add the forward declaration
to specify it as a structure.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Allow the default environment file to contain long lines split into
multiples lines.
Leading white spaces can be added for readability as well.
Signed-off-by: Samuel Mescoff <samuel@mescoff.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
- Revert "x86: use invd instead of wbinvd in real mode start code"
- Convert toradex boards README to reST
- serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()
- x86: apl: Use cpu_x86_get_count() for cpu_ops.get_count
Use cpu_x86_get_count() to read the number of cores.
cpu_x86_get_count() reads the number of CPUs from the device tree.
Using this function we can support multiple Apollo Lake
variants, e.g.: E3940 (4 cores) and E3930 (2 cores).
This was tested on the E3940 and E3930 Apollo Lake variants.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The function cpu_x86_get_count() is also useful for other modules.
Make it non-static and add a prototype + description.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The value for "Top of CAR region" should be fefc0000, not
fefc000. This matches the Kconfig default values, as
SYS_CAR_ADDR and SYS_CAR_SIZE are 0xfef00000 and 0xc0000
respectively.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Drop the Apollo Lake prefix 'apl' from the functions, types and
variables in the P2SB driver.
The P2SB is not Apollo Lake specific, and as such it was moved in
commit 2999846c11 ("x86: Move P2SB from Apollo Lake to a more generic
location") from the Apollo Lake folder to the intel_common folder.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Currently the ofdata_to_platdata() method calls dev_read_addr_pci(),
which potentially accesses the parent PCI bus. If this happens before
the parent PCI bus is probed the resulting address will be wrong.
This behavior was triggered by commit 82de42fa14 ("dm: core:
Allocate parent data separate from probing parent").
According to a comment in drivers/pci/pci-uclass.c [1] accessing
the PCI parent bus in ofdata_to_platdata() is not allowed, and the
access should be moved to the probe() function.
Move the call to dev_read_addr_pci() and the related handling of the
'addr' value from the ofdata_to_platdata() to its own function,
which is then called from the probe() method.
While moving the code, the comment /* try Processor Local Bus device
first */ was dropped. It was initially added with commit 3db886a5bf
("serial: ns16550: Support ns16550 compatible pci uart devices") and
later made obsolete with commit 33c215af4b ("dm: pci: Add a function
to read a PCI BAR").
[1] Comment in drivers/pci/pci-uclass.c:
"A common cause of this problem is that this function is called in the
ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
method is not allowed, since it has not yet been probed. To fix this,
move that access to the probe() method of @dev instead."
Fixes: 82de42fa14 ("dm: core: Allocate parent data separate from probing parent")
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
This reverts commit 0d67fac29f.
As real hardware testing (*) shows the above mentioned commit
breaks U-Boot on it. Revert for the upcoming release. We may get
more information in the future and optimize the code accordingly.
(*) on Intel Edison board.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix a typo in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
If all branches of a switch statement have a return instruction, all
subsequent lines are unreachable.
Identified with cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
- add initial index for toradex boards reST documentation
- add initial colibri_imx7.rst doc file which provides all needed
information for obtaining a workable image ready for flashing
for both eMMC/NAND versions of Colibri iMX7.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: make title underline the same length as the title itself]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This function doesn't use uclass_find_first_device() correctly. Add a
check that the device is found so we don't try to read properties from a
NULL device.
The fixes booting on minnoxmax.
Fixes: 87f1084a63 ("x86: Adjust mrccache_get_region() to use livetree")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add driver flag to skip power domain disabling on device removal.
Fixes: 52edfed65d ("dm: core: device: switch off power domain after device removal")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Guillaume La Roque <glaroque@baylibre.com>
In various cases a power domain must stay enabled after device
removal when booting OS (i.e. serial debug console or display).
Add a flag to selectively skip switching off a power domain.
Fixes: 52edfed65d ("dm: core: device: switch off power domain after device removal")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Denali SPL shim won't build without these options set,
set them accordingly to fix the build error and let the SPL
shim to work correctly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The default timer rate may be different than 25 MHz, permit overriding
the default rate in board configuration file. Ultimatelly, this should
be properly handled by a clock driver, however that is not available
on Gen5 yet.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This adds a compatible string for m41st87. This ensures that this driver
can be used for m41st87.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
After the commit 9b643e312d ("treewide: replace with error()
with pr_err()"), there are pr_err() usages without line break. Add
missing line breaks for pr_err() used in f_thor.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
In case dfu command is being executed with timeout option,
the timer may expire in the middle of DFU operation. If there
is DFU request coming, we may simple reset timeout value
to prevent aborting of ongoing DFU operation.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Ferry Toth <ftoth@exalondelft.nl>
The HF/QSPI flash layout permits up to 1 MiB large bootloader blob,
set CONFIG_BOARD_SIZE_LIMIT to enforce this limit and set the
monitor size to match accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Pull request for UEFI sub-system for efi-2020-04-rc4 (2)
In Linux next-20200228 patches have been merged to load an initial ramdisk
using an EFI_LOAD_FILE2_PROTOCOL provided by the firmware. See commit
ec93fc371f01 ("efi/libstub: Add support for loading the initrd from a
device path"). The idea behind it is that the firmware should be
responsible for validating the initrd in a secure boot setup.
This pull-request comprises a patch series which let's U-Boot provide an
initial implementation of the EFI_LOAD_FILE2_PROTOCOL providing the initrd.
UniPhier SoC updates for v2020.04 (3rd)
- Enable ADMA and HS400 for the eMMC driver on 64-bit SoCs
- Add some convenient environment variables to handle SD card
- Sanitize the NAND controller reset sequence and its WP handling
- Sync DT with Linux
The compatible string "i2c-eeprom" is U-Boot own compatible, which
has never been approved by the DT community. "u-boot,i2c-offset-len"
is also a U-Boot own hack.
Linux adds "atmel,*" as generic compatibles, and U-Boot also followed
it by commit d7e28918aa ("i2c_eeprom: Add reading support").
The U-Boot own hack is no longer needed. Just sync with Linux.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Import the nodename changes I made in Linux for avoiding dt-schama
warnings. This follows the $nodename patterns in the dt-schema.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The load file 2 protocol can be used by the Linux kernel to load the initial
RAM disk. U-Boot can be configured to provide an implementation.
Add a description to the UEFI overview and document the related functions
in the API section.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Provide a unit test loading an initial ramdisk using the
EFI_LOAD_FILE2_PROTOCOL. The test is only executed on request.
An example usage - given a file image with a file system in partition 1
holding file initrd - is:
* Configure the sandbox with
CONFIG_EFI_SELFTEST=y
CONFIG_EFI_LOAD_FILE2_INITRD=y
CONFIG_EFI_INITRD_FILESPEC="host 0:1 initrd"
* Run ./u-boot and execute
host bind 0 image
setenv efi_selftest load initrd
bootefi selftest
This would provide a test output like:
Testing EFI API implementation
Selected test: 'load initrd'
Setting up 'load initrd'
Setting up 'load initrd' succeeded
Executing 'load initrd'
Loaded 12378613 bytes
CRC32 2997478465
Executing 'load initrd' succeeded
Now the size and CRC32 can be compared to the provided file.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Following kernel's proposal for an arch-agnostic initrd loading
mechanism [1] let's implement the U-boot counterpart.
This new approach has a number of advantages compared to what we did up
to now. The file is loaded into memory only when requested limiting the
area of TOCTOU attacks. Users will be allowed to place the initramfs
file on any u-boot accessible partition instead of just the ESP one.
Finally this is an attempt of a generic interface across architectures
in the linux kernel so it makes sense to support that.
The file location is intentionally only supported as a config option
argument(CONFIG_EFI_INITRD_FILESPEC), in an effort to enhance security.
Although U-boot is not responsible for verifying the integrity of the
initramfs, we can enhance the offered security by only accepting a
built-in option, which will be naturally verified by UEFI Secure Boot.
This can easily change in the future if needed and configure that via ENV
or UEFI variable.
[1] https://lore.kernel.org/linux-efi/20200207202637.GA3464906@rani.riverdale.lan/T/#m4a25eb33112fab7a22faa0fd65d4d663209af32f
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Commit 06985289d4 ("watchdog: Implement generic watchdog_reset()
version") introduced an automatic selection of CONFIG_WATCHDOG by
CONFIG_WDT. But for boards selecting CONFIG_HW_WATCHDOG, like
boards have a powerpc 8xx, CONFIG_WATCHDOG shall not be selected
as they are mutually exclusive.
Make CONFIG_WATCHDOG dependent on !CONFIG_HW_WATCHDOG
Fixes: 06985289d4 ("watchdog: Implement generic watchdog_reset() version")
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit f3729ba6e7 ("watchdog: mpc8xx_wdt: Watchdog driver and macros
cleanup") switched the watchdog to CONFIG_WATCHDOG. But this is not
compatible with the 8xx because it starts the watchdog HW timer at
reset and must be serviced from the very beginning including while
U-boot is executed in the firmware before relocation in RAM.
Select CONFIG_HW_WATCHDOG and make hw_watchdog_reset() visible.
Meanwhile, finalise the cleanup of arch/powerpc/cpu/mpc8xx/Kconfig by
removing the lines put in comment in that commit, and also remove
again the selection of CONFIG_MPC8xx_WATCHDOG which was removed by
that commit and brought back by mistake by commit b3134ffbd9
("watchdog: Kconfig: Sort entry alphabetically")
Note that there was an 'imply WATCHDOG' in the original commit but
it disappeared in the Kconfig alphabetical sorting, so no need to
remove it here.
Fixes: f3729ba6e7 ("watchdog: mpc8xx_wdt: Watchdog driver and macros cleanup")
Fixes: b3134ffbd9 ("watchdog: Kconfig: Sort entry alphabetically")
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Stefan Roese <sr@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Very likely configs have been moved to Kconfig by scripts and this just
remains there that's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DEVICE_TREE variable is not exported from dts/Makefile that's why it is
necessary to setup directly before use.
Fixes: 312f2c5b14 ("arm: xilinx: Use device tree which can be passed on cmd line")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Driver probe function is called again and again in case of error.
Malloc space is getting full which is is reported by:
Insufficient RAM for page table: 0x15000 > 0x14000.
Please increase the size in get_page_table_size()
### ERROR ### Please RESET the board ###
The patch is freeing allocated buffers on error path to avoid panic.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.
Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.
Fixes: 37d6265f2b ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Fixed wrong enumeration of nand_config structure. Added chip select
function before reading the nand chip for maf/dev id's, without this
unable to access id's from some of the micron chips. Also added a
print statement to identify if a nand flash is using on-die ecc.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling versal_pm_clock_get_name() in versal_get_clock_info() function.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The board uses 100 MHz clock for UART bitrate generator,
but is configured as 50 MHz on defconfig.
This produces wrong console output.
The first message, "Debug uart enabled" is received as:
"������b"
Fix the issue by configuring the correct clock for the
UART baudrate generator
Signed-off-by: Milan Obuch <u-boot@dino.sk>
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The board has two push button connected to MIO pins
50 and 51, which have a pull-down resistor and are
connected to 1.8V when pressed.
These two pins are wrongly initialized with internal
pull-up enabled so they are reported as 1 all the time
with no change when pressed.
Disable the internal pull-up to fix the issue.
Signed-off-by: Milan Obuch <u-boot@dino.sk>
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
flush_dcache_range() expects unsigned long in the arguments. Here u32
variable is unable to hold the higher address value when ddr mapped
to higher addresses & flushing lower address dchache range instead
which is unmapped causing to crash.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The eMMC controller on LD20 or later supports HS-400 mode. It works on
a quick test. Enable it in case somebody may want to use it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The base address 0x43f00000 is no longer true for the future SoC.
Extract the base address from the device tree.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This workaround was previously needed for LD4, Pro4, sLD8, Pro5
SoCs. The boot ROM does not touch this register for PXs2/LD6b or
later.
Now that the reset signal of the Denali NAND controller is always
asserted in board_init() then deasserted in the driver, the
WRITE_PROTECT register gets back to the default value, which means
the write protect is deasserted.
This workaround can go away entirely.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The comment /* deassert reset */ is wrong. It asserts the reset.
It no longer needs to stay in SPL. The NAND controller reset is
handled in the driver. So, this assert can be moved to the
board_init() of U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add handy macros:
- sdscript: source boot.scr in the file system of the SD media
- sdboot : boot the kernel using the images in the file system
of the SD media
- sdscript: update the boot firmware in the SD media
(in raw block sectors)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Pull request for UEFI sub-system for efi-2020-04-rc4
UEFI spec 2.8 errata A replaces the RuntimeServicesSupported variable
defined in UEFI spec 2.8 by the configuration table
EFI_RT_PROPERTIES_TABLE. So let's follow suit.
UEFI spec 2.8 errata A replaces the RuntimeServicesSupported variable
defined in UEFI spec 2.8 by the configuration table
EFI_RT_PROPERTIES_TABLE. So let's follow suit.
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Ard Biesheuvel <ardb@kernel.org>
This fixes the inadvertent definition of CONFIG_DTB_RESELECT and
CONFIG_MULTI_DTB_FIT in the K2x HS defconfigs, that happened as part of
a resync of the defconfigs.
The inclusion of these config options causes ethernet to stop working on
K2x HS devices as they interfere with the installation of the secure
boot monitor.
This patch also removes the above configs for the K2 GP devices, as they
are not needed, and to keep the differences between the GP and HS
defconfigs to a minimum.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Its possible that k3_avs_priv is NULL because the driver may not have
been probed yet. Therefore check if pointer is valid before
dereferencing it.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
When the board was originally submitted, it was attempting to use the
ESDHC driver. The board uses the USDHC driver.
Signed-off-by: Carl Gelfand <carl@novtech.com>
Cc: Shawn Guo <shawn.guo@kernel.org> (maintainer:MEERKAT96 BOARD)
Acked-by: Shawn Guo <shawnguo@kernel.org>
Macro SZ_64K is undeclared. Include sizes.h to fix the compilation
error.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The include uboot_aes.h is not useful and
it breaks the compilation on android, so
we remove it.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reported-by: Praneeth Bajjuri <praneeth@ti.com>
Several patches delivered incorrect restructured text as documentation. We
should be able to discover this in Travis CI, Gitlab CI, or Azure CI.
So let us turn all build warnings into errors.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Several patches delivered incorrect restructured text as documentation. We
should be able to discover this in Azure CI.
Provide a build step for 'make htmldocs'.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Several patches delivered incorrect restructured text as documentation. We
should be able to discover this in Gitlab CI.
Provide a build step for 'make htmldocs'.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Several patches delivered incorrect restructured text as documentation.
We should be able to discover this in Travis CI.
Provide a build step for 'make htmldocs'.
Add required package graphviz.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The sata of our powerpc platforms are updated. These changes is to
fit the driver probe.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This reverts commit 02dc1599ba
Commit 02dc1599ba ("configs: enable sata, eSDHC, USB device module in
T2080QDS")
has some sata defconfig changes to fit support DM mode, Now the driver
will be reverted, So revert it.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This reverts commit 856b9cdb53.
Commit 856b9cdb53 ("powerpc: mpc85xx: delete FSL_SATA for T2080QDS
board.") is to fit support sata DM mode, Now the driver will be reverted,
So revert it.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This reverts commit 1ee4942918.
Commit 1ee4942918 ("ata: fsl_ahci: Add sata DM support for Freescale
powerpc socs") introduced SCSI layer to call AHCI private API in order
to support sata operations, In DM mode, This is not necessary for
non-AHCI sata. So revert it and have already updated the driver itself
to operate sata directly.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Update doc/sphinx/kerneldoc.py from Linux next-20200219 to avoid warnings
like:
doc/sphinx/kerneldoc.py:125: RemovedInSphinx20Warning:
AutodocReporter is now deprecated. Use
sphinx.util.docutils.switch_source_input() instead.
self.state.memo.reporter =
AutodocReporter(result, self.state.memo.reporter)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This driver currently performs cache operation before the DMA start,
but does nothing after the DMA completion.
When reading data by DMA, the cache invalidation is needed also after
finishing the DMA transfer. Otherwise, the CPU might read data from
the cache instead of from the main memory when speculative memory read
or memory prefetch occurs.
Instead of calling the cache operation directly, this commit adds
dma_unmap_single(), which performs cache invalidation internally,
but drivers do not need which operation is being run.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, sdhci_prepare_dma() calls flush_cache() regardless of the
DMA direction.
Actually, cache invalidation is enough when reading data from the device.
This is correctly handled by dma_map_single(), which mimics the DMA-API
in Linux kernel. Drivers can be agnostic which cache operation occurs
behind the scene.
This commit also sanitizes the difference between the virtual address
and the dma address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
host->mmc is already (struct mmc *).
memalign() returns an opaque pointer, so there is no need for casting.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The same code is run for both SDHCI_QUIRK_32BIT_DMA_ADDR and
define(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER).
Unify the code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Using the global variable does not look nice.
Add a new field sthci::align_buffer to point to the bounce buffer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
There are many boards share the board file and device header file with
rk3399 evb, add target type MACRO so that it is fixed instead of default
to the first target in "RK3399 board select".
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Pull request for UEFI sub-system for efi-2020-04-rc3
* Update the Kconfig description of CONFIG_EFI_RNG_PROTOCOL
* Fix a function comment resolving a warning in 'make htmldocs'
The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.
Factor them out to <linux/dma-mapping.h>, and make all drivers to
include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>.
If we need to differentiate them for some architectures, we can
move the generic definitions to <asm-generic/dma-mapping.h>.
Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The reference manuals for MPC8308 and MPC8309 both say that the
esdhcctl aka DMA Control Register "is implemented as SDHCCR" in the
System configuration registers. Unfortunately, that doesn't mean that
the registers are just mirrors of each other - any write to esdhcctl
is simply ignored. So to actually enable cache snooping, we
unfortunately have to add a little ifdeffery.
There is, naturally, no description of the bit fields of esdhcctl in
the MPC8309 manual, but comparing the description of esdhcctl from the
LS1021A reference manual to the description of the sdhccr in MPC8309,
one also finds that the fields are bit-reversed, so the bit to set is
0x02000000 rather than 0x00000040 - this is also what board_mmc_init()
uses in the two gdsys/mpc8308/ boards.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Yangbo Lu <yangbo.lu@nxp.com>
Added support for onboard LED's and push button. When powered board will be
in low power mode(yellow LED), on button press, board enters full power mode
(red LED) and boots u-boot.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
roc-pc-rk3399 board has one user button & three user LED's. Currently
we don't have any code support for these devices. Since button and LED's are
specific to roc-pc-rk3399 board, split it into its own board file and add code
support here.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
adc_channel_single_shot() requires the full device name e.g.
"saradc@ff100000", which differs between Rockchip SoC's, but they all
share the prefix "saradc"; find the ADC device with this name prefix and
use its full name.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add console settings like stdin, stdout and stderr as
cros-ec-keyb and vidconsole respectively for Vyasa Rk3288
board.
This would certainly help to detect the attached video
devices (like HDMI) and print the console message on display.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync rk3288-vyasa dts file from Linux.
This sync has changes required to work HDMI output on
Vyasa RK3288 board.
This sync excludes the io_domains node since it is not
available in rk3288.dtsi.
Changes like vcc50_hdmi, vdd10_lcd and ddc-i2c-bus are
not merged to Linux yet but wil resync later if any
further updates on this.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable pre console buffer for rk3288 platform.
This would help to capture the console messages prior to
the console being initialised. Enabling this would help
to capture all the console messages on video output source
like HDMI. So we can find the full console messages of
U-Boot proper on HDMI display when enabled it for RK3288
platform boards.
Buffer address used for pre console is 0x0f000000 which is
ram base plus 240MiB. right now the Allwinner SoC is using
similar computation.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There have been multiple peripherals added to the main px30 dtsi
in the Linux kernel since its addition to u-boot. So to make it easier
to sync board devicetrees, update the core dtsi from Linux.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Move the U-Boot specific bits to a -u-boot.dtsi include so all the
u-boot.dtsi hierarchy is included.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There's some bits in the U-Boot rk3399.dtsi that aren't yet in the
upstream Linux dtsi but are needed for early boot. This moves them
to the u-boot.dtsi to make it easier to sync the rest of rk3399.dtsi
with upstream.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The upstream linux kernel for the Rockchip 3399 SoC use usbdrd3 naming so move
the two remaining devices over to that for their device trees to make it
easier to sync with upstream DTs.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The core Rockchip spl code contains a default board_fit_config_name_match
implementation doing nothing. Individual boards may want to handle this
differently, so add a __weak atribute to make it possible to override
this function in other places.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The script iterates over the given devicetrees and creates both
fdt_x node as well as a conf-node for each passed dt.
But there is a slight bug in that it always references fdt_1 in each
conf node instead of the matching fdt_x as expected.
So fix that by referencing the number of the current dt similar to
how the fdt_x nodes gets created.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
i2c bugfixes for 2020.04
- i2c: designware_i2c: Correct the selection of speed mode
Fixes: d96440d1e3 ("i2c: designware_i2c: Add support for fast-plus speed")
Unfortunately a recent change adjusted the order of the checks here such
that 400MHz now shows up as fast-plus speed (1Mbps). Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: d96440d1e3 ("i2c: designware_i2c: Add support for fast-plus speed")
Since commit 01298da31d ("mmc: Change mode when switching to a boot
partition"), errors in mmc_select_mode_and_width() are ignored.
The return value should be checked.
Fixes: 01298da31d ("mmc: Change mode when switching to a boot partition")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Cadence sent out an errata report to their customers of this IP.
This errata is not so severe, but the tune request should be sent
twice to avoid the potential issue.
Quote from the report:
Problem Summary
---------------
The IP6116 SD/eMMC PHY design has a timing issue on receive data path.
This issue may lead to an incorrect values of read/write pointers of
the synchronization FIFO. Such a situation can happen at the SDR104
and HS200 tuning procedure when the PHY is requested to change a phase
of sampling clock when moving to the next tuning iteration.
Workarounds
-----------
The following are valid workarounds to resolve the issue:
1. In eMMC mode, software sends tune request twice instead of once at
each iteration. This means that the clock phase is not changed on
the second request so there is no potential for clock instability.
2. In SD mode, software must not use the hardware tuning and instead
perform an almost identical procedure to eMMC, using the HRS34 Tune
Force register.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
erase_grp_size is used, when MMC_WRITE is enabled.
- error: ‘struct mmc’ has no member named ‘erase_grp_size’
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme
For stm32 f4, f7 and h7 boards, remove fdt_high and
initrd_high as they shouldn't be used, this allows the fdt
and initrd relocation.
This implies to set CONFIG_SYS_BOOTMAPSZ to indicate the
amount of memory available to contain kernel, device tree
and initrd for relocation.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
For stm32f4, f7 and h7 boards, reserve:
- 4MB for kernel
- 64KB for fdt, boot script, pxefile
- the remaining memory for ramdisk
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Remove fdt_high and initrd_high as they shouldn't be used,
this allows the fdt and initrd relocation.
This implies to set CONFIG_SYS_BOOTMAPSZ to indicate the
amount of memory available to contain kernel, device tree
and initrd for relocation.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Remove fdt_high and initrd_high (set to 0xffffffff) in stm32mp1 board
enviromnent, and U-Boot always relocate FDT and initrd in bootm command.
This relocation is limited by CONFIG_SYS_BOOTMAPSZ which indicates
the size of the memory region where it is safe to place data passed
to the Linux kernel (DTB, initrd), it is
a) Less than or equal to RAM size.
b) not within the kernel's highmem region
So 256M seems large enough in most circumstances and users
can override this value via environment variable "bootm_mapsize"
if needed.
This modification increases the boot time but avoid assumption
on aligned address for bootm command.
A user can still define this variables themselves if the FDT or
initrd is either left in-place or copied to a specific location.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Solve type issue in stm32mp1_lse_enable and stm32mp1_clktree.
This patch solves the warnings when compiling with W=1
on stm32mp1 board:
clk_stm32mp1.c: In function ‘stm32mp1_lse_enable’:
clk_stm32mp1.c:1238:15: warning: comparison of integer expressions
of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
[-Wsign-compare]
clk_stm32mp1.c:1239:13: warning: comparison of integer expressions
of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
[-Wsign-compare]
clk_stm32mp1.c: In function ‘stm32mp1_clktree’:
clk_stm32mp1.c:1814:17: warning: comparison of integer expressions
of different signedness: ‘int’ and ‘unsigned int’
[-Wsign-compare]
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Use int as result of dm_i2c_reg_read to avoid warning with
W=1 (warning: comparison is always false due to limited range
of data type [-Wtype-limits])
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Change the dfu functions dfu_otp_read and dfu_pmic_read to static,
this patch avoids warning when compiling with W=1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add include for dfu, add prototype for set_dfu_alt_info
and avoid warning when compiling with W=1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Two header fields are not properly converted to little endian
before assignment, resulting in incorrect header while executing
mkimage on big endian hosts.
Convert the value of the header fields image_checksum and
edcsa_algorithm to little endian before the assignment.
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Update readme:
- list the supported SOC and change family to STM32MP15x
- add warning on OTP write and prerequisite:
check if MAC address is not yet provisioned.
- Use filesize for mmc write command (avoid to write all partition
with ${partsize}). ${filesize} and ${partsize} are set by previous
load command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Fix the following DT dtc warnings for stm32mp1 boards:
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@0:
node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@1:
node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@2:
node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@3:
node has a unit name, but no reg property
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This patch fix the warning:
dt.dts: Warning (simple_bus_reg): Node /soc/ddr@5A003000
simple-bus unit address format error, expected "5a003000"
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
cache the value at probe and pretend to use it later.
Keep the LTDC alone on PLL4_Q by moving the FDCAN to PLL4_R.
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Update the driver to use the latest binding from kernel v5.5-rc1:
no more use syscon or regmap to access to pwr register and
only one pwr_regulators node with the compatibility "st,stm32mp1,pwr-reg"
is available.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Activate early console functionality on AM65x devices to allow for
early diagnostic messages until the main console is ready
to get activated.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The boot parameter table index memory address for J721E was configured
to an incorrect value which prevented the use of this definition to
determine which boot parameter table is active which is needed to be
able to distinguish between primary and backup boot modes. Fix this
issue by updating the value to the correct one also in alignment with
the J721E Technical Reference Manual (TRM).
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Keystone2 u-boot loads the initrd image into non-LPAE addressed memory
but linux kernel is running in LPAE. This causes a conflict as kernel
detects that non-memory address is passed and kernel ignores initrd.
There is an existing fixup logic to modify the address in the proper
configuration, but this is disabled at the moment. Enable the fixup
by setting the env variable for this so that initrd can be used
properly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On am571x-idk there can be following configurations based on Jumper J51
and LCD panel detected.
1) J51 removed (6port): 6 port Ethernet. Disable LCD panel.
2) J51 placed (LCD) + Panel detected: 4 port Ethernet with appropriate LCD.
3) J51 placed (LCD) + Panel not detected/not supported.
Configuration 3 is considered invalid as we can't use display nor ICSS1
ethernet ports due to hardware muxing. Alert the user to fix the
configuration and prevent boot.
Alternative was to allow boot and limit to 4 port Ethernet with no display
but this involved introduction of another DTB for the kernel and was
considered not worth the hassle.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Data manual mentions the new silicon revisions as SR instead of PG. Use
the same nomenclature inside U-Boot as well.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add mmc device partition 0 as the seat of the environment.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
mcu uart will be used during uart boot for loading sysfw.itb. Since
sysfw is not yet available during uart load, power-domain cannot be
enabled. We need to rely on ROM for doing that, so disable power-domains
and clocks for mcu uart. Also fix the mcu uart frequency.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add scm_conf syscon node and its parents as well as the ethernet phy
node to u-boot.dtsi. This enables ethernet boot.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When running our tests there are some cases where as part of the Python
2.7 to Python 3.6 migration we didn't force Python 3.6 to be used as
everything wasn't yet migrated. Now that everything is, make sure to
tell virtualenv to use python3. In the case of Travis this is best done
by making the tools test happen after the main tests so that it will
already have been run in all cases, TEST_PY_TOOLS is a subset of
TEST_PY_BD.
Signed-off-by: Tom Rini <trini@konsulko.com>
clear_bss is already used by 3 arches (x86, arc, xtensa), so make it generic
and provide a weak nop stub for it. This also removes arch-specific ifdef
duplications around clear_bss.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
There is no reason to show RAM_ROCKCHIP_DEBUG entry in other .config files
as I see it for Xilinx ZynqMP.
\# CONFIG_U_QE is not set
\# CONFIG_RAM is not set
CONFIG_RAM_ROCKCHIP_DEBUG=y
Add missing dependency on RAM_ROCKCHIP driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fix a build error
checking consistency...
/doc/board/rockchip/index.rst:
WARNING: document isn't included in any toctree
Fixes: 338b86c9b3 ("doc: boards: Add rockchip documentation")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Avoid errors of like
common/console.c: In function ‘console_record_reset’:
common/console.c:615:16: error: passing argument 1 of ‘membuff_purge’
discards ‘volatile’ qualifier from pointer target type
[-Werror=discarded-qualifiers]
615 | membuff_purge(&gd->console_out);
| ^~~~~~~~~~~~~~~~
by casting to non-volatile.
The volatile property stems from declarations like
arch/arm/include/asm/global_data.h:114:
But there is no need to treat gd->console_out and gd->console_in as
volatile in the context of common/console.c.
Fixes: b612312816 ("console: Add a function to read a line of the output / eof")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the first version, the result of malloc is checked
with ut_assertnonnull. But on a fail, this macro exit
the function, so previously malloc are not freed.
So to avoid a memleak, we don't use ut_assertnonnull,
but simply check the return of malloc. If one has failed,
we freed all the allocated memory and quit the function.
Reported-by: Coverity (CID: 284403)
Reported-by: Coverity (CID: 284404)
Reported-by: Coverity (CID: 284405)
Reported-by: Coverity (CID: 284406)
Reported-by: Coverity (CID: 284407)
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Currently the size of pci_addr_t and pci_size_t depends on
CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads
to an error
pci_hose_phys_to_bus: invalid physical address
which is due to the truncation of the bus address in _dm_pci_phys_to_bus.
Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error
PCI: Failed autoconfig bar 10
So let's use unsigned long for pci_addr_t and pci_size_t if
CONFIG_SYS_PCI_64BIT is not defined.
Considering that 32bit U-Boot is used to launch some 64bit x86 systems we
cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
As usual a bit late a couple of tiny fixes and improvements for ARC.
1. Switch from ARC UART to a convenient DW UART on ARC
simulation platforms. This became avaialble when nSIM got support
of that much more standard UART (starting from nSIM v2019.06).
FWIW also available now in Free nSIM [1].
This among other things allows us finally to use the same one binary
on all our simulators & FPGA-based emulators.
2. Disable networking support on simulated platforms as there's no
network interface in them.
3. Add Virtio net & block devices for the configuration supported
by QEMU so that we may leverage those virtual peripherals and
in fact it's possible to load uImage from TFTP server and bootm it.
4. Minor fixes for HSDK clocks.
5. Rework of how we chose and use compiler options for ARC-based boards.
In real world ARC-based designs are customized more or less but very
rarely match any of our "templates" thus it makes not much sense to
pretend we have some fixed configs, instead we now will fully reply
on a SoC or even board on getting precise set of compiler options
preferably even extracted from real HW via "tcfgen" utility.
6. Well and finally yet another simplification - switch to generic
written in C accessors which are much more universal and just work
for any target supported by the complier as compared to GAS
implementation which is much more target-dependent.
This one was heavily "inspired" by similar implementation for RISCV
and ARM.
[1] https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi
Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier
board. This is an SoM with STM32MP15xx and an evaluation kit. The
baseboard provides Ethernet, UART, USB, CAN and optional display.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
First of all U-Boot is not that performance oriented as real run-time
software like OS or user bare-metal app so we may afford being not super
fast as we only being executed once. That in return allows us to be more
universal and support wider variety of devices.
And looking forward that will significantly reduce maintenance and simplify
support of newer architectures.
And while at it we add quad-word accessors like readq(), writeq() etc.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
It's a very rare if at all existing occasion when ARC CPU template
is used as is w/o any changes - in the end it's a beauty and competitive
advantage of ARC cores to be tailored for a particular use-case - and
so it doesn't make a lot of sense to offer template-based "-mcpu" selection.
Given for each and every platform we end-up adding quite a few more flags
it's logical to move "-mcpu" selection to platform's definition as well
which we exactly do here.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Given now nsim_hs38 configuration is usable on QEMU and in QEMU
we have Virtio working perfectly fine the next logical step
is to add support of supported & known to work net & bkl to this
config.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We don't have yet any brc700 or big-enadian platforms with networking
support to run this particular configuration.
Whenever QEMU for ARC supports arc700 or big-endian targets we may revisit
this one.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Since v2019.06 DesingWare nSIM supports DesignWare UART simulation
and so we may switch from pretty unusual ARC UART to much more standard
DesignWare UART (which in case of U-Boot is just an ordinary 16650 UART).
This among other things makes built dinaries compatible with our other
platforms to name a few: FPGA-based HAPS boards, QEMU and even ZeBU.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This is not needed now that we have SDL2 in the docker image. It causes
test failures for tests which need video to work.
This reverts commit af800722eb.
Signed-off-by: Simon Glass <sjg@chromium.org>
The commit e8e9715df2 ("regulator: fixed: Modify enable-active-high behavior")
fixed the regulator driver behavior when 'enable-active-high' is defined.
Unfortunately, this patch used dm_regulator_platdata()'s "boot_on" member
to set GPIOD_IS_OUT_ACTIVE flag and enable the regulator.
The issue here is that regulator_common_ofdata_to_platdata() is called
_before_ regulator_pre_probe() function in which the 'regulator-boot-on'
property is asserted.
As a result the GPIOD_IS_OUT_ACTIVE flag is not set and gpio_request_by_name()
called in the former function is not enabling the regulator.
This is problematic for e.g. i.MX ethernet driver, which then tries to
perform initialization without power (and fails).
The solution here is to explicitly enable regulator in regulator_pre_probe()
callback only when 'regulator-boot-on' property is present in device tree.
The GPIOD_IS_OUT_ACTIVE flag is not set at all, but relevant gpio is
requested.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
- Move P2SB from Apollo Lake to a more generic location
- Add a function to find a device by drvdata in DM core
- Enhancement of DM IRQ uclass driver
- Add a clock driver for Intel devices
- Add support for ACPI general-purpose events
- Add a TPM driver for H1/Cr50
- Enable TPM on Google Chromebook Coral
The add instruction on risc-v can have any three sources and targets, so there
is no need for an intermediate mov.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When debugging, it can be helpful to see more information about an
unhandled exception. This patch adds an option to view the registers at
the time of the trap, similar to the linux output on a kernel panic.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Due to the two-instruction sequence needed to access arbitrary memory
locations, the RISC-V linker aggressively optimises memory accesses and
jumps at link-time. This is called "linker relaxation," and is discussed
in this SiFive article
<https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain>.
One of the optimizations in place is to assume that the __global_pointer
symbol is placed in the gp register. To quote the article:
"...The magic __global_pointer$ symbol is defined to point 0x800 bytes
past the start of the .sdata section. The 0x800 magic number allows
signed 12-bit offsets from __global_pointer$ to address symbols at the
start of the .sdata section. The linker assumes that if this symbol is
defined, then the gp register contains that value, which it can then use
to relax accesses to global symbols within that 12-bit range. The
compiler treats the gp register as a constant so it doesn't need to be
saved or restored, which means it is generally only written by _start,
the ELF entry point."
However, U-Boot instead keeps the global data pointer in gp. This causes
memory accesses and jumps optimized to use the gp pointer to fail. To
fix this problem, we undefine the __global_pointer symbol.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Use `test' command to test for file existence instead of relying on the
old functionality of the `ext2load' command (which now reports an error
when attempting to load a zero length file).
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Drop PPD_UART_PAD_CTRL since it matches defaults.
Enable DM serial and MXC uart.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Add backlight and panel devicetree definitions
Use UCLASS_PANEL to enable backlight via display enable handler
Remove old explicit gpio code for handling backlight
Use cls command to initiate display in HW agnostic manner
Enable DM regulator and pwm
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Override the panel compatible string for LCD in U-Boot.
Include U-Boot device tree overrides in device-specific device trees so
that the panel compatible string is used.
Fixes: 8c26739859 ("board: ge: bx50v3: sync devicetrees from Linux")
Signed-off-by: Ian Ray <ian.ray@ge.com>
Enable DM_VIDEO for mx53ppd.
Enable DM_REGULATOR_FIXED and DM_PWM for the backlight.
Remove unused MX53PPD_LCD_POWER.
Remove old (incorrect) setup_iomux_lcd.
Enable backlight via display enable handler.
Use cls command to initiate display in HW agnostic manner.
Modify `failbootcmd' to use lcdputs.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Add bootcount node, linking to i2c eeprom "bootcount" partitions for
storage.
Enable i2c eeprom bootcount backend storage.
Enable bootcount command and use it for failbootcmd.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Add bootcount node, linking to i2c eeprom "bootcount" partitions for
storage.
Enable i2c eeprom bootcount backend storage.
Enable bootcount command and use it for failbootcmd.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Remove old (pre-DM) i2c setup code.
Enable DM i2c.
Convert common code to use DM rtc.
Convert common code to read VPD from eeprom partition.
Convert the generic i2c PMIC init code to use the new da9063 driver.
mx53ppd only:
Correct RTC compatible in device tree.
Enable MXC DM i2c driver.
Define CONFIG_SYS_MALLOC_F_LEN so that DM is available in pre-reloc.
Make GPIO banks available during preloc, since initialisation is done
in board_early_init_f().
Add gpio_request() calls to satisfy the DM_GPIO compatibility API.
Remove unused power configuration.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Set the correct offset length and chip address offset mask for each
device to allow correct access to total capacity of the devices.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
This should help keeping the screen black when booting the kernel.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Convert imx6sabresd PCI to driver model to fix the following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_PCI Please update
the board to use CONFIG_DM_PCI before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
After the conversion the following commands were used for testing:
=> pci enum
PCI: Failed autoconfig bar 10
PCI: Failed autoconfig bar 10
=> pci 1
Scanning PCI devices on bus 1
BusDevFun VendorId DeviceId Device Class Sub-Class
Reviewed-by: Fabio Estevam <festevam@gmail.com>
In preparation for converting to DM_ETH and moving the FEC symbols
to Kconfig we need to move the FEC definitions to mx6sabreauto.h
and mx6sabresd.h to avoid build breakage during the conversion.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
commit 88718be300 ("mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NAND")
moved CONFIG_NAND -> CONFIG_MTD_RAW_NAND. Adapt board code to this
change, as last merge did not respect the above commit.
Signed-off-by: Heiko Schocher <hs@denx.de>
Enable DM thermal driver and iMX thermal driver to get accurate
CPU frequency reporting in the boot log.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
Just move the defconfig entries which are required into the Novena
entry in arch Kconfig, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
These nodes are not in upstream kernel, so move these in u-boot.dtsi
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
With commit 6b503f9e6549("warp7: Switch to DM USB").
These configs are not necessary
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The 'enable-active-high' DTS property configures GPIO so it is active with
HIGH state (by default it is low).
The 'regulator-boot-on' property indicates that the regulator was enabled
in the 'earlier' stage - i.e. bootloader/firmware.
In the XEA case the 'fec-3v3' was configured (as a "wrapper" on GPIO0_0) in
very early SPL code, so it shouldn't be modified at latter stages.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Explicitly configure GPIO0_0 in SPL, which controlls 3V3 voltage
on the XEA board (it also supplies TIVAs).
This code would enable TIVAs power supply early (also when board
uses the falcon boot).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The 'local-mac-address' property needs to be adjusted to the MAC address
value stored in U-Boot's 'ethaddr' env variable.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Redundant envs help with assuring better reliability for the system as they
prevent from the situation when envs are stored only in a single place.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Since commit 9c27310ac2 ("mx7ulp: Move SoC base address to a common
file") we no longer need to have these SoC definitions in the board
file, so remove them.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Both CMD_MX_CYCLIC and MX_CYCLIC are in use and defined in Kconfig,
but only the non-CMD version currently does anything. This changes all
usages to prefer the CMD_MX_CYCLIC option (since it's only affecting
addition of the commands), and switches defconfigs using the non-CMD
version to use the CMD version.
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
When a firmware file is missing the warning message doesn't indicate the
firmware file name because '$tmp' var doesn't exist.
Fix the warning message and while at it reduce the if/else statement.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Currently there are two targets for the i.MX6SX SabreSD board:
mx6sxsabresd_defconfig and mx6sxsabresd_spl_defconfig.
This brings additional maintainance effort without a clear
advantage.
Keep only the mx6sxsabresd_defconfig one and remove
mx6sxsabresd_spl_defconfig to keep it simpler.
Also remove the SPL related code from the board file.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
The CONFIG_DM_74X164 symbols should be moved to the defconfig file,
as indicated in the comments.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Since commit bcee8d6764 ("dm: gpio: Allow control of GPIO uclass in SPL")
CONFIG_DM_74X164 is no longer built for mx7dsabresd_defconfig, as
this target does not use CONFIG_SPL_GPIO.
Remove such dependency and let the the 74X164 GPIO driver be built
again.
This restores Ethernet functionality on the imx7-sdb board as the
Ethernet reset PHY comes from a GPIO driven by a 74LV595PW I/O
expander.
Fixes: bcee8d6764 ("dm: gpio: Allow control of GPIO uclass in SPL")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Alifer Moraes <alifer.wsdm@gmail.com>
This adds initial minimal support for the Toradex Verdin iMX8M Mini Quad
2GB WB IT V1.0A module. They are now strapped to boot from eFuses which
are factory fused to properly boot from their on-module eMMC. U-Boot
supports booting from the on-module eMMC only, SDP support is disabled
for now due to missing i.MX 8M Mini USB support.
Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Ethernet
- GPIOs
- I2C
Boot sequence is:
SPL ---> ATF (TF-A) ---> U-boot proper
ATF, U-boot proper and u-boot.dtb images are packed into a FIT image,
loaded by SPL.
Boot:
U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
Normal Boot
Trying to boot from MMC1
NOTICE: Configuring TZASC380
NOTICE: RDC off
NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty
NOTICE: BL31: Built : 01:11:41, Jan 25 2020
NOTICE: sip svc init
U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
Reset cause: POR
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial#
06535149
Net: eth0: ethernet@30be0000
Hit any key to stop autoboot: 0
Verdin iMX8MM #
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
- 2 FAT fixes.
- MediaTek ethernet support improvement.
- Initial Cortina Access CAxxxx family support.
- Correct return value of do_gpio() and so gpio shell command.
The Cortina CAxxxx GPIO driver maintains DM_GPIO support
across different CPU ISA in the CAxxxx Soc Family; Not just ARM.
Therefore, it is not desirable to split out and maintain separete
gpio header file for each CPU architecture.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
Assign Alex Nemirovsky as custodian for all
Cortina Access (CA) for ARM and MIPS based SoCs.
Currently Cortina Access CAxxxx family of SoCs support both
ARM and MIPS ISA. Drivers have cross platform support for
both architectures.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
To match the other PowerPC platforms the function show_regs() must not
be marked static but instead be an exposed global function.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Christophe Leroy <christophe.leroy@c-s.fr>
Based on reading the text of the license comment this appears to be
the BSD-2-Clause license but with an imperfect word match as
BSD-2-Clause was not (as far as I recall) a common license choice at the
time the code was written.
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
building mtk ethernet driver for aarch64 (mt7622) results
in warnings/errors
"error: cast from pointer to integer of different size"
Fixes: 23f17164d9 ("ethernet: MediaTek: add ethernet driver for MediaTek ARM-based SoCs")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
This patch add sgmii init part for the mediatek SoC that
support sgmii mode. It is a must for mt7622.
Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
The code for handing file overwrite incorrectly assumed that the file on
disk is always contiguous. This resulted in corrupting disk structure
every time when write to existing fragmented file happened. Fix this
by adding proper check for cluster discontinuity and adjust chunk size
on each partial write.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
This patch partially fixes the issue revealed by the following test
script:
--->8-fat_test1.sh---
#!/bin/bash
make sandbox_defconfig
make
dd if=/dev/zero of=/tmp/10M.img bs=1024 count=10k
mkfs.vfat -v /tmp/10M.img
cat >/tmp/cmds <<EOF
x
host bind 0 /tmp/10M.img
fatls host 0
mw 0x1000000 0x0a434241 0x1000 # "ABC\n"
mw 0x1100000 0x0a464544 0x8000 # "DEF\n"
fatwrite host 0 0x1000000 file0001.raw 0x1000
fatwrite host 0 0x1000000 file0002.raw 0x1000
fatwrite host 0 0x1000000 file0003.raw 0x1000
fatwrite host 0 0x1000000 file0004.raw 0x1000
fatwrite host 0 0x1000000 file0005.raw 0x1000
fatrm host 0 file0002.raw
fatrm host 0 file0004.raw
fatls host 0
fatwrite host 0 0x1100000 file0007.raw 0x4000
fatwrite host 0 0x1100000 file0007.raw 0x4000
reset
EOF
./u-boot </tmp/cmds
#verify
rm -r /tmp/result /tmp/model
mkdir /tmp/result
mkdir /tmp/model
yes ABC | head -c 4096 >/tmp/model/file0001.raw
yes ABC | head -c 4096 >/tmp/model/file0003.raw
yes ABC | head -c 4096 >/tmp/model/file0005.raw
yes DEF | head -c 16384 >/tmp/model/file0007.raw
mcopy -n -i /tmp/10M.img ::file0001.raw /tmp/result
mcopy -n -i /tmp/10M.img ::file0003.raw /tmp/result
mcopy -n -i /tmp/10M.img ::file0005.raw /tmp/result
mcopy -n -i /tmp/10M.img ::file0007.raw /tmp/result
hd /tmp/10M.img
if diff -urq /tmp/model /tmp/result
then
echo Test okay
else
echo Test fail
fi
--->8---
Overwritting a discontiguous test file (file0007.raw) no longer causes
corruption to file0003.raw, which's data lies between the chunks of the
test file. The amount of data written to disk is still incorrect, what
causes damage to the file (file0005.raw), which's data lies next to the
test file. This will be fixed by the next patch.
Feel free to prepare a proper sandbox/py_test based tests based on the
provided test scripts.
Use the correct return value in function do_gpio() and update
commands documentation with the return values from command_ret_t enum.
CMD_RET_SUCCESS is returned on command success and CMD_RET_FAILURE is
returned on command failure.
The command was returning the pin value, which caused confusion when
debugging (#define DEBUG).
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Tested-by: Robert Marko <robert.marko@sartura.hr>
Up to now we have been relying on openSUSE repositories for GRUB on arm and
arm64 though we have included GRUB in our Docker image.
Use the GRUB included in our Docker image.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
H1 is a Google security chip present in recent Chromebooks, Pixel phones
and other devices. Cr50 is the name of the software that runs on H1 in
Chromebooks.
This chip is used to handle TPM-like functionality and also has quite a
few additional features.
Add a driver for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add definitions for access and status.
Need to drop the mixed case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add nodes to the device tree for Cr50 and other available I2C ports. Also
enable the ACPI interrupt driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ACPI GPEs are used to signal interrupts from peripherals that are accessed
via ACPI. In U-Boot these are modelled as interrupts using a separate
interrupt controller. Configuration is via the device tree.
Add a simple driver for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present driver model supports the IRQ uclass but there is no way to
request a particular interrupt for a driver.
Add a mechanism, similar to clock and reset, to read the interrupts
required by a device from the device tree and to request those interrupts.
U-Boot itself does not have interrupt-driven handlers, so just provide a
means to read and clear an interrupt. This can be useful to handle
peripherals which must use an interrupt to determine when data is
available, for example.
Bring over the basic binding file as well, from Linux v5.4. Note that the
older binding is not supported in U-Boot; the newer 'special form' must be
used.
Add a simple test of the new functionality.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow this driver to be used in TPL by setting up the interrupt type
correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add an IRQ type to each driver and use irq_first_device_type() to find
and probe the correct one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There can be different types of interrupt controllers in a system and some
drivers may need to distinguish between these. In general this can be
handled using the device tree by adding the interrupt information to
device nodes.
However on x86 devices we have interrupt controllers which are not tied
to any particular device and not really used in U-Boot. These still need
to be inited, so a convenient method is to give each controller a type
and allow a particular controller type to be probed.
Add support for this in sandbox along with a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove the new bland line at EOF of test/dm/irq.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This config is not actually used here and in U-Boot it seems better to set
this using the device tree for each individual controller. The monolithic
config of the FSP-S is only necessary if the FSP is actually configuring
something, but here it is not.
The FSP-S does enable/disable the various I2C ports. It might be nice to
handle this using the okay/disabled property of each port, but that can be
considered later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Enable the Intel clock driver and modify coral's device tree to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.
This driver can be expanded later as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have uclass_first_device_drvdata(), use it from the I2C driver
to reduce code duplication.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have uclass_first_device_drvdata(), use it from syscon to
reduce code duplication.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is sometimes useful to find a device in a uclass using only its driver
data. The driver data often indicates the 'subtype' of the device, e,g,
via its compatible string.
Add a function to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we have uclass_foreach_dev() which requires that uclass_get()
be called beforehand to find the uclass. This is good if we suspect that
that function might fail, but often we know that the uclass is available.
Add a new helper which does this uclass_get() automatically, so that only
the uclass ID is needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Primary to Sideband Bridge (P2SB) is not specific to Apollo Lake, so
move its driver to a common location within arch/x86.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This partially reverts changes by commit 2cc393f32f
("video: make BPP and ANSI configs optional") since it
caused issues with other boards (missing LCD console
output on pinebook, x86 platform or sandbox). Enable
all disabled options again and opt out of not supported
color depth in board defconfigs.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Vagrant Cascadian <vagrant@debian.org>
Now that we can use direct access to the system malloc() in sandbox, drop
the remaining uses of os_malloc().
The only one remaining now is for the RAM buffer, which we do want to be
at a known address, so this is intended.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most files don't need this header and it pulls in quite of lots of stuff,
malloc() in particular. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.
Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Add a new device-tree property to control the colour depth. At present we
support 16bpp and 32bpp.
While we are here, update the code to use livetree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
On high-DPI displays U-Boot's LCD window can look very small. Add a
-K flag to expand it to make things easier to read, while still using
the existing resolution internally.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Sandbox currently uses SDL1.2. SDL2 has been around for quite a while and
is widely supported. It has a number of useful features. It seems
appropriate to move sandbox over.
Update the code to use SDL2 instead of SDL1.2.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present when audio stops, any in-progress output is cut off. Fix this
by waiting for output to finish.
Also use booleans for the boolean variables.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present an error does not stop the sound-output loop. This is incorrect
since nothing can be gained by trying to continue. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present there is no positive indication that U-Boot has finished
sending sound data. This means that it is not possible to power down an
audio codec, for example. Add a new method that is called once all sound
data has been sent.
Add a new method for this, called when the sound_play() call is done.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some files use U-Boot headers but still need to access the system
malloc(). Allow this by creating a new asm/malloc.h which can be used so
long as U-Boot's malloc.h has not been included.
Signed-off-by: Simon Glass <sjg@chromium.org>
The last member of this array is supposed to be all zeroes according to
the getopt_long() man page. Fix the function to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some sandbox files are not built with U-Boot headers, so with the renamed
malloc functions there is now no need to use the special os_... allocation
functions to access the system routines. Instead we can just call them
directly.
Update the affected files accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
These functions include calls to a memory-allocation routine and so need
to use the system routine when called from a library.
To preserve access to these functions for libraries that need it, such as
SDL, rename these functions within U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
In order to allow use of both U-Boot's malloc() and the C library's
version, set a prefix for the allocation functions so that they can
co-exist.
This is only done for sandbox. For other archs everything remains the
same.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass <sjg@chromium.org>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass <sjg@chromium.org>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass <sjg@chromium.org>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass <sjg@chromium.org>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass <sjg@chromium.org>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass <sjg@chromium.org>
For sandbox we want to have the maximum possible build coverage, so enable
all colour depths for video.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
At present only a 16bpp display is supported for Truetype fonts. Add
support for 32bpp also since this is quite common.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
At present options are presented in essentially random order. It is easier
to browse them if they are sorted into alphabetical order. Adjust the
help function to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Following the recommendation of adding '#define DEBUG' at the top
of drivers/core/lists.c does not cause the debug messages to be
shown. Change it to '#define LOG_DEBUG' instead, which actually
makes it work as per doc/README.log.
While at it, provide the full path to lists.c to in order to make
the instructions clearer.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is needed when importing mainline DTs into U-Boot, as some started
using this /omit-if-no-ref/ tag, so won't compile with U-Boot's current
dtc copy. This is just a cherry-pick of the patch introducing this
feature.
Original commit message from Maxime:
------------------
A number of platforms have a need to reduce the number of DT nodes,
mostly because of two similar constraints: the size of the DT blob, and
the time it takes to parse it.
As the DT is used in more and more SoCs, and by more projects, some
constraints start to appear in bootloaders running from SRAM with an
order of magnitude of 10kB. A typical DT is in the same order of
magnitude, so any effort to reduce the blob size is welcome in such an
environment.
Some platforms also want to reach very fast boot time, and the time it
takes to parse a typical DT starts to be noticeable.
Both of these issues can be mitigated by reducing the number of nodes in
the DT. The biggest provider of nodes is usually the pin controller and
its subnodes, usually one for each valid pin configuration in a given
SoC.
Obviously, a single, fixed, set of these nodes will be used by a given
board, so we can introduce a node property that will tell the DT
compiler to drop the nodes when they are not referenced in the tree, and
as such wouldn't be useful in the targetted system.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a subcommand to dm to dump out what drivers are installed, and their
compatible strings. I have found this useful in ensuring that I have the correct
drivers compiled, and that I have put in the correct compatible strings.
Signed-off-by Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At kernel.org aarch64 toolchains are published in folder
arm64. Fix the URL for that case, so that we can fetch
toolchains on aarch64 machines.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If CONFIG_CMDLINE=n, common/cli.c calls board_run_command. This fails to
link on most architectures. However, the sandbox architecture has an
implementation which we can use.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The command tpm (and tpm2) search the tpm and use it.
On sandbox, there are two tpm (tpm 1.x and tpm 2.0).
So the command tpm and tpm2 are always executed with
the first tpm (tpm 1.x), and the command tpm2 always
fails.
This add a subcommand device to command tpm and
command tpm2. Then the command tpm and tpm2 use
the device selected with the subcommand device.
To be compatible with previous behaviour, if the
subcommand device is not used before a tpm (or tpm2)
command, the device 0 is selected.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
boot_fdt_add_mem_rsv_regions() scans the subnodes of
"/reserved-memory" and adds them to reserved lmb regions.
Currently this scanning does not take into "status" property.
Even if the subnode is disabled, it gets added to the
reserved lmb regions.
This patch checks the "status" property before adding it
to reserved lmb regions.
Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
When writing tests to check the output from commands it is useful to be
able to check the output line by line using an assertion. Add helper
macros to support this and to check that there is no unexpected trailing
data.
Also some commands produce a dump using print_buffer(). Add a way to check
that the correct number of bytes are dumped (ignoring the actual
contents).
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we reset the console buffer before each test but do not
actually set the recording flag. Without this, the output is not
recorded.
Update the code to set the flag before the test and clear it afterwards.
Signed-off-by: Simon Glass <sjg@chromium.org>
When recording the console output for testing it is useful to be able to
read the output a line at a time to check that the output is correct. Also
we need to check that we get to the end of the output.
Add a console function to return the next line and another to see how must
data is left.
Signed-off-by: Simon Glass <sjg@chromium.org>
This currently reads the uclass's private data in the ofdata_to_platdata
method which is not allowed, since the uclass has not read it from the
device tree. This happens in the probe method.
Fix it by adding a probe() method and moving the code there.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is convenient for bloblist to zero out the contents of a records when
it is added. This saves the callers having to do it.
Update the API accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
A common check is to see if a blob is present, create it if not and make
sure that the size is large enough. Add a function to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is sometimes useful to process all children, making sure they are
probed first. Add functions to help with this and a macro to make it more
convenient.
Signed-off-by: Simon Glass <sjg@chromium.org>
When generating ACPI tables we need to make sure that all devices have
read their platform data, so that they can generate the tables correctly.
Rather than adding this code in ACPI, create a core function to handle it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a function to read a property from the chosen node, providing access
to its length. Update ofnode_get_chosen_string() to make use of it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that we have ofnode_read_prop() we can rewrite this function using
that one, reducing the amount of duplicated code.
Update ofnode_read_size() and move it up next to the other similar
functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new function to read a property that supports reading the length as
well.
Reimplement ofnode_read_string() using it and fix its comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is actually intended to read a string rather than a
property. All of its current callers use it that way. Also there is no way
to return the length of the property from this function.
Rename it to better indicate its purpose, using ofnode_read as the prefix
since this matches most other functions.
Also add some tests which are missing for these functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
If a test happens to use the same variable as the macro parameter the
macro does not work as intended. Add an underscore to guard against this.
Signed-off-by: Simon Glass <sjg@chromium.org>
These functions do not modify the device so should use a const pointer to
it. Update the code accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
These functions do not modify the device so should use a const pointer to
it. Update the code accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this method uses a non-const udevice pointer, but the call
should not modify the device. Use a const pointer.
Signed-off-by: Simon Glass <sjg@chromium.org>
- DFU support file operations lager then the default max size
- add dfu support to dwc2 for bcm2835
- enable DFU for RPi4
- Fix RPi4 memory map to include the genet device
- add driver for the genet ethernet device
- enable network support in RPi4 config
Fix warnings issued by pylint:
* naming of variables
* usage of commas and semicolons
* indentation
* placement of module description
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated
by Quartus are named differently than the DDR3 ones, use anon unions to
store them in the same structures, without growing their size.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add DM_FLAG_OS_PREPARE flag to ensure that the driver's
remove() callback is invoked before booting the kernel.
This is required to stop the LCDIF controller. This was
the behaviour with old driver without DM_VIDEO support.
Without stopping the LCDIF we sometimes observe incorrect
Linux logo position.
Fixes: ae0760584b ("imx: mx6ul_14x14_evk: convert to DM_VIDEO")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Fix:
>>> CID 280902: Control flow issues (MISSING_BREAK)
>>> The case for value "VIDEO_BPP32" is not terminated
>>> by a 'break' statement.
Also fix
error: control reaches end of non-void function [-Werror=return-type]
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Various minor fixes for x86
- Switch to ACPI mode on Intel edison
- Support run-time configuration for NS16550 driver
- Update coreboot and slimbootloader serial drivers to use NS16550
run-time configuration
- ICH SPI driver fixes to hardware sequencing erase case
- Move ITSS from Apollo Lake to a more generic location
- Intel GPIO driver bug fixes
- Move to vs2017-win2016 platform build host for Azure pipelines
Inside Kconfig we must not use the CONFIG_ prefix with the imply statement.
Fixes: 28e3c39e53 ("board: freescale: ls1012a2g5rdb: enable network
support on ls1012a2g5rdb")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Updates the secure boot headers offsets of Kernel and other
firmware images for SD and NOR boot sources used by
esbc_validate command.
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Updates the secure boot headers offsets of Kernel and other
firmware images for SD and QSPI boot sources used by
esbc_validate command.
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Updates the secure boot headers offsets of Kernel and other
firmware images for SD and XSPI boot sources used by
esbc_validate command.
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Updates the secure boot headers offsets of Kernel and other
firmware images used by esbc_validate command.
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Updates the secure boot headers offsets of Kernel and other
firmware images for SD and QSPI boot sources used by
esbc_validate command.
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The default reserved memory for CMA is high memory. If LPAE is enabled,
highmem pages are non-remapped and can not be used with
dma_alloc_coherent. This patch will reserve low memory for CMA and fix
the issue on LS1021A.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1021A
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1012A
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The default value of CONFIG_SYS_MALLOC_F_LEN (0x400)
leaves U-Boot with not enough memory to load i2c driver
before relocate, causing it to hang.
Change the default value of CONFIG_SYS_MALLOC_F_LEN
for below SoCs,
- LS1012A
- LS1021A
- LS1043A
- LS1046A
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This adds DM_FLAG_PRE_RELOC flag to probe i2c driver
before relocation
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Fix below SPL build error when DM_I2C is enabled,
- arch/arm/cpu/armv8/built-in.o: In function `board_init_f:
arch/arm/cpu/armv8/fsl-layerscape/spl.c:74: undefined reference to `i2c_init_all'
arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:(.text.board_init_f+0x30):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`i2c_init_all'
make[2]: *** [spl/u-boot-spl] Error 1
make[1]: *** [spl/u-boot-spl] Error 2
make: *** [sub-make] Error 2
arch/arm/cpu/armv8/fsl-layerscape/spl.c: In function 'board_init_f':
arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:2: warning: implicit
declaration of function 'i2c_init_all'; did you mean 'misc_init_r'?
[-Wimplicit-function-declaration]`
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable FSPI controller support. So, flash environment can now be used
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Sync the interrupt properties with the ones from Linux. Also use the
constants provided by the dt-bindings header. Please note, that there
are actual changes/fixes in the irq flags. U-Boot won't use the
interrupt properties anyway. It's just to be consistent with the Linux
device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Azure is moving to remove the vs2015-win2012r2 platform build host. The
two suggested new platforms to use are vs2017-win2016 and windows-2019.
For now, move up to vs2017-win2016.
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Fix the following in intel_gpio_get_value():
* The value of the register is contained in the variable 'reg', not in
'mode'. The variable 'mode' contains only the configuration whether
the gpio is currently an input or an output.
* The correct bitmasks for the input and output value are
PAD_CFG0_RX_STATE and PAD_CFG0_TX_STATE.
Use them instead of the currently used PAD_CFG0_RX_STATE_BIT and
PAD_CFG0_TX_STATE_BIT.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add missing 'PAD_CFG0_TX_STATE' to the clear mask for pcr_clrsetbits32().
Otherwise this bit cannot be cleared again after it has been set once.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The function pcr_clrsetbits32() expects a device with a P2SB parent
device. In intel_gpio_direction_output() and intel_gpio_set_value()
the device 'dev' is passed to pcr_clrsetbits32(), which is a
gpio-controller with a device 'pinctrl' as parent. This does not match
the expectations of pcr_clrsetbits32(). But the 'pinctrl' device has a
P2SB as parent.
Pass the 'pinctrl' device instead of the 'dev' device to
pcr_clrsetbits32().
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so
remove the apl-prefix of the implemented functions/structures/...
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so
move it to a common location within arch/x86.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: conditionally build itss.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The watchdog timer value was never updated in the hardware by this
driver, so the watchdog triggered on some random stale value that
was left in the hardware. The TI SPRUH37C says, quote:
20.4.3.9 Modifying Timer Count/Load Values and Prescaler Setting
...
After a write access, the load register value and prescaler ratio
registers are updated immediately, but new values are considered
only after the next consecutive counter overflow or after a new
trigger command (the WDT_WTGR register).
This means at least one trigger must happen. The driver probably
depended on someone calling it's .reset() callback, however that
is not guaranteed e.g. if the WDT operates without servicing.
Add this missing trigger.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add "ti,keystone-gpio" compatible so as be able to use Linux DT files as
is.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Fix below compiler warning for 64bit builds
drivers/gpio/da8xx_gpio.c: In function ‘davinci_get_gpio_bank’:
drivers/gpio/da8xx_gpio.c:446:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
return (struct davinci_gpio *)addr;
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
IO expanders are required to power cycle SD card. So enable the same
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
J721e SoC has 2 I2C instances in MCU domain and 7 I2C instances in main
domain. Add DT nodes for the same
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
J721e EVM has a TCA6424 IO expander that has 24 GPIOs. Add support for
the same
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable DFU, Fastboot and USB mass storage gadget related configs
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable USB Gadget for R5 SPL, A72 SPL and A72 U-Boot to support DFU boot
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Increase R5 SPL early malloc memory pool by ~7K to accommodate SPL USB
DFU boot requirements
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable USB0 in peripheral mode so that it be used for DFU
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add support to download SYSFW into internal RAM via DFU in DFU boot
mode. Prepare a DFU config entity entry dynamically using buffer address
allocated for SYSFW and start DFU gadget to get SYSFW.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
J721e does not support USB Host MSC boot, but only supports DFU boot.
Since BOOT_DEVICE_USB is often used for host boot mode and
BOOT_DEVICE_DFU is used for DFU boot, rename BOOT_DEVICE_USB macro to
BOOT_DEVICE_DFU
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The current environment offset overlaps with the sysfw area and whenever
environment is saved in the redundant slot, it overwrites sysfw.itb. Fix
the offset to prevent this.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Changes:
- use boot.img instead of boot_fit.img
- use .dtb from boot.img v2
- implement recovery boot
- always boot ramdisk from boot.img, we can't mount system as root
now, as system is a logical partition inside of super partition
- don't add "skip_initramfs" to cmdline anymore
- to boot into recovery, use boot image from recovery partition
- prepare partition table:
- A/B scheme
- use 'super' partition instead of 'system' and 'vendor'
- add dtbo partitions
- introduce metadata partition
Not implemented: reading and applying dtbo blobs from dtbo partition.
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Unit test for 'abootimg' command. Right now it covers dtb/dtbo
functionality in Android Boot Image v2, which was added recently.
Running test:
$ ./test/py/test.py --bd sandbox --build -k test_abootimg
shows that 1/1 tests passes successfully.
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Convert Android documentation from regular txt format to Sphinx (RST).
Also add Android index.rst file and reference it in root index.rst, so
that Android documentation is visible.
Test:
$ make htmldocs
$ xdg-open doc/output/index.html
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Describe Android Boot Image format, how its support is implemented in
U-Boot and associated commands usage.
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This command can be used to extract fields and image payloads from
Android Boot Image. It can be used for example to implement boot flow
where dtb is taken from boot.img (as v2 incorporated dtb inside of
boot.img). Using this command, one can obtain needed dtb blob from
boot.img in scripting manner, and then apply needed dtbo's (from "dtbo"
partition) on top of that, providing then the resulting image to bootm
command in order to boot the Android.
Also right now this command has the sub-command to get an address and
size of recovery dtbo from recovery image (for non-A/B devices only,
see [1,2] for details).
It can be tested like this:
=> mmc dev 1
=> part start mmc 1 boot_a boot_start
=> part size mmc 1 boot_a boot_size
=> mmc read $loadaddr $boot_start $boot_size
=> abootimg get ver
=> abootimg dump dtb
[1] https://source.android.com/devices/bootloader/boot-image-header
[2] https://source.android.com/devices/architecture/dto/partitions
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Android Boot Image v1 adds "Recovery DTB" field in image header and
associate payload in boot image itself [1]. Payload should be in
Android DTB/DTBO format [2]. That "Recovery DTB" area should be only
populated for non-A/B devices, and only in recovery image.
Add function to get an address and size of that payload. That function
can be further used e.g. in 'abootimg' command to provide the user a way
to get the address of recovery dtbo from U-Boot shell, which can be
further parsed using 'adtimg' command.
[1] https://source.android.com/devices/bootloader/boot-image-header
[2] https://source.android.com/devices/architecture/dto/partitions
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Android Boot Image v2 adds "DTB" payload (and corresponding field in the
image header). Provide functions for its handling:
- android_image_get_dtb_by_index(): Obtain DTB blob from "DTB" part of
boot image, by blob's index
- android_image_print_dtb_contents(): Iterate over all DTB blobs in
"DTB" part of boot image and print those blobs info
"DTB" payload might be in one of the following formats:
1. concatenated DTB blobs
2. Android DTBO format
The latter requires "android-image-dt.c" functionality, so this commit
selects that file for building for CONFIG_ANDROID_BOOT_IMAGE option.
Right now this new functionality isn't used, but it can be used further.
As it's required to apply some specific dtbo blob(s) from "dtbo"
partition, we can't automate this process inside of "bootm" command. But
we can do next:
- come up with some new command like "abootimg" to extract dtb blob
from boot image (using functions from this patch)
- extract desired dtbo blobs from "dtbo" partition using "adtimg"
command
- merge dtbo blobs into dtb blob using "fdt apply" command
- pass resulting dtb blob into bootm command in order to boot the
Android kernel with Android ramdisk from boot image
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The code in this file is not specific to Apollo Lake. According to
coreboot sources (where this code comes from), it is common to at least:
* Apollo Lake
* Cannon Lake
* Ice Lake
* Skylake
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When ich_spi_exec_op_hwseq() is called to erase a 4k block
(opcode = SPINOR_OP_BE_4K), it expects to find a length value in
op->data.nbytes, but that value is always 0. As a result, the while loop
is never executed and no erase is carried out.
Fix this by dropping the loop code entirely, only keeping the relevant
parts of the loop body.
See http://patchwork.ozlabs.org/patch/1222779/ for more detailed
background information and discussion.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
SFI is quite poor and useless resource provider. Moreover it makes hard
to develop and extend functionality in the Linux kernel.
Enable a necessary minimum to use ACPI on Intel Edison.
Linux kernel have been prepared for this change since v5.4, where the last
crucial driver, i.e. for Basin Cove PMIC, has been submitted.
Note, that stock image won't suffer by this change since it doesn't have
ACPI enabled on the kernel level.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use valid restructured text to avoid warnings like
WARNING: Title underline too short.
WARNING: Block quote ends without a blank line; unexpected unindent.
when building with `make htmldocs`.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The fs segment is only used to get the global data pointer.
If it is accessed beyond sizeof(new_gd->arch.gd_addr), it is a bug.
To specify the byte-granule limit size, drop the G bit, so the
flag field is 0x8093 instead of 0xc093, and set the limit field
to sizeof(new_gd->arch.gd_addr) - 1.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed the comments about FS segement]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
I do not know why the boot code immediately after the system reset
should write-back the cache content. I think the cache invalidation
should be enough.
I tested this commit with qemu-x86_defconfig, and it worked for me.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Now, Slim Bootloader uses NS16550_DYNAMIC to support serial port
configuration at runtime, so no more code change is required.
Therefore, remove unnecessary steps and fix minor typo.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Slim Bootloader provides serial port info in its HOB to support
both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32
or SYS_NS16550_PORT_MAPPED in U-Boot.
To support both serial port configurations dynamically at runtime,
Slim Bootloader serial driver leverages NS16550_DYNAMIC.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove the obsolete comments for data->type]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Use this UART to improve the compatibility of U-Boot when used as a
coreboot payload.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Coreboot can provide information about the serial device in use on a
platform. Add a driver that uses this information to produce a working
UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since mid 2016, coreboot has additional fields in the serial struct that
it passes down to U-Boot. Add these so we are in sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this driver uses an assortment of CONFIG options to control
how it accesses the hardware. This is painful for platforms that are
supposed to be controlled by a device tree or a previous-stage bootloader.
Add a new CONFIG option to enable fully dynamic configuration. This
controls register spacing, size, offset and endianness.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
In Cyclone 5 SoC platform, the first USB probing is failed but second
probing is success. DWC2 USB driver read gsnpsid register right after
de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
Polling reset status after de-assert reset to solve the issue.
Retry with this fix more than 10 times without issue.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add a new option to enable the DROP_FFS flag when flashing UBI images to
NAND in order to drop trailing all-0xff pages.
This is similar to the existing FASTBOOT_FLASH_NAND_TRIMFFS option.
Signed-off-by: Guillermo Rodriguez <guille.rodriguez@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
Invalidate dcache line before accessing Setup Packet contents. Otherwise
driver will see stale content on non coherent architecture.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
UniPhier SoC updates for v2020.04 (2nd)
Denali NAND driver changes:
- Set up more registers in denali-spl for SOCFPGA
- Make clocks optional
- Do not assert reset signals in the remove hook
- associate SPARE_AREA_SKIP_BYTES with DT compatible
- switch to UCLASS_MTD
UniPhier platform changes:
- fix a bug in dram_init()
- specify loadaddr for "source" command
If the "source" command is not given the address, it uses
CONFIG_SYS_LOAD_ADDR, which is compile-time determined.
Using the "loadaddr" environment variable is handier because it is
relocated according to the memory base when CONFIG_POSITION_INDEPENDENT
is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
gd->ram_base is not set at all if the end address of the DRAM ch0
exceeds the 4GB limit.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
UCLASS_MTD is a better fit for NAND drivers.
Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile
drivers/mtd/mtd-uclass.c
Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig
of this platform enables NAND_DENALI_DT.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Now that the reset controlling of the Denali NAND driver (denali_dt.c)
works for this platform, remove the adhoc reset deassert code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, the denali NAND driver in U-Boot configures the
SPARE_AREA_SKIP_BYTES based on the CONFIG option.
Recently, Linux kernel merged a patch that associates the proper
value for this register with the DT compatible string.
Do likewise in U-Boot too.
The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
When the reset signal is de-asserted, the HW-controlled bootstrap
starts running unless it is disabled in the SoC integration.
It issues some commands to detect a NAND chip, and sets up registers
automatically. Until this process finishes, software should avoid
any register access.
Without this delay function, some of UniPhier boards hangs up while
executing nand_scan_ident(). (denali_read_byte() is blocked)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Denali NAND driver in mainline Linux currently cannot deassert the
reset. The upcoming Linux 5.6 will support the reset controlling, and
also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in
the future kernel will work without relying on any bootloader or firmware.
However, we still need to take care of stable kernel versions for a while.
U-boot should not assert the reset of this controller.
Fixes: ed784ac382 ("mtd: rawnand: denali: add reset handling")
Signed-off-by: Marek Vasut <marex@denx.de>
[yamada.masahiro: reword the commit description]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The "nand_x" and "ecc" clocks are currently optional. Make the core
clock optional in the same way. This will allow platforms with no clock
driver support to use this driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
On Altera SoCFPGA, upon either cold-boot or power-on reset, the
Denali NAND IP is initialized by the BootROM ; upon warm-reset,
the Denali NAND IP is NOT initialized by BootROM. In fact, upon
warm-reset, the SoCFPGA BootROM checks whether the SPL image in
on-chip RAM is valid and if so, completely skips re-loading the
SPL from the boot media.
This does sometimes lead to problems where the software left
the boot media in inconsistent state before warm-reset, and
because the BootROM does not reset the boot media, the boot
media is left in this inconsistent state, often until another
component attempts to access the boot media and fails with an
difficult to debug failure. To mitigate this problem, the SPL
on Altera SoCFPGA always resets all the IPs on the SoC early
on boot.
This results in a couple of register values, pre-programmed by
the BootROM, to be lost during this reset. To restore correct
operation of the IP on SoCFPGA, these values must be programmed
back into the controller by the driver. Note that on other SoCs
which do not use the HW-controlled bootstrap, more registers
may have to be programmed.
This also aligns the SPL behavior with the full Denali NAND
driver, which sets these values in denali_hw_init().
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since commit e1910d93b8 ("doc: driver-model: Convert MIGRATION.txt to
reST") MIGRATION.txt has been converted to migration.rst, so update
the Makefile references accordingly.
Fixes: e1910d93b8 ("doc: driver-model: Convert MIGRATION.txt to reST")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
In upstream libfdt, 6dcb8ba4 "libfdt: Add helpers for accessing
unaligned words" introduced changes to support unaligned reads for ARM
platforms and 11738cf01f15 "libfdt: Don't use memcpy to handle unaligned
reads on ARM" improved the performance of these helpers.
In practice however, this only occurs when the user has forced the
device tree to be placed in memory in a non-aligned way, which in turn
violates both our rules and the Linux Kernel rules for how things must
reside in memory to function.
This "in practice" part is important as handling these other cases adds
visible (1 second or more) delay to boot in what would be considered the
fast path of the code.
Cc: Patrice CHOTARD <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Link: https://www.spinics.net/lists/devicetree-compiler/msg02972.html
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Coreutils command nproc can be used on Linux and BSD to count the number of
available CPU cores. Use this instead of relying on the parsing of the
Linux specific proc file system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This removes the arch-specific checks for "checkcpu" function from the init
sequence. Make "checkcpu" generic and provide a weak nop stub instead.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
New analysis by the tool has shown that we have some cases where we
weren't handling the error exit condition correctly. When we ran into
the ENOMEM case we wouldn't exit the function and thus incorrect things
could happen. Rework the unwinding such that we don't need a helper
function now and free what we may have allocated.
Fixes: 18030d04d2 ("GPT: fix memory leaks identified by Coverity")
Reported-by: Coverity (CID: 275475, 275476)
Cc: Alison Chaiken <alison@she-devel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Jordy <jordy@simplyhacker.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This enables readning the cpuid from e-fuse, and deriving a static
MAC address from it.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip use CONFIG_SPL_OPTEE for OPTEE support, which is load and run
before U-Boot, but not use CONFIG_OPTEE which is after U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
No need to do twice data training for rk3328 ddr sdram, we re-use the
setting for both channel. And adjust the sdram_init properly for correct
init flow.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Rockchip has documentation file, doc/README.rockchip but
which is not so readable to add or understand the existing
contents. Even the format that support is legacy readme
in U-Boot.
Add rockchip specific documentation file using new rst
format, which describes the information about Rockchip
supported boards and it's usage steps.
Added minimal information about rk3288, rk3328, rk3368
and rk3399 boards and usage. This would indeed updated
further based on the requirements and updates.
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
All rockchip platforms support TPL or SPL-based bootloader
in mainline with U-Boot proper as final stage. For each
stage we need to burn the image on to flash with respective
offsets.
This patch creates a single boot image component using
- binman, for arm32 rockchip platforms
- pad_cat, for arm64 rockchip platforms.
This would help users to get rid of burning different
boot stage images.
The new image called 'u-boot-rockchip.bin'
which can burn into flash like:
₹ sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64
This would support all rockchip platforms, except rk3128
since it doesn't support for SPL yet.
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add U-Boot specific dtsi file for rk3188 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3188.
Right now, the file is empty, will add required changes
in future patches.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add U-Boot specific dtsi file for rk3036 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3036.
Right now, the file is empty, will add required changes
in future patches.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add SPL-alone mkimage tooling support via Makefile for
few platforms or boards used in rockchip family.
With this users would get rid of explicitly creating
mkimage tool for rockchip rksd or rkspi boot modes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Most of the platforms uses the platform type on their boot
stage image naming conventions in makefile like,
u-boot-x86-start16-tpl.bin - x86 start16 TPL bin
u-boot-spl-mtk.bin - Mediatek SPL bin
This would help to understand the users to what that
particular image belongs to? and less confused.
On that note, suffix platform type rockchip for existing
u-boot-tpl.img so now it become u-boot-tpl-rockchip.bin
Also, bin is more conventional way to include it on tools
like binman, pad_cat etc in future patches.
Note: usage of platform type doesn't follow consistent order
as of now.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add rockchip image type support. right now the image
type marked with rksd, So create image type variable
with required image type like rksd or rkspi.
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add bootcount support for Rockchip rk3399.
The bootcount value is preserved in PMU_SYS_REG0 register,
this would help to support redundent boot.
Once the redundant boot triggers, the altboot command
will look for extlinux-rollback.conf on particular
bootable partition which supposed to be a recovery
partition where redundant boot required.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add cpu reset cause in common cpu-info file.
This would help to print the reset cause for
various resets.
Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.
So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add cpu information for rockchip soc.
This would help to print the SoC family number, with
associated temparature, clock and reason for reset etc.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Sync the ROC-RK3399-PC device tree changes from Linux
with below commit details:
commit <c36308abe4110e4db362d5e2ae3797834a7b1192> ("arm64: dts:
rockchip: Enable MTD Flash on rk3399-roc-pc")
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Most of the SPI flash devices in rockchip are 16MiB size.
So, keeping U-Boot proper offset start from 128MiB with 1MiB
size and then start env of 8KiB would be a compatible location
between all variants of flash sizes.
This patch add env start from 0x14000 with a size of 8KiB.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip do support SPI flash as well, so there is
a possibility of using flash environment for those
use cases.
So, restrict the current env offset, size for MMC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rk3399 do support SPI flash as well, so there is
a possibility of using flash environment for those
usecases.
So define env device for MMC only when it is used
by specific configuration.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In the RK3399 DRAM driver, the function set_ds_odt() supports operating
in two different modes, selected by the ctl_phy_reg argument: when true,
the function reads and writes directly from the DRAM registers, accessed
through "chan->pctl->denali_*"; when false, the function reads and
writes from an array, accessed through "params->pctl_regs.denali_*",
which is written to DRAM registers at a later time.
However, phy_config_io(), which is called by set_ds_odt() to do a subset
of its register operations, operates directly on DRAM registers at all
times. This means that it reads incorrect values (and writes new values
prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by
passing in the address of the registers to work with.
This prevents an "Invalid DRV value" error in the SPL debug log and
(presumably) results in a more correct end state. See the following logs
from a RK3399 NanoPi M4 board (4GB LPDDR3):
Before:
sdram_init() Starting SDRAM initialization...
phy_io_config() Invalid DRV value.
phy_io_config() Invalid DRV value.
sdram_init() sdram_init: data trained for rank 2, ch 0
phy_io_config() Invalid DRV value.
phy_io_config() Invalid DRV value.
sdram_init() sdram_init: data trained for rank 2, ch 1
Channel 0: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
sdram_init() Finish SDRAM initialization...
After:
sdram_init() Starting SDRAM initialization...
sdram_init() sdram_init: data trained for rank 2, ch 0
sdram_init() sdram_init: data trained for rank 2, ch 1
Channel 0: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
sdram_init() Finish SDRAM initialization...
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Raspberry Pi 4 SoC features an integrated Gigabit Ethernet
controller, connected as a platform device.
Enable the new driver in the three applicable defconfigs, to allow
TFTP booting on the board.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
[Andre: Add joined and 32-bit configs]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Some of the devices(for instance, pcie and gnet controller) sitting on
SCB bus falls behind/below the memory range that we currenty have.
This patch updates the memory range to map those devices correctly.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs
and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4.
There is no publicly available documentation, so this driver is based
on the Linux driver. Compared to that the queue management is
drastically simplified, also we only support version 5 of the IP and
RGMII connections between MAC and PHY, as used on the RPi4.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: heavy cleanup and a few fixes]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Enable support for DFU over USB. This requires to enable USB gadget,
DWC2 UDC OTG driver and DFU command. DFU entities are defined for the
following firmware objects: u-boot.bin, uboot.env, config.txt, and
zImage/Image.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Broadcom 2835 SoC requires special conversion of physical memory addresses
for DMA purpose, so add needed wrappers to dwc2_udc_otg driver. Also extend
the list of compatible devices with 'brcm,bcm2835-usb' entry. This allows
to use USB gadget drivers (i.e. DFU) on Raspberry Pi4 boards.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Add support for operations on files larger than
CONFIG_SYS_DFU_MAX_FILE_SIZE. The buffered io mechanism is still used for
aggregating io requests, so for files up to CONFIG_SYS_DFU_MAX_FILE_SIZE
nothing is changed and they will be handled in a single filesystem call.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Rename functions for bufferred file io operations to make them easier to
understand. Also add missing file offset argument to them (currently
unused). All this is a preparation to remove predefined file size limit
(CONFIG_SYS_DFU_MAX_FILE_SIZE) for DFU read/write operations.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
i2c changes for 2020.04
- updates the Designware I2C driver
- get timings from device tree
- handle units in nanoseconds
- make sure that the requested bus speed is not exceeded
- few smaller clean-ups
- adds enums for i2c speed and update drivers which use them
- global_data: remove unused mxc_i2c specific field
Some PMICs (such as the DA9063) have non-contiguous register maps.
Attempting to read the non implemented registers returns an error
rather than a dummy value which causes 'pmic dump' to terminate
prematurely.
Fix this by allowing the PMIC driver to return -ENODATA for such
registers, which will then be displayed as '--' by pmic dump.
Use a single error code rather than any error code so that
we can distinguish between a hardware failure reading the PMIC
and a non implemented register known to the driver.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Add a driver for the regulators in the the DA9063 PMIC.
Robert Beckett: move regulator modes to header so board code can set
modes. Correct mode mask used in ldo_set_mode.
Add an option CONFIG_SPL_DM_REGULATOR_DA9063.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
This adds the basic register access operations and child regulator
binding (if a regulator driver exists).
Robert Beckett: simplify accesses by using bottom bit of address as
offset overflow. This avoids the need to track which page we are on.
Add an option CONFIG_SPL_DM_PMIC_DA9063.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
The 3-bit "command", or register, is encoded within the device address.
Configure the device accordingly, and pass command in DM I2C read/write
calls correctly.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
If we didn't unbind the sata from block device, the same devices would
be added after sata remove,
This patch is to resolve this issue as below:
=> sata info
SATA#0:
(3.0 Gbps)
SATA#1:
(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY30
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX30
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
=> sata stop
=> sata info
SATA#0:
(3.0 Gbps)
SATA#1:
(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 2: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 3: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This can be used for device tree size reduction similar as
CONFIG_OF_SPL_REMOVE_PROPS option. Some boards must pass the
built-in DTB unchanged to the kernel, thus we may not cut it
down unconditionally. Therefore enable the property removal
list option only if CONFIG_OF_DTB_PROPS_REMOVE is selected.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
XOM pins provide information for iROM bootloader about the boot device.
Those pins are mapped to lower bits of OP_MODE register (0x10000008),
which is common for all Exynos SoC variants. Set the default MMC device id
to reflect the boot device selected by XOM[7:5] pins (2 for the SD or 0 for
the eMMC).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for Direct Access Controller mode of Cadence QSPI. This
allows MMIO access to SPI NOR flash providing better read performance.
Direct mode is only exercised if AHB window size is greater than 8MB.
Support for flash address remapping is also not supported at the moment
and can be added in future.
For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Current Cadence QSPI driver has few limitations. It assumes all read
operations to be in Quad mode and thus does not support SFDP parsing.
Also, adding support for new mode such as Octal mode would not be
possible with current configuration. Therefore move the driver over to spi-mem
framework. This has added advantage that driver can be used to support
SPI NAND memories too.
Hence, move driver over to new spi-mem APIs.
Please note that this gets rid of mode bit setting done when
CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
that config option.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Make sure corresponding setup registers are updated depending on CS.
This ensures that driver can support QSPI flashes on ChipSelects other
than on CS0
Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The SPI stack relies on a proper bus speed/mode configuration
by calling dm_spi_claim_bus(). However the hitherto code
allowed to accidentally override those settings in
the spi_get_bus_and_cs() routine.
The initially established speed could be discarded by using
the slave platdata, which turned out to be an issue on
the platforms whose slave maximum supported frequency
is not on par with the maximum frequency of the bus controller.
This patch fixes above issue by configuring the bus from
spi_get_bus_and_cs() only in case it was not done before.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
The 'sspi' command hard-coded 1 MHz bus frequency for all transmissions.
Allow changing that at runtime by specifying '@freq' bus frequency in Hz.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Per sandbox_cs_info(), sandbox spi controller only supports chip
select 0. Current test case tries to locate devices on chip select
1, and any call to spi_get_bus_and_cs() or spi_cs_info() with cs
number 1 should not return 0.
This updates the test case to handle it correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.
The port was straightforward:
- remove the interrupt handling and the completion by busy polling the
controller
- remove locks
- move the setup of the memory windows into claim_bus()
- move the setup of the speed into set_speed()
- port the device tree bindings from the original fspi_probe() to
ofdata_to_platdata()
There were only some style change fixes, no change in any logic. For
example, there are busy loops where the return code is not handled
correctly, eg. only prints a warning with WARN_ON(). This port
intentionally left most functions unchanged to ease future bugfixes.
This was tested on a custom LS1028A board. Because the LS1028A doesn't
have proper clock framework support, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Move some of the code currently in the ofdata_to_platdata() method to
probe() so that it is not executed when generating ACPI tables.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to be able to calculate the speed separately from actually setting
the speed, so we can generate the required ACPI tables. Split out the
calculation into its own function.
Drop the double underscore on __dw_i2c_set_bus_speed while we are here.
That is reserved for compiler internals.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is used to store the speed information for a bus. We want to provide
this to ACPI so that it can tell the kernel. Move this struct to the
header file so it can be accessed by the ACPI i2c implementation being
added later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Convert the obvious uses of i2c bus speeds to use the enum.
Use livetree access for code changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Update this driver to use the new standard enums for speed.
Note: This driver needs to move to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Update this driver to use the new standard enums for speed.
Note: This driver needs to move to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some drivers define their own speed enums and use their own constants for
speed. It makes sense to have a unified defition of the different speeds.
Since many controllers have to do different things for fast/high speed, it
is a good idea to have an enum for the mode.
Add these as well as an enum for the address mode.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some versions of this peripheral include a spike-suppression phase of the
bus. Add support for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
At present the driver can end up with timing parameters which are slightly
faster than those expected. It is possible to optimise the parameters to
get the best possible result.
Create a new function to handle the timing calculation. This uses a table
of defaults for each speed mode rather than writing it in code.
The function works by calculating the 'period' of each bit on the bus in
terms of the input clock to the controller (IC_CLK). It makes sure that
the constraints are met and that the different components of that period
add up correctly.
This code was taken from coreboot which has ended up with this same
driver, but now in a much-different form.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Create a struct to hold the three timing parameters. This will make it
easier to move these calculations into a separate function in a later
patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Instead of passing this parameter into __dw_i2c_set_bus_speed(), pass in
the driver's private data, from which the function can obtain that
information. This allows the function to have access to the full state of
the driver.
Signed-off-by: Sicomp_param1mon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
The i2c controller defines a few timing properties. Read these in and
store them for use by the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
At present the driver uses an approximation for the bus clock, e.g. 166MHz
instead of 166 2/3 MHz.
This can result in small errors in the resulting I2C speed, perhaps 0.5%
or so.
Adjust the existing code to start from the accurate figure, even if later
rounding reduces this accuracy.
Update the bus speed code to work in KHz instead of MHz, which removes
most of the error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Group these #defines into an enum to make it easier to understand the
relationship between them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some SoCs support a higher speed than what is currently called 'max' in
this driver. Rename it to 'high' speed, which is the official name of the
3.4MHz speed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
We use struct clk here so really should include this header file to avoid
build errors. Also switch the order of clk.h in the C file to match the
required code style.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
If a different input clock is required then the correct way to do this is
with a clock driver. Don't allow boards to override IC_CLK.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some versions of this peripherals provide more control of the bus
behaviour. Add definitions for these registers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Since frac_pll_init() is only used in this file, change it to 'static'.
This fixes the following sparse warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:662:5: warning: no previous
prototype for ‘frac_pll_init’ [-Wmissing-prototypes]
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Function sscg_pll_init() is not used anywhere, so it can simply be deleted.
This was found because of the following sparse
warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:702:5: warning: no previous prototype for ‘sscg_pll_init’ [-Wmissing-prototypes]
int sscg_pll_init(u32 pll)
^~~~~~~~~~~~~
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Since do_imx8m_showclocks() is only used inside this file, make it 'static'.
This fixes the following sparse warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:836:5: warning: no previous prototype
for ‘do_imx8m_showclocks’ [-Wmissing-prototypes]
int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
^~~~~~~~~~~~~~~~~~~
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Function init_usb_clk() is not used anywhere, so it can simply be deleted.
This was detected by the following sparse warning:
arch/arm/mach-imx/imx8m/clock_imx8mq.c:377:6: warning: no previous prototype
for ‘init_usb_clk’ [-Wmissing-prototypes]
void init_usb_clk(void)
^~~~~~~~~~~~
Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Guard 'mfd==0' to prevent 'divide by zero' issue in
clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd
should never be 0 at all.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
m68k needs block cache list initialized after relocation.
Other architectures must not be involved.
Fixing regression related to:
commit 1526bcce0f
("common: add blkcache init")
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
This function parameter usage of load_addr was incorrectly caught in
the clarifying renames of commit bb872dd930, which results in boot
failures on Marvell A38x.
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Patch-to: Simon Glass <sjg@chromium.org>
Orange Pi Win has gigabit ethernet port, but default U-Boot
configuration for that board enabled ethernet driver but
didn't enable realtek phy.
Fix that.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Since commit 067e0b9684 ("sunxi: Allow booting from 128KB SD/eMMC offset")
we support having the SPL loaded from either the traditional 8KB SD
card/eMMC offset, or from the alternative location at 128KB. However the
sector to find the U-Boot image was still hard-coded at compile time,
and had to be adjusted for one of the two choices.
Since we can actually override the function to return the sector offset,
we can just check the boot source byte there to select the proper offset
based on from where the SPL was loaded.
This allows the very same binary image to be loaded from either 128KB or
8KB, with the U-Boot proper image always being located just behind the SPL.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
The Boot ROM write some boot source ID (SD card, eMMC, SPI, ...) into
a certain location in SRAM, so the SPL can easily determine where to
load U-Boot proper from.
Factor out reading this value, as it will come in handy again shortly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
clk_get_by_name() requires clk_get_by_id() that is not available if
CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else
condition of #if CONFIG_IS_ENABLED(OF_PLATDATA).
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.
This commit change the return type of mtk_clk_find_parent_rate to
ulong.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
This patch adds a prototype for the weak function
board_mtdparts_default().
It solves one warning when compiling with W=1 on stm32mp1 board:
board/st/stm32mp1/stm32mp1.c:
warning: no previous prototype for 'board_mtdparts_default'
[-Wmissing-prototypes]
void board_mtdparts_default(const char **mtdids,
const char **mtdparts)
^~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The blkcache_read() routine returns 1 (true) to indicate that a block was
found in the cache and returned, or 0 if not.
Signed-off-by: Eric Nelson <eric@nelint.com>
There is a typo in meerkat96 MAINTAINERS email address. Fix it.
Reported-by: Carl Gelfand <carl@novtech.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
On m68k, block_cache list is relocated, but next and prev list
pointers are not adjusted to the relocated struct list_head address,
so the first iteration over the block_cache list hangs.
This patch initializes the block_cache list after relocation.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Now that arch specific dma mapping APIs take care of cache
flush/invalidate, drop local cache flush operation.
While at that fix dma_unmap_single() call to match new prototype
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Subsystems such as USB expect dma_map_single() and dma_unmap_single() to
do dcache flush/invalidate operations as required. For example, see
see drivers/usb/gadget/udc/udc-core.c::usb_gadget_map_request().
Currently drivers do this locally, (see drivers/usb/dwc3/ep0.c,
drivers/mtd/nand/raw/denali.c etc..)
Update arch specific dma_map_single() and dma_unmap_single() APIs to do
cache flush/invalidate operations, so that drivers need not implement
them locally.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This patch includes the following:
1. Add fastboot command to erase the whole EMMC_USER
2. Add fastboot command to flash image at EMMC_BOOT1
3. Add fastboot command to erase the whole EMMC_BOOT1
4. Enale CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT for mt8518
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
Function mod_exp_sw() is only used via the operators of the uclass.
It is not defined in any include.
Make mod_exp_sw() static.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
drivers/rng/sandbox_rng.c requires rand() to be defined but configuration
option CONFIG_CONFIG_LIB_RAND selected in drivers/rng/Kconfig does not
exist.
test/lib/test_aes.c requires rand() to be defined.
Fix the selection criteria for choice "Pseudo-random library support type".
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
CONFIG_SPL_RSA is meant to control if lib/rsa/* is used for SPL. Adjust
lib/Makefile to consider this setting.
This was correctly setup with commit 51c14cd128 ("verified-boot: Minimal
support for booting U-Boot proper from SPL") and got lost with commit
089df18bfe ("lib: move hash CONFIG options to Kconfig").
Fixes: 089df18bfe ("lib: move hash CONFIG options to Kconfig")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The Libre Computer ALL-H5-CC board is an upgraded version of the
ALL-H3-CC. Changes include:
- Gigabit Ethernet via external RTL8211E Ethernet PHY
- 16 MiB SPI NOR flash memory
- PoE tap header
- Line out jack removed
Only H5 variant test samples were made available, and the vendor is not
certain whether other SoC variants would be made or not. Furthermore the
board is a minor upgrade compared to the ALL-H3-CC. Thus the device tree
simply includes the one for the ALL-H3-CC, and adds the changes on top.
The device tree was synced over from the Linux kernel, along with other
H3/H5 changes, in a previous patch. Thus only the defconfig and an entry
to the MAINTAINERS file is added.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[jagan: drop CONFIG_SYS_SPI_U_BOOT_OFFS]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The Libre Computer ALL-H3-IT board is a small single board computer that
is roughly the same size as the Raspberry Pi Zero, or around 20% smaller
than a credit card.
The board features:
- H2, H3, or H5 SoC from Allwinner
- 2 DDR3 DRAM chips
- Realtek RTL8821CU based WiFi module
- 128 Mbit SPI-NOR flash
- micro-SD card slot
- micro HDMI video output
- FPC connector for camera sensor module
- generic Raspberri-Pi style 40 pin GPIO header
- additional pin headers for extra USB host ports, ananlog audio and
IR receiver
Only H5 variant test samples were made available, but the vendor does
have plans to include at least an H3 variant. Thus the device tree is
split much like the ALL-H3-CC, with a common dtsi file for the board
design, and separate dts files including the common board file and the
SoC dtsi file. The other variants will be added as they are made
available.
The device tree was synced over from the Linux kernel, along with other
H3/H5 changes, in a previous patch. Thus only the defconfig and an entry
to the MAINTAINERS file is added.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[jagan: drop CONFIG_SYS_SPI_U_BOOT_OFFS]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
For Allwinner SoCs the CONFIG_SYS_SPI_U_BOOT_OFFS value is not really a
board choice: The boot ROM only loads the SPL from offset 0 of the SPI
NOR flash, and loads at most 32KB. This is a similar situation as on MMC,
so consequently we create our "joint" image (SPL + U-Boot proper) with
that 32KB offset during the build.
So define the value of this symbol to be 32KB by default for every
Allwinner SoC. This removes the definition of this symbol from the
_defconfig files, and avoids every board to define this over and over
again.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Now that the USB PHY on the Allwinner R40 SoC is supported, enable USB
support for the two R40 boards U-Boot supports.
For this we need to add the GPIO pin that powers the USB port(s), also
enable the usual suspects (OHCI/EHCI support).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Since every Allwinner USB PHY seems to be slightly different from each
other, we need to add the compatible string and the respective data
structure to make it work on the R40/V40 SoC.
Nothing spectacular this time, just one less USB controller than the H3.
Copied from the Linux kernel.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The M2 Berry features the normal Gigabit PHY connected to the SoC's MAC,
so enable the sun8i-emac driver to support Ethernet on the board.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Update the .dts file from the kernel, which carries much more nodes,
some of them we need to enable USB and Ethernet support for the board.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sync the device tree files and device tree header files from upstream
Linux kernel, as of 2020-01-08. The commit synced to in the sunxi repo
98d25b0b266d Merge branch 'sunxi/dt-for-5.6' into sunxi/for-next
which is also part of next-20200108.
Changes brought in include:
- cleanup of pinmux node names
- addition of Security ID, MBUS, CSI, crypto engine, video codec,
pmu, and thermal sensor device nodes for both SoCs
- addition of deinterlacing engine device node on H3
- cleanup of RTC device node and addition of its clocks
- various board cleanups and improvements
- removal of pinmux node for GPIO lines
- cpufreq / DVFS
- HDMI output
- UART-based Bluetooth
- audio codec
- USB ports
- new boards
Most of the changes don't concern U-boot.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This file doesn't include any declarations anymore but it does include
other headers. Update the header comment to mention this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not really a CONFIG since it is not intended to be set by boards.
Move it into the compiler header with other similar defines, and rename
it.
Signed-off-by: Simon Glass <sjg@chromium.org>
The kernel.h file has a number of useful macros including a few related
to structures. Move check_member() there too.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
This function has a very generic name which does not adequately describe
its purpose. Rename it and move it to image.h, since it relates to reading
a script from an image.
Signed-off-by: Simon Glass <sjg@chromium.org>
These global variables are quite short and generic. In fact the same name
is more often used locally for struct members and function arguments.
Add a image_ prefix to make them easier to distinguish.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function related to timer and most of the timer functions are in
time.h, so move this function there.
Signed-off-by: Simon Glass <sjg@chromium.org>
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is only used on ARM devices so does not belong in the global
common header file. Move it to an ARM header.
Signed-off-by: Simon Glass <sjg@chromium.org>
These functions relate to setting up the device tree for booting the OS.
The fdt_support.h header file supports similar functions, so move these
there.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is not called anywhere so we can drop the declaration. If
it is needed one day, it should be added in its own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
This only exists to control whether the post/ directory is build. It is
just as easy to check this in the Makefile. Remove CONFIG_HAS_POST and use
an ifdef in the Makefile instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
These CONFIG options are not used anymore. CONFIG_POST_ALT_LIST just
causes CONFIG_POST_STD_LIST to be set and it causes tests.c to be
compiled. So just make compiling tests.c unconditional.
Signed-off-by: Simon Glass <sjg@chromium.org>
This define seems better suited to the eeprom header file, particularly
as it is only used in the eeprom.c file.
Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is defined in exports.c so move it to its header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This is an init function so move it out of the common header. Avoid using
the typedef so that we don't have to include the global_data header file.
Also tidy up the function style in comments while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function belongs more in flash.h than common.h so move it.
Also remove the space before the bracket in some calls.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use realloc and update the loop executed in do_fdtgrep to find all
the regions: only test count > max_region after the second pass.
This patch solve an issue if the number of region found (count)
is greater then the default value (max_region = count = 100):
the second pass is never executed, because the loop stops after
the first pass (i = 0, count > 100, max_regions = 100)
with error -1 and the error message
"Internal error with fdtgrep_find_region".
I also update the error message.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add an arch-specific handoff header so that we can use the HANDOFF feature
on arm devices.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If baud_divisor is not set (i.e. == -1), we should use the baud divisor
already in use for flushing the xmit register. If we don't flush the
xmit register, then SPL will hang.
Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
This patch modify the loop in mtd erase command to erase one by one
the blocks in the requested area.
It solves issue on "mtd erase" command on nand with existing bad block,
the command is interrupted on the first bad block with the trace:
"Skipping bad block at 0xffffffffffffffff"
In MTD driver (nand/raw), when a bad block is present on the MTD
device, the erase_op.fail_addr is not updated and we have the initial
value MTD_FAIL_ADDR_UNKNOWN = (ULL)-1.
This case seems normal in nand_base.c:nand_erase_nand(),
we have the 2 exit cases during the loop:
1/ we have a bad block (nand_block_checkbad)
instr->state = MTD_ERASE_FAILED
loop interrupted (goto erase_exit)
2/ if block erase failed (status & NAND_STATUS_FAIL)
instr->state = MTD_ERASE_FAILED;
instr->fail_addr =
((loff_t)page << chip->page_shift);
loop interrupted (goto erase_exit)
So erase_op.fail_addr can't be used if bad blocks were present
in the erased area; we need to use mtd_erase only one block to detect
and skip these existing bad blocks (as it is done in nand_util.c).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Fix an issue where some sections are never loaded : if p_type is
different from PT_LOAD the phdr pointer must be incremented.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Suman Anna <s-anna@ti.com>
LS1028A QDS boards have a MDIO MUX and they require the driver for it for
PHYs to work.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
setexpr command is used while running secure boot
(chain of trust with confidentiality) feature.
Enable CONFIG_CMD_SETEXPR to enable setexpr command.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Fix loop in board_fix_fdt that erroneously increments the counter
in all cases whereas the counter should be incremented only if a
matching string has been found.
Fixes: 5d535aa40b ("board: fsl: lx2160a: implement board_fix_fdt")
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Exports the serdes configuration as an environment variable for LS gen 3
SoCs, so it can be used in u-boot command line. It should particularly
be useful for applying Linux DT overlays for the given serdes
configuration.
This code is called from arch_misc_init and not from the existing
serdes_init function because it depends on U-Boot environment being set
up.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Currently LS1028A board code uses arch_misc_init to set up the board mux
on QDS. Move this code to misc_init_r. This is consistent with LS gen 2
and T series SoCs/boards.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Currently LX2 board code uses arch_misc_init to set up the board mux on
RDB and QDS. Move this code to misc_init_r. This is consistent with LS
gen 2 and T series SoCs/boards.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list.
These protocols are supported and functional but they trigger a warning
in U-Boot console at boot because they are not on this list.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Separate MAC and serdes configuration, MAC configuration must be applied
at each enetc_start() as FLR clears it.
This restores traffic for ENETC interfaces in USXGMII mode.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The linux kernel Image is growing quite quickly,
if kernel Image size grow beyond 36 MB then
kernel Image at load address 0x81000000
overlaps with the reserved memory region
at 0x83400000.
Adjust kernel load address(kernel_addr_r) from
0x81000000 to 0x96000000 to avoid kernel Image
overlapping with reserved memory region.
This change fixes the below U-Boot error while
booting uncompressed kernel Image through booti command,
ERROR: reserving fdt memory region failed (addr=83400000 size=c00000)
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The linux kernel Image is growing quite quickly,
if kernel Image size grow beyond 36 MB then
kernel Image at load address 0x81000000
overlaps with the reserved memory region
at 0x83400000.
Adjust kernel load address(kernel_addr_r) from
0x81000000 to 0x96000000 to avoid kernel Image
overlapping with reserved memory region.
This change fixes the below U-Boot error while
booting uncompressed kernel Image through booti command,
ERROR: reserving fdt memory region failed (addr=83400000 size=c00000)
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
LS1088A has four personalities, LS1088A, LS1084A, LS1048A and LS1044A.
LS1044A, LS1048A are LS1088A personalities, which support only one
1x 10GE port.
MAC1 and MAC2 are associated with 1G SGMII, 2.5G SGMII, and XFI.
Disable MAC1 to have only one 1x 10GE port for LS1044A, LS1048A.
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
These config entries are inside the menu block, which already
depends on ARCH_LS1021A:
menu "LS102xA architecture"
depends on ARCH_LS1021A
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The dts node of the DSPI controller in kernel is spi instead of dspi,
it is not correct if use "/soc/dspi@" to fix up the status of the dts
in kernel, so, modify it to "/soc/spi@".
The DSPI2 and I2C5 are muxed, and the status of DSPI2 node in kernel dts
default value is okay, So set the status of DSPI2 node in kernel dts to
disabled if it is muxed as I2C5.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
lx2160a rev1 and rev2 SoC has different pcie controller.
The pcie controller device tree node fields "compatible"
and registers names needs to be updated accordingly.
Enable CONFIG_OF_BOARD_FIXUP to apply board_fix_fdt
which updates the "compatible" and registers names.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
lx2160a rev1 requires layerscape_gen4 device tree fixup and
lx2160a rev2 requires layerscape device tree fixup.
Add device tree fixup for lx2160a based on SoC and Version.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Move streamId allocation to layerscape common device tree fixup.
Calculate streamId based on SoC variant.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add Common device tree fixup for NXP SoCs. Based on
SoC and revision call pcie_layerscape or pcie_layerscape_gen4
fixup.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Program register bit of SCFG_SNPCNFGCR_USBRDSNP and
SCFG_SNPCNFGCR_USBWRSNP to drive USB read/write
snoop signal on LS1012A.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The LS1028A SoC is special in the handling of the MAC addresses. We need
to write to the IERB version of the PSIPMAR0/1 register. This value will
be sampled into the corresponding port PSIPMAR0/1 register if the PCI
memory access is enabled.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Intead of setting the MAC address in enetc_start() use the proper
write_hwaddr(). U-Boot takes care of the random MAC address, too.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
There is not any difference for disabling BARs in RC mode
between PCIe controllers with and without SRIOV.
Fixes: 80afc63fc3 ("pci: layerscape: add pci driver based on DM")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The software will still get non-zero Expansion ROM BAR size
even when the BAR_EN bit is cleared. The BAR_EN bit of
register EXP_ROM_BAR_MASK_RC is not working as expected,
so this patch changes to mask all the bits.
Fixes: 80afc63fc3 ("pci: layerscape: add pci driver based on DM")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable RTL8152, AX88179 and AX8817X USB network cards support
for ls1012afwry
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable RTL8152, AX88179 and AX8817X USB network cards support
for ls1088ardb
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable RTL8152, AX88179 and AX8817X USB network cards support
for ls1046afrwy
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Passes on the primary address used by u-boot to Linux. The code does a DT
fix-up for ENETC PFs and sets the primary MAC address in IERB. The address
in IERB is restored on ENETC PCI functions at FLR.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
div_by is a misleading parameter name, when we are doing >> div_by.
Rename it to right_shift.
Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
FIT image contents can be larger than default bootm limit 8M
with initrd. Raise limit to 64MB which is commonly used
elsewhere.
Signed-off-by: Dhananjay Phadke <dphadke@linux.microsoft.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds the possibility in both debug and ramfs modes to
optionally load an env file from /tftpboot/$tftppath (this is ignored if
not present, so the change is backward compatible). This gives the debug
and ramfs scripts the possibility to set uboot environment variables
that were previously asked the users to manually set (nfs path in debug
and rootfs size in ramfs).
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
CC: Tom Rini <trini@konsulko.com>
The tftppath was not set in case of run ramfs. It worked only by chance
if was already set before.
Also check the boardname before setting the tftppath for COGE5.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
CC: Tom Rini <trini@konsulko.com>
The CPUWD reset reason is used for kmp204x.
And the qrio cpu reset request is configured to operate in
core reset mode.
But for the evaluation of the qrio's reset reason register
the CPUWD figures as a unit reset source rather than a core
reset source. This patch defines the CPUWD reset as a core
reset source when evaluating the reset reason register.
Signed-off-by: Rainer Boschung <rainer.boschung@ch.abb.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
This patch moves the qrio and i2c deblocking code to
keymile/common as it will also be used by the upcoming CENT2 board.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
Take up maintainership of random number generator drivers with
Heinrich Schuchardt as the reviewer.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
When using fitImage in AARCH64, the fdt is only 4 byte aligned.
According to linux kernel -> Documentation/arm64/booting.txt, the
fdt *must* be 8 byte aligned. Therefore, it is somewhat random,
if you build a kernel that the fdt is 4 or 8 byte aligned.
Removing fdt_high (or changing it to a valid 8 byte aligned
address) solves this issue.
Signed-off-by: Matthias Schoepfer <matthias.schoepfer@ithinx.io>
CC: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
This add the initial support of the broadcom reference
board bcm968360bg with a bcm68360 SoC.
This board has 512 MB of RAM, 256 MB of flash (nand),
2 USB port, 1 UART, and 4 ethernet ports.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch bcm68360.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
In order to generate a bootable U-Boot binary for i.MX8QXP MEK
we need to run:
$ make imx8qxp_mek_defconfig
$ make flash.bin
The resultant flash.bin and flash.log are not removed after
running 'make mrproper'.
Include these files into the CLEAN_FILES list entry so that
they can be properly deleted after 'make mrproper'.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Use MMC0 for eMMC and MMC2 for SD-card as other Exynos-based boards do.
This allows to use common code to get MMC device id based on the XOM[7:5]
pins.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Card detect line for SD-card on Odroid U3/X2 boards are active low, so
add cd-inverted property to indicate this, as u-boot's GPIO driver doesn't
support specifying line polarity. This restores S5P_SDHCI driver operation
on Odroid U3/X2 boards.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Read generic MMC properties from device-tree. This allows to specify for
example cd-inverted property and let MMC core to properly handle such
case.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since commit 4213609cc7 ("drivers: core: use strcmp when find device by
name") one has to provide full name to get requested object. Fix the code
used to detect enable power regulators on the supported Exynos boards to
use proper PMIC device device name then.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since commit 4213609cc7 ("drivers: core: use strcmp when find device by
name") one has to provide full name to get requested object. Fix the code
used to detect Odroid board revision to use proper ADC device name then.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
u-boot uses the same DTS for the all Odroid XU3-based boards, so list
them in the model description to let user know that those boards are
supported.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Execute the command cls (for clear screen), when the "menu background"
keyword is present in extlinux.conf file, only if the command is supported.
This patch avoid the warning "Unknown command 'cls'"
with "menu background" in extlinux.conf when CONFIG_CMD_BMP is activated
and CONFIG_CMD_CLS not activated (default for CONFIG_DM_VIDEO).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Correct some function comments. Convert to Sphinx style.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Allow reading compressed content from fit image, even if
CONFIG_SPL_OS_BOOT is not set.
This allow booting compressed 2nd stage u-boot from fit image.
Additionally, do not print warning message if compression node is not
found, since it simply implies the content is uncompressed.
Signed-off-by: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The ST-Ericsson U8500 SoC has been used in mass-production for
some Android smartphones released around 2012.
In particular, Samsung has released more than 5 different
smartphones based on U8500, e.g.
- Samsung Galaxy S III mini (GT-I8190) "golden"
- Samsung Galaxy S Advance (GT-I9070) "janice"
- Samsung Galaxy Xcover 2 (GT-S7710) "skomer"
and a few others.
Mainline Linux has great support for the Ux500 SoC, so these
smartphones can also run Linux mainline quite well.
Unfortunately, the original Samsung bootloader used on these devices
has limitations that prevent booting Linux mainline directly.
It keeps the L2 cache enabled, which causes Linux to crash very early,
shortly after decompressing the kernel.
Using U-Boot allows to circumvent these limitations. We can let the
Samsung bootloader chain-load U-Boot and U-Boot locks the L2 cache
before booting into Linux. U-Boot has several other advantages
- it supports device-trees directly and we are no longer limited to
flashing Android boot images through Samsung's proprietary download
mode.
The Samsung "stemmy" board covers all Samsung devices based on U8500.
Add minimal support for "stemmy". For now only UART is supported but
this will be extended later.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Add myself as maintainer for ST-Ericsson U8500 SoC to MAINTAINERS.
Linus Walleij usually reviews all Ux500 related patches,
so add him as a reviewer.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
The NovaThor U8500 SoC was released by ST-Ericsson in 2011.
It was used for some development boards like the CALAO Systems
Snowball SBC, but mass production was primarily for Android
smartphones like the Samsung Galaxy S III mini.
Previous support for U8500 was removed in
commit 68282f55b8 ("arm: Remove unused ST-Ericsson u8500 arch")
since none of the boards were converted to generic boards
before the deadline.
The new code does not have much in common with the previous code.
I have completely rewritten everything, embracing the Driver Model
and device trees wherever possible.
The U8500 support is a bit more minimal for now - my primary
use case is to use U-Boot as alternative bootloader for some of the
U8500 Samsung smartphones. At the moment U-Boot is chain-loaded from
the original Samsung bootloader. A side effect of this is that we
can (temporarily) get away without implementing some functionality
- e.g. all clocks are already enabled by the original bootloader.
More functionality will be added in future patches.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
The Nomadik Multi Timer Unit (MTU) provides 4 decrementing
free-running timers. It is used in ST-Ericsson Ux500 SoCs.
The driver uses the first timer to implement UCLASS_TIMER.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
I'm also seeing the build failure that commit
7d4776545b env: solve compilation error in SPL
tried to fix, namely that the reference to env_flags_validate from
env_htab cannot be satisfied when flags.o is not built in. However,
that commit got reverted by
d90fc9c3de Revert "env: solve compilation error in SPL"
Necessary, but not sufficient conditions to see this are
CONFIG_SPL=y (obviously)
CONFIG_SPL_ENV_SUPPORT=n (so flags.o does not get compiled)
CONFIG_SPL_LIBCOMMON_SUPPORT=y (so env/built-in.o is part of the SPL link)
Now, these are satisfied for e.g. imx6q_logic_defconfig. But that
builds just fine, and spl/u-boot-spl.map lists .data.env_htab among
the discarded (garbage collected) sections. Yet, on our
mpc8309-derived board, we do see the build failure, so perhaps the
linker works a bit differently on ppc than on ARM, or there's yet some
other configuration option needed to observe the break.
This is another attempt at solving it, which also cleans up
env/Makefile a bit: Introduce a def_bool y symbol CONFIG_ENV_SUPPORT
which complements CONFIG_(SPL/TPL)_SUPPORT. Then use
CONFIG_$(SPL_TPL_)ENV_SUPPORT to decide whether to include the five
basic env/*.o files. For attr.o, flags.o and callback.o, this
shouldn't change anything. Also, common.o and env.o still get
unconditionally built for U-boot proper. But for TPL/SPL, those two
are only included if CONFIG_(SPL/TPL)_SUPPORT is set.
Having that symbol should also allow simplifying conditionals such as
#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
found in drivers/reset/reset-socfpga.c to just
CONFIG_IS_ENABLED(ENV_SUPPORT).
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Clearfog Base carrier uses serdes lane #5 as USB host. Use EEPROM stored
device identification to configure the serdes accordingly when
available.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Select the serdes configuration table based on the platform identity
read from EEPROM TLV data. Clearfog GTR needs a slightly different
serdes configuration.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Set the kernel device-tree file (fdtfile environment variable) based on
run-time detection of the platform.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Read RAM die capacity from the EEPROM TLV.
Follow the ONIE standard that defines the Vendor Extension entry type
for vendor specific data. We have no Private Enterprise Number at the
moment as the standard requires. Use the dummy all 0xff value for now.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Add support for read/write of ONIE "Tlvinfo" EEPROM data format. TLV
stands for Type-Length-Value. The data format is described here:
https://opencomputeproject.github.io/onie/design-spec/hw_requirements.html#board-eeprom-information-format
Based on U-Boot patch from the Open Compute project:
ec87e872d4/patches/u-boot/common/feature-sys-eeprom-tlv-common.patch
Keep only I2C EEPROM support. Use the generic eeprom driver. Fix
checkpatch issues.
Add support for multiple EEPROM TLV stores on the same system. This is
useful in case of SOM and carrier that both provide ID and hardware
configuration information.
Add option to enable for SPL. This allows selection of RAM configuration
based on EEPROM stored board identification.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Add device-tree description for the EEPROM devices on Armada 388 SOM rev
2.1.
Another EEPROM is now on Clearfog Pro carrier rev 2.2, and Clearfog Base
rev 1.3.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Enabled both DDR clock signals to support Clearfog variants (currently,
Clearfog GTR) that need both clocks.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
DDR clock out might be unrelated to the number of active chip-select.
For example, the board might have two DDR components, but only one
chip-select. The clk_enable mask allows the board to enable DDR clocks
regardless of active chip-selects.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
K3 J721E:
* DMA support.
* MMC and ADMA support.
* EEPROM support.
* J721e High Security EVM support.
* USB DT nodes
K3 AM654:
* Fixed boot due to pmic probe error.
* USB support and DT nodes.
* ADMA support
DRA7xx/AM57xx:
* BBAI board support
* Clean up of net platform code under board/ti
AM33/AM43/Davinci:
* Reduce SPL size for omap3 boards.
* SPL DT support for da850-lcdk
* PLL divider fix for AM335x
detail_board_ddr_info() is not used anywhere, so simply remove it.
This function is only used by Layerscape, not by i.MX.
This was detected by the following sparse warning:
board/toradex/colibri-imx8x/colibri-imx8x.c:104:6: warning: no previous
prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
detail_board_ddr_info() is not used anywhere, so simply remove it.
This function is only used by Layerscape, not by i.MX.
This was detected by the following sparse warning:
board/toradex/apalis-imx8/apalis-imx8.c:92:6: warning: no previous
prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
detail_board_ddr_info() is not used anywhere, so simply remove it.
This function is only used by Layerscape, not by i.MX.
This was detected by the following sparse warning:
board/freescale/imx8qxp_mek/imx8qxp_mek.c:115:6: warning: no previous
prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
detail_board_ddr_info() is not used anywhere, so simply remove it.
This function is only used by Layerscape, not by i.MX.
This was detected by the following sparse warning:
board/freescale/imx8qm_mek/imx8qm_mek.c:102:6: warning: no previous
prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes]
detail_board_ddr_info() is not used anywhere, so simply remove it.
This function is only used by Layerscape, not by i.MX.
This was detected by the following sparse warning:
board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c:110:6: warning: no previous
prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Reviewed-by: Oliver Graute <oliver.graute@kococonnector.com>
Include fdt_support.h header file to fix the following sparse warning:
board/freescale/imx8qm_mek/imx8qm_mek.c:116:5: warning: no previous
prototype for ‘ft_board_setup’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Include fdt_support.h header file to fix the following sparse warning:
board/freescale/imx8qxp_mek/imx8qxp_mek.c:129:5: warning: no previous
prototype for ‘ft_board_setup’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Add prototype to function spl_board_boot_device to fix the following
sparse warning:
board/freescale/imx8mm_evk/spl.c:26:5: warning: no previous prototype
for ‘spl_board_boot_device’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Functions spl_dram_init() and power_init_board() are used only in
the scope of this file, so make them static to fix the following sparse
warnings:
board/freescale/imx8mm_evk/spl.c:40:6: warning: no previous prototype
for ‘spl_dram_init’ [-Wmissing-prototypes]
board/freescale/imx8mm_evk/spl.c:85:5: warning: no previous prototype
for ‘power_init_board’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Functions fracpll_configure(), decode_intpll(), decode_fracpll(),
get_root_src_clk() and get_root_clk() are used only in the scope of this
file, so make them static to fix the following sparse warnings:
arch/arm/mach-imx/imx8m/clock_imx8mm.c:50:5: warning: no previous
prototype for ‘fracpll_configure’ [-Wmissing-prototypes]
arch/arm/mach-imx/imx8m/clock_imx8mm.c:271:5: warning: no previous
prototype for ‘decode_intpll’ [-Wmissing-prototypes]
arch/arm/mach-imx/imx8m/clock_imx8mm.c:418:5: warning: no previous
prototype for ‘decode_fracpll’ [-Wmissing-prototypes]
arch/arm/mach-imx/imx8m/clock_imx8mm.c:483:5: warning: no previous
prototype for ‘get_root_src_clk’ [-Wmissing-prototypes]
arch/arm/mach-imx/imx8m/clock_imx8mm.c:527:5: warning: no previous
prototype for ‘get_root_clk’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Add sys_proto.h header file to fix the following sparse warning:
board/freescale/imx8mm_evk/imx8mm_evk.c:59:5: warning: no previous
prototype for ‘board_mmc_get_env_dev’ [-Wmissing-prototypes]
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
The mux mode is embedded in the PAD definition and therefore there is
no need to repeat it in the PAD configuration value (more over since
this information will be masked out when the configuration value is
applied).
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The imx8mm doesn't require the hdmi firmware.
Update also the fw version.
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
With commit 0d52bab462 ("mx7dsabre: Enable DM_ETH")
Device Tree has been update and change pfuze3000 node
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
On SPL enabled systems, the current s_init code (wdog, clock and ldo
init) is executed twice (by SPL and u-boot). This is not necessary and
might lead to boot issues (ie, starting PMC1 when it is already running).
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Currently the following build warning is seen:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
===================================================
Since the mx7ulp-evk board does not have networking support, explicitly
disable networking.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Add iMX6ULL VisionSOM SoM and VisionCB-RT-STD evaluation board support.
The SoM has an iMX6ULL, 512 MiB of DRAM and microSD slot. The carrier
board has Ethernet, USB host port, USB OTG port.
Signed-off-by: Arkadiusz Karas <arkadiusz.karas@somlabs.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
The PFUZE100 and PFUZE200 PMICs can be discerned by bit 0 in DeviceID
register. Print the correct identification of the PMICs.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
Simplify the uSDHC4 eMMC controller setup. This is the only eMMC
present on the system and only controller that is used, so drop
the extra logic.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Add slack to the clock frequency parameters passed to firmware within
clk_set_rate. min-freq is changed to 0 and max-rate is changed to
ULONG_MAX. This fixes certain issues with pll clock rounding when the
firmware is not able to set the frequency exactly to the target, the
current implementation fails if the available frequency is even 1Hz off
the target. With the change, the firmware still tries its best to set
the frequency as close as possible to the target.
Reported-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable USB keyboard to be used as input device at U-Boot prompt. Both
serial and USB keyboard will be active inputs simultaneously.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable configs related to USB Host mode, Peripheral mode and DFU.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add env variables that set up dfu_alt_info for MMC/EMMC/OSPI. This
is required to allow update of firmware on these media.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add pinmux for USB1 and enable it as a peripheral port in U-Boot
specific dtsi since U-Boot does not support OTG.
Disable USB0 as its not available on the baseboard.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add support for USB0 and USB1 instances on the AM6 SoC.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM654 SoC has USB2 PHY which is similar to existing USB2 PHYs on OMAP
SoCs. Add support for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Below warning is seen when this driver is built for devices with 64 bit
physical address space.
drivers/phy/omap-usb2-phy.c: In function ‘omap_usb2_phy_probe’:
drivers/phy/omap-usb2-phy.c:187:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
priv->phy_base = (void *)base;
^
Fix this by using dev_read_addr_ptr() instead of dev_read_addr().
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM654 has DWC3 USB controller that is very similar to other TI SoCs. Add
a new compatible to enable the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
None of these boards boot, but the solution appears to be the same.
All the boards have SPL that is too large. With a few defconfig
options removed, these corresponding options can be removed from
their respective SPL dtb files.
This patch unifies the DM37/OMAP35 boards' -u-boot.dtsi files
to remove gpio's, i2c, bandgap, thermal zones, unneeded uarts, and
unneeded MMC nodes.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently the DM37 and OMAP35 boards do not boot due to SPL
bring too large.
SPL doesn't need GPIO, I2C nor MMC sector access since it uses
a FAT file system.
This patch unifies all these boards to remove these unused features
from their defconfigs
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add new defconfig files for the J721e High Security EVM.
These defconfigs are the same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_BOOTCOMMAND uses FIT images for booting
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
This was 276000 bytes but now needs to be grown to 277000 to make room
for the slightly larger SYSFW image used on J721e High-Security devices.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ROM configures certain firewalls based on its usage, which includes
the one in front of boot peripherals. In specific case of boot
peripherals, ROM does not open up the full address space corresponding
to the peripherals. Like in OSPI, ROM only configures the firewall region
for 32 bit address space and mark 64bit address space flash regions
as in-accessible.
When security-cfg is initialized by sysfw, all the non-configured
firewalls are kept in bypass state using a global setting. Since ROM
configured firewalls for certain peripherals, these will not be touched.
So when bootloader touches any of the address space that ROM marked as
in-accessible, system raises a firewall exception causing boot hang.
It would have been ideal if sysfw cleans up the ROM configured boot
peripheral firewalls. Given the memory overhead to store this
information provided by ROM and the boot time increase in re configuring
the firewalls, it is concluded to clean this up in bootloaders.
So disable all the firewalls that ROM doesn't open up the full address
space.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This file used to be the common location for K3 init when AM6 was the
only device, but common code was moved to common.c and this file became
AM6 specific, correct this header text.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Both 'loadfit' and 'mmcloados' start with a call to 'args_mmc' so this
can be factored out to before eithers only call site. This also allows us
to remove that call from 'loadfit', which should not have been calling it
anyway as that command should not be MMC specific. Without the call to
'args_mmc' the command 'loadfit' becomes just a call to 'run_fit' so
remove the indirection and call 'run_fit' directly, this removes the need
for 'loadfit' command (which was misnamed anyway). Drop it.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Some of the environment configuration in AM65x is not available in
J721e due to additions on one but not the other. These two platforms
are similar enough these common definitions should be factored out
to a common area, prepare for this by synchronizing them.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Commit 8502fe84a4 ("configs: am57xx_evm: define
CONFIG_SPL_LOAD_FIT_ADDRESS for SPL-DFU") implements incorrect ifdef
logic, which leads to DFU variables absence in non-SPL environment. Fix
that in order to bring back DFU variables, by reflecting the logic in
include/configs/dra7xx_evm.h.
Fixes: 8502fe84a4 ("configs: am57xx_evm: define CONFIG_SPL_LOAD_F...")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
wkup_vtm populates only 1 power-domain cell in it's node. But the
power-domain cell are defined as 2. Due to this the following warning
comes during build:
arch/arm/dts/k3-am654-r5-base-board.dtb: Warning (power_domains_property):
/interconnect@100000/interconnect@28380000/interconnect@42040000/
wkup_vtm@42050000:power-domains: property size (8) too small for cell size 2
Fix this by updating the power-domain cells.
Fixes: cfa6bd549c ("arm: dts: k3-am654-r5-base-board: Add VTM node")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
commit 29f7d05a34 ("dm: core: Move ofdata_to_platdata() call earlier")
introduces changes in the order of device_probe execution.
ofdata_to_platdata now comes before the probe function which resulted in
a deadlock and caused boot hang on AM6 devices.
Deadlock sequence: tps62360_regulator_ofdata_to_platdata --> i2c_get_chip
--> device_probe(tps62360) --> tps62360_regulator_ofdata_to_platdata
Hence convert ofdata_to_platdata to the missing probe function to fix the
hang.
Fixes: 22e8f18980 ("power: regulator: tps6236x: add support for tps6236x regulators")
Signed-off-by: Keerthy <j-keerthy@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On K3 systems U-Boot runs on both an R5 and a large ARM cores (usually
A53 or A72). The large ARMs are coherent with the DMA controllers and
the SYSFW that perform authentication. And previously the R5 core did
not enable caches. Now that R5 does enable caching we need to be sure
to clean out any of the image that may still only be in cache before we
read it using external DMA for authentication.
Although not expected to happen, it may be possible that the data was
read back into cache after the flush but before the external operation,
in this case we must invalidate our stale local cached version.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Not finding a node that we try to disable does not always need to be
fatal to boot but should at least print out a warning. Return error
from fdt_disable_node as it did fail to disable the node, but only
warn in the case of disabling the TRNG as this will not prevent boot.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Sync new additions to non-HS defconfig with HS defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Sync new additions to non-HS defconfig with HS defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Make the wkup_i2c0 module usable across all stages of U-Boot by adding
the needed definitions including the associated pinmux definitions.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The TI J721E EVM system on module (SOM), the common processor board, and
the associated daughtercards have on-board I2C-based EEPROMs containing
board config data. Use the board detection infrastructure to do the
following:
1) Parse the J721E SOM EEPROM and populate items like board name, board
HW and SW revision as well as board serial number into the TI common
EEPROM data structure residing in SRAM scratch space
2) Check for presence of daughter card(s) by probing associated I2C
addresses used for on-board EEPROMs containing daughter card-specific
data. If such a card is found, parse the EEPROM data such as for
additional Ethernet MAC addresses and populate those into U-Boot
accordingly
3) Dynamically apply daughter card DTB overlays to the U-Boot (proper)
DTB during SPL execution
4) Dynamically create an U-Boot ENV variable called name_overlays
during U-Boot execution containing a list of daugherboard-specific
DTB overlays based on daughercards found to be used during Kernel
boot.
This patch adds support for the J721E system on module boards containing
the actual SoC ("J721EX-PM2-SOM", accessed via CONFIG_EEPROM_CHIP_ADDRESS),
the common processor board ("J7X-BASE-CPB"), the Quad-Port Ethernet
Expansion Board ("J7X-VSC8514-ETH"), the infotainment board
("J7X-INFOTAN-EXP") as well as for the gateway/Ethernet switch/industrial
expansion board ("J7X-GESI-EXP").
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use dm_i2c_probe() rather than i2c_get_chip() when trying to access
board-detection EEPROM devices. This has the advantage of more gracefully
handling the case when the EEPROM is not present by allowing to exit the
function early rather than failing and outputting an error message on the
I2C transactions that follow.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Adding the configurations to the evm_defconfig file
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
BeagleBoard.org BeagleBone AI is an open source hardware single board
computer based on the Texas Instruments AM5729 SoC featuring dual-core
1.5GHz Arm Cortex-A15 processor, dual-core C66 digital signal
processor (DSP), quad-core embedded vision engine (EVE), Arm Cortex-M4
processors, dual programmable realtime unit industrial control
subsystems and more. The board features 1GB DDR3L, USB3.0 Type-C, USB
HS Type-A, microHDMI, 16GB eMMC flash, 1G Ethernet, 802.11ac 2/5GHz,
Bluetooth, and BeagleBone expansion headers.
For more information, refer to:
https://beaglebone.ai
The corresponding patch against the mainline linux kernel can be found
at: https://patchwork.kernel.org/patch/11254903/
This patch introduces the BeagleBone AI device tree.
Note that the device use the "ti,tpd12s016" component which is software
compatible with "ti,tpd12s015". Thus we only use the latter driver.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
These are necessities for beaglebone ai boot. There is the addition of
CONFIG_SUPPORT_EMMC_CONFIG to the Kconfig file. This is present upstream
but not in 19.01 yet.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This patch configures the pinmux settings for the BeagleBone AI after
the emmc read has completed.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
BeagleBoard.org BeagleBone AI rev A1 does not include a board
identifier I2C EEPROM due to a design oversight. These boards have
been put into production and are generally available now.
The board identifier information, however, has been included in the
second eMMC linear boot partition (/dev/mmcblk1boot1).
This patch works by:
* First, looking for a board identifier I2C EEPROM and if not found,
* Then seeing if the boot mode matches BeagleBone AI with eMMC in the
boot chain to make sure we don't enable eMMC pinmuxes on boards
that don't support it, and
* Finally, initializes the eMMC pins and reading the header.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add Support for writing to PHY registers for J721e. There are number of
differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY.
Create a driver_data structure with an ops and flags field and use the
flags field to indicate these differences. The differences are as
follows:
1. The J721e 4 bit instance PHY does not have a DLL. Introduce a
DLL_PRESENT flag to make sure that DLL related registers are accessed
only where they are present. Also add a separate set_ios_post()
callback.
2. The J721e 8 bit instance is not muxed with anything else inside the
SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is
used to indicate the presence of this field.
3. The register field used to select DLL frequency is 3 bit wide in
J721e as compared to 2 bits in AM65x. Add another flag that
distinguishes these fields.
4. The strobe select field is 8 bit wide as compared to 4 bit wide for
AM65x. Add yet another flag to indicate this difference. Strobe select
is used only for HS400 speed mode, support for which has not been added
in AM65x.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Get clk_xin by name instead of by index to avoid having to put clocks in
the same order in all devices.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Cast pointers properly so as to avoid warnings when driver is built for
32 bit platforms
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
UDMA always expects 64 bit address pointer of the transfer descriptor in
the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size.
Therefore copy over 32 bit pointer value to 64 bit variable before
pushing it over to the ring, so that upper 32 bits are 0s.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Exposed ring mode works well with 32 bit and 64 bit cores without need
for Proxies for 32 bit cores. Therefore switch to exposed ring mode.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Fix up the debug prints that were dumping state of TCHAN RT registers to
use tchan for MEM_TO_DEV transfers.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Remove redundant coherency checks before calling cache ops in UDMA
driver. This is now handled in arch specific cache operation
implementation based on Kconfig option
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Instead of looking getting reference to SYSFW device using name which
is not guaranteed to be constant, use phandle supplied in the DT node to
get reference to SYSFW
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Flush caches when pushing an element to ring and invalidate caches when
popping an element from ring in Exposed Ring mode. Otherwise DMA
transfers don't work properly in R5 SPL (with caches enabled) where the
core is not in coherency domain.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}())
and their dependencies from Linux. These are required for upcoming DMA
resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently, the da850-lcdk uses SPL_OF_PLATDATA and manually loads
the necessary source code instead of using the auto-generated,
because the drivers don't properly autogenerate the code.
This patch simply enables the various device tree options to
mimic the da850-evm which doesn't need or use OF_PLATDATA for
device tree support. It does not disable OF_PLATDATA.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to
be indexed into a lookup table to get the actual temperature. Fix the
naming and datatype of the adc value variable.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
J721e has two instances of Cadence USB3 controller. Add DT nodes for the
same. USB0 is configured to device mode and USB1 is configured to host
mode. For now only high speed mode is supported.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This file doesn't include any declarations anymore but it does include
other headers. Update the header comment to mention this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not really a CONFIG since it is not intended to be set by boards.
Move it into the compiler header with other similar defines, and rename
it.
Signed-off-by: Simon Glass <sjg@chromium.org>
The kernel.h file has a number of useful macros including a few related
to structures. Move check_member() there too.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
This function has a very generic name which does not adequately describe
its purpose. Rename it and move it to image.h, since it relates to reading
a script from an image.
Signed-off-by: Simon Glass <sjg@chromium.org>
These global variables are quite short and generic. In fact the same name
is more often used locally for struct members and function arguments.
Add a image_ prefix to make them easier to distinguish.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function related to timer and most of the timer functions are in
time.h, so move this function there.
Signed-off-by: Simon Glass <sjg@chromium.org>
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is only used on ARM devices so does not belong in the global
common header file. Move it to an ARM header.
Signed-off-by: Simon Glass <sjg@chromium.org>
These functions relate to setting up the device tree for booting the OS.
The fdt_support.h header file supports similar functions, so move these
there.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is not called anywhere so we can drop the declaration. If
it is needed one day, it should be added in its own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
This only exists to control whether the post/ directory is build. It is
just as easy to check this in the Makefile. Remove CONFIG_HAS_POST and use
an ifdef in the Makefile instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
These CONFIG options are not used anymore. CONFIG_POST_ALT_LIST just
causes CONFIG_POST_STD_LIST to be set and it causes tests.c to be
compiled. So just make compiling tests.c unconditional.
Signed-off-by: Simon Glass <sjg@chromium.org>
This define seems better suited to the eeprom header file, particularly
as it is only used in the eeprom.c file.
Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is defined in exports.c so move it to its header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This is an init function so move it out of the common header. Avoid using
the typedef so that we don't have to include the global_data header file.
Also tidy up the function style in comments while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function belongs more in flash.h than common.h so move it.
Also remove the space before the bracket in some calls.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add missing 'eth-ck' clock to the ethernet node. These clock are used to
generate external clock signal for the PHY in case 'st,eth_ref_clk_sel'
is specified.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Since CONFIG_LOADADDR is not set, the default value of $loadaddr
variable is not set in the environment either. Set the default
load address to 32 MiB from the start of DRAM (same value than
kernel_addr_r).
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit add to u-boot the support to decrypt
fit image encrypted with aes. The FIT image contains
the key name and the IV name. Then u-boot look for
the key and IV in his device tree and decrypt images
before moving to the next stage.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
This commit add the support of encrypting image with aes
in mkimage. To enable the ciphering, a node cipher with
a reference to a key and IV (Initialization Vector) must
be added to the its file. Then mkimage add the encrypted
image to the FIT and add the key and IV to the u-boot
device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Until now, we only support aes128. This commit add the support
of aes192 and aes256.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the code, we use the size of the key for the
size of the block. It's true when the key is 128 bits,
but it become false for key of 192 bits and 256 bits.
So to prepare the support of aes192 and 256,
we introduce a constant for the iaes block size.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Split the board and SOC support for STM32MP15x family and
prepare the introduction of new boards with STM32MP15x.
This path define the 2 configurations:
- STM32MP15x: STM32MP15x soc support (new)
- TARGET_ST_STM32MP15x: STMicroelectronics board support (choice)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Move CONFIG_ENV_SECT_SIZE and CONFIG_ENV_OFFSET in stm32mp15_*_defconfig
for ST board with NOR support (STM32MP15xx-EV1 boards)
- CONFIG_SECT_SIZE values = the max supported NOR erase size (256KB)
- CONFIG_ENV_OFFSET = offset for NOR (ENV_IS_IN_SPI_FLASH)
This Patch prepares the U-Boot support of boards with STM32MP15x SOC
not provided by STMicroelectronics.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Move the ST command in board/st/common, as this command is only used
by ST board. Prepare the support in U-Boot of boards with STM32MP15x
SOC but not STMicroelectronics.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Not all systems have all the boot devices enabled, e.g. not all systems
have MTD devices and thus do not enable UBI. Make all the boot devices
in the distro bootcmd conditional to avoid failures.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Let board code override setup_mac_address(), which is useful e.g. if the
board derives the MAC address from another source, like an I2C EEPROM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
The main prompt for this (defined in /Kconfig) is visible at all times,
which means there's no reason to have an additional, machine-specific
prompt to set the same option.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
SoC base addresses should better go into a common SoC file instead
of repeating the definition in each board file.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
As we use the driver model for ESDHC there is no need
for defining CONFIG_SYS_FSL_USDHC_NUM and CONFIG_SYS_FSL_ESDHC_ADDR,
so simply remove them.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Currently the following build warning is seen:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
===================================================
Since the mx7ulp-evk board does not have networking support, explicitly
disable networking.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
- Clearfog: Fix SD booting (Baruch)
- Misc updates to MMC handling in SPL to support booting from
main data partition (vs hardware boot partition) on MVEBU (Baruch)
Xilinx/FPGA changes for v2020.04
ARM64:
- Add INIT_SPL_RELATIVE dependency
SPL:
- FIT image fix
- Enable customization of bl2_plat_get_bl31_params()
Pytest:
- Add test for octal/hex conversions
Microblaze:
- Fix manual relocation for one SPI instance
Nand:
- Convert zynq/zynqmp drivers to DM
Xilinx:
- Enable boot script location via Kconfig
- Support OF_SEPARATE in board FDT selection
- Remove low level uart setup it is done later by code
- Add support for DEVICE_TREE variable passing for SPL
Zynq:
- Enable jtag boot mode via distro boot
- Removing unused baseaddresses from hardware.h
- DT fixups
ZynqMP:
- Fix emmc boot sequence
- Simplify spl logic around bss and board_init_r()
- Support psu_post_config_data() calling
- Tune mini-nand DTS
- Fix psu wiring for a2197 boards
- Add runtime MMC device boot order filling in spl
- Clear ATF handoff handling with custom bl2_plat_get_bl31_params()
- Add support u-boot.its generation
- Use single image configuration for all platforms
- Enable PANIC_HANG via Kconfig
- DT fixups
- Firmware fixes
- Add support for zcu208 and zcu1285
Versal:
- Fix emmc boot sequence
- Enable board_late_init() by default
This patch add CONFIG_TARGET_MT7623 into mt7623n_bpir2_defconfig
to fix the mt7623 compile error after building others mediatek target
platform
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
This adds a general board file based on MT7622 SoCs from MediaTek.
This commit is adding the basic boot support for the MT7622 rfb.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
This patch fix clock-rate overflow problem in mediatek
clock driver common part.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Due to the pinctrl hardware of MT7622 is difference from others
SoC which using the common part of mediatek pinctrl.
So we need to modify the common part of mediatek pinctrl.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Add support for MediaTek MT7622 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
If make the ref clock optional, no need refer to fixed-clock when
the ref clock is always on or comes from oscillator directly.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Sometimes we may need get (optional) clock without a device,
that means use ofnode.
e.g. when the phy node has subnode, and there is no device created
for subnode, in this case, we need these new APIs to get subnode's
clock.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Add valid check for clk->dev, it's useful when get optional
clock even when the clk point is valid, but its dev will be
NULL.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
If skip all return error number, it may skip some real error cases,
so only skip the error when the clock is not provided in DTS
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
This adds a general board file based on MT8512 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8512 eMMC board.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
For CMD21 tuning data, the 128/64 bytes data may coming in very
short time, before msdc_start_data(), the read data has already
come, in this case, clear MSDC_INT will cause the interrupt disappear
and lead to the thread hang.
the solution is just clear all interrupts before command was sent.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs.
MT8512/MT8110 SoCs puts the tune register at top layer, so
need add new code to support it.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
Add support for MediaTek MT8512 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
Sam doesn't work for Linaro anymore, so Linaro mail is not valid. Change
it to his home mail instead.
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
When no partition table is found, users should be warned so.
Warning that no device is available in this case could be misleading,
especially as it is the same error when no device is selected.
Signed-off-by: Alexandre Besnard <alexandre.besnard@softathome.com>
SPL now automatically selects the correct U-Boot image offset for both
eMMC and SD card. No need to tweak
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR anymore.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Armada 38x ROM skips the first SD card offset when loading SPL. This
affects the location of the main U-Boot image. SPL MMC code now supports
U-Boot image offset based on run-time detection of the boot partition.
Use this feature to make the same generated image support both SD card
and eMMC boot partition.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
On Armada 38x platforms the ROM code loads SPL from offset 0 of eMMC
hardware boot partitions. When there are no boot partitions (i.e. SD
card) the ROM skips the first sector that usually contains the (logical)
partition table. Since the generated .kwb image contains the main U-Boot
image in a fixed location (0x140 sectors by default), we end up with the
main U-Boot image in offset of 1 sector. The current workaround is to
manually set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x141 to
compensate for that.
This patch uses the run-time detected boot partition to determine the
right offset of the main U-Boot partition. The generated .kwb image is
now compatible with both eMMC boot partition, and SD card main data
partition.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
SPL needs DM GPIO to read the SD card-detect signal. This complements
the fix in commit 70bae02f71 ("arm: mvebu: clearfog: fix boot from SD
card").
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
It was observed (on ClearFog Base) that sending MMC APP_CMD returned
an error on the first attempt. The issue appears to be timing related
since even inserting a puts() short debug entry before the execution
added sufficient delay to receive success on first attempt.
Follow the existing quirks pattern to retry if initial issuance
failed so as to not introduce any delay unless needed.
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
The eSDHC reference clocks should be provided by speed.c in arch/.
And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to
select which clock to use. Because we can make the driver to select
the periperhal clock which is better (provides higher frequency)
automatically if its value is provided by speed.c.
This patch is to drop this option and make driver to select clock
automatically. Also fix peripheral clock calculation issue in
fsl_lsch2_speed.c/fsl_lsch3_speed.c.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The QorIQ eSDHC controller supports two reference clocks. They are
platform clock and periperhal clock. The global variable sdhc_clk
has already been used for platform clock.
This patch is to add another global variable sdhc_per_clk for
periperhal clock, which provides higher frequency and is required
to be used for SD UHS and eMMC HS200/HS400 speed modes.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The below patch added eSDHC periperhal clock code initially.
2d9ca2c mmc: fsl_esdhc: Add peripheral clock support
The purpose was to fix up device tree properties "peripheral-frequency"
so that linux could get the periperhal clock by it.
However the implementation on both u-boot and linux was only
for a Freescale SDK release. The linux part implementation had never
been upstreamed. These code should not have been exist on u-boot
mainline.
Let's remove the powerpc part changes but keep the changes in
fsl_esdhc driver. The changes in fsl_esdhc driver could be utilized
to support SD UHS and eMMC HS200/HS400 speed modes for current
Layerscape ARM platforms.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The fdt fixup for properties "peripheral-frequency" and "adapter-type"
was once for a Freescale SDK release. The properties haven't been existed
in linux mainline. Drop these useless code.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The device tree compiler expects that a node with a unit-address has a reg
property.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some features implicitly depended on MALLOC_F and OF_LIBFDT and would
fail at link-time if these features were not enabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add stub for dma_memcpy() and dma_get_device when CONFIG_DMA is
disabled. This avoids ifdefs in driver code using DMA APIs
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use
macros such as CONFIG_IS_ENABLED() that allow conditional compilation of
code for SPL and U-Boot.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Pull request for UEFI sub-system for efi-2020-04-rc1-2
Bug fixes for the UEFI sub-system are provided:
* imply VIDEO_ANSI for correct cursor positioning and colors
* fix issues in the UEFI block device driver
* add missing documentation
UEFI programs like GRUB make change terminal colors which requires support
for ANSI escape sequences.
Let CONFIG_EFI_LOADER=y imply CONFIG_VIDEO_ANSI.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Use the correct protocol in efi_uc_stop() when detaching the driver from
the controller.
Change the block IO unit test for the block device driver to throw an error
instead of a todo if teardown fails.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
For automating testing we should be able to power off the test system.
The implementation of EFI_RESET_SHUTDOWN requires the do_poweroff()
function which is only available if CONFIG_CMD_POWEROFF=y.
Enable CONFIG_CMD_POWEROFF if PSCI reset is available.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms
with CONFIG_DM_MMC=y.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK
instead. So building could result in failure due to missing
mxc_get_clock().
Make if(CONFIG_IS_ENABLED(CLK)) an #if statement.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Add i.MXRT compatible string and cpu type support to lpuart driver,
to use little endian 32 bits configurations.
Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART
FIFO register is bit 3, so this definition should change to 0x08 as done
for i.MX8. It needs also to set baudrate the same way as i.MX8 does.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
This driver assumes that lpuart clock is already enabled before probing
but using DM only lpuart won't be automatically enabled so add
clk_enable() when probing if CONFIG_CLK is defined. If clock is not
found, because DM is not used, let's emit a warning and proceed, because
serial clock could also be already enabled by non DM code. If clock is
found but cna't be enabled then return with error.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
generic enable()/disable(). Add a different driver because ops are
different respect to GENERIC/USB.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Before set_rate() pllv3 needs enable() to power the pll up.
Add enable() taking into account different power_bit and
different powerup_set, because some pll needs its power_bit to be
set or reset to be powered on.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Better to register the 2 clock as 2 different drivers because they work
slightly differently depending on power_bit and powerup_set bits coming
on next patches.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Since some driver requires this function add it as an empty stub
when DCACHE is OFF.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
At the moment entry_point is set to image_get_load(header) that sets it
to "load address" instead of "entry point", assuming entry_point is
equal to load_addr, but it's not true. Then load_addr is set to
"entry_point - header_size", but this is wrong too since load_addr is
not an entry point.
So use image_get_ep() for entry_point assignment and image_get_load()
for load_addr assignment.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
IPG clock description is missing for I2C0 and I2C2 busses,
add it. Otherwise we see -ENODATA error when trying to get
I2C clock for these busses.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
imx6ul-14x14-evk does not have a GPIO dedicated for reading the card
detect pin on the eSDHC2 port. In such cases the "broken-cd" property
must be passed, otherwise the card cannot be detected.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
When no GPIO is used to read the card detect status the following
error is seen:
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment
Fix it by handling the "broken-cd" property in the same way
that drivers/mmc/sdhci.c does, which considers that the SD card
is present when the "broken-cd" property is passed.
Tested on a imx6ul-evk board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
For DM_ETH support , it's require to disable this config.
When this config is enable, This generate a error with spl in linker script
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Currently the following SPL hang is observed:
U-Boot SPL 2020.01-rc5-00079-g797eee36a1 (Jan 06 2020 - 11:24:09 -0300)
Trying to boot from MMC1
Card did not respond to voltage select!
spl: mmc init failed with error: -95
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Fix it by moving the eSDHC2 initialization to SPL.
While at it, since this board uses DM_MMC all the esdhc board
code can be removed to make the code simpler.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Only the wandboard revD1 boards have PMIC, so when running on a wandboard
of different revision the following error is always shown on every boot:
pmic_get() ret -19
Instead of printing this error message, move it to debug level instead.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Some i.MX8QXP MEK boards do not have MAC address stored
and hang during eth driver probe:
Error: ethernet@5b040000 address not set.
(Board hangs)
To fix this problem select CONFIG_NET_RANDOM_ETHADDR so that
a valid MAC address can be used in such case.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
All Tegra chips except Tegra186 have a tegraNNN-u-boot.dtsi. Duplicate
Tegra210's copy of this file for Tegra186. This ensures that a /binman node
exists in U-Boot's control DT. Subsequent to 3c10dc95bd ("binman: Add a
library to access binman entries") this appears to be required. I haven't
really investigated why all this is necessary or how it works, but simply
observed the boot failure listed below, bisected it, noticed the
inconsistency in DT files, and found that fixing it resolved the boot
issue.
U-Boot 2020.01-rc4-00256-g3c10dc95bdd0 (Jan 07 2020 - 10:25:00 -0700)
SoC: tegra186
Model: NVIDIA P2771-0000-500
Board: NVIDIA P2771-0000
DRAM: 7.8 GiB
initcall sequence 00000000fffb7858 failed at call 00000000800955a8 (err=-22)
### ERROR ### Please RESET the board ###
Fixes: 3c10dc95bd ("binman: Add a library to access binman entries")
Fixes: f2faffecb0 ("binman: tegra: Convert to use binman")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Qemu v4.2.0 maps bootmode registers to address space which was the reason
why board_late_init() was disabled and accesses were failing.
With new Qemu board_late_init() can be called without any issue.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Most of the legacy "gpio-key,wakeup" boolean property is already
replaced with "wakeup-source". However few occurrences of old property
has popped up again, probably from the remnants in downstream trees.
This patch replaces the legacy properties with the unified
"wakeup-source" property introduced by:
"Input: gpio_keys - switch to using generic device properties"
(sha1: 700a38b27eefc582099fdf69effacfad0ad738a4)
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Somewhere along recent changes to power control of the wl1831, power-on
became very unreliable on the Ultra96, failing like this:
wl1271_sdio: probe of mmc2:0001:1 failed with error -16
wl1271_sdio: probe of mmc2:0001:2 failed with error -16
After playing with some dt parameters and comparing to other users of
this chip, it turned out we need some power-on delay to make things
stable again. In contrast to those other users which define 200 ms,
Ultra96 is already happy with 10 ms.
Fixes: 5869ba0653b9 ("arm64: zynqmp: Add support for Xilinx zcu100-revC")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
s/_/-/ for node names.
It fixes warnings like this:
... Warning (node_name_chars_strict): /cpu_opp_table:
Character '_' not recommended in node name ...
Issues reported by make dtbs W=12
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zcu102-revB/up are not removing phy from revA properly because of incorrect
name.
Fixes: 2975a42b42 ("arm64: zynqmp: Use ethernet-phy as node name for ethernet phys")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Removed no-1-8-v property from zynqmp sdhci devicetree nodes to
allow UHS-I capable SD cards to work in SD3.0 UHS modes.
Boards that does not have level shifter for SD, does not support 1.8v.
so no-1-8-v property to sdhci dt nodes should be present in zcu102 Rev-A,B,
zcu104 Rev-A,C, zcu100, zcu1275 Rev-B boards.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove probe function dm_scan_fdt_dev from zynqmp-firmware driver.
It is just binding its subnode zynqmp-clk.
As a result one extra node is showing up in dm tree.
This is not required, it is anyway bound from it's own zynqmp-clk driver.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fix shunt resistor value for ina226 vccint_ams and vccint_io_bram_ps.
2mOhm shunt was only in early board revision schematics but never got to
real revA board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Decrease amount of the similar defconfigs and use generic one instead.
The change was declared by commit 4b37c13dc3
("arm64: zynqmp: Introduce virtual defconfig") and this patch removes
configs for the most of the boards.
Utra96/zcu100/zcu102/zcu102 and ZynqMP based System controllers *a2197*.
have been also boot tested to make sure that funcionality
remains the same.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
These options are taken from zcu102/104 platforms. Also use OF_SEPARATE
instead of OF_BOARD. Maybe at some point this option will be taken back but
as of now board detection is not ready.
export DEVICE_TREE="zynqmp-zcu102-revA"
make xilinx_zynqmp_virt_defconfig
make -j
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which
includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for
quite a long time but with using out of tree solution. The patch is filling
this gap.
Tested on zcu102, zcu104 and zcu100/Ultra96.
zcu100/Ultra96 v2.2 ATF build by:
make DEBUG=0 ZYNQMP_CONSOLE=cadence1 RESET_TO_BL31=1 PLAT=zynqmp bl31
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
All drivers should be converted to DM already that's why these hardcoded
base addresses are not needed anymore.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove hardcoded base addresses of smc controller and nand controller.
Get those addresses from dt and replace wherever they are used.
Remove smc and nand base address from header file too.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds new jtag distro boot command to look for bootscript
file in DDR and execute it first incase of jtag bootmode.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
handoff_setup() was used to generate fixed handoff structure for ATF on
ZynqMP platform.
Switching to bl2_plat_get_bl31_params() platform brings more flexibility
because information can be taken from fit image where /fit-images node is
created at run time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Xilinx ZynqMP platform is passing information to ATF in private format and
ATF bl31 parameters are not used. That's why enable option to rewrite this
function by platform specific implementation.
The patch also move and update kernel-doc format with missing parameters.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When two instances of AXI QSPI with flash are added and tested
simultaneously the spi driver operations are relocated twice.
As a result code is accessing addresses outside of RAM when
relocated second time which is causing a crash.
Tested on Microblaze.
Similar change was done in past by:
commit f238b3f0fb ("watchdog: dm: Support manual relocation for watchdogs")
commit 2588f2ddfd ("dm: sf: Add support for all targets which requires MANUAL_RELOC")
commit 1b4c2aa25b ("gpio: dm: Support manual relocation for gpio")
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DEVICE_TREE variable has been added by commit 6ab6b2afa0
("dts: re-write dts/Makefile more simply with Kbuild")
where DT can be specified on command line. If it is not then
CONFIG_DEFAULT_DEVICE_TREE is used to ensure backward compatibility.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Empty implementation should not return 0 (success) because that mean that
passed name matches the board configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In past SPL_ZYNQMP_TWO_SDHCI symbol was introduced to handle boards with
two sdhci controllers. The problem was that U-Boot is registering
controllers based on aliases in DT but bootmode targets specific controller
ID. That's why on boards with one "second" sdhci controller bootmode was
pointing to second controller(MMC2) but alias was setup to mmc0 (the first
controller). And SPL requires to point to mmc0 in this case.
Long time ago commit f101e4bd37
("spl: add support for alternative boot device") added support for handling
multiple bootmodes in SPL. Use this functionality and setup second sdhci
controller as backup boot device.
Below is table with behavior:
HW/bootmode bootorder
sd0/sd0 mmc0/mmc1 (mmc1 never called)
sd1/sd1 mmc1/mmc0 (mmc0 fails and mmc1 is called)
sd0+sd1/sd0 mmc0/mmc1 (mmc1 never called)
sd0+sd1/sd1 mmc1/mmc0 (mmc0 never called)
All other bootmodes are not affected but order can be extended to cover
advance boot flows.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Names have to match device tree file names. Also add missing one.
Fixes: 50d9283347 ("arm64: zynqmp: Sync names for SC with Versal")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There shouldn't be a need to use any partition description because it
can be used for writing data anywhere.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
These commands are useful in connection to usb and other devices that's why
enable it by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no reason to do serial initializationin low level code. Uart
driver does it already based on DT.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no reason to do serial initialization. Uart driver does it already
based on DT. Good effect is that it is clear which interface is console.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
MIO34 is connected to POWER_KILL signal. When MIO configuration is done in
psu_init() and this pin is assigned to PMU but PMU configuration is not
loaded yet. PMU gpio output is high that means board is powered off
immediately.
The patch is fixing this sequence that MIO34 stays assing to ps gpio IP.
PMU config is loaded in SPL and then pin assigned to PMU through
psu_post_config_data().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
OF_BOARD and OF_SEPARATE can use board specific board_fdt_blob_setup().
OF_BOARD option is mostly used for picking up DTB from certain location.
OF_SEPARATE option is used when DTB is appended after u-boot binary.
This board specific function is aligned with current version in
lib/fdtdec.c with checking CONFIG_XILINX_OF_BOARD_DTB_ADDR address first.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The reason for this change is just get in sync with board_fdt_blob_setup()
available at lib/fdtdec.c.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When position-independent pre-relocation code is enable there is also
necessary to enable relative early stack pointer not to use origin location
pointed by CONFIG_SYS_INIT_SP_ADDR macro.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no reason to clear bss and call board_init_r() from board_init_f()
beca it can be called directly from crt0_64.S with also support for SPL
stack relocation to SDRAM.
For more information please take a look at arch/arm/lib/crt0_64.S
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ndepth needs to be initialized before it is used in fdt_next_node().
Uninitialized value is causing that node is found and depth increase but
won't pass condition below because initial state wasn't setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Currently "script_offset_f" env variable is hardcoded, this variable
specifies from which offset of the flash boot.scr should be read/write.
As flashes are of different sizes having a fixed offset makes it
difficult to load other images into the flash which may overwrite the
boot script or cannot utilize the full memory. This current fix
creates a new config "CONFIG_BOOT_SCRIPT_OFFSET" which holds the
offset address, overwrites the "script_offset_f" variable.
Also removed existing variable with default values, as the default
values are held by CONFIG_BOOT_SCRIPT_OFFSET
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Emmc boot devcie is mounted to mmc@ff160000 controller on zynqmp.
Detect mmc alias at run time for setting up proper boot_targets
sequence instead of setting boot_targets manually.
Removed setting "modeboot" variable as it not longer need as we
switched to distro boot.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Emmc boot devcie is mounted to sdhci@f1050000 controller on versal, while
in emmc boot mode, boot tragets are set to mmc0. So removed mmc0 and using
the dev seq number from the sdhci@f1050000 controller.
Dev seq number is setup based on DT aliases that's why needs to be setup at
run time.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove hardcoded base address of nand and replace it with the
value taken from device tree. Remove base address from header
file too.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Make changes to arasan nand driver to move it to driver model.
Select DM_MTD if arasan nand driver is selected.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Trying to extend 'adtimg' functionality [1], we've been severely hit
by a major limitation in the command's usage scheme. Specifically, the
command's user interface appears to be too centric to getting the
DTB/DTBO entry [3] based on the index of the desired DT in the image,
which makes it really difficult retrieving the DT entry based on
alternative criteria (e.g. filtering by id/rev fields), the
latter being demanded by real life customer use-cases [1].
This went to the point of receiving below feedback from Sam [2]:
-- snip --
As for 'dtimg' command: after giving it some thought, I think not much
people using it yet. So in this particular case I don't have some
strong preference, and if you think the 'dtimg' interface is ugly, and
it overcomes "don't break interfaces" rule, maybe now is a good time
to rework it (before it gets widely used).
-- snip --
Given the above, rework the usage pattern from [4] to [5], in order to
allow an intuitive enablement of "by id|rev" DT search [6].
[1] https://patchwork.ozlabs.org/cover/1202575/
("cmd: dtimg: Enhance with --id and --rev options (take #1)")
[2] https://patchwork.ozlabs.org/patch/1182207/#2317020
[3] https://source.android.com/devices/architecture/dto/partitions
[4] Old usage
adtimg dump <addr> - Print image contents
adtimg start <addr> <index> <varname> - Get DT address by index
adtimg size <addr> <index> <varname> - Get DT size by index
[5] New usage
adtimg addr <addr> - Set image location to <addr>
adtimg dump - Print out image contents
adtimg get dt --index=<i> [avar [svar]] - Get DT address and size by index
[6] Soon-to-be-provided "by id|rev" add-on functionality
adtimg get dt --id=<id> --rev=<rev> [avar [svar [ivar]]]
- Get DT address/size/index by id|rev fields
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
With 'dtimg.c' renamed to 'adtimg.c', now ensure the naming
consistency in the internal implementation of 'adtimg.c'.
No functional change intended.
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rename the existing 'dtimg' command to 'adtimg', in order to:
- Suggest the Android origins and scope
- Be consistent with the upcoming 'abootimg' command (naming
suggested by Simon [*])
The change in _not_ backward compatible, but its benefits outweigh its
downsides, given that we don't expect active users of 'dtimg' today.
Perform the rename in several steps:
1. Rename *.c file and Kconfig symbol. This should allow
'git log --follow' to properly track the history of 'adtimg.c'
2. 's/dtimg/adtimg/g' in the internal namespace of 'adtimg.c'
ELF comparison [**] before and after shows no functional change.
[*] https://patchwork.ozlabs.org/patch/1182212/#2291600
[**] diff -u <(objdump -d cmd/dtimg.o) <(objdump -d cmd/adtimg.o)
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Simon Glass<sjg@chromium.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Current U-Boot has only support for psci reset.
Adding support for arm psci reset2 allows passing of reset level
and other platform sepcific parameters like strap settings
to lowlevel psci implementation.
Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Programs the following:
1. Redistributor PROCBASER configuration table (which
is common for all redistributors)
2. Redistributor pending table (PENDBASER), for all the
available redistributors.
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
fit_check_params() wants at least two of dflag, fflag, and lflag set.
Simplify the logical constraint checking this.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
If the numbers do not happen to contain any digits from [a-f], it's
not clear that they are base 16.
Signed-off-by: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
In the function cmd_ut_category, the prefix is used with
the function strncmp to know if the prefix should be
removed from the test name, even if the prefix is NULL.
To avoid this issue, we consider that a prefix NULL
mean no prefix. So we only try to remove the prefix
from the test_name if the prefix is not NULL, then
we avoid to call the function strncmp with a NULL
prefix.
Reported-by: Coverity CID 281110
Fixes: 4ad4edfe ("cmd_ut: add a parameter prefix to the function cmd_ut_category")
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
GCC 9.x starts complaining about potential misalignment of the pointer to
the array (in this case alignment=2) in the packed (alignment=1) structures.
Repeating Linus' Torvalds commit 6f303d60534c in the Linux kernel.
Original commit message:
We already did this for clang, but now gcc has that warning too.
Yes, yes, the address may be unaligned. And that's kind of the point.
This in particular hides the warnings like
drivers/usb/gadget/composite.c:545:23: warning: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Waddress-of-packed-member]
545 | collect_langs(sp, s->wData);
drivers/usb/gadget/composite.c:550:24: warning: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Waddress-of-packed-member]
550 | collect_langs(sp, s->wData);
drivers/usb/gadget/composite.c:555:25: warning: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Waddress-of-packed-member]
555 | collect_langs(sp, s->wData);
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
For upcoming SECU board we have different MAC address offsets depending
on which functional unit we are running. In this case we need to pass
this value to the ivm_populate_env function instead of using the hard
coded config option there.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
CC: Stefan Roese <sr@denx.de>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
CC: Marek Vasut <marex@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
DS3232 is an i2c RTC with 236 bytes of battery-backed SRAM.
Add an RTC driver for DS3232 device, which provides time and
date support. Also read and write functions are provided,
which can be used to access the SRAM memory.
Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Most platforms do not set up gd->start_addr_sp in SPL. Since this is
required for CONFIG_SPL_SYS_REPORT_SACK_F_USAGE to work correctly, set
up gd->start_addr_sp in SPL to the value passed to
board_init_f_init_reserve if it is not set yet.
Fixes: d8c0332031 ("spl: implement stack usage check")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This driver allows the use of i2c eeprom device or partition as backing
store for boot counter values with DM enabled.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Add specific dm code, but maintaining this driver as is, so more in the
shape of a mii library. Can be moved to dm in a further step.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
Pull request for UEFI sub-system for efi-2020-04-rc1
This pull request provides:
* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
As previous CONFIG_SYS_UBOOT_START is now set by default to
CONFIG_SYS_TEXT_BASE when not defined, CONFIG_SYS_UBOOT_START
can be removed from include/configs board files.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
This patches restores boot on boards which rely on
CONFIG_SYS_UBOOT_START equal to CONFIG_SYS_TEXT_BASE when using SPL
Fixes: d3e97b53c1 ("spl: fix entry_point equal to load_addr")
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Per Enea OSE documentation, it supports some classes of ARM, PowerPC and
X86. Limit the option to those platforms.
Signed-off-by: Tom Rini <trini@konsulko.com>
enable CONFIG_CMD_ERASEENV to make it easy to erase env.
Use savedefconfig to generate new defconfig.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add board_mmc_get_env_dev, otherwise,
Loading Environment from MMC...
MMC Device 0 not found
*** Warning - No MMC card found, using default environment
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add imximage-8mp-lpddr4.cfg for imximage usage, almost same
as i.MX8MN ddr4 cfg, but with different ddr firmware
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The drivers/clk/imx/*.c are used for CLK dm case, the
clock_imx8mm.c is used for non CLK dm case, let's split
it. Sometimes it is hard to enable CLK dm in SPL stage,
considering code size, malloc size requirement, the splittion
will make it easy to use non CLK dm in SPL stage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The i.MX8M Plus Media Applications Processor is part of the growing
mScale family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in Samsung 14LPP to achieve both
high performance and low power consumption and relies on a powerful
fully coherent core complex based on a quad core ARM Cortex-A53 cluster
and Cortex-M7 low-power coprocessor, audio digital signal processor,
machine learning and graphics accelerators.
Add the basic dtsi support for i.MX8MP.
Patch from Anson Huang for Kernel
https://patchwork.kernel.org/patch/11310915/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP has similar architecture as i.MX8MN, but it has different
clk root and index, so add that to make i.MX8MP could use
the non-dm clock driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP use 0x182 as dummy id, 0xFF is not able the get the highest
bit, so enlarge bit mask to 0x1FF to make it could detect
cpu type correctly
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
fsl_esdhc_imx driver will call "mxc_get_clock(MXC_ESDHC_CLK +
dev->seq)", however mxc_get_clock wrongly handle MXC_ESDHC_CLK
as root clk and cause sd card could not be detected in U-Boot proper,
as below:
"Loading Environment from MMC... unable to select a mode"
Handle MXC_ESDHC_CLK in mxc_get_clock to fix the issue.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Fabio Estevam <festevam@gmail.com>
After the conversion to DM_PMIC the following output is seen:
PMIC: PMIC: PFUZE100 ID=0x10
Remove the unnecessary PMIC string from the board file to
avoid the repetead string.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Commit ec837c82d7 ("imx6: wandboard: convert to DM_PMIC")
caused the following pmic_get() error:
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM: 2 GiB
PMIC: pmic_get() ret -19
...
and since the PMIC presence is used to determine the board D1 revision,
the following error is seen when booting a board rev D1:
WARNING: Could not determine dtb to use
and the kernel does not boot at all.
Fix the regression by passing "pfuze100@8" as the correct parameter
to the pmic_get() function in the DM case.
Fixes: ec837c82d7 ("imx6: wandboard: convert to DM_PMIC")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
The current mpc83xx_clk driver is broken for any board for which
mpc83xx_has_pci() is true, i.e. anything not MPC8308:
When is_clk_valid() reports that MPC83XX_CLK_PCI is valid,
init_all_clks() proceeds to call init_single_clk(), but that doesn't
know about either MPC83XX_CLK_PCI or has any handling of the
TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence
init_single_clk() ends up returning -EINVAL, and the whole board hangs
in serial_init().
The quickest fix is to simply pretend that clock is invalid for
all, since nobody can have been relying on it. Adding proper support
seems to be a bit more involved than just handling TYPE_SCCR_ONOFF:
- The power-on-reset value of SCCR[PCICM] is 0, so
mpc83xx_clk_enable() would probably need to be tought to enable the
clock.
- The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2
depending on the CFG_CLKIN_DIV configuration input, but that can't
be read from software, so to properly fill out
->speed[MPC83XX_CLK_PCI] I think one would need guidance from
Kconfig or dtb.
Partially fixes: 07d538d281 clk: Add MPC83xx clock driver
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
The MPC8309 has two gpio controllers (which is already correctly
reflected in its struct immap definition).
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
The mpc8309 is also affected by the "Manual Asynchronous CMD12 abort
operation causes protocol violations" erratum, though it is enumerated
as eSDHC16 in the errata sheet for mpc8309.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
This adds a message to lists_bind_fdt when it skips initializing a device
pre-relocation. I've had a couple errors where a device didn't initialize
properly because one of its dependencies was missing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we only support two phases where devres can be used:
bind and probe. This is handled with a boolean. We want to add a new
phase (platdata), so change this to an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
The devres functionality has very few users in U-Boot, but it still should
have tests. Add a few basic tests of the main functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present when CONFIG_DEBUG_DEVRES is enabled, U-Boot prints log messages
to the console with every devres allocation/free event. This causes most
tests to fail since the console output is not as expected.
In particular this prevents us from adding a device to sandbox which uses
devres in its bind method.
Move devres over to use U-Boot's logging feature instead, and add a new
category for devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
The malloc() implementations provides a way of finding out the approximate
amount of memory that is allocated. Add helper functions to make it easier
to access this and see changes over time. This is useful for tests that
want to check if memory has been allocated or freed.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present these functions are lumped in with the core device functions.
They have their own #ifdef to control their availability, so it seems
better to split them out.
Move them into their own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to avoid allocating platform data twice. This could happen if
device_probe() is called after device_ofdata_to_platdata() for the same
device.
Add a flag to track whether device_ofdata_to_platdata() has been called on
a device. Check the flag to make sure it doesn't happen twice, and clear
the flag when the data is freed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new internal function, device_ofdata_to_platdata() to handle
allocating private space associated with each device and reading the
platform data from the device tree.
Call this new function from device_probe().
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the parent is probed before the child's ofdata_to_platdata()
method is called. Adjust the logic slightly so that probing parents is
not done until afterwards.
Signed-off-by: Simon Glass <sjg@chromium.org>
This method is supposed to extract platform data from the device tree. It
should be done before the device itself is probed. Move it earlier in the
device_probe() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the clock driver reads its ofdata in the probe() method. This
is not correct although it is often harmless.
However in this case it causes a problem, something like this:
- ast_get_scu() is called (from somewhere) to get the SCI address
- this probes the clock
- first sets up ofdata (which does nothing at present)
- DM marks clock device as active
- DM calls pinctrl
- pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe()
- ast_get_scu() probes the clock, but sees it already marked as
probed
- ast_get_scu() accesses the clock's private data, with scu as NULL
- DM calls clock probe function ast2500_clk_probe() which reads scu
By putting the read of scu into the correct method, scu is read as part of
ofdata setup, and everything is OK.
Note: This problem did not matter until now since DM always probed all
parents before reading a child's ofdata. The fact that pinctrl is a child
of clock seems to trigger this strange bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
It is not possible to access a device on a PCI bus that has not yet been
probed, since the bus number is not known. Add a warning to catch this
error.
Signed-off-by: Simon Glass <sjg@chromium.org>
The PCI bus is not actually probed by the time the ofdata_to_platdata()
method is called since that happens in the uclass's post_probe() method.
Update the PMC and P2SB drivers to access the bus in its probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
These macros use __FILE__ which inserts the full path of the object file
into U-Boot, thus increasing file size. Drop these usages.
An older version of this patch was submitted here:
http://patchwork.ozlabs.org/patch/1205784/
Signed-off-by: Simon Glass <sjg@chromium.org>
Some U-Boot code uses BUG_ON() and WARN_ON() macros. These use __FILE__
which can include quite a large path, depending on how U-Boot is built.
The existing assert() is only checked if DEBUG is enabled. Add a new one
which is always checked, and prints a (smaller) error in that case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Provide a unit test for the EFI_RNG_PROTOCOL.
The list of algorithms is read. Two random numbers are generated. The test
checks that the two numbers differ.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Install the EFI_RNG_PROTOCOL implementation for it's subsequent use by
the kernel for features like kaslr.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add support for the EFI_RNG_PROTOCOL routines for the qemu arm64
platform. EFI_RNG_PROTOCOL is an uefi boottime service which is
invoked by the efi stub in the kernel for getting random seed for
kaslr.
The routines are platform specific, and use the virtio-rng device on
the platform to get random data.
The feature can be enabled through the following config
CONFIG_EFI_RNG_PROTOCOL
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Changed SPDX header to use /* instead of //.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
For the RNG uclass we currently only have a test working on the sandbox.
Provide a command to test the hardware random number generator on
non-sandbox systems.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add a driver for the virtio-rng device on the qemu platform. The
device uses pci as a transport medium. The driver can be enabled with
the following configs
CONFIG_VIRTIO
CONFIG_DM_RNG
CONFIG_VIRTIO_PCI
CONFIG_VIRTIO_RNG
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Enable support for random number generator on sandbox configs. This is
aimed primarily at adding unit test support for rng uclass.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a sandbox driver for random number generation. Mostly aimed at
providing a unit test for rng uclass.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a driver for the rng device found on stm32mp1 platforms. The
driver provides a routine for reading the random number seed from the
hardware device.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove a superfluous blank line
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This test verifies the implementation of the 'bootm' extension that
handles UEFI binaries inside FIT images (enabled via CONFIG_BOOTM_EFI).
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This patch adds a new section "Launching a UEFI binary from a FIT image"
documenting the usage of the CONFIG_BOOTM_EFI extension to bootm command
that offers a verified boot alternative for UEFI binaries such as GRUB2.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This patch adds an example FIT image description file demonstrating
the usage of bootm command to securely launch UEFI binaries.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add support for booting EFI binaries contained in FIT images.
A typical usage scenario is chain-loading GRUB2 in a verified
boot environment.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add a new OS type to be used for chain-loading an EFI compatible
firmware or boot loader like GRUB2, possibly in a verified boot
scenario.
Bellow is sample ITS file that generates a FIT image supporting
secure boot. Please note the presence of 'os = "efi";' line, which
identifies the currently introduced OS type:
/ {
#address-cells = <1>;
images {
efi-grub {
description = "GRUB EFI";
data = /incbin/("bootarm.efi");
type = "kernel_noload";
arch = "arm";
os = "efi";
compression = "none";
load = <0x0>;
entry = <0x0>;
hash-1 {
algo = "sha256";
};
};
};
configurations {
default = "config-grub";
config-grub {
kernel = "efi-grub";
signature-1 {
algo = "sha256,rsa2048";
sign-images = "kernel";
};
};
};
};
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
When we hit a matching GUID we can directly return the text. There is no
need for a check after the loop.
efi_guid_t is defined as 8 byte aligned but GUIDs in packed structures do
not follow this alignment. Do not require the argument of get_guid_text()
to be correctly aligned.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Of all warning status codes up to now only EFI_WARN_DELETE_FAILURE is
defined.
The patch adds the missing definitions for later usage.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
When be launch a binary via bootefi the bootargs environment variable is
used to set the load options in the loaded image protocol.
Free memory allocated for load options when the UEFI binary exits.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add guidcpy function to copy the source guid to the destination
guid. Use this function instead of memcpy for copying to the
destination guid.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Use void * instead of efi_guid_t * for arguments to allow copying unaligned
GUIDs. The GUIDs of configuration tables are __packed.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
U-Boot can be compiled with function tracing enabled.
When compiling with FTRACE __cyg_profile_func_enter() is called when a
function is entered and __cyg_profile_func_exit() when the function is
left.
To avoid a crash we have to define these function for the free-standing
UEFI binaries.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add a comment indicating that the value of GPT_HEADER_SIGNATURE_UBOOT
equals the ASCII string 'EFI PART'.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
On a VT100 terminal <ESC>[2J should be enough to both clear the whole
screen and set the cursor to position (1, 1). But the Linux console does
not behave like this. So send an extra <ESC>[H. For reference see the
console_codes(4) man page.
Add a function description.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add the following file to .gitignore
efi_miniapp_file_image_exception.h
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Use efi_miniapp_*.h instead of file enumeration.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Use a pointer to addressable memory instead of a "physical" address in the
virtual address space of the sandbox to efi_install_fdt().
Export the efi_install_fdt() function.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
If the bootefi command is called without passing the address of a device
tree, the internal device tree is used. For devices with a hardware device
tree it is preferable to used the hardware device tree in this case.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
As part of moving the parsing of command line arguments to do_bootefi()
call efi_install_fdt() with the address of the device tree instead of a
string.
If the address is EFI_FDT_USE_INTERNAL (= 0), the internal device tree
is used.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
When the GetInfo() method of the EFI_FILE_PROTOCOL is called to retrieve
the file system info we claim that the volume is read only and has no free
space. This leads to failures in programs that check this information
before writing to the volume like SCT's InstallSct.efi.
Currently there is no function to determine these parameters in U-Boot. So
let's return optimistic values:
Return that the volume is writable.
Return the volume size as free space.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
UEFI applications like GRUB and SCT assume that function keys are enabled
on the keyboard.
Let EFI_LOADER imply USB_KEYBOARD_FN_KEYS.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The index (IMAGE_DIRECTORY_ENTRY_SECURITY) in a table points to
a region containing authentication information (image's signature)
in PE format.
WIN_CERTIFICATE structure defines an embedded signature format.
Those definitions will be used in my UEFI secure boot patch.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Consider the following test sample:
@pytest.mark.buildconfigspec('fit')
@pytest.mark.notbuildconfigspec('generate_acpi_table')
def test_sample(u_boot_console):
Whatever the argument of the 'notbuildconfigspec' is,
the test ends up being skipped with the message:
('/uboot/test/py/conftest.py', 463,
'Skipped: .config feature "fit" enabled')
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
if MULTI_DTB_FIT is enabled it is helpful to display
the value of gd->multi_dtb_fit in bdinfo.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is black magic in the file conftest.py that list
all the test unit. Then, all those test unit are called
in pytest. This call is done with the end of the name
(for example checksum if the full name is bloblist_test_checksum).
The result is that only test for dm are really executed.
by pytest, all others tests are listed but never executed.
This behaviour happens because the dm test unit only check
the end of the name and others tests checks the full name.
To fix this issue, I've added a prefix to the function
cmd_ut_category, and this prefix is removed when looking
for the unit test.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Load the optional resource table from the firmware, and write its
address in the dedicated backup register.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Since the coprocessor state is tracked in a backup register, there is
no more need for tracking it in an environment variable : remove it.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Update the dedicated backup register to track the coprocessor state and
rely on that register to compute the .is_running() value (which expects
a return value of 0 -not 1- if the processor is running).
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Reset ResourceTableAddress and CoprocessorState at cold boot, preserve
these values at standby wakeup.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Use the backup register #17 as coprocessor resource table address and
backup register #18 as coprocessor state.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Add rproc_elf_load_rsc_table(), which searches for a resource table in
an elf64/elf32 image, and if found, copies it to device memory.
Add also the elf32 and elf64 variants of this API.
Add a test for this.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
spl_fit_get_image_name() is used to get the names of the images that the
SPL must load from the FIT. It relies on the content of a property present
in the FIT. The list of images is thus statically defined in the FIT.
With this scheme, it quickly becomes hard to manage combinations of more
than a handful of images.
To address this problem, give the board driver code the opportunity to
add to the list of images. The images from the FIT property are loaded
first, and then the board_get_fit_loadable() is called to get more image
names.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If u-boot.img is a FIT image, CONFIG_OF_OVERLAY_LIST can be used to add
DT overlays to u-boot.img.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Useful to avoid #ifdef throughout the code that uses the board driver API.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This function will be used by the SPL to get the names of images to load
from the FIT. This allows to load different images based on runtime HW
detection.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make the board driver available in the SPL too. The board driver is a way
to provide useful information about the board and that can be useful in
the SPL too.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no need for it to be non-constant. Making it constant, allows to
return constant string without warning.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In order to apply an overlay to a DTB. The DTB must have been generated
with the option '-@'.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There are many ways the overlay application can fail.
2 of them are probably the most common:
- the application itself failed. Usually this is comes from an unresolved
reference
- DTBO not available in FIT (could be because of a typo)
In both case it is good to be more explicit about the error and at least
show which overlay is failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If one overlay that must be applied cannot be found in the FIT, the current
implementation stops applying the overlays. Let's make it skip only the
failing overlay instead.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If the node describing an overlay does not specify a load address, it will
be loaded at the address previously used.
Fixing it by allocating a temporary buffer that will be used as a
default load address. By default, the size of the buffer is 64kB which
should be plenty for most use cases.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make room in the FDT before applying the overlay, otherwise it may fail if
the overlay is big. As the exact added size is not known in advance, just
add the size of the overlay.
Move after the end of the application of the overlays, the resize of the
FDT for the injection of the details on the loadables.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
doc/uImage.FIT/overlay-fdt-boot.txt is describing how to create FIT
image with DT overlays in it.
Add support for this feature to SPL.
Here is the ZynqMP fragment where dtb points to full DT and dtbo is
overlay which should be applied on the top of dtb.
config {
description = "ATF with full u-boot overlay";
firmware = "atf";
loadables = "uboot";
fdt = "dtb", "dtbo";
};
The whole feature depends on OF_LIBFDT_OVERLAY which is adding +4kB code
and 0 for platforms which are not enabling this feature.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When u-boot.img is a FIT image generated automatically by mkimage, the
configuration node has the following structure:
conf-1 {
description = "k3-am654-base-board";
firmware = "firmware-1";
loadables = "firmware-1";
fdt = "fdt-1";
};
The firmware is referenced twice. Once by the 'firmware' property and
once by the 'loadables' property. Currently this result in the firmware
being loaded twice. This is not a big problem but has an impact on the
boot time.
Fixing it by not loading a loadable image if it is also the firmware image.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
This has the same result but some compilers will warn about this
fall-through if there are statements as part of the label block.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This is very similar to fit_image_get_data but has the benefit of working
on FIT images with external data unlike fit_image_get_data. This is
useful for extracting sub-images from type of FIT image as this would
previously just silently fail. Add an error message also so if this
still fails it is easier to find out why.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The dumpimage utility errors out in a number of places without providing
sufficient feedback to allow the user to easily determine what has gone
wrong. Add additional error messages to make the cause of the failure
more obvious.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
commit a10388dc69 ("mmc: meson-gx: add support for mmc-pwrseq-emmc")
introduce CONFIG_PWRSEQ for power sequence for eMMC module on
amlogic platform, so enable this to all amlogic boards.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Khadas VIM3L uses the same board layout as VIM3, but with an S905D3 chip
instead of A311D. Board config is derived from khadas-vim3_defconfig and
sei610_defconfig. README is based on README.khadas-vim3; the difference
is that VIM3L uses FIP files from the g12a folder in vendor sources not
the g12b folder.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added vim3l readme into w400 MAINTAINERS]
First set of u-boot-atmel features for 2020.04 cycle
This feature set is a patch series from Tudor Ambarus which includes
parsing of the spi flash SFDP parser for SST flashes, and using those
tables to retrieve unique saved per device MAC address. This is then
used as base mac address on the SAMA5D2 Wireless SOM EK board.
The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.
The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
This fixes a merge error that accidentally left CONFIG_MTD_DEVICE
active by removing it from the config file.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add device tree files for Agilex SoC platform.
socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
Uboot specific DT properties.
socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux
(kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc)
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.
Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.
agilex-clock.h is from Linux commit ID cd2e1ad12247.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.
SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add base address for Intel Agilex SoC.
Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get reset manager base address from DT node instead of using
#define.
spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
In preparation to get base address from DT.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The stock U-Boot on Intel Edison has timeout parameter for DFU command.
Enable it here to be compatible with the original U-Boot configuration.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
When the `dfu` command is called from the U-Boot environment,
it now accepts an optional parameter that specifies a timeout (in seconds).
If a DFU connection is not made within that time the `dfu` command exits
(as it would if Ctrl+C was pressed). If the timeout is left empty or being
zero the `dfu` command behaves as it does now.
This is useful for allowing U-Boot to check to see if anything wants to
upload new firmware before continuing to boot.
The patch is based on the commit
5e966ccc3c
by Sebastien Colleur, which has been heavily reworked due to U-Boot changes
in the past.
Signed-off-by: Brad Campbell <bradjc5@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
In the future we may utilize optional argument in 'dfu' command line.
As a preparation for this, refactor do_dfu().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
After the commit 1cc03c5c53 ("dfu: Provide means to find difference between
dfu-util -e and -R") the dangling ptototype appeared. Remove it here.
Fixes: 1cc03c5c53 ("dfu: Provide means to find difference between dfu-util -e and -R")
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Import the Khadas VIM3L device-tree from [1]
[1] e42617b825f8 ("Linux 5.5-rc1")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
These files should not be included in meson header files. Drop them and
tidy up the affected C files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
It's true that booting normally doesn't take long enough for the
register to roll (which actually happens in a little over an hour, not
just a few seconds). However, the counter starts at power-on, and if
the board is held in reset to be booted over USB, one actually risks
hitting wrap-around during boot, which can both result in too short
delays (if the "st += delay" calculation makes st small) and
theoretically also unbound delays (if st ends up being UINT_MAX and
one just misses sampling digctl_microseconds at that point).
It doesn't take more code to DTRT, and once bitten, twice shy.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Engicam i.CoreM6 1.5 Quad/Dual MIPI dtsi is reusing fec node
from Engicam i.CoreM6 dtsi but have sampe copy of phy-reset-gpio
and phy-mode properties.
So, drop this phy reset methods from imx6qdl-icore-1.5 dsti file.
Cc: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation is based on
the 1.5 version of the i.Core MX6 cpu module. The 1.5 version
differs from the original one for a few details, including the
ethernet PHY interface clock provider.
With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver
While before using the 1.5 version, ethernet failed to startup
do to un-clocked PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY
Similar fix has merged for i.Core MX6Q but missed to update for DL.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Now all the fec related phy properties are now accessible
via dts. So drop the explicit config items from common
config file, imx6-engicam.h
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
According to the SOM and reference board the clock
can be taken from the external pin or provided from
ENET_REF_CLK. Add a new function that make the proper
set according the board type.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Make easy to map fdt file to board in order to use
this information later to apply specific change to
specific board combination.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The data sheet says that the DIV field cannot change while the CLKGATE
bit is set or modified. So do it a little more carefully, by first
clearing the bit, waiting for that to appear, then setting the DIV
field.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The comment says to clear the bypass bit, but in fact it sets it, thus
selecting ref_xtal. And the next line of code does not set the divider
to 12, but to (the reset value of) 1.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
I tried clearing a bit by writing to hw_clkctrl_gpmi_clr, then
busy-waiting for it to actually clear. My board hung. The data sheet
agrees, these registers do not have _set, _clr, _tog, so fix up the
definitions. git grep -E 'clkctrl_(gpmi|ssp[0-9])_' says that nobody
uses those non-existing ops registers.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Adjust the environment for booting a mainline kernel by default.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.
Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
The DDR firmware binaries are not part of the U-Boot source code, so
we should look for them in the build directory, where they need to be
copied to before building U-Boot.
The ATF binary is already fetched from the build directory, but the
README files for the i.MX8M EVKs claim that it needs to be copied to
the source directory (which is still true for in-tree builds, but not
in general). Therefore we also fix the READMEs to use the build
directory as the correct location for all additional binary files.
Sined-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
In the case of i.MX6 and i.MX7 family SoCs it is safe (from an errata
point of view) to use thumb2 by default to save space.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Currently imx-specific bootaux command doesn't support ELF format
firmware for Cortex-M4 core.
This patches introduces a PoC implementation of handling elf firmware
(load_elf_image_phdr() was copy-pasted from elf.c just for PoC).
ELF64 binaries isn't supported yet.
This has the advantage that the user does not need to know to which
address the binary has been linked to. However, in order to handle
and load the elf sections to the right address, we need to translate the
Cortex-M4 core memory addresses to primary/host CPU memory
addresses (Cortex A7/A9 cores).
This allows to boot firmwares from any location with just using
bootaux, e.g.:
> tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr}
Similar translation table can be found in the Linux remoteproc
driver [1].
[1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Sync DTS with the mainline Linux and introduce fec node and
regulator configuration for rn5t567 PMU.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
The Embedded Artists COM board is based on NXP i.MX7ULP.
It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).
Add the initial support for the board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
We switch from custom boot commands relying on uEnv.txt to distro boot.
This removes the automatic fpga bitstream loading in favor of loading
bitstreams via custom bootscripts (boot.scr) or after booting the
kernel.
Acked-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Note: gpio7_8 was never used for usb power regulator so we remove it here
Acked-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Sync the Linux Kernel 5.4-rc6 device tree for Phytec Phycore
SoM and Segin board based on imx6UL and imx6ULL.
Changes includes Phytec naming convention for the devicetree files.
Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
This patch fixes the issue with broken bootaux command,
when M4 binary is loaded and data cache isn't flushed
before M4 core is enabled.
Reproducing:
> tftpboot ${loadaddr} ${board_name}/hello_world.bin
> cp.b ${loadaddr} 0x7F8000 $filesize
> bootaux 0x7F8000
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
1. Change information printed about loaded M4 binary, print the stack
pointer and reset vector addressed.
2. Add sanity check for the address provided as param.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Enable driver model for SPI and SPI_FLASH to remove the following
compile warning on CM-FX6 SOM:
===================== WARNING ======================
This board does not use CONFIG_DM_SPI_FLASH. Please update
the board to use CONFIG_SPI_FLASH before the v2019.07 release.
====================================================
This change introduced SPL build error as shown:
In file included from include/common.h:47:0,
from drivers/mtd/spi/sf_probe.c:10:
drivers/mtd/spi/sf_probe.c: In function 'spi_flash_std_probe':
drivers/mtd/spi/sf_probe.c:149:54: error: dereferencing pointer to incomplete type 'struct dm_spi_slave_platdata'
scripts/Makefile.build:278: recipe for target 'spl/drivers/mtd/spi/sf_probe.o' failed
make[3]: *** [spl/drivers/mtd/spi/sf_probe.o] Error 1
scripts/Makefile.build:432: recipe for target 'spl/drivers/mtd/spi' failed
make[2]: *** [spl/drivers/mtd/spi] Error 2
Disabling DM for SPI support(SPI and SF) in SPL resolves the issue.
Target was compile tested, build was clean.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Enable CONFIG_DM_ETH to remove compile warning on CM-FX6
SOM based target:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release.
====================================================
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Enable driver model for Video to remove the following
compile warning on CM-FX6 SOM based target:
===================== WARNING ======================
This board does not use CONFIG_DM_VIDEO Please update
the board to use CONFIG_DM_VIDEO before the v2019.07 release.
====================================================
This change introduced build error as shown:
LD u-boot
drivers/built-in.o: In function ipu_displays_init'
arm-linux-ld.bfd: BFD (GNU Binutils) 2.29.1 assertion fail elf32-arm.c:9509
Makefile:1621: recipe for target 'u-boot' failed
make: *** [u-boot] Error 1
The DM converted video driver calls ipu_displays_init
in its probe, which inturn calls relevant board_video_skip.
Defining ipu_displays_init in the board file fixes build error.
Target was compile tested, build was clean.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
This patch adds support for iMX6SX MMDC into the DDR calibration
code. The only difference between MX6DQ and MX6SX is that the SX
has 2 SDQS registers, while the DQ has 8.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
Pull out the code turning SDQS pullups on and off into a separate
function, since it is replicated in two places in the code and it
is the single place in the entire function which is SoC dependent.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
The %08X format returns just zeroes with tiny printf, which is
horribly confusing, especially when debugging DRAM calibration
problems. Change the format to %08x (with lowercase x), which
behaves correctly with either implementation of printf in SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
The SPL does not have DM enabled and therefor still needs to use the
hardware watchdog interface provided by the imx-watchdog driver.
Fixes: broken reset command after f2929d11a6 ("watchdog: imx: Use
immediate reset bits for expire_now")
Signed-off-by: Claudius Heine <ch@denx.de>
The wdt-reboot node is needed for the sysreset_watchdog driver to
register a watchdog as a reset handler in case 'CONFIG_SYSRESET' is
enabled.
Signed-off-by: Claudius Heine <ch@denx.de>
Make first step in DT/DM migration. Enable OF_CONTROL only for the main
U-Boot image for now.
Remove mmc_init_main() because board_mmc_init() is not called when
DM_MMC is enabled.
DM_MMC requires DM_GPIO for card-detect to work. That in turn makes gpio
request mandatory. Add code to request/free gpios in platform code.
MMC devices are now numbered according to DT. The SD card is 1, and eMMC
is 2. Account for that in board_mmc_get_env_dev(), BOOT_TARGET_DEVICES,
and has_emmc().
DM_MMC requires BLK. However, the (BLK && !DM_USB) combination disables
USB_STORAGE. Enable DM_USB to preserve USB functionality. Add also
DM_REGULATORS for the USB power controller. This allows us to drop
board_ehci_hcd_init() and setup_usb().
Runtime selection of DT is necessary because of the i.MX6QD vs i.MX6SDL
incompatibility. DT selection does not rely on GPIOs, since DM_GPIO
depends on DT. Instead, we take one "fully featured" DT of each variant.
That should be enough to boot from both SD card and eMMC.
Since we don't select the exact DT, override the generic
show_board_info() that shows the selected DT 'model' field.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
These DT files are copied from kernel v5.3 with no changes.
This is part 2 of 2 commits. Included are DT files for SOM rev 1.5, and
Hummingboard2 Gate/Edge.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
These DT files are copied from kernel v5.3 with no changes.
This is part 1 of 2 commits. Included are DT files for the original
Cubox-i and Hummingboard Base/Pro.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Import fsl-imx-audmux.h from Linux as of v5.4-rc6. The header is
unchanged since v4.18.
That would make it easier to import DT files that depend on imx-audmux
definitions from the kernel tree.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Pass rtc_status via the device tree, instead of on kernel command line.
Additionally, the 2038 mitigation is reported, if applied successfully.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
DM for PCI pulls DM for ethernet that also needs other changes described
below to build u-boot and keep existing functionality - ability to update
MAC addresses of FEC ethernet adapter and I210 adapter connected to the
Marvell switch.
- fec_mxc driver with DM needs PHYLIB;
- configuration items are moved from ge_bx50v3.h to ge_bx50v3_defconfig;
- FEC is marked as eth0 because it is always present, so indices changed:
I210 are still probed in the same order;
- board_eth_init() was used by legacy ethernet, setup for enet iomux and
pcie is moved to the board_late_init();
- pci_init() is called from the board_late_init() to initiate PCI bus
probing, so I210 devices are propagated to the device tree;
Signed-off-by: Denis Zalevskiy <denis.zalevskiy@ge.com>
[Describe PHY reset in device tree]
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
DM should be used for USB since 2019.07, it also requires DM for
regulators.
Signed-off-by: Denis Zalevskiy <denis.zalevskiy@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Use vidconsole for output to the LCD, now that DM_VIDEO is used. Write
white text on a black background, like before migrating to DM_VIDEO.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Fix GPIO reservation warning on code paths that do not need LVDS power.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Copy device trees from linux, keeping them as separate files for
each board to ease future sync.
Update board code to use generic bx50v3 dt initially, then select
the specific dt based on board detection.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
This patch introduces support for i.MX28 based XEA board.
This board supports DM/DTS in U-Boot proper as well as DM aware drivers
in SPL (u-boot.sb) by using OF_PLATDATA.
More detailed information regarding usage of it can be found in
./board/liebherr/xea/README file.
U-Boot SPL 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200)
Trying to boot from MMC1
MMC0: Command 8 timeout (status 0xf0344020)
mmc_load_image_raw_sector: mmc block read error
U-Boot 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200)
CPU: Freescale i.MX28 rev1.2 at 454 MHz
BOOT: SSP SPI #3, master, 3V3 NOR
Model: Liebherr (LWE) XEA i.MX28 Board
DRAM: 128 MiB
MMC: MXS MMC: 0
Loading Environment from SPI Flash... SF: Detected n25q128a13 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
OK
In: serial
Out: serial
Err: serial
Net:
Warning: ethernet@800f0000 (eth0) using random MAC address - ce:e1:9e:46:f3:a2
eth0: ethernet@800f0000
Hit any key to stop autoboot: 0
Signed-off-by: Lukasz Majewski <lukma@denx.de>
sync defaut Envoronment with customer changes.
Unfortunately they are not changeable, as already
board is in production mode.
Get rid of the big bootcommand and set bootcommand
through Kconfig option.
Signed-off-by: Heiko Schocher <hs@denx.de>
add DM_VIDEO support and remove now unneeded board
code. As we show a bmp logo on boot, call now
bmp_display() from board code and do not use
cfb_console anymore.
Signed-off-by: Heiko Schocher <hs@denx.de>
enable CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH
and get rid of build removal warnings.
define CONFIG_GPIO_ENABLE_SPI_FLASH is not longer
needed, so remove it from config_whitelist.txt
Signed-off-by: Heiko Schocher <hs@denx.de>
Enable DM_GPIO, GPIO_HOG, LED and LED_GPIO as gpio
and LEDs are now defined in DTS. Enable also here
the pinctrl driver, so pinmux setup is also done.
Signed-off-by: Heiko Schocher <hs@denx.de>
add DM_SERIAL support for the aristainetos board, and
remove not used code from board code.
remove CONSOLE_OVERWRITE_ROUTINE.
Signed-off-by: Heiko Schocher <hs@denx.de>
as we switch to support DM and DTS, rework the existing
DTS trees. Change also Linux specific Device trees, goal
is to push this changes to linux.
Collect U-Boot specific changes in separate "*u-boot*" dts
files.
Signed-off-by: Heiko Schocher <hs@denx.de>
remove aristainetos-v2.c file, as we now want to
switch to DM/DTS support and have all board specific
code in one file. Goal is to setup differences
through DT.
Signed-off-by: Heiko Schocher <hs@denx.de>
Add device trees from Linux in preparation for driver model
conversions.
device tree files taken from Linux:
71ae5fc87c34: "Merge tag 'linux-kselftest-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest"
and added SPDX license identifier.
Signed-off-by: Heiko Schocher <hs@denx.de>
remove 2b version of aristainetos board, as it
is easier to make the DM / DTS port and introduce
the 2b board version again (also some more board
version).
Signed-off-by: Heiko Schocher <hs@denx.de>
Adam Ford reports that this change breaks booting on da850-evm and
Bartosz Golaszewski agrees that with the impending release we should
revert the change for now. With that noted:
This reverts commit 21a4d80a71.
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
cacheable write back/write allocate memory region and later
on software execute barrier operation (DSB or DMB). R5F may
hang at the barrier instruction.
2.When software is performing a mix of load and store operations
within a tight loop and store operations are all writing to
cacheable write back/write allocates memory regions, R5F may
hang at one of the load instruction.
To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
The build failure was originally reported on arm64-musl
target at https://bugs.gentoo.org/703132. Here is the amd64-musl
variant:
```
$ LANG=C make CROSS_COMPILE=x86_64-gentoo-linux-musl- tools-only_defconfig -j$(nproc)
$ LANG=C make CROSS_COMPILE=x86_64-gentoo-linux-musl- tools-all -j$(nproc)
...
include/u-boot/crc.h:37:44: error: unknown type name 'uint'; did you mean 'int'?
37 | void crc16_ccitt_wd_buf(const uint8_t *in, uint len,
| ^~~~
| int
```
Note: 'uint' is not defined there.
On glibc 'uint' comes from <sys/types.h> and happens to work on most .c files.
The change imports 'uint' declaration from '<compiler.h>'.
Bug: https://bugs.gentoo.org/703132
Signed-off-by: Sergei Trofimovich <slyfox@gentoo.org>
The build failure was originally reported on arm64-musl
target at https://bugs.gentoo.org/703132. Here is the amd64-musl
variant:
```
$ LANG=C make CROSS_COMPILE=x86_64-gentoo-linux-musl- tools-only_defconfig -j$(nproc)
$ LANG=C make CROSS_COMPILE=x86_64-gentoo-linux-musl- tools-all -j$(nproc)
...
In file included from tools/env/../../env/flags.c:7,
from tools/env/env_flags.c:1:
include/env.h:159:1: error: unknown type name 'ulong'; did you mean 'long'?
159 | ulong env_get_ulong(const char *name, int base, ulong default_val);
| ^~~~~
| long
```
Note: 'ulong' is not defined there.
On glibc 'ulong' comes from <sys/types.h>:
```c
/* Old compatibility names for C types. */
typedef unsigned long int ulong;
```
On musl it comes from <sys/types.h> as well but from under different guards:
```c
typedef unsigned long u_long, ulong;
```
The change inlines 'ulong' define similar to 'uint' define.
Bug: https://bugs.gentoo.org/703132
Signed-off-by: Sergei Trofimovich <slyfox@gentoo.org>
The scripts/Makefile.lib generates an assembler file (*.S) to wrap the
font data for each file of type ttf defined in Kconfig.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
- Fix latest mainline kernel for rk3308
- Update rk3288-evb config to suport OP-TEE
- Fix for firefly-px30 DEBUG_UART channel and make it standalone
- Script make_fit_atf add python3 support
- Fix rk3328 timer with correct COUNTER_FREQUENCY
- Fix rk3328 ATF support with enable spl-fifo-mode
My address at Linaro doesn't exist anymore, so people
keep getting mail delivery error responses. Map this address
to the actual one.
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
get_env() was originally written to strip() the output of printenv to
isolate the test from any whitespace changes in printenv's output.
However, this throws away any whitespace in the variable value, which can
cause issues when test code expects to see that whitespace. In fact,
printenv never adds any whitespace at all, so there's no need to strip.
The strip causes a practical problem for test_env_echo_exists() if
state_test_env.get_existent_var() happens to choose a U-Boot variable that
contains trailing whitespace. This is true for variable boot_targets.
With Python 2, get_existent_var() never returned boot_targets so this
issue never caused a practical problem.
With Python 3, get_existent_var does sometimes return boot_targets, no
doubt due to Python 3's different dict hash key order implementation,
about 0.5-2% of the time, so this test appears intermittent. With the
strip removed, this intermittency is solved, since the test passes for all
possible U-Boot variables.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
As described in doc/README.asn1 document the tools/asn1_compiler is used
to "generate bytecode as a C file (*.asn1.[ch]) from *.asn1 file".
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Add the tool to the ignore list to prevent being marked as unversioned.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.
Change the #ifdefs to use IS_ENABLED(), etc., instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.
Change the #ifdefs to use CONFIG_IS_ENABLED() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.
Change the #ifdefs to use IS_ENABLED() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.
Change the #ifdefs to use IS_ENABLED() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most x86 boards that use video make use of 32bpp graphics. Enable this by
default. This fixes missing graphics output on some x86 boards.
Also remove the unnecessary 'default n' while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
The ep node device tree name is governed by these bindings:
https://github.com/torvalds/linux/blob/master/Documentation/
devicetree/bindings/pci/layerscape-pci.txt#L24
As per above the ep compatible node contains platform name.
Therefore, define the ep node compatible as CONFIG to find the
pcie ep node in device tree during device tree fixup.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
move the PCIE related config from arch Kconfig to PCI Kconfig.
As the PCI_LAYERSCAPE driver is being used in platform other than
fsl-layerscape platforms like ls102xa.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable the ATF in SPL and adjust the SPL STACK/HEAD at the same time to
support ATF entry at 0x40000.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The arch timer needs COUNTER_FREQUENCY to get correct counter, add it to
make the timer works correct.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The omap3_beagle NAND ECC scheme was changed in 4b37928d35 for unknown
reasons, leading to uncorrectible ecc errors. This commit changes it
back to what it was before.
Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
The board_boot_order() function currenly assumes that the boot source
is MMC/eMMC, but this isn't true for the NAND devices.
This patch cleans up board_boot_order() to check for NAND, SD, ESD,
MMC or EMMC. Anything beyond these are not supported, so it will
default back to the serial downloader if any of those devices are not
available.
Fixes: 9fb50c68da ("ARM: imx6q_logic: Fix MMC2 booting")
Signed-off-by: Adam Ford <aford173@gmail.com>
This fixes commit <91435cd40d30> "ARM: i.MX6: exclude the ARM errata
from i.MX6 UP system"
for nitrogen6x. The above commit removed the errata for the board
since MX6Q/MXDL/MX6S is selected via CONFIG_SYS_EXTRA_OPTIONS
This restores the errata configs.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.
Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.
Note, that the size is further divided into 'minus 1' while writing
into CTRLR1.
This change fixed two different read issues,
1. sf read failure when with > 0x10000
2. Boot from SPI flash failed during spi_flash_read call in
common/spl/spl_spi.c
Observed and Tested in
- Rockpro64 with Gigadevice flash
- ROC-RK3399-PC with Winbond flash
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Static checker warns 'ret' variable may be used uninitialized in
spi_nor_erase() and spi_nor_write() in case of zero length requests.
Fix these warnings by checking for zero length requests and returning
early.
Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
IMX based platforms can have the DCD table located on different
addresses due to differences in their memory maps (ie iMX7ULP).
This information is required by the user to sign the images for secure
boot so continue making it accessible via mkimage.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
Following the README instructions leads to a non-booting
U-Boot:
U-Boot SPL 2020.01-rc3-00070-g9a0cbae22a (Nov 25 2019 - 13:08:24 -0300)
PMIC: PFUZE100 ID=0x10
DDRINFO: start DRAM init
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Trying to boot from MMC2
(It hangs here)
Use the "imx_4.19.35_1.0.0" ATF branch instead, which
fixes such problem and allow the boot to complete again.
Suggested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Passing earlycon string in the command line may be
useful during bring up, but not after such phase.
Remove the earlycon string to align with the other i.MX SoCs
command lines.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Currently inside ddr_init() there is a mix of printf() and debug()
level messages.
Since this type of information is useful for debug purposes,
convert all of them to debug level for consistency.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.
Running "saveenv" followed by a "reset" causes U-Boot to hang because
of this overlap.
Fix this problem by increasing the CONFIG_ENV_OFFSET size.
Also, in order to prevent this same problem to happen in the future,
use CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time.
CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare
CONFIG_ENV_OFFSET with its direct value instead.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
After the DM conversion the boot SD card is now device 3.
Adjust it so that we can boot the kernel again.
While at it avoid a hardcoded mmc dev inside the finduuid script.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Currently the following hang is observed when booting a imx6sx-sdb
board:
U-Boot 2020.01-rc5-00004-g643366bcd5 (Dec 19 2019 - 14:56:23 -0300)
CPU: Freescale i.MX6SX rev1.0 996 MHz (running at 792 MHz)
CPU: Extended Commercial temperature grade (-20C to 105C) at 32C
Reset cause: POR
Model: Freescale i.MX6 SoloX SDB RevB Board
Board: MX6SX SABRE SDB revA
DRAM: 1 GiB
initcall sequence bffd8514 failed at call 87804cc0 (err=-19)
### ERROR ### Please RESET the board ###
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address.
Fix the pmic_get() parameter to fix the boot regression.
Tested on a imx6sx-sdb and imx6q-sabresd boards.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Not all CONFIG_FSL_ESDHC defines were properly replaced with
CONFIG_FSL_ESDHC_IMX, which broke U-boot proper booting on
Colibri iMX6 SoMs.
U-boot is stuck after this message:
Commercial temperature grade DDR3 timings, 64bit bus width.
Trying to boot from MMC1
Fixes: e37ac717d7("Convert to use fsl_esdhc_imx for i.MX platforms")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
The defconfig file for ROC-CC-RK3308 is roc-cc-rk3308_defconfig.
Fixes: 7f08bfb74f ("doc: rockchip: Add documentation for rk3308 based
boards")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When compile the curren mainline linux kernel(Linux 5.5-rc3)
with defconfig, the final Image is 29M, it's much
larger than Linux 5.4.
On the current u-boot side on rk3308, the gap between
kernel and fdt is 25M, the fdt will overwrite kernel
Image, so move ftd to a higher memory to give 34M
gab for them.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but
this one doesn't for some reason. Add a description to make the menu
easier to read.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot
proper will use the dts setting to do the IOMUX init, and a separate dts
is needed for px30-firefly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The Macro has update without update the defconfig, update the defconfig
to make Mcaro correct.
Fixes: ec4fafdf1f ("rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to...")
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
On a distribution with no python2 installed and no
python->python3 symlink the script will fail to execute.
Specify python3 explicitly as it's already a requirement
to build u-boot.
Signed-off-by: Jack Mitchell <ml@embed.me.uk>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence"
in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX.
[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
For increased DPLL stability use the settings recommended in
the TRM [1] for PHY_RX registers for SATA and USB.
For SATA we need to use spread spectrum settings even
though we don't have spread spectrum enabled. The
suggested non-spread spectrum settings don't work.
[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Introduce a mode property in the driver data so that
we don't have to keep using "of_device_is_compatible()"
throughtout the driver.
No functional change.
Signed-off-by: Roger Quadros <rogerq@ti.com>
The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.
Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.
[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Upstream kernel and rockchip kernel has default enable PSCI which needs
OPTEE in trust word, enable OPTEE support for evb by default and SPL_FIT
option to pack OPTEE with U-Boot proper.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Update the SPL_STACK_R_MALLOC_SIMPLE_LEN which also including space for
STACK and the size may not enough when loding FIT image in SPL.
If the size is not enough, you can see log like this when loding FIT:
U-Boot TPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53)
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53 +0800)
Trying to boot from MMC2
And if enable the DEBUG for everyting in SPL, the log will hang at dwmmc
sending CMD16 for 'uboot' loadables binary because this step need a
large stack cost(about 0x2d00).
External data: dst=8400000, offset=72638, size=b3580
Image OS is Trusted Execution Environment
board_fit_config_name_match: rk3288-evb
Selecting config 'rk3288-evb'loadables: 'uboot'
blk_find_device: if_type=6, devnum=1: dwmmc@ff0c0000.blk, 6, 0
blk_find_device: if_type=6, devnum=1: dwmmc@ff0f0000.blk, 6, 1
Sending CMD16
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Instead of hardcode the base address, we can get them from the build
output, eg. get the SYS_TEXT_BASE from .config and get optee base from
DRAM_BASE.
We can use this script for SoCs with DRAM base not from 0x60000000(rk3229
and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Update API names for layerscape gen4 fixup.
Suffix layerscape_gen4 fixup API names with _ls_gen4.
This is required to organize device tree fixup in common, layerscape
and layerscape_gen4 specific code.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Suffix layerscape fixup API names with _ls.
This is required to organize device tree fixup in common,
layerscape and layerscape_gen4 specific code.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add stream_id_cur field to ls_pcie structure and initialize
it with 0 for all pcie controllers. This field will be used
for streamId calculation.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses
pcie_layerscape driver.
Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4.
Based on SoC and revision pcie controller probe will be invoked.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable DP_PWR signal to power the DP to HDMI converter cable.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Current implementation to get board version through GPIO is
broken due to endianness issue hence it is not working for rev B
board.
Fix it to make it work for Rev A as well as Rev B boards
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
In commit <db4080d56dec>, SPL_FSL_PBL is removed from the configs of
some LayerScape platforms. Actually, SPL_FSL_PBL is needed for SD/NAND
boot on LS1021A/LS1043A/LS1046A to create boot binary having SPL binary
in PBI format concatenated with u-boot binary. SPL_FRAMEWORK is used on
these platforms too.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
LX2160A PL011 UART driver fetch IP block values using
platform data from board file instead of device tree.
Modified UART nodes in device tree to disable state.
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Mark board_fit_config_name_match() as weak so a board can overwrite the
empty function.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Maximum size of secure boot header to be read from MMC is
12KB which spans across 0x20 blocks.
Hence increase the mmc read size for secure boot
headers from MMC to 0x20 blocks.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add support for DPSPARSER object (create/destroy, open/close, apply spb)
which is required to configure Soft Parser by using MC.
Also add uboot command to apply Soft Parser Blob with command:
fsl_mc apply spb <spb_load_addr>
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
- Enable DM driver on ppc/km boards
- Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
T104x, P4080, P2041, P2020, P1020, P3041
- Some updates in mpc85xx-ddr driver, km boards
Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.
The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.
So, handle the phy masking bits accordingly on respective interface
type cases.
Fixes: 6b7ebff001 ("usb: dwc3: Add phy interface for dwc3_uboot")
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Since, commit 62f9b65447 ("common: Move older CPU functions to their own header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
In the case where one deletes an already-non-existing variable, or sets
a variable to the value it already has, there is no point in writing the
environment back, thus reducing wear on the underlying storage
device.
In the case of redundant environments, if the two environments
differ (e.g. because one is corrupt), make sure that any call of
fw_setenv causes the two to become synchronized, even if the fw_setenv
call does not change anything in the good copy.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in
the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or
is scanning the bus, passing -1 here should keep it functional either way.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Cc: Jiandong Zheng <jdzheng@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
struct sunxi_prcm_reg is naturally packed. There is no need to define it as
packed. Defining it as packed leads to compilation errors with GCC 9.2.1:
CC arch/arm/lib/reloc_arm_efi.o
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
:qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed
member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
163 | sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
Remove __packed attribute from struct sunxi_prcm_reg.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Orangepi Zero Plus 2 is an open-source single-board computer, available
in two Allwinner SOC variants, H3 and H5. We add support for H3 variant
here, as the H5 is already supported.
H3 Orangepi Zero Plus 2 has:
- Quad-core Cortex-A7
- 512MB DDR3
- microSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG + power supply
Sync dts from linux v5.2 commit:
"ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry"
(sha1: 75f9a058838be9880afd75c4cb14e1bf4fe34a0b)
Commit:
"ARM: dts: sun8i: h3: Refactor the pinctrl node names"
(sha1: a4dc791974e568a15f7f37131729b1a6912f4811)
has been avoided as it breaks U-Boot build.
Signed-off-by: Diego Rondini <diego.rondini@kynetics.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Compiling with GCC 9.2.1 leads to build errors:
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
| ^~~~~~~~~~~~~~~~~~~~
Use memcpy() and void* pointers to resolve the problem caused by packing
the struct sunxi_cpucfg_reg.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
This patch is only a temporarily workaround for crash introduced by
commit ac9cd4805c ("bootstage: Correct relocation algorithm").
The crash occurs because the bootstage struct is not correctly aligned
when BOOTSTAGE feature is activated.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Activate by default the command CLS (clear screen);
this command used in pxe or sysboot command (DISTRO support)
when the "menu background" keyword is present.
This patch avoid the warning "Unknown command 'cls'"
with extlinux.conf:
# Generic Distro Configuration file generated by OpenEmbedded
menu title Select the boot mode
MENU BACKGROUND /splash.bmp
TIMEOUT 20
DEFAULT stm32mp157c-ev1-emmc
LABEL stm32mp157c-ev1-emmc
KERNEL /uImage
FDT /stm32mp157c-ev1.dtb
APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200
...
Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf
614 bytes read in 36 ms (16.6 KiB/s)
Retrieving file: /splash.bmp
46180 bytes read in 40 ms (1.1 MiB/s)
Unknown command 'cls' - try 'help'
Select the boot mode
1: stm32mp157c-ev1-sdcard
...
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
i2c: for next
- misc: i2c_eeprom:
Add partition support and add ability to query size
of eeprom device and partitions
- i2c common:
add support for offset overflow in to address and add
sandbox tests for it.
Enable the SPI NOR SFDP support and the Microchip QSPI driver.
CONFIG_SPI_FLASH_SFDP_SUPPORT enables the SFDP Vendor parser,
and for the SST case, the retrieval of the ethaddr from the
SPI NOR flash.
While touching the SPI NOR logic, sync with the
sama5d27_wlsom1_ek_qspiflash_defconfig and enable
CONFIG_SPI_FLASH_SPANSION.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
CONFIG_SPI_FLASH_SFDP_SUPPORT enables the SFDP Vendor parser,
and for the SST case, the retrieval of the ethaddr from the
SPI NOR flash.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
The SST26VF064BEUI spi-nor flash is programmed at the factory with a
globally unique address stored in the SFDP vendor parameter table and
it is permanently writeprotected. Retrieve the EUI-48 address and set it
as ethaddr env.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
JESD216 allow vendors to define their own SFDP tables.
Add SST SFDP parser. The vendor table is allocated using resource-managed
kmalloc - the table will be freed on driver detach. It will be accessible
by getting the UCLASS_SPI_FLASH's private data.
The SST's SFDP table is particularly of interest because contains
pre-programmed globally unique EUI-48 and EUI-64 identifiers.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Add ability to query size of eeprom device and partitions
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.
Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some devices (2 wire eeproms for example) use some bits from the chip
address to represent the high bits of the offset instead of or as well
as using multiple bytes for the offset, effectively stealing chip
addresses on the bus.
Add a chip offset mask that can be set for any i2c chip which gets
filled with the offset overflow during offset setup.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Binman supports writing the position and size of U-Boot proper and SPL
into the previous phase of U-Boot. This allows the next phase to be easily
located and loaded.
Add functions to return these useful values, along with symbols to allow
TPL to load SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a
syscon driver since it only needs to be probed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add some fixed IO and mmap addresses for use in the device tree and with
some early-init code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is specific to qemu so it seems best to keep it separate
from the generic code.
Move it out to a new file and update the condition to use if() instead of
#ifdef
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.
As well as a pinctrl driver this provides a GPIO driver based on the same
code.
Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This subsystem is present on various Intel SoCs.
Add very basic support for taking an lpss device out of reset.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With of-platdata we need to create drivers for particular chips, or at
least drivers that are separate from the standard code, since C structures
are created by dtoc which are private to that driver.
To avoid duplicating the probing code, export this probe function for use
by these drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for Apollo Lake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add this method so that the memory-mapped location of the SPI flash can
be queried.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't want to include dt-structs.h in header files, so add a note about
that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use dev_get_driver_data() to obtain the device type. It has the same
effect and is shorter.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reduce the size of the probe function but putting this code into its own
function.
Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.
Drop the default enabling of this option on x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we have to have an xfer() method even if it does nothing. This
is not correct, so fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is used on several boards so add it to the common file. Also add a
useful power-limit value while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present binman does not support updating a device tree that is part of
U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
updated entry information. This makes binman_entry_find() work correctly.
Do the same for SPL tool.
In both cases, group the two parts into a section so that SPL symbols get
the correct total size.
It may be possible for binman to handle this automatically at some point,
by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and
u-boot.dtb
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present if SPL sets up the microcode then it is still included in
U-Boot as well. This is wasteful as microcode is large. Adjust the logic
in the image to prevent this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add these entries to the ROM so that we can list the contents of an image
with 'binman ls'. The image-header is not essential but does speed up
access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.
Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.
Also drop the FSP binary as this relates only to FSP1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The current 'fsp' command only works with FSP1. Update it to handle FSP2
as well. Convert everything to hex which is what U-Boot uses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Many Intel SoCs require a FIT in order to boot properly. Add an option to
include this and enable it by default.
This term can be confused with FIT (Flat Image Tree) in U-Boot so the
CONFIG option has to include 'X86'.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't generally have enough space to run this, so don't build it into
TPL. This helps reduce the size of TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new
common API file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
FSP-S is used by the notify call after it has been used for silicon init.
To avoid having to load it again, add a field to store the location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With FSP2 we need to run silicon init early after relocation. Add a new
hook for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The FSP-S may do this but at least for coral it does not. Set this up so
that graphics is not deathly slow.
It isn't clear whether the FSP is expected to set up MTRR. It is not
mentioned in the APL FSP document.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.
Support for the FSP_S binary is also included.
Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI
reads.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This generic FSP file should include the generic FSP support header, not
the FSP1 version. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Both versions of FSP can use the same graphics support, so move it into
the common directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the interrupt table is included in all phases of U-Boot. Allow
it to be omitted, e.g. in TPL, to reduce size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These drivers are not needed on all platforms. While they are small, it
is useful in TPL to drop then. Add Kconfig control to allow this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't want to pull in libfdt if of-platdata is being used, since it
reduces the available code-size saves. Also, SPI flash is seldom needed
in TPL.
Drop these options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Set up MTRRs for the FSP SDRAM regions to improve performance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present with fsp a single DRAM bank is added which extends to the
whole size of memory. However there is typically only 2GB of memory
available below the 4GB boundary, and this is what is used by U-Boot while
running in 32-bit mode.
Scan the tables to set the banks correct. The first bank is set to memory
below 4GB, and the rest of memory is put into subsequent banks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function needs to be different for FSP2, so move the existing
function into the fsp1 directory. Since it is only called from one file,
drop it from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is only used within the implementation so make it static.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With Apollo Lake we need to support a normal cache, which almost never
changes and a much smaller 'variable' cache which changes every time.
Update the code to add a cache type, use an array for the caches and use a
for loop to iterate over the caches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is a bit confusing at present due to the error handling.
Update it to remove the goto, returning errors as they happen.
While we are here, use hex for the data size since this is the norm in
U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we reuse the mrc_output char * to also point to the cache
record after it has been set up. This is confusing and doesn't save much
data space.
Add a new mrc_cache member instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is now possible to obtain the memory map for a SPI controllers instead
of having it hard-coded in the device tree. Update the code to support
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Change the algorithm to first find the flash device then read the
properties using the livetree API. With this change the device is not
probed so this needs to be done in mrccache_save().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This should take account of the end of the new cache record since a record
cannot extend beyond the end of the flash region. This problem was not
seen before due to the alignment of the relatively small amount of MRC
data.
But with Apollo Lake the MRC data is about 45KB, even if most of it is
zeroes.
Fix this bug and update the parameter name to be less confusing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollo Lake's 24-byte variable-data record.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Define this symbol so that we can use binman symbols correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.
Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When reseting sandbox for tests, disable mmio support since that is the
default state.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.
This adds a uclass and enables it for sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Intel x86 SoCs have a power manager/controller which handles several
power-related aspects of the platform. Add a uclass for this, with a few
useful operations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't expect an exception in TPL and don't need to set up interrupts in
TPL. Drop this whole file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need to know every detail about the CPU in TPL. Drop some
superfluous functions to reduce code size. Add a simple CPU detection
algorithm which just supports Intel and AMD, since we only support TPL
on Intel, so far.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.
Note that version 1 of this commit caused bootstage to crash since the CPU
was not identified. This is corrected by changes previously applied to
make sure that the CPU is identified before spl_init() is called, such as
39146a2e0b x86: Move CPU init to before spl_init()
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.
When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the time since reset. This
particularly affects bootstage.
Change the default to not read the timer base, leaving it at 0. Add an
option for when U-Boot is the secondary bootloader.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the early timer init happens as soon as driver model is set up.
This makes it impossible to do anything that needs driver model but must
run before devices are probed (as needed with Intel's FSP-S, for example).
In any case it is not a good idea to tie probing of particular drivers too
closely to the DM init.
Create a new function to init the timer and put it a bit later in the
sequence.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present these options cannot be enabled for SPL/TPL, but this can be
useful in some cases. Add Kconfig options to allow it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When device-tree compilation fails it is sometimes tricky to see which
line is broken, since the input file to dtc is a pre-processed version
of the device tree.
Add a line that points to the file that needs to be checked:
When the error is in the main .dts file, output is something like this:
output: 'Error: arch/x86/dts/.chromebook_coral.dtb.pre.tmp:478.46-47
syntax error
FATAL ERROR: Unable to parse input tree
but in fact looking at that file shows nothing useful:
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD)
Instead we need to look at the preprocessed file, which shows:
163 ((1U << 30) | (1 << 10)) ((0xb << 10) | PAD_CFG1_IOSSTATE_HIZCRX1)
Here it is clear that PAD_CFG1_IOSSTATE_HIZCRX1 is not defined and so is
not being resolved by the preprocessor.
This commit adds an additional useful message:
Check arch/x86/dts/.chromebook_coral.dtb.dts.tmp for errors
Note that if the error is reported in an included file, such as
u-boot.dtsi then the output is the following:
Error: arch/x86/dts/u-boot.dtsi:137.14-15 syntax error
FATAL ERROR: Unable to parse input tree
But again, if the error is due to a preprocessor failure, like this:
filename = CONFIG_IFW_INPUT_FILE;
then you can't tell what the problem is by looking at the source. All you
see is the original code:
intel-ifwi {
filename = CONFIG_IFW_INPUT_FILE;
...
};
};
intel-fsp-m {
filename = CONFIG_FSP_FILE_M;
};
Everything looks fine. But looking at the output of the preprocessor:
intel-ifwi {
filename = CONFIG_IFW_INPUT_FILE;
...
};
intel-fsp-m {
filename = "fsp_m.bin";
};
This shows that the filename (normally "fitimage.bin") has not been
inserted the preprocess, leading to the realisation that the value should
be CONFIG_IFWI_INPUT_FILE.
If the above does not make sense, I encourage people to try introducing
errors in the device tree preprocessed values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
top of 32-bit address space, so that it can be executed in place and read
simply by copying from memory. For an 8MB ROM the mapping starts at
0xff800000.
However some recent Intel CPUs do not use a simple 1:1 memory map. Instead
the map starts at a different address and not all of the SPI flash is
accessible through the map. This 'Fast SPI' feature requires that U-Boot
check the location of the map. It is also possible (optionally) to read
from the SPI flash using a driver.
Add support for booting from Fast SPI. The memory-mapped version is used
by both TPL and SPL on Apollo Lake.
In respect of a SPI flash driver, the actual SPI driver is ich.c - this
just adds a few helper functions and definitions.
This is used by Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow this driver to set up an IO address in SPL using an 'early-regs'
property. This allows SPL to use the I2C driver without having to enable
the full PCI stack.
Also split out ofdata_to_platdata in designware driver since this is more
correct, and more convenient for the new logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Drivers are not allowed to use static data since they may be used in SPL
where BSS is not available.
It is possible that driver model may provide support for numbering devices
in the future. But for now, move this to global_data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is hacked into the driver at present. It seems better to have it as
a separate driver that uses the base driver. Create a new file and put
the X86 code into it.
Actually the Baytrail settings should really come from the device tree.
Note that 'has_max_speed' is added as well. This is currently always false
but since only Baytrail provides the config, it does not affect operation
for other devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These functions are used by code outside the network support, so move them
to lib/ to be more accessible.
Without this, the functions are only accessible in SPL/TPL only if
CONFIG_SPL/TPL_NET are defined. Many boards do not enable those option but
still want to do checksums in this format.
Fix up a few code-style nits while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.
To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.
Also add a function for use by of-platdata, to convert a reg property to
a pci_dev_t.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.
This is needed for Apollo Lake for debugging the silicon-init code. Once
the UART is moved to a different MMIO address the debug UART does not work
and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If the offset is -1 this function correctly sets up a null ofnode. But if
the offset is any other negative number (e.g. -FDT_ERR_BADPATH) then it
does the wrong thing.
An offset of -1 in ofnode indicates that the ofnode is not valid. Any
other negative value is not handled by ofnode_valid(). We could of course
change that function, but it seems much better to always use the same
value for an invalid node.
Fix it by setting the offset to -1 if it is invalid for any reason.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.
Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.
Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.
This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
SPL and TPL can access information about binman entries using link-time
symbols but this is not available in U-Boot proper. Of course it could be
made available, but the intention is to just read the device tree.
Add support for this, so that U-Boot can locate entries.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With commit 37db55b7e9 ("linux/types.h: fix typo unchar") we have a
duplicate typedef for uchar. As linux/types.h is included in common.h we
don't need another typedef for uchar there.
Fixes: 37db55b7e9 ("linux/types.h: fix typo unchar")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Describe that a signature node can be added to a binary device tree using
the mkimage tool.
Provide an example device tree node.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Commit 656d8da9d2 (doc: Remove duplicated documentation directory) got
rid of most of Documentation/. But there's still an obviously useless
.gitignore left behind.
Also, there's a copy of the linux kernel's net/ethernet.txt binding
imported from v5.0, while the existing one in doc/ is from 4.0-rc1. So
replace the latter by the former, and making Documentation/ finally
empty.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
commit 3b3e8a37d3
("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id")
did sync with recent linux kernel and replaced therefore the 'phy_id'
property with a phy-handle pointing to the mdio.
This is OK for linux, but introduces trouble with the already running
vxWorks on this target.
So this commit here re-inerts the phy_id property beside the phy-handle
property to be compatible with both.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
i2c bugfixes for 2020.01
- i2c: i2c_cdns: fix write timeout on fifo boundary
fixes timout issue when writting number of bytes is multiple
of the FIFO depth.
- First set of u-boot-atmel fixes for 2020.01 cycle:
This set includes a small fix for gpio bank names, one for removing
unused headers (also touches some other boards), and a fix for the QSPI
env read on one of the boards.
The rpi_4_32b_defconfig states that only one DRAM bank is present. This
leads to a wrong configuration of the available DRAM. Fix this by
setting the DRAM bank config accordingly.
Fixes: 193279d784 ("RPI: Add defconfigs for rpi4 (32/64)")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Up to now we only update the DRAM banks when we are define
CONFIG_BCM2711. But our one binary approach uses a config that supports
BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on
Raspberry Pi 4, even if it has more RAM.
Fix this by calling dram_init_banksize.
Fixes: 5694090670 ("ARM: defconfig: add unified config for RPi3 and RPi4")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
To update the dram bank information from device-tree we use
fdtdec_decode_ram_size() which expectes the the size-cells and
address-cells to be defined in the memory node. For normal system RAM
these values are defined in the root node. When the values differ from
the default values defined in the spec, we can end up with wrong RAM
bank information.
Switch to the "standard" way to update the RAM bank information to
avoid this.
Fixes: 9de5b89e4c ("rpi4: enable dram bank initialization")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
This fixes an issue that would cause I2C writes to timeout when the
number of bytes is a multiple of the FIFO depth (i.e. 16 bytes).
Within the transfer loop, after writing the data register with a new
byte to transfer, if the transfer size equals the FIFO depth, the loop
pauses until the INTERRUPT_COMP bit asserts to indicate data has been
sent. This same check is performed after the loop as well to ensure data
has been transferred prior to returning.
In the case where the amount of data to be written is a multiple of the
FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to
assert after writing the final byte, and then wait for this bit to
assert once more. However, since the transfer has finished at this
point, no new data has been written to the data register, and hence
INTERRUPT_COMP will never assert.
Fix this by only waiting for INTERRUPT_COMP in the transfer loop if
there's still data to be written.
Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Chromium EC commands can be up to 16-bits, so using a uint8_t here can
cause truncation. Update to use a uint instead.
It looks like this should likely have been done as a part of
9fea76f5d3, but this function was skipped
for some reason.
Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Today when parsing the .sizes files we get a warning about an invalid
line in the file as it's blank. Solve this by checking that we have a
non-blank line prior to processing.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sometimes it is useful for external tools to use buildman to provide the
toolchain information. Add an -a option which shows the value to use for
the ARCH environment variable, and -A which does the same for
CROSS_COMPILE
Signed-off-by: Simon Glass <sjg@chromium.org>
At present buildman looks at toolchains, then commits and then boards.
Move the board processing up above the commit processing, since it relates
to the toolchain code. This will make it easier to check the toolchains
needed for a board without processing commits first.
Signed-off-by: Simon Glass <sjg@chromium.org>
We don't really need buildman to print this every time it runs. Add a flag
to run quietly, that buildman can use.
Signed-off-by: Simon Glass <sjg@chromium.org>
- fix crash and board reset when drawing RLE8 bitmaps
bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
(tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
stm32f746-disco, stm32f769-disco and wandboard)
Buildman doesn't store this file in the same directory as a normal build.
Update the conftest code to handle both cases.
Change-Id: I1fd0e56054d7dc77394a7589336aa0991bd0133d
Signed-off-by: Simon Glass <sjg@chromium.org>
The parser responsible for the '[make-flags]' section in
the '.buildman' settings file is currently not able to
handle quoted strings, as given in the sample bellow:
[make-flags]
qemu_arm=HOSTCC="cc -isystem /add/include" HOSTLDFLAGS="-L/add/lib"
This patch replaces the simple string splitter based on the <space>
delimiter with a regex tokenizer that preserves spaces inside double
quoted strings.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Due to a conversion error the sandbox does not accept byte values 0x80-0xff
from the keyboard. The UEFI extended text input unit test requires Unicode
support.
Use unsigned char for the serial buffer.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
In the device tree UEFI unit test the compatible property of the device is
read.
Provide the missing property.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
In the initial SPI flash setup, the default bus mode being used was 3,
which is incorrect, causing a CRC error when the ENV was being read from
QSPI. Setting the default bus mode to 0 which is the correct mode.
Signed-off-by: Swapna Gurumani <swapna.gurumani@microchip.com>
- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
At the start, OpenSBI relocates itself to its link address. If the link
address ranges of U-Boot SPL and OpenSBI overlap, the relocation can
lead to code corruption if a hart is still running U-Boot SPL during
relocation. To avoid this problem, the main hart is specified as the
preferred boot hart to perform the relocation. This fixes the code
corruption problems based on the assumption that since the main hart
schedules the secondary harts to enter OpenSBI, it will be the last to
enter OpenSBI. However it was reported that this assumption is not
always correct.
To make sure the assumption always holds true, wait for all secondary
harts to acknowledge the call-function request before entering OpenSBI
on the main hart.
Reported-by: Rick Chen <rick@andestech.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.
As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.
Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.
The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").
Reported-by: Rick Chen <rick@andestech.com>
Suggested-by: Anup Patel <Anup.Patel@wdc.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Fix two wrong settings of andes plic driver as below:
1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
int can help to fix wrong plic enabling setting in RV64.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSBI.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
This patch provides four configurations which can support U-Boot SPL
to boot from RAM or FLASH and then boot FIT image including OpenSBI
FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices.
With ae350_rv[32|64]_spl_defconfigs:
U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
and then load FIT image from RAM device on AE350.
With ae350_rv[32|64]_spl_xip_defconfigs:
U-Boot SPL can be burned into SPI flash and run in flash in machine mode
and then load FIT image from SPI flash or MMC device on AE350.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
The U-Boot SPL will boot in M mode and load the FIT image which
include OpenSBI and U-Boot proper images. After loading progress,
it will jump to OpenSBI first and then U-Boot proper which will
run in S mode.
Also remove V5L2_CACHE due to U-Boot SPL code size consideration.
Without this concern, it can be enable manually for performance.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
This would help to make the necessary changes in drivers and device trees
in U-Boot tree itself. This feature would also be helpful to not pass
dtb during opensbi builds.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Rick Chen <rick@andestech.com>
Sync the hifive-unleashed-a00 dts from Linux with
below commit details:
commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive
Unleashed: add default chosen/stdout-path")
Idea is to periodically sync the dts from Linux instead of
tweaking internal changes one after another, so better not
add any intermediate changes in between. This would help to
maintain the dts files easy and meaningful since we are
reusing device tree files from Linux.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This fixes a problem, where booting Linux using distro boot will
sometimes lead to an invalid instruction exception on the main hart. The
secondary harts are not affected and boot Linux successfully. The root
cause of this problem is a stack overflow on the main hart.
With distro boot, the current default stack size of 8KiB on RISC-V is
not sufficient and will cause a stack overflow. The stacks are allocated
sequentially. In the case of a stack overflow the stack of the main hart
can reach into that of another hart and be corrupted.
The stack overflow previously did not cause any problems, because only
stack frames, which are not used anymore since the hart enters Linux,
were corrupted. Starting with GCC 9, the stack usage has decreased. Now,
only the most recent stack frame overflows into the stack of a secondary
hart and is corrupted. The illegal instruction exception is caused by
the secondary hart overwriting the return address in the stack frame of
the main hart with an address that does not include valid code.
Increase the default stack size of each hart to 16KiB to avoid this
problem.
Reported-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Rick Chen <rick@andestech.com>
The commit 1b42ab3eda ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") added the core logic to update the kernel
device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
family of SoCs.
The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
provide a higher performance and can run at a higher clock frequency
of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
correct clock rates on these SoCs. Note that this higher clock rate is
not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
AM574x SoCs) that follow the ABZ package.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
On NixOS, cross compiled kernels have long suffixes that cause them to
exceed the current maximum path length. The PXE/TFTP max path length is
used for extlinux.conf support as well, which is where this problem
usually manifest's itself.
Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Enable configs related to DMA and Ethernet so as to support networking at
U-Boot prompt
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Implement dma_get_cfg() interface to pass flow id information for DMA
clients to use. This is needed because on K3 SoCs, CPSW (ethernet) and
UDMA (DMA provider) support "flows" within a given RX DMA channel. This
allows different network packets to be segregated while using same RX
DMA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Sometimes, there would be a need to exchange data between DMA provider
and DMA client which are very specific to DMA driver of the SoC/platform
and are not generic enough to be put into struct dma. Therefore, introduce
dma_get_cfg() interface to get DMA provider specific data from client
device. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
This bus is used to access internal SoC PHYs. These PHYs are configured
by the ENETC driver directly, but it's useful to have command line access
to this MDIO to debug the system especially when using new external PHYs.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On some boards MDIO may get stuck if it detects echo on the line. This is
a know hardware issue, there is a board fix for it. In case we're running
on a board that doesn't have the fix, we don't want to loop here forever
and freeze U-Boot.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This reduces the time needed to establish a link as we don't reset the link
each time the interface is used. Our Link capabilities do not change at
run-time so there is no need to re-apply PHY configuration each time.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The original code enabled link speeds up to 1Gbps, but the interface can
go up to 2.5G, enable that speed to in PHY AN mask.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The function connects an ethernet device to a PHY using DT information.
This API is only available for eth devices with an associated device tree
node.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Renamed dm_mdio_phy_connect arguments dev to mdiodev and addr to phyaddr
for a bit more clarity and consistency with the following patches.
Also use NULL instead of 0 on error return path.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit b618b37076 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig")
accidentally set the default *option* TFTP block size to 512 bytes, even
though the comment in the code says that this is a terrible choice. Most
boards didn't define the symbol before, so they got the default block size
of 1468 bytes before, but now use 512 bytes, which is also the fallback.
This leads to both abysmal performance and a lot of hashes printed
on the screen (one character for every 5K), which is both annoying and
slow over serial links.
Set the default block size in Kconfig back to the value it had before.
This improves TFTP performance from 2.8 MB/s to 6.9 MB/s on a Pine64.
Fixes: b618b37076 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
A couple of optional properties have been introduced for Aquantia PHY
allowing the driver to set up wiring related configuration points that
are otherwise driven by firmware.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
It defines that PHY nodes must be children on MDIO bus nodes and defines
the only required property in U-Boot, reg. This property along with the
example provided are copied over from Linux.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface. The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to avoid losing the 1st packet.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique. Add an optional DT property used
to change SMBus address if needed.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If PHY is not ready for data by the time _config is called, reconfigure the
PHY system interface to use the proper protocol based on phydev->interface,
just in case the defaults set by PHY firmware don't match current
configuration.
Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Uses the data field in phy_driver structure to identify the PHY generation.
This is useful for custom configuration as non-generic PHY registers are
not 100% compatible between generations.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The PHY supports XFI and USXGMII, the notable difference being that USX AN
is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and
detects whether USX AN should be enabled or not using a PHY status
register. Keep that functionality too, so we don't break existing drivers.
Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This is useful to carry custom information between the driver structure
associated with a specific HW and the driver code.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Drivers currently use XGMII for XFI and USXGMII and, where needed, use
other information to identify the actual protocol on the board. With these
two defined drivers can now rely on DT phy-mode property.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On mv88E6071 the 'EDet' field offset, width and sense control
bits are different, adjust the driver to init the PHY control
register as needed. This fixes not working link detection and
tftp transfers.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On 88E6071 chip the port status register bit field offsets
for duplex and link bits differ. Extend the driver to use
88E6071 specific offset values. The width of bit fields for
speed status differ, too. Adapt for proper port speed
detection on 88E6071.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Extend the driver to init switch register offsets from variables
instead of compile time macros and enable detection of 88E6071 and
compatible devices. Ethernet transfer (e.g. tftp) does not work yet,
so enable the registration of the 'indirect mii' bus for easier PHY
register access by 'mii' command.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The KSZ8081 PHY has a factory test mode which is set at the de-assertion
of the reset line based on the RXER (KSZ8081RNA/RND) or TXC
(KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a
pull-up, the factory test mode should be cleared by manually writing a 0
(according to the datasheet).
Create another ksz8081_config function to handle this case.
Suggested-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
device_probe() may fail in which case the seq_id will be -1. Don't
display these devices during startup. While this is only a cosmetic
change, the return value of eth_initialize() will also change to the
actual number of available devices. The return value is only used in
spl_net to decide whether there are any devices to boot from. So
returning only available devices is also more correct in that case.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia quad-phys may take longer to initialize. This commit adds
a polling mechanism for a global alarm bit that tells if phy init
sequence is completed.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This allows passing arbitrary addresses through macb_miiphy_read and
macb_miiphy_write, therefore enabling the mii command to access
all mdio bus devices instead of only the defined phy.
Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
To support accessing arbitrary addresses the mii/mdio bus it is
necessary that the macb_mdio_read and macb_mdio_write functions
do not implicitly use the address of the connected phy.
The function signature is extended according to the Linux kernel
equivalent.
Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
I've noticed that in most cases when genphy_update_link() is called, the
ethernet driver (mt7628-eth in this case) fails with the first ethernet
packets. Resulting in a timeout of the first tftp command. Increasing
the delay in the link check look from 1 to 50 ms and moving it below the
BMSR register read fixes this issue, resulting in a stable ethernet
traffic, even after initial link autonogotiation.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Add Kconfig help describing the purpose of each command.
* Add CONFIG_CMD_MDIO so it could be selected individually, as
it doesn't depend on the mii command.
* Add Kconfig imply to mii to automatically select the mdio
command.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This version of the RTL-8168 chip can be found on some add-in cards sold
by CSL-Computer GmbH & Co. KG. The chip isn't special in any way, but it
needs to have the ChipCmd register programmed after the DMA descriptors
have been set up, so make sure that happens by adding an entry to the
chip information table.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit ports mvpp2 to use the recently introduced Marvell MDIO
(MVMDIO) driver. It removes direct interaction with the SMI & XSMI
busses. This commit is based in part on earlier work by
Ken Ma <make@marvell.com> in Marvell's own downstream repo:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39.
The above refrenced work was based on an MVMDIO implementation that
never made it into U-Boot. With this patch the mvpp2 driver switches
to use the new MVMDIO driver that is based on a more universal
mdio-uclass implementation.
Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If the phy doesn't match with any existing u-boot drivers, the phy
framework will connect it to the generic one which uid ==
0xffffffff. In this case, act as if the phy wouldn't be declared in
dts. Otherwise, in case of 3310 (for which the driver doesn't exist)
the link is marked as always down. Removing phy entry from dts in case
of 3310 is not a good option because it is required for the
phy_fw_down procedure.
This patch fixes the issue with the link always down on MCBIN board.
nhed: added NULL deref test.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Issue:
- Network stuck if autonegotion fails.
Issue root cause:
- When autonegotiation fails during port open procedure, the packet
processor configuration does not finish and open procedure exits
with error.
- However, this doesn't prevent u-boot network framework from
calling send and receive procedures.
- Using transmit and receive functions of misconfigured packet
processor will cause traffic to get stuck.
Fix:
- Continue packet processor configuration even if autonegotiation
fails. Only error message is triggered in this case.
- Exit transmit and receive functions if there is no PHY link
indication.
- U-boot network framework now calls open procedure again during next
transmit initiation.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Refactor SGMII configuration to group all settings together and reduce
number of MDIO transactions.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not
dependent on RGMII delay") of mainline linux kernel.
The driver would only set the IO impedance value when RGMII internal delays
were enabled. There is no reason for this. Move the IO impedance block
out of the RGMII delay block.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay
handling") of mainline linux kernel.
The current code is assuming the reset default of the delay control
register was to have delay disabled. This is what the datasheet shows as
the register's initial value. However, that's not actually true: the
default is controlled by the PHY's pin strapping.
This patch:
- insures the other direction's delay is disabled If the interface mode is
selected as RX or TX delay only
- validates the delay values and fail if they are not in range
- checks if the board is strapped to have a delay and is configured to use
"rgmii" mode and warning is generated that "rgmii-id" should have been
used.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable
output clock") of mainline linux kernel.
Generally, the output clock pin is only used for testing and only serves as
a source of RF noise after this. It could be used to daisy-chain PHYs, but
this is uncommon. Since the PHY can disable the output, make doing so an
option. I do this by adding another enumeration to the allowed values of
ti,clk-output-sel.
The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might
expect: to select the REF_CLK as the output. Rather it meant "keep clock
output setting as is", which, depending on PHY strapping, might not be
outputting REF_CLK.
Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output.
Omitting the property will leave the setting as is (which was the previous
behavior in this case).
Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK.
Change this so they generate an error.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit 980066e6d964 ("dt-bindings: phy: dp83867: Add documentation
for disabling clock output") of mainline linux kernel.
The clock output is generally only used for testing and development and not
used to daisy-chain PHYs. It's just a source of RF noise afterward.
Add a mux value for "off". I've added it as another enumeration to the
output property. In the actual PHY, the mux and the output enable are
independently controllable. However, it doesn't seem useful to be able
to describe the mux setting when the output is disabled.
Document that PHY's default setting will be left as is if the property
is omitted.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The driver ti.c is actually driver for TI DP83867x PHYs, so rename it
accordingly.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
During testing of qemu-riscv32 with a 2GiB memory configuration,
tftp always fails with a error message:
Load address: 0x84000000
Loading: #
TFTP error: trying to overwrite reserved memory...
It turns out the result of 'tftp_load_addr + tftp_load_size' just
overflows (0x100000000) and the test logic in store_block() fails.
Fix this by adjusting the end address to ULONG_MAX when overflow
is detected.
Fixes: a156c47e39 ("tftp: prevent overwriting reserved memory")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
sandbox_defconfig does not compile using GCC 9.2.1:
net/net.c: In function ‘net_process_received_packet’:
net/net.c:1288:23: error: taking address of packed member of ‘struct
ip_udp_hdr’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
1288 | sumptr = (ushort *)&(ip->udp_src);
| ^~~~~~~~~~~~~~
Avoid the error by using a u8 pointer instead of an u16 pointer and
in-lining ntohs().
Simplify the checksumming of the last message byte.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix 'mask' calculation in phy_connect() for phy addr '0'.
'mask' is getting set to '0xffffffff' for phy addr '0'
in phy_connect() whereas expected value is '0'.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reported-by: tetsu-aoki via github
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
While we have networking use cases within SPL we do not support loading
files via NFS at this point in time. Disable calling nfs_start() so
that the NFS related code can be garbage collected at link time.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Even if not communicating over the network in U-Boot, code may be manipulating
and storing IP or MAC addresses to pass to Linux, etc.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Part of the env cleanup moved this out of the environment code and into
the net code. However, this helper is sometimes needed even when the net
stack isn't included.
Move the helper to lib/net_utils.c like it's similarly-purposed
string_to_ip(). Also rename the moved function to similar naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Ondrej Jirman <megous@megous.com>
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html
Commit 16540d07fd ("arm: fix -march for ARM11") changed the value of the
compiler flag from -march=armv5 and -march=armv5t into -march=armv6 for
ARM11.
The values prior to this patch were:
arch-$(CONFIG_CPU_ARM1136) =-march=armv5
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
The change lead to a regression with the Raspberry Pi Zero W not booting
anymore.
Use -march=armv5t both for ARM1136 and ARM1176.
Fixes: 16540d07fd ("arm: fix -march for ARM11")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Joris Offouga <offougajoris@gmail.com>
unsigned char should be called uchar and not unchar.
This fixes a build error in lib/crypto/x509_cert_parser.c.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Fixes for 2020.01
-----------------
- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
Recently the version check was improved to be able to determine that
we're running on SoC revision 2.1. A check for B0 was tightened so
that it now must equal 0x20 instead of being bigger than 0x20. On
some B0 chips the value returned is 0x1020 instead of 0x20. This
means even though it's B0, the check will fail and code relying on
the correct chip revision will make wrong decisions. There is no
documentation of those bits, but it seems that NXP always uses a
byte to encode the revision. Thus remove the upper bits to fix the
regression.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
You can directly specify the label as the operand for ljmp.
This commit saves 4-byte code.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed the gas warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This file defines 'a32' and 'o32' macros to avoid magic numbers
of operand/address-size prefixing.
GAS supports 'data32' and 'addr32' for that purpose.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
- Allow for the sysboot command, which is used to parse extlinux.conf
files to be used without PXE support. There is no functional change
here aside from fixing distro boot in a few cases where we actually
lacked the ability to parse the extlinux.conf file
- Add the x509/pkcs7 parsers from Linux, a pre-requisite to EFI Secure
Boot support.
With the change to make tools/version.h a file we need to make sure that
the output directory exists first otherwise we will get a build failure.
Reported-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Fixes: 4d90f6cd98 ("tools: Avoid creating symbolic links for tools/version.h")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This test will exercise asn1 compiler as well as asn1 decoder functions
via various parsers.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Imported from linux kernel v5.3:
pkcs7.asn1 without changes
pkcs7.h with changes marked as __UBOOT__
pkcs7_parser.h without changes
pkcs7_parser.c with changes marked as __UBOOT__
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Imported from linux kernel v5.3:
x509.asn1 without changes
x509_akid.asn1 without changes
x509_parser.h without changes
x509_cert_parser.c with changes marked as __UBOOT__
x509_public_key.c with changes marked as __UBOOT__
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Imported from linux kernel v5.3:
rsapubkey.asn1 without changes
rsa.h without changes
rsa_helper.c with changes marked as __UBOOT__
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Imported from linux kernel v5.3:
asymmetric-type.h with changes marked as __UBOOT__
asymmetric_type.c with changes marked as __UBOOT__
public_key.h with changes marked as __UBOOT__
public_key.c with changes marked as __UBOOT__
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Imported from linux kernel v5.3:
build_OID_registry without changes
oid_registry.h without changes
oid_registry.c with changes marked as __UBOOT__
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Imported from linux kernel v5.3:
asn1.h without changes
asn1_ber_bytecode.h without changes
asn1_decoder.h without changes
asn1_compiler.c without changes
This host command will be used to create a ASN1 parser, for example,
for pkcs7 messages or x509 certificates. More specifically, it will
generate *byte code* which will be interpreted by asn1 decoder library.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Adding "printk.h" will help improve portability from linux kernel
code (in my case, lib/asn1_decoder.c and others) where printf and
pr_* variant functions are used.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
This function will be used in lib/crypto/x509_cert_parser.c, which
will also be imported from linux code in a later commit.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
In the next commit, rtc_mktime(), for compatibility with linux, will be
implemented using rtc_mktime(), which is no longer drivers/rtc specific.
So move this file under lib/.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
linux_compat.c is the best place for kmemdup(), which is currenly used
only in ubifs.c, but will also be used when other kernel files
(in my case, lib/crypto/x509_cert_parser.c and pkcs7_parser.c) will be
imported. So just move it.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Extract all sysboot command related code from pxe.c to new sysboot.c
Update Kconfig to insure that DISTRO_DEFAULT select new CMD_SYSBOOT
command.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
As sysboot and pxe commands are sharing piece of code, migrate this
common code into a new file pxe_utils.c to prepare sysboot command
code extraction from pxe.c
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Many boards do not use all selected framebuffer depth
configurations, for such boards there is some unused
code in video and console uclass routines. Make depth
specific code optional to avoid dead code and slightly
reduce binary size. Also make ANSI code optional for
the same reason. When i.e. using only VIDEO_BPP16 the
code size shrinks (below values when using gcc-7.3.0):
$ ./tools/buildman/buildman -b video-wip -sS wandboard
...
01: Merge git://git.denx.de/u-boot-sh
02: video: add guards around 16bpp/32bbp code
03: video: make BPP and ANSI configs optional
arm: (for 1/1 boards) all -776.0 bss -8.0 text -768.0
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Many boards use only single depth configuration, for such boards
there is some unused code in video and console uclass routines.
Add guards to avoid dead code.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
- rockchip pwm driver update to support all the SoCs
- RK3308 GMAC and pinctrl support
- More UART interface support on PX30 and pmugrf reg fix
- Fixup on misc for eth_addr/serial#
- Other updates on variant SoCs
Due to the (seemingly bogus) assumption of a default
CONFIG_SYS_UBOOT_START value we will revert this change for now and
evaluate it again for the next release along with changes to
CONFIG_SYS_UBOOT_START.
This reverts commit d3e97b53c1.
Signed-off-by: Tom Rini <trini@konsulko.com>
The default value of CONFIG_SYS_CBSIZE is too small when we need
to input long commands or when using long kernel command line.
The default value of CONFIG_SYS_MAXARGS is too small to add a long
command line, and the kernel might not boot as intended without the
complete bootargs. Increase argument buffer sizes and the number of
arguments.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The 24MHz oscillator clock is referenced by "clock-osc-24m" and not
"osc_24m".
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The board has both VDD_SOC_IN and VDD_ARM_IN rails connected to the same
PMIC rail, align the LDO voltages to avoid leaking inside the MX6SX SoC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
Ever since the conversion to DM PCI, the board was missing the PCIe DT
nodes, hence the PCI did not really work. Fill in the DT nodes and add
missing PCIe device reset.
Moreover, bring the PCIe power domain up before booting Linux. This is
mandatory to keep old broken vendor kernels working, as they do not do
so and depend on the bootloader to bring the power domain up.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
The fitImage support was enabled in the downstream U-Boot port and the
kernel images on the device are fitImage, yet this functionality is not
enabled in mainline U-Boot. Enable it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
Convert the board to ethernet DM support. Adjust board file accordingly,
as the board_eth_init() contains custom clock configuration required for
this board to work. Furthermore, enable FEC1 clock to make FEC1 work as
well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
Enable DRAM calibration in SPL to improve behavior of the board
in edge conditions of the thermal envelope of the board and make
it even more stable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
In preparation for use of DDR DRAM fine-tuning upon boot,
convert the board to SPL framework instead of using DCD
tables to bring up DRAM and pinmux.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
Make the PMU LDO configuration interface available to board code,
so that board code can reconfigure the internal LDOs of the SoC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for
the rpmsg communication. Both use cases need a fixed location of
memory reserved. For the rpmsg use case the reserved area needs
to be in sync with the kernel's hardcoded vring descriptor location.
Use the linux,usable-memory property to carve out 1MB of memory
in case the M4 core is running. Also make sure that the i.MX 7
specific rpmsg driver does not get loaded in case we do not carve
out memory.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.
Running "saveenv" followed by a "reset" causes U-Boot to hang because
of this overlap.
Fix this problem by increasing the CONFIG_ENV_OFFSET size.
Also, in order to prevent this same problem in the future, use
CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time.
CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare
CONFIG_ENV_OFFSET with its direct value instead.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Tested-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Acked-by: Joris Offouga <offougajoris@gmail.com>
Tested-by: Joris Offouga <offougajoris@gmail.com>
The NoC registers on i.MX6QP needs to be configured, otherwise some
usecases in the kernel behave incorrectly, such as rotation and resize.
Currently the NoC registers are not configured in the kernel, so
configure them in U-Boot like it is done in the NXP U-Boot tree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Sync the mx7ulp device tree related files with the one from
NXP U-Boot vendor tree (imx_v2019.04_4.19.35_1.0.0).
The mainline support for i.MX7ULP is very premature at this stage.
We should probably re-sync with mainline Linux dts when it gets
in better shape, but for now sync with the U-Boot vendor code.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
The LDOVL definitions is common to all the modes, not only RUN mode,
so in order to avoid confusion, remove the _RUN notation from the PMC1
LDOVL definitions.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards
designed to operate with LDO enabled mode can work with 0.95V at LDO
output in RUN mode as per the datasheet.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
As per the i.MX7ULP datasheet, it can boot in LDO enabled mode
or LDO bypass mode.
Print the LDO mode status in the U-Boot log for convenience.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
In case the BMP size is bigger than the frame buffer, don't use
the BMP's width and height in video_display_rle8_bitmap, but the
one's checked in video_bmp_display() as parameters to
video_display_rle8_bitmap().
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
CC: Yannick Fertré <yannick.fertre@st.com>
Convert panel_picture_delta and axis_alignment from unsigned long
to long to insure to store correctly the difference between
panel_size and picture_size in case the panel_size is smaller
than picture_size.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
CC: Yannick Fertré <yannick.fertre@st.com>
[agust: change axis_alignment to long]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Recent versions of the Linux kernel with many options enabled have
grown large enough to overwrite the beginning of the initrd. For
example, the kernel I use on my Rock64 and RockPro64 is 34.1 MiB,
while only 31.5 MiB are available between kernel_addr_r and
ramdisk_addr_r.
This patch moves ramdisk_addr_r up by 32 MiB on the RK3328 and RK3399,
allowing for much larger kernels.
Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
An iomux register contains 8 pins, each of which is represented
by 2 bits, but the register offset is 0x8.
For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX
offset is 0x8, the offset 0x4 is reserved.
So add a type IOMUX_8WIDTH_2BIT to calculate offset.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This PWM driver can be used to support pwm functions
for on all Rockchip Socs.
The previous chips than RK3288 did not support polarity,
and register layout was different from the RK3288 PWM.
The RK3288 keep the current functions.
RK3328 and the chips after it, which can support hardware lock,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add the glue code to allow the rk3308 variant of the Rockchip gmac
to provide network functionality.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This is a core board named Core-PX30-JD4 with a mainboard from Firefly,
name it as firefly-px30 for now.
This board can re-use the dts of PX30, the only difference is the UART IO,
the firefly use UART2 M1 while evb use UART2 M0.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
serial# is one of the vendor properties and thus protected from being
overwritten if already set. If env_set is called anyway this result in
some nasty warnings, so check for presence before trying that.
In the same direction check for the presence of cpuid# and compare it
to the actual hardware and emit a warning if they don't match.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip_setup_macaddr() runs from an initcall, so returning an error
code will make that initcall fail thus breaking the boot process.
And if an ethernet address is already set this is definitly not a
cause for that, so just return success in that case.
Fixes: 0482538499 ("rockchip: rk3399: derive ethaddr from cpuid");
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.
Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1).
Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
UART3 also has two sets of pins that can be selected.
Rename the config option to a common name, to allow it to be used for both
UART2 and UART3.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.
And show my best respect to Heiko's work for this solution.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
After commit d8765e2422 ("Enable building of u-boot.itb
on Rockchip platform"), u-boot.itb will automatically
generated by "make all" command, manually command
"make u-boot.itb" is no longer needed.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
SPL has limited available resources, and the performance between
ARM and Thumb isn't that significant.
This patch builds using Thumb instruction set to reduce the code
size by nearly 6K.
Original:
text data bss dec hex filename
26526 4004 1376 31906 7ca2 spl/u-boot-spl
Thumb:
text data bss dec hex filename
20232 4004 1376 25612 640c spl/u-boot-spl
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The da850-evm doesn't have the boot pins configured in a way
to make MMC/SD booting an option, and MMC/SD support is not
enabled in SPL. Therefore, there is no need to support raw mode
mmc/sd support in SPL.
This patch disables CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
Signed-off-by: Adam Ford <aford173@gmail.com>
At the moment entry_point is set to image_get_load(header) that sets it
to "load address" instead of "entry point", assuming entry_point is
equal to load_addr, but it's not true. Then load_addr is set to
"entry_point - header_size", but this is wrong too since load_addr is
not an entry point.
So use image_get_ep() for entry_point assignment and image_get_load()
for load_addr assignment.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
# This is actually a resent patch of
# [1] https://lists.denx.de/pipermail/u-boot/2019-May/369170.html
Two test cases are added under test_fs_ext:
test case 10: for root directory
test case 11: for non-root directory
Those will verify a behavior fixed by the commits related to
root directory
("fs: fat: allocate a new cluster for root directory of fat32" and
"fs: fat: flush a directory cluster properly"), and focus on
handling long-file-name directory entries under a directory.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Unlink test for FAT file system seems to fail at test_unlink2.
(When I added this test, I haven't seen any errors though.)
for example,
===8<===
fs_obj_unlink = ['fat', '/home/akashi/tmp/uboot_sandbox_test/128MB.fat32.img']
def test_unlink2(self, u_boot_console, fs_obj_unlink):
"""
Test Case 2 - delete many files
"""
fs_type,fs_img = fs_obj_unlink
with u_boot_console.log.section('Test Case 2 - unlink (many)'):
output = u_boot_console.run_command('host bind 0 %s' % fs_img)
for i in range(0, 20):
output = u_boot_console.run_command_list([
'%srm host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i),
'%sls host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i)])
assert('' == ''.join(output))
output = u_boot_console.run_command(
'%sls host 0:0 dir2' % fs_type)
> assert('0 file(s), 2 dir(s)' in output)
E AssertionError: assert '0 file(s), 2 dir(s)' in ' ./\r\r\n ../\r\r\n 0 0123456789abcdef11\r\r\n\r\r\n1 file(s), 2 dir(s)'
test/py/tests/test_fs/test_unlink.py:52: AssertionError
===>8===
This can happen when fat_itr_next() wrongly detects an already-
deleted directory entry.
File deletion, which was added in the commit f8240ce95d ("fs: fat:
support unlink"), is implemented by marking its entry for a short name
with DELETED_FLAG, but related entry slots for a long file name are kept
unmodified. (So entries will never be actually deleted from media.)
To handle this case correctly, an additional check for a directory slot
will be needed in fat_itr_next().
In addition, I added extra comments about long file name and short file
name format in FAT file system. Although they are not directly related
to the issue, I hope it will be helpful for better understandings
in general.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
The mmc CID value is one of the input parameters used to provision the
RPMB key. The trusted execution environment expects this value to be
specified in big endian format.
Before this fix, on little endian systems, the value returned by the
linux kernel mmc driver differed from the one returned by u-boot.
This meant that if linux provisioned the RPMB key, u-boot would not
have access to the partition (and the other way around).
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
The command cp fails on sandbox because the address is used
directly. To fix this issue, we call the function map_sysmem
to translate the address.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
The command iminfo fails on sandbox because the address
is used directly. To fix this issue, we call the function
map_sysmem to translate the address.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
This define indicates if DM_GPIO shall be supported in SPL. This allows
proper operation of DM converted GPIO drivers in SPL, which use
boards.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
PCI devices may be disabled in the device tree. Devices which are probed
by the device tree handle the "status" property and are skipped if
disabled. Devices which are probed by the PCI enumeration don't check
that property. Fix it.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Move MTD-related lines out of the root Makefile. Put them in their
respective directories. Enclose some of these new lines to skip them
when building the SPL. MTD core files and some MTD device drivers are
compiled in a mtd.o object and included in the final object only if
MTD support is required (there are two different symbols for that, one
for U-Boot and one for the SPL).
Now that all defconfigs have been fixed, we can stop the logic where
enabling a command selects the core files to compile. This logic is
broken since selecting a symbol with a 'depends on' will not enforce
this secondary dependency.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Defconfigs have been fixed, now we can add proper dependencies in
Kconfig. SPI FLASH is still not dependent on MTD (deeper rework needed).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
The 'sf' command is not supposed to rely on the MTD stack, but both
'sf' and 'nand' commands use helpers located in mtd_uboot.c. Despite
their location, these functions do not depend at all on the MTD
stack.
This file (drivers/mtd/mtd_uboot.c) is only compiled if CONFIG_MTD is
selected, which is inconsistent with the current situation. Solve this
by moving these three functions (which are only used by the above two
commands) out of mtd_uboot.c and put them in a C file only compiled
with cmd/sf.c and cmd/nand.c.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Don't export get_part function now]
Signed-off-by: Tom Rini <trini@konsulko.com>
It is already the case that all defconfigs with SPI_FLASH_MTD also
declare using MTD, but let's make this consistent and enforce it in
Kconfig. Most of the time SPI_FLASH_MTD is used in conjunction with
UBI, which already depends on MTD.
Suggested-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
CONFIG_DFU_NAND needs the raw NAND core being compiled.
Also fix the colibri_vf defconfig to reflect this dependency.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Because of the include's game, when some files are compiled for a SPI
NAND device, no warning appears. But when it is for a raw NAND device,
GCC complains. Fix these warning by including <common.h>.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Enabling TFABOOT configuration will compile-in a call to nand_read in
the boot sequence. Handle the situation by also selecting officially
the raw NAND core in this case.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
There is no flash on this board, there is no reason to define MTD
environment variables nor UBI. Drop them from the configuration file.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Wolfgang Grandegger <wg@aries-embedded.de>
While the right Kconfig entries were selected, because of the missing
CMD_NAND symbol the raw NAND core was never compiled. Remove it from
the defconfigs otherwise the build will fail.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Also do this on bcm11130_nand]
Signed-off-by: Tom Rini <trini@konsulko.com>
Due to previous Makefile organization, the raw NAND subdirectory was
not compiled in if CMD_NAND was not enabled. Because the Denali driver
does not compile with these boards (undefined environment offset),
remove the dependency within the defconfig over the controller driver
(was ignored anyway in the past).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
MTD support must be enabled when using mtdparts. Indeed, functions
like get_mtd_info(), get_mtd_device() and put_mtd_device() are in
drivers/mtd/mtd_uboot.c and are built only with CONFIG_MTD.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
In some files, options of CMD_NAND are selected but not the command
itself. Fix this inconsistency.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Both symbols must be enabled when there is a raw NAND driver
selected. Also enable them when CONFIG_CMD_NAND is selected to avoid
breaking things when we'll further rework the MTD dependency
description.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
[trini: Rebase and migrate a few more boards here]
Signed-off-by: Tom Rini <trini@konsulko.com>
CONFIG_MTD must be reserved for the MTD core. Like any other
subsystem, prefix the symbol by DM when it comes to DM support.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
[trini: Add Kconfig files]
Signed-off-by: Tom Rini <trini@konsulko.com>
I detected the following error in sandbox with Clang on Travis CI:
+cmd/efidebug.c:703:15: error: result of comparison of constant
9223372036854775822 with expression of type 'int' is always false
[-Werror,-Wtautological-constant-out-of-range-compare]
+ else if (ret == EFI_NOT_FOUND)
+ ~~~ ^ ~~~~~~~~~~~~~
Simply changing a type of 'ret' to efi_status_t will fix this error.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This adds a general board file based on MT8518 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8518 eMMC board.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
[trini: Migrate env location to defconfig, set ENV_IS_IN_MMC]
Signeed-off-by: Tom Rini <trini@konsulko.com>
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
Add null pointer check to take care of out of memory errors.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
spl ymodem driver always assumes that 1 BUF_SIZE is read in one stream.
This might not be true when image is not padded to BUF_SIZE and the last
sector that gets loaded will be < BUF_SIZE. Drop this assumption and use
the actual size that is loaded.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The MMC boot is currently broken on omapl138-lcdk after enabling the
driver model in SPL. The main problem is the driver's bind callback not
being called after probe in SPL (even with the DM_FLAG_PRE_RELOC flag
specified).
While a proper fix is still being worked on, this hacky changeset at
least fixes the MMC boot on this platform by calling mmc_bind()
manually from probe().
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
We don't have full device-tree support in SPL yet - add an appropriate
U_BOOT_DEVICE() to the board file.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
struct mmc_config & struct mmc don't need to be exported over platform
data, but can instead be private in the driver.
Remove struct davinci_mmc_plat.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The DM family of DaVinci SoCs is no longer supported. Drop the
irrelevant code from the driver.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Currently the omapl138_lcdk has SKIP_LOWLEVEL_INIT set.
The README states there is a variation of this for the ARM926EJ-S
which allows the board to just skip the call to lowlevel_init()
and do the normal CP15 init which enables the instruction cache.
On the da850evm, this was shown to improve startup time.
This patch switches SKIP_LOWLEVEL_INIT to SKIP_LOWLEVEL_INIT_ONLY
thus, enabling the cache.
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
In order to further prepare for full device tree support in SPL,
this patch enables both SPL_DM_SEQ_ALIAS and SPL_OF_TRANSLATE.
Both of these are already enabled in U-Boot, so SPL will have
the same functionality
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Driver model requires a malloc pool to allocate memory before
relocations to operate serial and some other devices. This patch
increases the pool size to 2K.
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
In preparation to use full device tree support, SPL can separate
BSS from text region.
This patch enables SPL_SEPARATE_BSS.
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
pxe command parses the init ramfs address(through initrd lable in
pxe config file), but is not passing it to bootm command as argument
as bootm_argc count is not increased.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit:
d409c96216
causes build failure with ICACHE enabled. This is due to missing
invalidate_icache_all() stub. Let's add empty invalidate_icache_all() in
the case where ICACHE is not enabled.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
The bcm283x has grown in files, which was not reflected in the
MAINTAINERS file. Fix this by adding the missing entries.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
When we do not have CONFIG_BLK (or SPL/TPL) enabled there are very few
cases where we need the blk_legacy code linked in. To catch these, build
when we have CONFIG_HAVE_BLOCK_DEVICE set. In addition, we only need
cmd/blk_common.o to be linked in when we have CONFIG_HAVE_BLOCK_DEVICE
set, so make use of that directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
The array 'mtd_table' is unused in the code. Remove this as gcc doesn't
always discard unused global variables.
Signed-off-by: Tom Rini <trini@konsulko.com>
The content of pci_rom.c is only used in a few cases. Only build and
link in these cases to avoid a global variable as gcc doesn't always
discard those when they are unused.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SYS_CORTINA_FW_IN_MMC
CONFIG_SYS_CORTINA_FW_IN_NAND
CONFIG_SYS_CORTINA_FW_IN_NOR
CONFIG_SYS_CORTINA_FW_IN_REMOTE
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
Signed-off-by: Tom Rini <trini@konsulko.com>
Enhance do_bootm_vxworks() to support Linux compatible standard DTB
for ARM and PPC, when the least significant bit of flags in VxWorks
bootargs is set. Otherwise it falls back to the existing bootm flow
which is now legacy.
Signed-off-by: Lihua Zhao <lihua.zhao@windriver.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There are currently no known users of this functionality on this
platform, disable it to prepare for additional VxWorks functionality
that would cause this platform to fail to link.
Cc: Soeren Moch <smoch@web.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Soeren Moch <smoch@web.de>
This file is generated in the root during Rockchip builds and so should
be cleaned up.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Currently, we have two places where we list files that should always be
cleaned if they exist. One, the CLEAN_FILES variable, is from the Linux
build system and is the proper place to list files.
The other, a set of extra arguments passed in the xargs template used to
remove files with certain extensions, was introduced by 8f06f0cee3
("Makefile: clean image.map") and is clearly wrong: by extending the
xargs template, we attempt to remove the files once for each batch of
arguments that xargs produces and we reduce the number of files from
stdin that xargs can include in each of its rm commands.
To fix this, put all hardcoded files into CLEAN_FILES.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
All of the clean targets (clean, dist-clean, mrproper) are run without
loading a configuration. That means that any conditional modification of
CLEAN_FILES will either always apply or never apply and so shouldn't be
in a conditional in the first place.
Since CLEAN_FILES is allowed to list nonexistent files, just add
everything to it unconditionally to fix the issue.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
27084c03d3 ("spl: Allow tiny printf() to be controlled in SPL and
TPL") split this option in two for TPL and SPL, but didn't change the
Kconfig names, making them hard to set quickly.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
There are currently no known users of this functionality on this
platform, disable it to prepare for additional VxWorks functionality
that would cause this platform to fail to link.
Cc: Soeren Moch <smoch@web.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Soeren Moch <smoch@web.de>
Make the at91_gpio driver set sensible GPIO bank names in the platform
data. This makes the 'gpio status' command a lot more useful.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
Several boards still unnecessarily included micrel.h but no longer
require it since the switch to Device Tree configuration.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
These functions do not use driver model but are still used. Move them to a
new eeprom.h header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function can be dropped when all boards use driver model for PCI. For
now, move it into init.h with a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
A number of board function belong in init.h with the others. Move them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this function into init.h which seems to be designed for this sort
of thing. Also update the header to declare struct global_data so that it
can be included without global_data.h being needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function is not defined by any boards so the feature is not used.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move these functions into the command.h header file which is a better fit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move these two functions into the irq_funcs.h header file. Also move
interrupt_handler_t as this is used by the irq_install_handler() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions do not use driver model but are fairly widely used in
U-Boot. But it is not clear that they will use driver model anytime soon,
so we don't want to label them as 'legacy'.
Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it
is widely used in U-Boot already.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These are used by only one arch and only within a single file. Drop the
declarations from the common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.
Move them over.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in cpu_func.h since they do not use driver model.
Move them over. Don't bother adding comments since these functions should
be deleted.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function belongs in time.h so move it over and update the comment
style.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function has a similar name to the common wait_ticks(). It is only
used in one place and seems small enough to drop.
Inline it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in time.h so move them over and add comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add a header file to house the lz4 compression function. Add a comment
while we are here, since it not even clear from the name what the function
actuall does.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this function header to serial.h since this function is clearly
related to serial. The function itself stays in console.c since we don't
have a single serial file. DM and non-DM each has a separate file so we
would have to either create a new common serial file, or repeat the
function in both serial.c and serial-uclass.c, neither of which seem
worthwhile.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The function declarations in serial.h are not in sync with what is
currently used in usbtty. Fix this by updating the header and including
it, to help catch future such problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.
Use the vsprintf.h include file explicitly where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These don't need to be in common.h so move them out into a new header.
Also add some missing comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
It is not good practice to write code in a header file. If it is included
multiple times then the code can cause duplicate functions.
Move the bootcount_store() and bootcount_load() functions into SPL.
Note: bootcount is a bit strange in that it uses driver model but does not
define proper drivers. This should be fixed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Drop inclusion of crc.h in common.h and use the correct header directly
instead.
With this we can drop the conflicting definition in fw_env.h and rely on
the crc.h header, which is already included.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Some of these have a space before the bracket. Drop it to fix the style.
Add some missing function comments while here.
Note that u32 and u8 cannot be used here since crc.h is included on the
host side.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
We have an existing U-Boot header for the one function that this defines.
Use that instead of the linux/ one. Move over the nice comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Create a new rand.h header file and move functions into it, to reduce
the size of common.h
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are a few whitespace problems with this code. Tidy them up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is only used by a few files so it should not be in the common header.
Move it out.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These should be moved to driver model, but in the meantime, move them
out of the common header to help reduce its size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
With commit f0921f5098 ("fdt: Sync up to the latest libfdt"),
SiFive Unleashed board does not boot any more. This was due to
the U-Boot local changes commit 77d7fff8ce ("fdt: Fix handling
of paths with options in them") to libfdt/fdt_ro.c was dropped
during the libfdt upgrade.
>From the history [1] it was mentioned that the U-Boot changes
commit 77d7fff8ce ("fdt: Fix handling of paths with options in
them") was rejected by libfdt upstream, hence we need find another
way to fix the things.
This commit uses another method, by updating serial_check_stdout()
directly to handle the situation of "stdout-path" with ":options".
A simpler way is to change the logic in fdtdec_get_chosen_node()
to do similar thing, but I feel that not every property in chosen
node may have the option in them, hence it would make more sense
to do the special handling in serial_check_stdout() directly.
[1]: http://patchwork.ozlabs.org/patch/462756/
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The deadline for migration to CONFIG_DM is v2020.01. The VCT
baords would need an almost complete rewrite of all drivers to
support driver model.
Unless someone has access to the hardware and volunteers to do the migration,
the board should be scheduled for removal.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Since at least some of the drivers relevant to LS1028A are now following
DM, it's useful to have dm command enabled by default.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
- Solve warning for stih410-b2260
- Device tree alignment on v5.4-rc4 for all stm32 boards
- Correct the eMMC pin configuration on stm32mp157c-ev1
- Add DFU and SPI-NAND support for stm32mp1 board
Instead of using single fixed value for the calibration offset,
add tables which dynamically adjust this per calibration code
from the SCC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Retain the tap number from last calibration in private data. This
will be later used for SCC error checking after each command.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The clock.h was to define mxc_get_clock() providing clock value
to fsl_esdhc driver. Since fsl_esdhc driver is using global data
gd->arch.sdhc_clk directly now, we can remove this file.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Although layerscape platforms reuse mxc_get_clock() of i.MX platforms,
eSDHC clock getting do not have to use it. It uses global data
gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more
than one eSDHC controllers on SoC, they use same reference clock.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The board_mmc_init() defined in board files is actually
doing same thing with the cpu_mmc_init() defined in
arch/arm/cpu/armv7/ls102xa/cpu.c. So drop it.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This patch is to get clock directly from global data.
- Remove uclass clk api method. This was what i.MX platforms were
using, while QorIQ platforms weren't.
- Get clock only from global data, dropping mxc_get_clock().
QorIQ eSDHC controllers on one silicon use same reference clock.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This adds pfe stop command before boot linux kernel
to fix a problem that ethernet won't be workable
after enter linux. Because there is a h/w limitation
in LS1012A PFE, to re-initialize PFE it has to be
safe shutdown, these steps are done through PFE stop.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Fix the kernel offset of qspi_bootcmd scripts, followed
the qoriq_memory_layout definition.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
LS1028A QDS board supports multiple combinations of SerDes protocols and
multiple add-on cards with Ethernet PHYs. Some of them require specific
configuration in Linux DT, and the plan is to use DT overlays for them.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add some environment variables to facilitate the auto boot.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This patch adds the support of the spi nand device in mtdparts command
and in dfu_alt_info.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Generate automatically dfu_alt_info for the supported device.
The simple command "dfu 0" allows to start the dfu stack on usb 0
for the supported devices:
- dfu mtd for nand0
- dfu mtd for nor0
- dfu mmc for SDCard
- dfu mmc for eMMC
- dfu ram for images in DDR
The DUF alternate use the "part", "partubi" and "mmcpart" options
to select the correct MTD or GPT partition or the eMMC hw boot partition.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Update the sdmmc2 node for eMMC support on eval board stm32mp157c-ev1.
- update slew-rate for pin configuration
- update "vqmmc-supply"
- remove "st,sig-dir"
- add mandatory "pinctrl-names"
- add "mmc-ddr-3_3v"
This patch solve the eMMC detection issue for command "mmc dev 1".
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Device tree and binding alignment with kernel v5.3
and converted to SPDX.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This patch allows to fix the following compilation warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Enable the support of function keys on the USB keyboard. This is necessary
to test the USB keyboard driver.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Allow the unit test to pass full 8 byte scan code sequences to the USB
keyboard emulation driver and to parse multi-byte escape sequences.
The following features are not yet tested:
* LED status
* caps-lock
* num-lock
* numerical pad keys
The following features are not yet implemented by the USB keyboard
driver and therefore not tested:
* modifiers for non-alpha-numeric keys, e.g. <SHIFT><TAB> and <ALT><F4>
* some special keys, e.g. <PRINT>
* some modifiers, e.g. <ALT> and <META>
* alternative keyboard layouts
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Move constant USB_KBD_BOOT_REPORT_SIZE. This allows us to reuse it.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Provide support for F1-F12, Insert, Delete, Home, End, Page Up, Page Down.
As this leads to a size increase provide a customizing setting
CONFIG_USB_KEYBOARD_FN_KEYS.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Avoid duplicate translation of arrow key codes.
Reduce code size by avoiding strings and eliminating
usb_kbd_put_sequence().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
usb_kbd_buffer is defined as u8[]. So let usb_kbd_put_queue() use u8 as
type of the parameter for the new byte.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
On Gen5, when the FPGA is loaded and there was some prior interaction
between the HPS and the FPGA via bridges (e.g. Linux was running and
using some of the IPs in the FPGA) followed by warm reset, it has been
observed that there might be outstanding unfinished transactions. This
leads to an obscure misbehavior of the bridge.
When the bridge is enabled again in U-Boot and there are outstanding
transactions, a read from within the bridge address range would return
a result of the previous read instead. Example:
=> bridge enable ; md 0xff200000 1
ff200000: 1234abcd
=> bridge enable ; md 0xff200010 1
ff200010: 5678dcba <------- this is in fact a value which is stored in
a memory at 0xff200000
=> bridge enable ; md 0xff200000 1
ff200000: 90effe09 <------- this is in fact a value which is stored in
a memory at 0xff200010
and so it continues. Issuing a write does lock the system up completely.
This patch opens the FPGA bridges in 'bridge enable' command, the tears
them down again, and then opens them again. This allows these outstanding
transactions to complete and makes this misbehavior go away.
However, it is not entirely clear whether this is the correct solution.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Commit ec3dcea744 ("video: mxsfb: Configure the clock after eLCDIF reset")
causes boot regression on imx7d-pico/imx7d-sdb boards, so revert it
until a better solution is prepared.
This reverts commit ec3dcea744.
Reported-by: Joris Offouga <offougajoris@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Provide a defconfig which allows us to boot Raspberrry Pi 4
and Raspberry Pi 3 Model B/B+
Instead of using the embedded DTB as done in RPi3 we use the
devicetree provided by the firmware.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
For bcm283x based on arm64 we also have to change the mm_region.
Add assign this in mach_cpu_init() so we can create now one binary
for RPi3 and RPi4.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
As part of the effort to create one binary for several bcm83x SoCs
we read the IO base address from device-tree.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
We move the per SOC define BCM283x_BASE to a global variable.
This is a first step to provide a single binary for several bcm283x
SoCs.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
The fw_dtb_pointer was defined in the assembly code, which makes him
live in section .text_rest
Put that's not necessary, we can push the variable in the .data section.
This will prevent relocation errors like:
board/raspberrypi/rpi/rpi.c:317:(.text.board_get_usable_ram_top+0x8):
relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol
`fw_dtb_pointer' defined in .text section in board/raspberrypi/rpi/built-in.o
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
U-Boot support on Raspberry Pi 4 relies on the device-tree
provided by the firmware. The blob does not contain the
U-Boot specific pre-loc-rel properties. The result is, that
the U-Boot banner is not printed.
We fix this by setting the DM_FLAG_PRE_RELOC flag in the driver,
if we rely on a device-tree provided by the firmware.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Rename the file bcm283x-uboot.dtsi so that it get
automatically include through the scripts/Makefile.lib
using $(CONFIG_SYS_SOC))-u-boot.dtsi
Without this uarts and pincontroller miss the property dm-pre-reloc
and the first call to bcm283x_mu_serial_ofdata_to_platdata() fails
as the pins are not set correctly.
As a result the U-Boot banner isn't shown on boot.
Before commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we included bcm283x-uboot.dtsi directly in the device-tree file.
Which got deleted by the metioned commit.
This is a much robuster solution.
Reported-by: Tom Rini <trini@konsulko.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we deleted the label for the node soc from bcm283x.dtsi
As we don't need to add the property dm-pre-reloc to the soc node,
we can delete it from bcm283x-uboot.dtsi
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
The Raspberry Pi 4 upstream kernel device tree instroduces
a new compatible for the pinctroller. Add this to the driver
so that we can boot with the upstream kernel DT.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
- Clean vid/pid in Kconfig and add fastboot for rk3399
- add 'u-boot, spl-fifo-mode' for mmc
- Use FIT generator for rk3229 optee and rk3368 ATF
- fan53555: add support for Silergy SYR82X and SYR83X
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html
ARM11 is an armv6 implementation. So change the architecture flag for the
compiler to armv6 for ARM11.
Suggested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Now that we have buildman telling genboards.cfg to use an output
directory we need to ensure that it exists.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Fixes: bc750bca12 ("tools: buildman: Honor output directory when generating boards.cfg")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add __pycache__ to ignored files and extend the rule for _libfdt to also
include generated shared objects (e.g. _libfdt.cpython-37m-x86_64-linux-gnu.so).
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
With the move to using Python 3 for real, we encounter two different
issues. First, the file include/video_font_data.h includes at least one
UTF-16 character. Given that it does not include any CONFIG symbols it
is easiest to just ignore this file. Next, we encounter similar
problems with some dts/dtsi files that come from Linux. In this case
it's easiest to simply ignore all dts/dtsi files as there will not be
CONFIG symbols for us to migrate in them.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
As part of loading trustedfirmware, the SPL is required to place portions
of code into the socs sram but the mmc controllers can only do dma
transfers into the regular memory, not sram.
The results of this are not directly visible in u-boot itself, but
manifest as security-relate cpu aborts during boot of for example Linux.
There were a number of attempts to solve this elegantly but so far
discussion is still ongoing, so to make the board at least boot correctly
put both mmc controllers into fifo-mode, which also circumvents the
issue for now.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Rockchips dwmmc controllers can't do dma to non-ddr addresses,
like for example the soc-internal sram but during boot parts of
TrustedFirmware need to be placed there from the read FIT image.
So add handling for a u-boot,spl-fifo-mode to not put the mmc
controllers into fifo mode for all time.
The regular fifo-mode property still takes precedent and only
if not set do we check for the spl-specific property.
Suggested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Setup dwc3_device structure for non-dm gadgets, which is used
in rk3399 platforms.
dwc3_device would have basic regbase, dr_mode, high speed
and 16-bit UTMI+ etc.
Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix to use CONFIG_USB_DWC3_GADGET instead of CONFIG_USB_DWC3)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The 'debug' and 'printf' functions were previously added to the list of
logFunctions in commit 0cab42110d ("checkpatch.pl: Add 'debug' to
the list of logFunctions") and commit 397bfd4642 ("checkpatch.pl:
Add 'printf' to logFunctions") but these additions were lost when newer
versions of checkpatch were pulled in from the upstream Linux
kernel version.
This restores them so that you don't end up in a situation where
checkpatch will give a warning for "quoted string split across lines"
which you cannot fix without getting a warning for "line over 80
characters" instead.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
remove from NXP arm32 all layerscape boards and
build them instead in already existing layerscape
jobs (which now not only build aarch64 boards)
Signed-off-by: Heiko Schocher <hs@denx.de>
move orangepi builds into a new job, and exclude
orangepi builds from sunxi and rockchip jobs.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
U-Boot has two different variants of dwc3 initializations,
- with dm variant gadget, so the respective dm driver would
call the dwc3_init in core.
- with non-dm variant gadget, so the usage board file would
call dwc3_uboot_init in core.
The driver probe would handle all respective gadget properties
including phy interface via phy_type property and then trigger
dwc3_init for dm-variant gadgets.
So, to support the phy interface for non-dm variant gadgets,
the better option is dwc3_uboot_init since there is no
dedicated controller for non-dm variant gadgets.
This patch support for adding phy interface like 8/16-bit UTMI+
code for dwc3_uboot.
This change used Linux phy.h enum list, to make proper code
compatibility.
Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Technically the default mmc device for fastboot would
use eMMC if the board support for it.
Rockchip platform access device 0 for eMMC so, use the
same device number for rk3328.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Select CONFIG_FASTBOOT_FLASH, CONFIG_FASTBOOT_FLASH_MMC_DEV
for rockchip SoC plaforms in fastboot Kconfig file instead
of defined it in board defconfig.
This eventually drop the explicit configs defined in
supporting board defconfig files.
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip support differnet or common gadget product number
between Rockchip SoCs like,
0x310a - rk3036
0x320a - rk3229, rk3288
0x330a - rk3328
So, select them on Kconfig based on platform specific
config defined.
This eventually drop the explicit configs defined in
supporting board defconfig files.
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Gadget vendor number, 0x2207 is common across all platfroms
supported in Rockchip SoC.
So, select the same number globally, if ARCH_ROCKCHIP.
This eventually drop the explicit configs defined in supported
board defconfig files.
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Select the gadget manufacturer as 'Rockchip' for
all rockchip platform SoC's.
This eventually drop the explicit defined added
on supported board defconfig files.
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
fan53555_regulator_set_value() passes its own dev to pmic_clrsetbits()
instead of its parent (pmic). As result u-boot crashes when you try to
set voltage on fan53555 regulator
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
That's not correct and it breaks SMBUS-style reads and and writes for
some chips (e.g. SYR82X/SYR83X).
Stop bit should be sent only after the last message.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
SYR82X and SYR83X are almost identical to FAN53555, the only difference
is different die ID and revision, voltage ranges and steps.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
For all the Rockchip SoCs with SPL_LOAD_FIT enable, we need to build
u-boot.itb with U-Boot proper and ATF/OPTEE.
All the Rockchip boards with SPL_LOAD_FIT now supports FIT generator to
get ATF/OPTEE binary path from environment and pass the build even if no
ATF/OPTEE binary exist, so we can enable this feature for the rockchip
platform.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The RK3368 lion board ATF can use bl31.elf like RK3399 and get the FIT
source with generic FIT generator script at:
arch/arm/mach-rockchip/make_fit_atf.py
And then we can use 'BL31' environment to get the path of bl31.elf
instead of copy it into U-Boot folder.
CC: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use generator script so that we can use environment for TEE source.
$TEE for tee.bin, and if file not exist, the script can report a warning,
and meke the build success without a error.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Some of the ARM11 boards have tight limits on the size of U-Boots. Hence
use EFI_LOADER=n as default on ARM11.
Set EFI_LOADER=y for the Raspberry Pi and Raspberry Pi Zero as these boards
have sufficient storage on the SD card.
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA
drive strength has caused CE test to fail. This requires changes on the
pad skew for EMAC0 PHY driver. Based on several measurements done, Tx
clock does not require the extra 0.96ns delay which was needed in
Arria10.
Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting dwc2_fifo_read to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting two functions to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
- In ARMv8 NXP Layerscape platforms we also need to make use of
CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so.
- On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define
to 0.
- Add Kconfig entry for ENV_ADDR.
- Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it.
- Add ENV_xxx_REDUND options that depend on their primary option and
SYS_REDUNDAND_ENVIRONMENT
- On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR
for the pre-main-U-Boot environment location.
- On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but
rather it being non-zero, as it will now be zero by default.
- Rework the env_offset absolute in env/embedded.o to not use
CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within
ENV_IS_IN_FLASH.
- Migrate all platforms.
Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: uboot-stm32@st-md-mailman.stormreply.com
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
We can only configure and set the environment in SPL when we have a
particular environment location set that is not "nowhere" like it is in
SECURE_BOOT designs. Update the code to reflect that.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
These functions can only be built and used when we have
ENV_IS_IN_SPI_FLASH, use that as a guard.
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
We have CONFIG_ENV_SIZE_IS_REDUND but don't really use it. We have one
board where we can simply multiple CONFIG_ENV_SIZE by two for the same
result. The other place where we could but were not previously using
this is for where env_internal.h checks for if we should set
ENV_IS_EMBEDDED. This seems like the most likely use, historically, of
the variable, but it was not used. Add logic to check for this now.
Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The board file has a build time check to ensure that we do not have the
redundant environment overwriting the factory data. However, using the
symbol CONFIG_ENV_SIZE_REDUND isn't strictly needed as that is always
the same as CONFIG_ENV_SIZE. Use CONFIG_ENV_SIZE instead so that we can
later drop CONFIG_ENV_SIZE_REDUND.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The default mtdparts value grew a trailing zero during the Kconfig
conversion. This is because the mtdparts value in the header file
had a \0 at the end, which got misconverted into plain 0 instead of
being dropped.
Signed-off-by: Marek Vasut <marex@denx.de>
Fixes: 43ede0bca7 ("Kconfig: Migrate MTDIDS_DEFAULT / MTDPARTS_DEFAULT")
Reviewed-by: Tom Rini <trini@konsulko.com>
To use this DM timer on socfpga as system tick, it needs to take itself
out of reset.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The file arch/arm/mach-socfpga/include/mach/misc.h used the same include
guard as the global include/misc.h.
Fix this by giving the arch file an arch prefix.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Make the function pointer struct const, as it does not need to be
writable. This doesn't really change anything other than moving this
variable to a different section. No functional change.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Commit 2a51e16bd5 ("configs: Make USE_TINY_PRINTF depend on SPL||TPL and be default")
enable USE_TINY_PRINTF by default, disable it for Stratix10.
Resync with savedefconfig.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add #address-cells and #size-cells to memory node to fix incorrect memory
size decoding in recent Uboot version.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Today in initr_reloc_global_data() we use some non-obvious tests to
determine if we need to relocate the env_addr within gd or not. In
order to facilitate migration of other symbols to Kconfig we need to
introduce a new symbol for this particular use case.
Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
We only need to build and link input.o when we have any of
CONFIG_KEYBOARD, CONFIG_DM_KEYBOARD (and SPL/TPL variants) or
CONFIG_TEGRA_KEYBOARD set.
Signed-off-by: Tom Rini <trini@konsulko.com>
Pull request for UEFI sub-system for efi-2020-01-rc4
Fix errors due to unaligned memory access:
* disable UEFI except for ARMv8, ARMv7, ARM11
* enable unaligned access support on ARM11
Remove an unused function.
xhci.h has now been moved to include/usb/ directory. Therefore, update the
path in the Cadence USB drivers.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
With an implementation for allow_unaligned() available for arm1136 and
arm1176 UEFI can be supported on these architectures.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The UEFI spec mandates that unaligned memory access should be enabled if
supported by the CPU architecture.
This patch implements the function unaligned_access() to set the enable
unaligned data support flag and to clear the aligned flag in the system
control register (SCTLR). It is called when UEFI related commands like
bootefi are invoked.
Reported-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Tested-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Tested-by: Guillaume Gardet <Guillaume.Gardet@arm.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
fatload USB was reported to fail on the Sheevaplug. Debugging showed that
this was caused by an incorrect unaligned write to memory in
path_to_uefi().
UEFI on ARM requires that unaligned memory access is enabled.
* ARMv5 does not support unaligned access at all.
* ARMv6 supports unaligned access when we clear the A flag and set the
U flag.
* On ARMv7 unaligned access is possible when clearing the aligned flag,
which we do in function allow_unaligned() (arch/arm/cpu/armv7/sctlr.S).
For none of the other cpus in arch/arm/cpu/ we have implemented a
similar function.
* ARMv8 allows unaligned access.
Let EFI_LOADER on ARM depend on SYS_CPU=armv7 or SYS_CPU=armv8.
Once we have implemented allow_unaligned() for other ARM CPUs we can add
these to Kconfig.
Reported-by: Gray Remlin <gryrmln@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add DM support for Silicon(SIL3131 / SIL3132 / SIL3124) sata driver as
few of the PowerPC platforms such as P series based boards need to
use SATA_SIL with DM,
Also fix below warning while PowerPC P series boards compilation,
===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add DM support for Freescale PowerPC sata driver used for PowerPC T series
SoCs,
CONFIG_BLK needs to be enabled on these platforms. It adds the SATA
controller as AHCI device, which is strictly speaking not correct,
as the controller is not AHCI compatible, But the U-Boot AHCI uclass
interface enables the usage of this DM driver,
Also fix below warning while PowerPC T series boards compilation,
===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
- fix i.MX6ULL evk black screen observed while reboot stress tests
- remove "synopsys,dw-mipi-dsi" compatible to reduce the device tree
differences between Linux and U-Boot for stm32mp1 platform
- Add support for rockchip SoC: PX30, RK3308
- Add and migrate to use common dram driver: PX30, RK3328, RK3399
- Add rk3399 board Tinker-s support
- Board config update for Rock960, Rockpro64
Support tinker-s board. The board is equivalent of tinker board
except of emmc.
TODO:
- support of usb current burst when the board is powered from pc
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
dmc is used to initialize the memory controller. It's needed by
u-boot. Move it in the specific section
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
We shouldn't force which allocator the SPL uses, since there's no
platform requirement for one over the other: in fact, we currently allow
selection of the TPL allocator but not the SPL one!
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The common SPL removed SoC-specific code for RK3399's SPL and in the
process caused the previously-unconditional DRAM initialization in
board_init_f() to only happen when compiling a configuration that does not
support TPL, meaning DRAM never gets initialized if TPL is supported but
disabled.
Fix this by omitting the DRAM init in SPL only when we are configured to
also build a TPL. This fixes custom configurations that have disabled
TPL, and it should also unbreak the "ficus-rk3399", "rock960-rk3399",
and "chromebook_bob" defconfigs, although since I don't have any of
those devices I can't confirm they're broken now.
Fixes: b7abef2ecb ("rockchip: rk3399: Migrate to use common spl board file")
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The common SPL code reordered the DRAM initialization before
rockchip_stimer_init(), which as far as I can tell causes the RK3399 to
lock up completely.
Fix this issue in the common code by putting the DRAM init back after
timer init. I have only tested this on the RK3399, but it wouldn't make
any sense for the timer init to require DRAM be set up on any system.
Fixes: b7abef2ecb ("rockchip: rk3399: Migrate to use common spl board file")
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
ROC-RK3308-CC is a rk3308 based board designed by
Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi
on board.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add dts file for ROC-RK3308-CC from firefly.
Sync form linux rockchip for v5.5-armsoc/dts64:
"arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc"
(sha1: 4403e1237be3af0977aa23ef399e3496316317a0)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Usage:
(1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
(2) cat spl/u-boot-spl.bin >> idbloader.img
(3) upgrade_tool wl 0x40 idbloader.img
Note:
When use ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in(1)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Add vdd_log node according to rock960 schematic V13.
This patch affect two boards:
- Rock960 Model A
- Ficus
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The u-boot specific pieces in the dts files should be in u-boot.dtsi
not the main files, this allows easier sync with upstream. The
rk3399.dtsi has a mix of both so move them all for consistency.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix with missing pmugrf)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
rockpro64 needs to setup I/O domains in order for USB to work in u-boot.
Since we currently don't have a driver to do that, split it into its own
board file and initialize I/O domains here.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so
without the leading CONFIG_. The clock drivers all wrongly check for
CONFIG_RESET_ROCKCHIP, fix that
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.
So we can get rid of the open-coded reset init and just fix
the correct cru reference.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The rk3399 VD_CENTER voltage domain is not subject to dynamic voltage
scaling. So the regulator reset voltage of 0.9V is used on this board.
Let u-boot initialize the center voltage to 0.95V as it is done for the
VD_LOGIC domain. This avoids instability and occasional linux kernel
Opses on this board.
Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The most important change for u-boot is the fix for the vdd-log pwm
voltage regulator to avoid overvoltage for the VD_LOGIC power domain.
Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
roc-rk3399-pc_defconfig is committed in below
commit <8a681f4c5aa15db51ad0209734859c9fe7c29cfd> ("rockchip: rk3399:
Add ROC-RK3399-PC support")
which doesn't follow the existing defconfigs on rk3399.
So, rename as followed with other rk3399 defconfigs.
Cc: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Few important regulator power rails fixes are available in
linux-next, so sync them same.
Here is the last commit details:
commit <9f7f9b610e1b7d2dc86c543ab0dfcf781bd42326> ("arm64: dts:
rockchip: Fix roc-rk3399-pc regulator input rails")
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The px30 evb is an evaluation board for the px30 together with a dsi-
connected display. This adds board and config files for it.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add core architecture code to support the px30 soc.
This includes a separate tpl board file due to very limited
sram size as well as a non-dm sdram driver, as this also has
to fit into the tiny sram.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Newer Rockchip socs use a different ip block to handle one-time-
programmable memory, so depending on what got enabled get the cpuid
from either source.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all
cases, making the TPL bigger. There may be cases where the TPL is really
size constrained due to its underlying ram size.
Therefore introduce a new TPL_FRAMEWORK option and make the relevant
conditionals check for both. The default is set to "y if SPL_FRAMEWORK"
to mimic the previous behaviour where the TPL would always get the
SPL framework if it was enabled in SPL.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There are some code different with rockchip vendor code which may lead
to different bugs, including:
1) Fix setting error about LPDDR3 dram size ODT.
2) Set phy io speed to 0x2.
3) Fix setting error about phy_pad_fdbk_drive.
4) Fix setting error about PI_WDQLVL_VREF_EN
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The io setting are updated after some bugfix in different rk3399 boards,
sync the code from vendor.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip
vendor code;
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Add capacity detect for rk3399 so that the driver able to detect the
capacity automatically.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.
For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The noc register bit definition may be the same for different SoC while
the offset of the register may be different, add the struction
definition as common code.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This sdram_phy_px30.c is based on PX30 SoC, the functions are common
for phy, other SoCs with similar hardware could re-use it.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The debug info for dram is main about the capacity related info which is
very important the board init, so set this default enable.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We are using sys_reg2 and sys_reg3 as ddr cap info, sync the variable
name to what we real use to avoid confuse people.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Since we have new DRAM type and to support different DRAM size in different
CS, we need more bits, so introduce sys_reg3 to record the info.
Note that the info in sys_reg3 is extension to sys_reg2 and the info in
sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as
VERSION2.
All the ENC macro are moved to sdram_common.h since the sdram.c only
need to do the info decode.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The sdram.h suppose to be helper file for sdram.c which including dram
size decode and some u-boot related dram init interface, and all
structure and function for dram driver move to sdram_common.h
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The header file sdram.h is used for rk3288 and similar SoCs, rename it
to make it more understandable.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
According to discussion in the Linux PCI list [1], the dma-ranges should
be continuous and describe the entire inbound window which the controller
can address and not take into account the possible DRAM holes.
Temporarily disable this code which updates the dma-ranges until this
meaning is sorted out.
[1] PCI: rcar: Do not abort on too many inbound dma-ranges
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Pull request for UEFI sub-system for efi-2020-01-rc3
The following changes for the UEFI subsystem are provided:
* allow building UEFI binaries on the sandbox
* enable access to file systems without partition tables
* correctly check the return value of efi_dp_from_file()
fixes: 8ab452d587
When compiling list of cover letter cc addresses, using null as a
separater, then encoding to utf-8 results in lots of "\x00" as
separators. patman then doesnt understand that when it comes to
repoting the list to send-email.
Fix this by not encoding to utf-8, as done for the other patch files.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Compiling arch/sandbox/cpu/os.c results in an error
../arch/sandbox/cpu/os.c: In function ‘os_find_text_base’:
../arch/sandbox/cpu/os.c:823:12: error: cast to pointer from
integer of different size [-Werror=int-to-pointer-cast]
823 | base = (void *)addr;
| ^
cc1: all warnings being treated as errors
The size of void* differs from that of unsigned long long on 32bit
systems.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
OP-TEE can get supplied with a devicetree and will then insert
its firmware node and reserved-memory sections into it.
As this devicetree often is not the one supplied to a later
loaded kernel, a previous commit added functionality to transfer
these nodes onto that new devicetree.
To make sure this functionality stays intact, also add a test
for the transfer functionality.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The loading convention for optee or any other tee on arm64 is as bl32
parameter to the trusted-firmware. So TF-A gets invoked with the TEE as
bl32 and main u-boot as bl33. Once it has done its startup TF-A jumps
into the bl32 for the TEE startup, returns to TF-A and then jumps to bl33.
All of them get passed a devicetree as parameter and all components often
get loaded from a FIT image.
OP-TEE will create additional nodes in that devicetree namely a firmware
node and possibly multiple reserved-memory nodes.
While this devicetree is used in main u-boot, in most cases it won't be
the one passed to the actual kernel. Instead most boot commands will load
a new devicetree from somewhere like mass storage of the network, so if
that happens u-boot should transfer the optee nodes to that new devicetree.
To make that happen introduce optee_copy_fdt_nodes() called from the dt
setup function in image-fdt which after checking for the optee presence
in the u-boot dt will make sure a optee node is present in the kernel dt
and transfer any reserved-memory regions it can find.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
The phandlep pointer returning the phandle to the caller is optional
and if it is not set when calling fdtdec_add_reserved_memory() it is
highly likely that the caller is not interested in a phandle to the
created reserved-memory area and really just wants that area added.
So just don't create a phandle in that case.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The change adding fdtdec_add_reserved_memory() already protected the added
phandle against the phandlep being NULL - making the phandlep var optional.
But in the early code checking for an already existing carveout this check
was not done and thus the phandle assignment could run into trouble,
so add a check there as well, which makes the function still return
successfully if a matching region is found, even though no-one wants to
work with the phandle.
Fixes: c9222a08b3 ("fdtdec: Implement fdtdec_add_reserved_memory()")
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove the pinctrl_decode_pin_config() API, because this
function is unused and not compatible with livetree
(it uses fdtdec_get_bool instead of ofnode API).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable gpio0 in SPL to allow the sdhci driver read the SD card-detect
signal.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
As mentioned in doc/README.arm-relocation gd->bd is not available in
dram_init() so we shouldn't attempt to access it.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
As we can build relocation code for the sandbox now we should enable the
unit tests that had to be disabled up to now.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
On the sandbox the UEFI binaries must match the host architectures.
Adjust the Makefiles. Provide the PE/COFF header and relocation files.
Allow building helloworld.efi on the sandbox.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
On the sandbox we should mark the stack area as EFI runtime memory like we
do on any other architecture.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Currently, a whole disk without any partitions is not associated
with EFI_SIMPLE_FILE_SYSTEM_PROTOCOL. So even if it houses some
file system, there is a chance that we may not be able to access
it, particularly, when accesses are to be attempted after searching
that protocol against a device handle.
With this patch, EFI_SIMPLE_FILE_SYSTEM_PROTOCOL is installed
to such a disk if part_get_info() shows there is no partition
table installed on it.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Only if no partition table exists, check for a file system on disk level.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Correctly check the return value of efi_dp_from_file().
If we can determine device path for the file, should not depend on the
device path for the device being requested.
Provide a function description for efi_dp_from_name().
Reported-by: Coverity CID 273159, CID 273158
Fixes: 08c51fff30 ("efi_loader: device_path: check against file path length")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
- Migrate the symbol CONFIG_SYS_REDUNDAND_ENVIRONMENT to Kconfig. This
is size neutral outside of two platforms with latent bugs being fixed
now and they no longer have "ENV_IS_NOWHERE" set along with their
intended location.
Move this symbol to Kconfig. As part of this we can drop a UBI-specific
symbol that was a stop-gap for not having this particular symbol in
Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
This board is setting CONFIG_ENV_IS_IN_SPI_FLASH in the header rather
than defconfig, fix.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board is setting CONFIG_ENV_IS_IN_MMC in the header rather than
defconfig, fix.
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove the compatible "synopsys,dw-mipi-dsi" added in U-Boot
(it don't exist in Linux kernel binding); it is only used
to bind the generic synopsys UCLASS_DSI_HOST "dw_mipi_dsi" to
the driver "stm32-display-dsi" UCLASS_VIDEO_BRIDGE
This binding is done in Linux kernel drivers without compatible
(dw_mipi_dsi_bind() is called in bind of driver, for example in
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c).
This patch does the same in U-Boot driver, the STM32 driver
calls during its bind the function device_bind_driver_to_node
to bind the generic driver "dw_mipi_dsi" at the same address.
This patch reduces the device tree differences
between Linux kernel and U-Boot for stm32mp1 platform.
Tested with v2020.01-rc1 on STM32MP157C-EV1 and STM32MP157C-DK2.
The dependency of driver is clearer and the probe order is guaranteed.
STM32MP> dm tree
Class Index Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
sysreset 0 [ ] syscon_reboot |-- reboot
simple_bus 0 [ + ] generic_simple_bus |-- soc
serial 0 [ + ] serial_stm32 | |-- serial@40010000
...
video_brid 0 [ + ] stm32-display-dsi | |-- dsi@5a000000
dsi_host 0 [ + ] dw_mipi_dsi | | |-- dsihost
panel 0 [ + ] rm68200_panel | | `-- panel-dsi@0
...
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Running stress reboot test on a i.MX6ULL evk board with a
custom LCD can lead to splash screen failure (black screen).
After comparing the eLCDIF initialization with the Linux kernel
driver, it was noticed that the eLCDIF reset is the first operation
that needs to be done.
So do like the eLCDIF Linux driver and move the eLCDIF clock
frequency configuration after the eLCDIF reset and just prior to
setting the RUN bit.
With this change applied, no more black screen issues has been
found during overnight reboot stress tests.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
With recent update in u-boot gitattributes all files are treated as regular
text files. This creates problems with special files and repo always
shows uncommitted files like below.
Your branch is up-to-date with 'origin/master'.
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git checkout -- <file>..." to discard changes in working directory)
modified: tools/logos/compulab.bmp
modified: tools/logos/denx-comp.bmp
modified: tools/logos/toradex.bmp
To fix above problem special files bmp/ttf files are treated as binary
files in the gitattributes.
Signed-off-by: Vignesh Rajendran <vignesh.rajendran@in.bosch.com>
Signed-off-by: Veeraiyan Chidambaram <veeraiyan.chidambaram@in.bosch.com>
The generated idbloader.img file that rockchip uses should
be not included in git status report
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
A recent change adjusted the symbol calculation to work on x86 but broke
it for Tegra. In fact this is because they have different needs.
On x86 devices the code is linked to a ROM address and the end-at-4gb
property is used for the image. In this case there is no need to add the
base address of the image, since the base address is already built into
the offset and image-pos properties.
On other devices we must add the base address since the offsets start at
zero.
In addition the base address is currently added to the 'offset' and 'size'
values. It should in fact only be added to 'image-pos', since 'offset' is
relative to its parent and 'size' is not actually an address. This code
should have been adjusted when support for 'image-pos' and 'size' was
added, but it was not.
To correct these problems:
- move the code that handles adding the base address to section.py, which
can check the end-at-4gb property and which property
(offset/size/image-pos) is being read
- add the base address only when needed (only for image-pos and not if the
image uses end-at-4gb)
- add a note to the documentation
- add a separate test to cover x86 behaviour
Fixes: 15c981cc (binman: Correct symbol calculation with non-zero image base)
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
This patch enable TPL support for firefly-rk3288 board, which works ths
same way with other RK3288 board like Tinker, evb.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work
as expected. When board_boot_order() `spl-boot-order.c` meets
"same-as-spl", it gets the conf by looking the boot_devices table by boot
source, and parse the node by the conf with:
node = fdt_path_offset(blob, conf);
which will failed without the "/" indicating the path.
Currently only entries of boot_devices in rk3399 have the "/" prefix.
Therefore add the missing ones in other boards.
Signed-off-by: Levin Du <djw@t-chip.com.cn>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to
limit the SPL size in 0x40000(start from 0) so that we don't need to do
the relocate for ATF loading.
Note that there will be separate BSS, STACK and MALLOC heap, so the size
0x40000(256KB) should be enough for SPL text.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config;
default to 0x4000000(64MB) instead of 0x80000(512KB) for this address
can support all the SoCs including those may have only 64MB memory, and
also reserve enough space for atf, kernel(in falcon mode) loading.
After the ATF entry move to 0x40000, the stack from 0x80000 may be override
when loading ATF bl31.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Trusted-Firmware can also initialize a secure payload to use as a trusted
execution environment. In general for the arm64 case this is provided as
separate image and uboot is supposed to also place it in a predetermined
location in memory and add the necessary parameters to the ATF boot params.
So add the possibility to get this tee payload from the provided FIT image
and setup things as necessary.
Tested on a Rockchip PX30 with mainline TF-A, mainline OP-Tee (with pending
PX30 support) and mainline 5.4-rc1 Linux kernel.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
A trusted execution environment should also get loaded as loadable from
a fit image, so add the possibility to present a tee.elf to make_fit_atf.py
that then gets included as additional loadable into the generated its.
For ease of integration the additional loadable is created as atf_(x+1)
after all others to re-use core generation loops.
Tested against the combinations of 1-part-atf and multi-part-atf each
time with and without a tee binary present.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fix a typo that caused incorrect values to be loaded into the DRAM
controller's deskew registers.
Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units
for the DDR frequency, causing the DRAM controller to be misconfigured
in most cases.
Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rk3328 can use same-as-spl option so next loaders are loaded from the same
medium.
Add the boot order in the rock64 dts otherwise booting from sdcard
will result in u-boot looking into the eMMC.
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.
Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Specification
- Rockchip RK3399
- LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply
Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1:
"arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC"
(sha1: fc702ed49a8668a17343811ee28214d845bfc5e6)
Signed-off-by: Andy Yan <andyshrk@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RK809 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(5*BUCKs, 9*LDOs, 2*SWITCHes)
- RTC
- Clocking
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RK817 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 1* BOOST, 9*LDOs, 1*SWITCH)
- RTC
- Clocking
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RK805 are a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 3*LDOs)
- RTC
- Clocking
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RK816 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 1*BOOST, 6*LDOs, 1*SWITCH)
- RTC
- Clocking
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to adapt the following pmics, make the interface more compatible.
Support buck and ldo suspend voltage setting and getting.
Supprot buck and ldo suspend enable/disable setting and getting.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This script was only used on the MX1ADS board (and possibly other MX1
platforms) to program the flash. As we no longer have any boards for
that SoC, remove this tool.
Fixes: e570aca947 ("mx1ads: remove board support")
Signed-off-by: Tom Rini <trini@konsulko.com>
Due to the commit 4b0bcfa7c4 ("Kconfig: Migrate CONFIG_BOOTM_* options")
BOOTEFI and BOOTEFI_HELLO_COMPILE (and other BOOTEFI configs) are
displayed in a long distance. This will make it difficult for us to
understand that those configurations are closely related.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry
is missed by
commit 6d82517836 ("configs: Don't use SPI_FLASH_BAR as default")
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
While getting the 'subarg' of 'hwconfig' env variable in
config_core_prefetch(), if no hwconfig variable is defined,
below warning is received:
WARNING: Calling __hwconfig without a buffer and
before environment is ready
Fix this by checking 'hwconfig' env variable.
If not found return without further processing.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Add the missing RGMII PHY modes in which case the MAC has configure its
RGMII settings. The only difference between these modes is the RX and
TX delay configuration. A user might choose any RGMII mode in the device
tree.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The saved ofnode is used by some PHY drivers to access the device tree
node of the PHY.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The fsl-layerscape already occupies board_late_init(), therefore it is
not possible for a board to have its own board_late_init(). Introduce
fsl_board_late_init() which can be implemented in the board specific
code.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The clocks are not dependent on the target but only on the SoC.
Therefore, convert the CONFIG_TARGET_x macros to the corresponding
CONFIG_ARCH_x. This will allow other targets to automatically use the
common code. Otherwise every new target would have to add itself to the
"#if defined(CONFIG_TARGET_x) || .." macros.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below
compilation error appears
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
Fix it by wrapping with CONFIG_IS_ENABLED().
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
If the secure world reset handlers are used (via CONFIG_PSCI_RESET),
then do not use the layerscape-specific implementation.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This allows the use of PSCI calls to trusted firmware to
initiate reset and poweroff events with CONFIG_PSCI_RESET and
CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target
board has implemented a custom reset or poweroff procedure in EL3.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.
While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.
Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The SPL FIT will only have one DTB, so remove support for multi-DTB. This
also removes an early access to EEPROM used to select the DTB that is not
valid in SPL at the point at which it is accessed, that always returns
false for GP devices and causes a firewall expection on HS.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
There is an option to enable the board detection for TI platforms.
If this is option is not set, there is no reason to set the EEPROM
bus address or chip address.
This patch makes both EEPROM_BUS_ADDRESS and EEPROM_CHIP_ADDRESS
depend on TI_I2C_BOARD_DETECT.
Signed-off-by: Adam Ford <aford173@gmail.com>
The SPL is too tight, and it cannot start any longer. To
help reduce the size of SPL, we need to remove some non-critical
features.
This patch removes SPL_GPIO_SUPPORT to free up some operating space.
Signed-off-by: Adam Ford <aford173@gmail.com>
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight.
This patch removes the all but GPIO4 from the spl device tree to
reduce the SPL footprint.
Signed-off-by: Adam Ford <aford173@gmail.com>
The SPL is too tight, and it cannot start any longer. To
help reduce the size of SPL, we need to remove some non-critical
features.
This reverts commit 66063a7c13.
Signed-off-by: Adam Ford <aford173@gmail.com>
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight.
This patch removes the all but GPIO4 from the spl device tree to
reduce the SPL footprint.
Signed-off-by: Adam Ford <aford173@gmail.com>
The PMIC enables power to the MMC card by default, but depending
on the state it was left when restarted, it's possible the MMC
may be powered down.
This patch patch explicitly tells the twl4030 to power the MMC.
Signed-off-by: Adam Ford <aford173@gmail.com>
TPS62363 is used to control the MPU_VDD voltage, so enable the driver
for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add VTM node for voltage and thermal management. For u-boot, this is needed
for supporting AVS class 0, as the efuse values for the OPPs are stored
under the VTM.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Link the vdd-supplies for the voltage domains under the VTM node. Also,
enable the node under SPL. This will enable the AVS class 0 support on
am65x-evm board.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
MPU voltage on AM65x-evm is controlled via the TPS62363 chip attached
to i2c0 bus. Add device node for this so that it can be controlled via
a regulator driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add VTM node for voltage and thermal management. For u-boot, this is needed
for supporting AVS class 0, as the efuse values for the OPPs are stored
under the VTM.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
j721e SoCs have different OPP tables. Add support for the same.
Note: DM Still has lot of voltages TBD hence the correct
values need to be programmed once they are published.
Signed-off-by: Keerthy <j-keerthy@ti.com>
TPS6236x is a family of step down DC-DC converters optimized for battery
powered portable applications for a small solution size. Add a regulator
driver for supporting these devices.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
That option is currently not used by any defconfig and could not be set
anymore since it became mandatory to used Kconfig when introducing new
options with U-Boot v2016.11 or commit eed921d923 ("Kconfig: Add a
whitelist of ad-hoc CONFIG options") and commit 371244cb19 ("Makefile:
Give a build error if ad-hoc CONFIG options are added").
It was also not considered when fixing build warnings in
commit 39ac34473f ("cmd_mtdparts: use 64 bits for flash size,
partition size & offset") and could probably not be compiled anyway
after commit dfe64e2c89 ("mtd: resync with Linux-3.7.1"), which
renamed some members of struct mtd_info … so it was probably broken
since then, which was U-Boot v2013.07-rc1.
However it still seems to work, see example output below:
U-Boot 2019.10-00035-g06a9b259ca-dirty (Oct 30 2019 - 14:03:44 +0100)
CPU: SAMA5D27 1G bits DDR2 SDRAM
Crystal frequency: 24 MHz
CPU clock : 492 MHz
Master clock : 164 MHz
Model: ***
DRAM: 128 MiB
NAND: 256 MiB
Loading Environment from NAND... OK
In: serial@f8020000
Out: serial@f8020000
Err: serial@f8020000
Net: eth0: ethernet@f8008000
Hit keys 'tt' to stop autoboot (3 seconds).
U-Boot> mtdparts
device nand0 <atmel_nand>, # parts = 8
#: name size net size offset mask_flags
0: bootstrap 0x00040000 0x00040000 0x00000000 1
1: uboot 0x000c0000 0x000c0000 0x00040000 1
2: env1 0x00040000 0x00040000 0x00100000 0
3: env2 0x00040000 0x00040000 0x00140000 0
4: fpga_led 0x00040000 0x00040000 0x00180000 1
5: reserved 0x00040000 0x00040000 0x001c0000 1
6: rootfs_rec 0x03200000 0x03200000 0x00200000 1
7: filesystem 0x0cc00000 0x0cb80000 (!) 0x03400000 0
active partition: nand0,0 - (bootstrap) 0x00040000 @ 0x00000000
defaults:
mtdids : nand0=atmel_nand
mtdparts: mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env1),256k(env2),256k(fpga_led)ro,256k(reserved)ro,50M(rootfs_rec)ro,-(filesystem)
Signed-off-by: Alexander Dahl <ada@thorsis.com>
This declaration is not used anywhere in the whole tree. There is a
function 'mtd_id_parse()' which was renamed from 'id_parse()' in
commit 68d7d65100 ("Separate mtdparts command from jffs2"), but that
function is not used (anymore?) in cmd nand and build is fine without
that declaration, so it's probably just safe to remove.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
As part of disabling caches MMU as well gets disabled. But MMU is not
available on all armv7 cores like R5F. So disable MMU only if it is
available.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
'make tests' on a 32bit ARM system leads to
In file included from ../common/cli_hush.c:79:
../include/malloc.h:364:7: error: conflicting types for ‘memset’
void* memset(void*, int, size_t);
^~~~~~
In file included from ../include/compiler.h:126,
from ../include/env.h:12,
from ../common/cli_hush.c:78:
../include/linux/string.h:103:15:
note: previous declaration of ‘memset’ was here
extern void * memset(void *,int,__kernel_size_t);
^~~~~~
In file included from ../common/cli_hush.c:79:
../include/malloc.h:365:7: error: conflicting types for ‘memcpy’
void* memcpy(void*, const void*, size_t);
^~~~~~
In file included from ../include/compiler.h:126,
from ../include/env.h:12,
from ../common/cli_hush.c:78:
../include/linux/string.h:106:15:
note: previous declaration of ‘memcpy’ was here
extern void * memcpy(void *,const void *,__kernel_size_t);
^~~~~~
According to the U-Boot coding style guide common.h should be the first
include.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
When full malloc is enabled and SYS_MALLOC_F is also enabled, the simple
pre-reloc heap is used before relocation. In this case, calloc() uses
the MALLOC_ZERO macro to zero out the allocated memory. However, since
this macro is specially crafted for the dlmalloc implementation, it
does not always work for simple malloc.
For example, when allocating 16 bytes via simple malloc, only the first
12 bytes get zeroed out. The last 4 bytes will remain untouched.
This is a problem for DM drivers that are allocated before relocation:
memory allocated via 'platdata_auto_alloc_size' might not be set to
zero, resulting in bogus behaviour.
To fix this, use 'memset' instead of 'MALLOC_ZERO' to zero out memory
that compes from simple malloc.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
As SPL_SPI_FLASH_SUPPORT cannot work without SPL_SPI_SUPPORT, fix
dependencies to prevent enabling SPI flash support without basic SPI
support.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
The default implementation of ERR_PTR/PTR_ERR maps errno values at the
and of the address range (e.g. -EINVAL/-22 gets 0xFFFFFFEA).
For socfpga gen5 SPL, this doesn't really work, as the heap is nearly
at the end of the 32 bit address range.
This patch adjusts the ERR_PTR_OFFSET to map errno values into the range
of the Boot ROM, which should not be used for valid pointers.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This patch changes ERR_PTR/PTR_ERR to use CONFIG_ERR_PTR_OFFSET to map
errno values into a pointer region that cannot contain valid pointers.
IS_ERR and IS_ERR_OR_NULL have to be converted to use PTR_ERR, too,
for this to work.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Some U-Boot pointers have redundant information, so we can use a scheme
where we can return either an error code or a pointer with the same
return value. The default implementation just casts the pointer to a
number, however, this may fail on platforms where the end of the address
range is used for valid pointers (e.g. 0xffffff00 is a valid heap pointer
in socfpga SPL). For such platforms, this value provides an upper range
of those error pointer values - up to 'MAX_ERRNO' bytes below this value
must be unused/invalid addresses.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Provide optimized memcpy_{from,to}io() and memset_io(). This is required
when moving large amount of data to and from IO regions such as IP
registers or accessing memory mapped flashes.
Code is borrowed from Linux Kernel v5.4.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
API_dev_write(va_list ap) is currently lacking the write support
to storage devices because, historically, those devices did not
implement block_write()
The solution has been tested by loading and booting a (patched)
GRUB instance in a QEMU vexpress-a9 environment. The disk write
operations were triggered with GRUB's save_env command.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Now that we have again fixed the problems that building with clang
exposes, enable these tests on Azure and GitLab-CI as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
When using the OVERRIDE variable we need to pass -O to buildman as well
to use the "override" option to buildman.
Fixed: e9500f49ea ("travis: Use buildman for building with clang")
Signed-off-by: Tom Rini <trini@konsulko.com>
Newer versions of LLVM-7 will provide an unused function warning over
console_doenv() in the case of SYS_CONSOLE_IS_IN_ENV not being enabled
as can be the case in SPL. Add guards around this function.
Signed-off-by: Tom Rini <trini@konsulko.com>
Add a new bcdDevice entry for Cadence USB gadget controller similar to
other controller and add gadget_is_cdns3() macro as well.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add driver to handle TI specific wrapper for Cadence USB3 controller
present on J721e SoC. Based on Linux driver for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Implement udc_set_speed() callback to limit Controller's speed to
high-speed/full-speed when working with gadgets that are high-speed or
full-speed only
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add support for USB3 host and gadget driver. This is a direct sync of
Linux kernel Cadence USB stack that from v5.4-rc1 release.
Driver has been modified so that it compiles without errors against
U-Boot code base.
Features not required for U-Boot such as scatter-gather DMA and OTG
interrupt handling has been dropped.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
[jjhiblot@ti.com: Add PHY support]
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This patch was copied from kernel commit: 67fdfda4a99ed.
Sometimes, the gadget driver we want to run has max_speed lower than
what the UDC supports. In such situations, UDC might want to make sure
we don't try to connect on speeds not supported by the gadget
driver because that will just fail.
So here introduce a new optional ->udc_set_speed() method which can be
implemented by interested UDC drivers to achieve this purpose.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add match_ep() op to usb_gadget_ops similar to Linux kernel which is
useful in finding a suitable ep match for the function driver. This will
avoid adding more gadget_is_xxx() handling code to usb_ep_autoconfig().
Also sync usb_ep_caps struct thats is usually used in the match_ep()
callback by the gadget controller driver
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Import for_each_set_bit() and associated macros and functions from
Linux. This is useful in parsing interrupt registers and take action on
each bit that is set.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
imx targets are defined in arch/arm/mach-imx/Makefile.
Some of them are dependent on targets defined in main
Makefile. For the Makefile in arch/arm/mach-imx this
targets must be finished before the imx targets are
build, if not you get for example the error:
make -f /home/hs/abb/mainlining/u-boot/scripts/Makefile.build obj=arch/arm/mach-imx u-boot-dtb.imx
make[2]: *** No rule to make target 'u-boot-fit-dtb.bin', needed by 'u-boot-dtb.imx'. Stop.
make[1]: *** [/home/hs/abb/mainlining/u-boot/Makefile:1123: u-boot-dtb.imx] Error 2
make[1]: *** Waiting for unfinished jobs....
make[1]: Leaving directory '/work/hs/compile/u-boot/aristainetos2_defconfig'
make: *** [Makefile:148: sub-make] Error 2
compile failed
In above case of CONFIG_MULTI_DTB_FIT is defined, the
u-boot-dtb.imx is dependent on the u-boot-fit-dtb.bin
which may is not build yet ...
I could reproduce this error on a travis build also if
I build an out-of-tree build on a local machine with a
build directory on a "slow" slow storage device. If
building the same source target with a build dir on a
fast storage device, the build works.
I found no solution to tell the arch/arm/mach-imx/Makefile
to find the targets in main Makefile, if there is a way
this would be the better fix.
I solved it by adding a IMX_DEPS var, which holds a list
of main u-boot targets, which must be finished, before
calling imx targets and fixed the build for imx
targets which enabled CONFIG_MULTI_DTB_FIT.
I think it is just luck, that imx targets with
CONFIG_OF_SEPARATE enabled build, because the
u-boot-dtb.imx target depends on u-boot-dtb.bin
which gets build early enough before starting with
u-boot-dtb.imx. May this targets should be fixed too.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
add DM PCI support on the socrates board.
use PCIE_FSL now.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
add socrates device tree from linux:
commit 71ae5fc87c34 ("Merge tag 'linux-kselftest-5.2-rc1' of
git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest")
and added SPDX license identifier.
Did not fix checkpatch warnings:
arch/powerpc/dts/socrates.dts:235: check: Please don't use multiple blank lines
arch/powerpc/dts/socrates.dts:238: error: code indent should use tabs where possible
Also, add me as board maintainer.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c
In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
With python3 we're now tripping over a long-standing problem with how we
add to the buildman file with some toolchains. We cannot have multiple
toolchain-alias sections as that leads to a parse error.
Signed-off-by: Tom Rini <trini@konsulko.com>
Update to latest libfdt and pylibfdt, with added size control
Update binman, dtoc, patman, buildman to Python 3
Update move_config, rkmux, microcode_tool to Python 3
Add more clks for fec_mxc according to Linux Kernel 5.4.0-rc1
drivers/net/ethernet/freescale/fec_main.c.
Since i.MX8MQ not support CLK_CCF, so add a check to restrict
the code only effect when CONFIG_IMX8M and CONFIG_CLK_CCF both defined.
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When CONFIG_$(SPL_)CLK not defined, the clock controller device
not exist, so to avoid boot failure for platform not have
CONFIG_$(SPL_)CLK, add a check.
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add i.MX8MM ccf driver support.
Modifed from Linux Kernel 5.3.0-rc1, drop some entries
that not used in U-Boot and adapt to U-Boot CCF style.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Lukasz Majewski <lukma@denx.de>
The IVT offset is changed on i.MX8MN. Use ROM_VERSION to pass the
v1 or v2 to mkimage.
v1 is for iMX8MQ and iMX8MM
v2 is for iMX8M Nano (iMX8MN)
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MN support loading images with rom api, so we implement
reuse board_return_to_bootrom to let ROM loading images.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MN has similar architecture with i.MX8MM, so it could reuse
the clock code of i.MX8MM, but i.MX8MN has different CCM root
configurations, so need a separate root entry.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The power domain tree is not accepted by Linux Kernel upstream.
only a single pd node is used currently, as following:
pd: imx8qx-pd {
compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
So to migrate to use upstream linux dts, we also need a driver
to support this.
This patch is to support the new method, compared with legacy power
domain tree, it will be simpiler, because each device will
has resource id as power domain index, it will be directly passed
to scfw, and no need to let power domain build that tree. If multiple
power domain is needed, it is the dts node should has correctly power
domains entry added and sequence correct.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The current i.MX8 power domain driver is based on i.MX vendor
power domain tree which will retire later.
The Linux upstream use a single pd node for power domain driver,
and U-Boot will adopt that. When U-Boot i.MX8 dts synced with
Linux Kernel upstream and related driver ready, the legacy
driver will be removed.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
clk and pinctrl will be get(probed) during each device probe,
we don't need to probe them in scu driver. Only need to bind the sub-nodes
(clk and iomuxc) of MU node with their drivers.
So drop the code to probe the clk/pinctrl, and this patch will make it
easy to add more subnodes.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
lpuart0 is the uart used by SPL and U-Boot proper, and DM_SERIAL
is enabled. Since uclass power domain is also enabled, to make
lpuart work properly, need add u-boot,dm-spl for lpuart power domain
and its parent.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
lpuart0 is the uart used by SPL and U-Boot proper, and DM_SERIAL
is enabled. Since uclass power domain is also enabled, to make
lpuart work properly, need add u-boot,dm-spl for lpuart power domain
and its parent.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
with u-boot,dm-spl added for imx8qm-pm node, and SPL_SIMPLE_BUS enabled,
the bind and probe code in board file could be removed.
Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To enable HS400(ES) and UHS for imx8m platforms, update the driver data
to share with imx8qm esdhc_soc_data.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
During mmc initialization, there are several calls to mmc_set_clock
and mmc_set_ios. When mmc_power_off, the mmc->clock will be set,
but the imx driver will use 400KHz. So the following calls
to mmc_set_ios will set the clock several times which is redundant
in fsl_esdhc_imx driver. So let's simplify to remove redundant
clock settings.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The QorIQ eSDHC on all platforms supports checking write protect
state through register bit. So check it always.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The fsl_esdhc_init() was actually to get configuration of mmc_config.
So rename it to fsl_esdhc_get_cfg_common() and make it common for both
DM_MMC and non-DM_MMC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This patch is to clean up bus width setting code.
- For DM_MMC, remove getting "bus-width" from device tree.
This has been done in mmc_of_parse().
- For non-DM_MMC, move bus width configuration from fsl_esdhc_init()
to fsl_esdhc_initialize() which is non-DM_MMC specific.
And fix up bus width configuration to support only 1-bit, 4-bit,
or 8-bit. Keep using 8-bit if it's not set because many platforms
use driver without providing max bus width.
- Remove bus_width member from fsl_esdhc_priv structure.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Voltage validation should be done by CMD8. Current comparison between
mmc_cfg voltages and host voltage capabilities is meaningless.
So drop current comparison and let voltage validation is through CMD8.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Controller initialization is not needed in fsl_esdhc_init().
It will be done in esdhc_init() for non-DM_MMC, and in
esdhc_init_common() in probe for DM_MMC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Update this tool to use Python 3 to meet the 2020 deadline.
Unfortunately this introduces a test failure due to a problem in pylibfdt
on Python 3. I will investigate.
Signed-off-by: Simon Glass <sjg@chromium.org>
When preparing to possible expand or contract an entry we reset the size
to the original value from the binman device-tree definition, which is
often None.
This causes binman to forget the original size of the entry. Remember this
so that it can be used when needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function should use a void * type, not char *. This causes an error:
TypeError: in method 'fdt_property_stub', argument 3 of type 'char const *'
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present patman test fail in some environments which don't use utf-8
as the default file encoding. Add this explicitly.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present all the 'command' methods return bytes. Most of the time we
actually want strings, so change this. We still need to keep the internal
representation as bytes since otherwise unicode strings might break over
a read() boundary (e.g. 4KB), causing errors. But we can convert the end
result to strings.
Add a 'binary' parameter to cover the few cases where bytes are needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bring over the fdt from this commit:
430419c (origin/master) tests: fix some python warnings
adding in the 'assumptions' series designed to reduce code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
This board appears to be very near its size limit and cannot accept the
new checking code in libfdt. Disable this code so this the board can
continue to build.
Signed-off-by: Simon Glass <sjg@chromium.org>
For better or worse libfdt recent grew a lot of code that checks the
validity of the device tree in great detail. When using unsigned or
unverified data this makes things safer, but it does add to code size.
Add some controls to select the trade-off between safety and code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Unfortunately libfdt needs this value now, which is present in the
stdint.h header. That file is just a placeholder in U-Boot and these sorts
of constants appear in the linux/kernel.h header instead.
To keep libfdt happy, add INT32_MAX too.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Conver TI CPSW driver to use dev/ofnode api.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
[trini: Add <dm/ofnode.h> to provide the prototype to ofnode]
Signed-off-by: Tom Rini <trini@konsulko.com>
- Add support for Intel FSP-S and FSP-T in binman
- Correct priority selection for image loaders for SPL
- Add a size check for TPL
- Various small SPL/TPL bug fixes and changes
- SPI: Add support for memory-mapped flash
We have once again reached a point where this board does not build in
some cases with supported toolchains due to reaching a size constraint.
To regain some space, disable support for Plan 9 / RTEMS images with the
bootm command.
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add subcommand for add writing BCB only, where we provide appropriate
offsets for firmware1 and firmware2 and size.
Example of usage:
> nandbcb bcbonly 0x00180000 0x00080000 0x00200000
Writing 1024 bytes to 0x0: randomizing
OK
Writing 1024 bytes to 0x20000: randomizing
OK
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Tested-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
On i.MX7 in a sake of reducing the disturbances caused by a neighboring
cells in the FCB page in the NAND chip, a randomizer is enabled when
reading the FCB page by ROM bootloader.
Add API for setting BCH to specific layout (and restoring it back) used by
ROM bootloader to be able to burn it in a proper way to NAND using
nandbcb command.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee>
Tested-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
We have once again reached a point where this board does not build in
some cases with supported toolchains due to reaching a size constraint.
To regain some space, disable support for Plan 9 / RTEMS images with the
bootm command.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This commit adds support for the brppt2 board. The board is based on the
i.mx6 dual-lite SoC.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Borrow ID reading code from Ye Li (NXP U-Boot, commit ID 5b443e3e2617)
but drop imx-mkimage commit ID reading since we now use in tree mkimage.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ,
so update the interface to add new argument.
Signed-off-by: Ye Li <ye.li@nxp.com>
[agust: fixed imx8m-power-domain build]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add function and new command "auth_cntr" for secure boot support.
When booting with life cycle set to OEM closed, we need to use
this function to authenticate the OS container and load kernel & FDT
from OS container to their destination.
Also add image authentication call when loading container images.
Users can set CONFIG_AHAB_BOOT=y to enable the feature. It is not
set at default.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Enable bd71837 pmic for i.MX8MM EVK board, need to set voltage for
DRAM and linux suspend voltage requirement.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We are going to add i2c pmic support before dram could be used.
So we need enable clk driver earlier, so use spl_early_init
and move clock controller probe eariler to board_init_f.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
It will be easy to separate SD/EMMC when booting in SPL stage, then
no need to bother which device is BOOT_DEVICE_MMC1/2.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add init_nand_clk to enable gpmi nand clock. Since i.MX8MQ not use CCF,
so we still use legacy mode to configure the clock.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The i.MX8MQ B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id.
It returns a magic number 0xff0055aa. update get_cpu_rev to support it,
and enable ocotp clock to access ocotp.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Migrate to DM_VIDEO, update the device tree and remove code that is no
longer necessary.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
This updates the i.MX8MQ device trees and, necessarily, also the
i.MX8MQ clock bindings. These are taken verbatim from from the
Linux kernel version v5.4-rc2, which three small changes which
were already part of the previous device tree:
* Keep the PSCI reserved memory range
* Keep the alias for ethernet, so that the MAC address can be set
* Keep the modified #include for the IOMUXC pins
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Acked-by: Peng Fan <peng.fan@nxp.com>
This commit adds falcon boot support (by also copying args necessary for
booting) to the SPL NOR memory driver.
After this change it is possible to use the falcon boot in the same way
as on NAND memories. The necessary configs (i.e. CONFIG_CMD_SPL_NOR_OFS)
are now defined in Kconfig.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
The mccmon6 has been used a "mixed" approach between SPL and
U-Boot proper sources.
This commit decoupes SPL and u-boot proper, which allows clear
distinction between those two code bases and facilitates
conversion to DM/DTS on this particular board.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit converts mccmon6's u-boot proper (in a single commit to avoid
build breaks) to use solely DM/DTS.
The DTS description of the mccmon6 has been ported from Linux kernel
(v4.20, SHA1: 8fe28cb58bcb235034b64cbbb7550a8a43fd88be)
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In order for 'bmode emmc' to work, the eMMC needs to be initialized in the
SPL. This change initializes the eMMC as BOOT_DEVICE_MMC1 (index=0).
Signed-off-by: Claudius Heine <ch@denx.de>
The board_boot_modes contained the wrong values for the emmc entry.
The eMMC here is connected over a 8-bit bus.
This change allows to use the 'bmode emmc' command to boot from emmc.
Signed-off-by: Claudius Heine <ch@denx.de>
The expire_now function was previously setting the watchdog timeout to
minimum and waiting for the watchdog to expire. However, this watchdog
also has bits to trigger immediate reset. Use those instead, like the
Linux imx2_wdt driver does.
Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
The Linux imx2_wdt driver uses a fsl,ext-reset-output boolean in the
device tree to specify whether the board design should use the external
reset instead of the internal reset. Use this boolean to determine which
mode to use rather than using external reset unconditionally.
For the legacy non-DM mode, the external reset is always used in order
to maintain the previous behavior.
Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Add u-boot,dm-pre-reloc properties for uart pinmux configuration
nodes, which enables UART as early as possible (before relocation).
Without this we miss almost the half of output (U-boot version,
CPU defails, Reset cause, DRAM details etc.).
Fixes: cd69e8ef9b ("colibri-imx6ull: migrate pinctrl and regulators to dtb/dm")
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Introduce imx6ull-colibri-u-boot.dtsi for u-boot specific properties to
keep original imx6ull-colibri.dts in sync with Linux.
Move all contents of imx6ull-colibri.dts to imx6ull-colibri.dtsi +
additionally fix checkpatch warnings.
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
According to IMX28CEC rev. 4, 10/2018, Table 15. Recommended Operating
Conditions, page 16, the VDDD should be set to 1.55V when the CPU is
operating at 454MHz. This is the case in U-Boot, hence increase the
VDDD voltage. This fixes instability when performing TFTP transfers.
Increase the brownout threshold to 1.4V. The documentation recommends
1.45V setting for the brownout, however, this triggers failure during
power block init, so keep the brownout slightly lower.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
imx6_is_bmode_from_gpr9 always returns false, because
IMX6_SRC_GPR10_BMODE is 1<<28 and gets casted to u8 on return.
This moves the function body into imx6_src_get_boot_mode, since that is the
only one using it and it is on the same abstraction level (accessing
registers directly).
Signed-off-by: Claudius Heine <ch@denx.de>
After the following commit:
commit 772b55723b ("imx: Introduce CONFIG_SPL_FORCE_MMC_BOOT to force MMC
boot on falcon mode")
it is possible to set the CONFIG_SPL_FORCE_MMC_BOOT flag, which allows
using MMC device as boot device regardless of the device used by Boot ROM
(FBL) as the first boot medium.
Display5 board needs this flag set to allow falcon boot from eMMC device.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Now AM65x CPSW2G driver will disable MAC TX internal delay for PHY
interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping
default value (enabled) for MAC TX internal delay when "rgmii-rxid"
interface mode is selected.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Now TI CPSW driver will disable MAC TX internal delay for PHY interface
mode "rgmii-rxid" which is incorrect.
Hence, fix it by keeping default value (enabled) for MAC TX internal delay
when "rgmii-rxid" interface mode is selected.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
This patch adds support for standard Ethernet "max-speed" DT property to
allow PHY link speed limitation.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
According to TRMs the 10Mbps link speed is supported in RGMII only when
CPSW2G MAC SL is configured for External Control ("in band") mode
CPSW_SL_MACCTRL.EXT_EN(18) = 1.
Hence update cpsw_slave_update_link() to follow documentation.
[1] https://patchwork.kernel.org/patch/10285239/
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Introduce disable_ipu_clock(). This is done in preparation for
configuring the NoC registers on i.MX6QP in SPL.
Afer the NoC registers are set the IPU clocks can be disabled.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The code can be made simpler by using setbits_le32(), so switch
to it.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
We already a message indicating that U-Boot is about to jump to SPL, so
make this one a debug() to reduce code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need to do this and it is done (in more detail) in U-Boot proper.
Drop this to save code space.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we call spl_init() before identifying the CPU. This is not a
good idea - e.g. if bootstage is enabled then it will try to set up the
timer which works better if the CPU is identified.
Put explicit code at each entry pointer to identify the CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For TPL we only need to set up the features and identify the CPU to a
basic level. Add a function to handle that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In TPL we try to minimise code size so do not include the PCI subsystem.
We can use fixed BARs and drivers can directly program the devices that
they need.
However we do need to bind the devices on the PCI bus and without PCI this
does not ordinarily happen. As a work-around, define a fake PCI bus which
does this binding, but no other PCI operations. This is a convenient way
to ensure that we can use the same device tree for TPL, SPL and U-Boot
proper:
TPL - CONFIG_TPL_PCI is not set (no auto-config, fake PCI bus)
SPL - CONFIG_SPL_PCI is set (no auto-config but with real PCI bus)
U-Boot - CONFIG_PCI is set (full auto-config after relocation)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The x86 power unit handles power management. Support initing this device
which is modelled as a new type of system controller since there are no
operations needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.
Update the code to use a separate flag instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function can be called before the timer is set up. Make sure that the
init function is called so that it works correctly.
This is needed so that bootstage can work correctly in TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We have the ability to enforce a maximum size for SPL but not yet for TPL.
Add a new option for this.
Document the size check macro while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a note about the driver name in the of-platdata documentation since
the naming must follow the compatible string.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On x86 platforms the SPI flash can be mapped into memory so that the
contents can be read with normal memory accesses.
Add a new SPI method to find the location of the SPI flash in memory. This
differs from the existing device-tree "memory-map" mechanism in that the
location can be discovered at run-time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the name of the image comes first in the linker-list symbol
used. This means that the name of the function sets the sort order, which
is not the intention.
Update it to put the boot-device type first, then the priority. This
produces the expected behaviour.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This entry is used to hold an Intel FSP-T (Firmware Support Package
Temp-RAM init) binary. Add support for this in binman.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This entry is used to hold an Intel FSP-S (Firmware Support Package
Silicon init) binary. Add support for this in binman.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present binman adds the image base address to the symbol value before
it writes it to the binary. This is not correct since the symbol value
itself (e.g. image position) has no relationship to the image base.
Fix this and update the tests to cover this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With the __packed attribute sandbox_defconfig cannot be compiled with GCC
9.2.1:
fs/cbfs/cbfs.c: In function ‘file_cbfs_fill_cache’:
fs/cbfs/cbfs.c:164:16: error: taking address of packed member of
‘struct cbfs_cachenode’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
164 | cache_tail = &new_node->next;
| ^~~~~~~~~~~~~~~
struct cbfs_cachenode is only an internal structure. So let's rearrange the
fields such that the structure is naturally packed and remove the __packed
attribute.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ARC fixes for v2020.01-rc2
The main change is move to DM_MMC of yet 2 another ARC boards:
AXS101 & IoTDK.
Among that we improve handling of stock-formatted SD-cards of high volume
on EM SDP as well as introduction of reset driver for HSDK which is required
for prepser reinitialization of some peripherals like USB etc.
Similar to 90d3d78a1c ("gitlab-ci: Prepend to PATH rather than replace
it") we need to prepend the PATH with our additional binaries and not
replace the value fully as doing so breaks virtualenv.
Signed-off-by: Tom Rini <trini@konsulko.com>
Back in the day on early board samples built-in Digilent JTAG probe
was not functional so we used externally attached Ashling Opella-XD
probe. But now with production units everything works as expected and
so we anybody may enjoy readily avaialble built-in JTAG probe so
we specify Digilent oprion on MDB's command line example.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Some especially large SD-cards come from stock formatted with
larger FAT cluster size so to accommodate those we just increase
what we expect to have here in U-Boot given we have a plenty of
space on EM SDP (16 MiB).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Pull request for UEFI sub-system for efi-2020-01-rc2
Provide a better user interface for setting UEFI variables.
Bug fixes:
- ext4 file system not discovered on UEFI block device
- 'make tests' build error on 32bit systems
Similar to the rework for GitLab-CI and Travis-CI, rework the Azure
Pipeline to use python3 and requirements.txt to install the necessary
modules.
Signed-off-by: Tom Rini <trini@konsulko.com>
Add optional parameter to 'avb verify' sub-command, so that user is able
to specify which slot to use, in case when user's partitions are
slotted. If that parameter is omitted, the behavior of 'avb verify' will
be the same as before, so user API is content.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Acked-by: Igor Opaniuk <igor.opaniuk@gmail.com>
After updating libavb to most recent version from AOSP/master, two new
warnings appear:
Warning #1:
lib/libavb/avb_cmdline.c: In function 'avb_append_options':
lib/libavb/avb_cmdline.c:365:15: warning: 'dm_verity_mode' may be
used uninitialized in this function
[-Wmaybe-uninitialized]
new_ret = avb_replace(
^~~~~~~~~~~~
slot_data->cmdline, "$(ANDROID_VERITY_MODE)", dm_verity_mode);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
lib/libavb/avb_cmdline.c:374:8: warning: 'verity_mode' may be used
uninitialized in this function
[-Wmaybe-uninitialized]
if (!cmdline_append_option(
^~~~~~~~~~~~~~~~~~~~~~
slot_data, "androidboot.veritymode", verity_mode)) {
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Warning #2:
lib/libavb/avb_slot_verify.c: In function 'avb_slot_verify':
lib/libavb/avb_slot_verify.c:1349:23: warning: 'ret' may be used
uninitialized in this function
[-Wmaybe-uninitialized]
AvbSlotVerifyResult ret;
^~~
Fix those by providing default return values to affected functions.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Update libavb to commit 5fbb42a189aa in AOSP/master, because new version
has support for super partition [1], which we need for implementing
Android dynamic partitions. All changes from previous patches for libavb
in U-Boot are accounted for in this commit:
- commit ecc6f6bea6 ("libavb: Handle wrong hashtree_error_mode in
avb_append_options()")
- commit 897a1d947e ("libavb: Update SPDX tag style")
- commit d8f9d2af96 ("avb2.0: add Android Verified Boot 2.0 library")
Tested on X15:
## Android Verified Boot 2.0 version 1.1.0
read_is_device_unlocked not supported yet
read_rollback_index not supported yet
read_is_device_unlocked not supported yet
Verification passed successfully
AVB verification OK.
Unit test passes:
$ ./test/py/test.py --bd sandbox --build -k test_avb
test/py/tests/test_android/test_avb.py ss..s.
[1] 49936b4c01
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Acked-by: Igor Opaniuk <igor.opaniuk@gmail.com>
When running the following command
mkimage -f auto -A arm -O linux -T kernel -C none -a 0x8000 -e 0x8000 \
-d zImage -b zynq-microzed.dtb -i initramfs.cpio image.ub
the type of fdt subimage is the same as of the main kernel image and
the architecture of the initramfs image is not set. Such an image is
refused by U-Boot when booting. This commits sets the mentioned
attributes, allowing to use the "-f auto" mode in this case instead of
writing full .its file.
Following is the diff of mkimage output without and with this commit:
FIT description: Kernel Image image with one or more FDT blobs
Created: Thu Sep 12 23:23:16 2019
Image 0 (kernel-1)
Description:
Created: Thu Sep 12 23:23:16 2019
Type: Kernel Image
Compression: uncompressed
Data Size: 4192744 Bytes = 4094.48 KiB = 4.00 MiB
Architecture: ARM
OS: Linux
Load Address: 0x00008000
Entry Point: 0x00008000
Image 1 (fdt-1)
Description: zynq-microzed
Created: Thu Sep 12 23:23:16 2019
- Type: Kernel Image
+ Type: Flat Device Tree
Compression: uncompressed
Data Size: 9398 Bytes = 9.18 KiB = 0.01 MiB
Architecture: ARM
- OS: Unknown OS
- Load Address: unavailable
- Entry Point: unavailable
Image 2 (ramdisk-1)
Description: unavailable
Created: Thu Sep 12 23:23:16 2019
Type: RAMDisk Image
Compression: Unknown Compression
Data Size: 760672 Bytes = 742.84 KiB = 0.73 MiB
- Architecture: Unknown Architecture
+ Architecture: ARM
OS: Linux
Load Address: unavailable
Entry Point: unavailable
Default Configuration: 'conf-1'
Configuration 0 (conf-1)
Description: zynq-microzed
Kernel: kernel-1
Init Ramdisk: ramdisk-1
FDT: fdt-1
Loadables: kernel-1
Signed-off-by: Michal Sojka <michal.sojka@cvut.cz>
For some controllers PHYs can be optional. Handling NULL pointers without
crashing nor failing, makes it easy to handle optional PHYs.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
malloc_cache_aligned() might return zero, so fix potential NULL pointer
access if __GFP_ZERO flag is set.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Add a simple implementation of this function, to allow logging to be
enabled in the SPL or TPL for systems that rely on the tiny printf()
implementation.
To keep the code size small,
- The function is built only when logging is enabled, as it
(currently) is not needed otherwise; and
- Like the existing implementation of snprintf(), its buffer-size
parameter is ignored.
Signed-off-by: Simon South <simon@simonsouth.net>
In cmd/regulator.c an error occurs with GCC 9.2.1 if CONFIG_ERRNO_STR is
not defined:
cmd/regulator.c: In function ‘failure’:
cmd/regulator.c:20:2: error: ‘%s’ directive argument is null
[-Werror=format-overflow=]
20 | printf("Error: %d (%s)\n", ret, errno_str(ret));
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In function ‘constraint’,
inlined from ‘constraint’ at cmd/regulator.c:111:12:
cmd/regulator.c:115:3: error: ‘%s’ directive argument is null
[-Werror=format-overflow=]
115 | printf(" %s (err: %d)\n", errno_str(val), val);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
errno_str() should return a valid string instead of NULL if
CONFIG_ERRNO_STR is not defined.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Macro ERRNO_MSG() ignores the error number but we should still use the same
constants as in include/linux/errno.h.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This choice is not about SPL for which we have a separate choice.
Fixes: 95f4bbd581 ("lib: fdt: Allow LZO and GZIP DT compression in U-Boot")
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
The signature 0x55 0xAA in bytes 510 and 511 of the first sector can either
indicate a DOS partition table of the first sector of a FAT file system.
The current code tries to check if the partition table is valid by looking
at the boot indicator of the partition entries. But first of all it does
not count from 0 to 3 but only from 0 to 2. And second it misses to
increment the pointer for the partition entry.
If it is a FAT file system can be discovered by looking for the text 'FAT'
at offset 0x36 or 'FAT32' at offset 0x52. In a DOS PBR there are no
partition entries, so those bytes are undefined. Don't require the byte at
offset 0x1BE to differ from 0x00 and 0x80.
With the patch the logic is changed as follows:
If the partition table has either an invalid boot flag for any partition or
has no partition at all, check if the first sector is a DOS PBR by looking
at the FAT* signature.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Provide a unit test for errno_str(). Test that known and unknown error
numbers are handled correctly.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
If errno_str() is called with an unsupported error number, do not return a
random pointer but a reasonable text.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make sure that the PCI busses are enumerated before trying to
find a NVMe device.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Change the stack-allocated buffer for the identification command
to explicitly allocate page-aligned buffers. Even though the spec
seems to allow having admin queue commands on non page-aligned
buffers, it seems to not be possible on my i.MX8MQ board with a
a Silicon Power P34A80. Since all of the NVMe drivers I have seen
always do admin commands on a page-aligned buffer, which does work
on my system, it makes sense for us to do that as well.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It's possible that the data cache for the buffer still holds data
to be flushed to memory, since the buffer was probably used as stack
before. Thus we need to make sure to flush it also on reads, since
it's possible that the cache is automatically flused to memory after
the NVMe DMA transfer happened, thus overwriting the NVMe transfer's
data. Also add a missing dcache flush for the prp list.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update from upstream.
Just minor changes like checking that the author has also done a sign-off.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Profiling the EHCI driver shows a significant performance problem in
ehci_submit_async(). Specifically, this function keeps enabling and
disabling async schedule back and forth for every single transaction.
However, enabling/disabling the async schedule does not take effect
immediatelly, but instead may take up to 1 mS (8 uFrames) to complete.
This impacts USB storage significantly, esp. since the recent reduction
of maximum transfer size to support more USB storage devices. This in
turn results in sharp increase in the number of ehci_submit_async()
calls. Since one USB storage BBB transfer does three such calls and
the maximum transfer size is 120 kiB, the overhead is 6 mS per 120 kiB,
which is unacceptable.
However, this overhead can be removed simply by keeping the async
schedule running. Specifically, the first transfer starts the async
schedule and then each and every subsequent transfer only adds a new
QH into that schedule, waits until the QH is completed and does NOT
disable the async schedule. The async schedule is stopped only by
shutting down the controller, which must happen before moving out
of U-Boot, otherwise the controller will corrupt memory.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Clear the USB_READY flag in the storage driver only in case there
is an error, otherwise usb_stor_BBB_transport() waits 5 mS before
doing anything every single time.
This is because the USB_READY flag is only ever set in
usb_test_unit_ready(), which is called only upon storage device
probe, not between each and every request. However, the device
cannot move out of USB_READY state once it was initialized.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Due to constant influx of more and more weird and broken USB sticks,
do as Linux does in commit 779b457f66e10de3471479373463b27fd308dc85
usb: storage: scsiglue: further describe our 240 sector limit
Just so we have some sort of documentation as to why
we limit our Mass Storage transfers to 240 sectors,
let's update the comment to make clearer that
devices were found that would choke with larger
transfers.
While at that, also make sure to clarify that other
operating systems have similar, albeit different,
limits on mass storage transfers.
And reduce the maximum transfer length of USB storage to 120 kiB.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Add weak callback to allow board specific behavior
- flush
- initiated
This patch prepare usage of DFU back end for communication with
STM32CubeProgrammer on stm32mp1 platform with stm32prog command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add a virtual DFU backend to allow board specific read and write
(for OTP update for example).
Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add the support of MTD partition for the MTD backend.
The expected dfu_alt_info for one alternate on the mtd device :
<name> part <part_id>
<name> partubi <part_id>
"partubi" also erase up to the end of the partition after write operation.
For example: dfu_alt_info = "spl part 1;u-boot part 2; UBI partubi 3"
U-Boot> dfu 0 mtd nand0
Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add DFU backend for MTD device: allow to read
and write on all MTD device (NAND, SPI-NOR,
SPI-NAND,...)
For example :
> set dfu_alt_info "nand_raw raw 0x0 0x100000"
> dfu 0 mtd nand0
This MTD backend provides the same level than dfu nand
backend for NAND and dfu sf backend for SPI-NOR;
So it can replace booth of them but it also
add support of spi-nand.
> set dfu_alt_info "nand_raw raw 0x0 0x100000"
> dfu 0 mtd spi-nand0
The backend code is based on the "mtd" command
introduced by commit 5db66b3aee ("cmd: mtd:
add 'mtd' command")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch allows the DFU backend to indicate that that it can't
provide no more data to fill the DFU buffer, by setting b_left =0
without error, even if the size of received data is lower of the
expected total size indicated by get_medium_size.
For USB DFU stack point of view, it is acceptable:
the read length < requested size in DFU_UPLOAD and the
transaction is stopped.
That avoid infinite loop issue in dfu_read_buffer_fill because the
size for the DFU read is limited by get_medium_size = r_left
and the DFU stack expects that read is allowed up to this size.
This issue never occurs for current flash device (where chunk are
always completely read, and b_left will be never 0) but it is useful for
virtual partition when the backend only know the max size of this
alternate, the real size of the data are only known in the read
treatment.
PS: for file access on mmc, EOF is never reached as
dfu_get_medium_size_mmc returns the exact size of the file.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add support of DFU for several interface/device
with one command.
The format for "dfu_alt_info" in this case is :
- <interface> <dev>'='alternate list (';' separated)
- each interface is separated by '&'
The previous behavior is always supported.
One example for NOR (bootloaders) + NAND (rootfs in UBI):
U-Boot> env set dfu_alt_info \
"sf 0:0:10000000:0=spl part 0 1;u-boot part 0 2; \
u-boot-env part 0 3&nand 0=UBI partubi 0,3"
U-Boot> dfu 0 list
DFU alt settings list:
dev: SF alt: 0 name: spl layout: RAW_ADDR
dev: SF alt: 1 name: ssbl layout: RAW_ADDR
dev: SF alt: 2 name: u-boot-env layout: RAW_ADDR
dev: NAND alt: 3 name: UBI layout: RAW_ADDR
U-Boot> dfu 0
$> dfu-util -l
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
intf=0, alt=3, name="UBI", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
intf=0, alt=2, name="u-boot-env", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
intf=0, alt=1, name="u-boot", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
intf=0, alt=0, name="spl", serial="002700333338511934383330"
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Copy the partition support from NAND backend to SF,
support part and partubi option.
In case of ubi partition, erase the rest of the
partition as it is mandatory for UBI.
The added code is under compilation flag CONFIG_DFU_SF_PART
activated by default.
for example:
U-Boot> env set dfu_alt_info "spl part 0 1;\
u-boot part 0 2;u-boot-env part 0 3;UBI partubi 0 4"
U-Boot> dfu 0 sf 0:0:10000000:0
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Calling cache flush on invalid buffer, even with zero length might cause
an exception on certain platforms.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Add possibility to define a part of partition as a separate DFU entity.
This allows to have more than one items on the given partition.
The real use case for this option is TM2 board. It can use u-boot stored
as Linux kernel on the defined partition (as RAW data) and load the real
kernel from the same partition, but stored under the certain offset.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
'THOR' download command requires DFU infrastructure to properly flash
board images. It can be used without enabling DFU command, so add such
dependency to Kconfig.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
This is needed to make Windows THOR flash tool happy, because it
starts sending data only when interrupt packet is received on the 3rd
endpoint.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
In combination with multiple partitions in NAND, this printf() ends up
being more noise than helpful. Change it to debug() instead.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Acked-by: Lukasz Majewski <lukma@denx.de>
Some boards don't populate clk/reset entries as these are are optional
as per binding documentation. Therefore, don't fail driver probe if
clk/reset entries are absent in DT.
This fixes fastboot failures seen due to enabling of CONFIG_CLK on AM57xx
Fixes: e8e683d33b ("board: ti: am57xx-idk: Configure the CDCE913 clock synthesizer")
Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Some configurations (i.e. sandbox) result in unused
splash_display_banner() and we get build errors like:
common/splash.c:148:20: error: unused function 'splash_display_banner' [-Werror,-Wunused-function]
static inline void splash_display_banner(void) { }
Drop empty inline function and add guards around the call.
Fixes: d2a8271c88 ("splash: fix splash banner output")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
As initially this feature was implemented as a negative CONFIG and
later it was redesigned to be positive the help text should be
updated to reflect this change.
This commit updates the help text to match the current implementation.
Signed-off-by: Walter Lozano <wlozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When we have an excess size growth, fix the "limit" printf call to pass
in just the limit variable rather than the string bytes to the format
character.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
_gpio_direction_output function currently calls gpio_set_value
with the wrong gpio number. gpio_set_value in the uclass driver
expects a different gpio number and the _gpio_direction_output
is currently providing the number specific to the bank.
Hence fix it by calling the _gpio_set_value function instead.
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Fixes: 8e51c0f254 ("dm: gpio: Add DM compatibility to GPIO driver for Davinci")
Signed-off-by: Keerthy <j-keerthy@ti.com>
We have two further uses of raw string usage in the test/py codebase
that are used under CI. The first of which is under the bind test and
is a direct update. The second of which is to strip VT100 codes from
the match buffer. While switching this to a raw string is also a direct
update, the comment it notes that problems were encountered on Ubuntu
14.04 (and whatever Python 2 version that was) that required slight
tweaks to the regex. Replace that now that we're saying Python 3.5 is
the minimum.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
As things stand today, we have tools that CI requires where "python"
must be "python2". We need to use a virtualenv and pip in order to
ensure that our pytest tests can be run. Rework things slightly so
that:
- On Travis-CI, we install python-pyelftools for the platforms that
require pyelftools to be installed.
- On GitLab-CI, we move to a newer base image that includes python3-pip
and continue to use a virtualenv per job that needs it, for the
correct set of packages.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
To be more closely aligned with Python community best practices, we need
to better document our usage of pip and make use of a requirements.txt
file that shows the versions of the tools that we are using. This will
aide in ensuring reproducibility of our tests as well.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that we have moved to being based on pytest for python3 we need to
make our test.py wrapper more robust in terms of only calling python3
rather than possibly finding and using python2. To do this, change from
execvp()'ing pytest to invoking the package itself via python. In the
event that pytest is unavailable we still get a user-friendly error:
pkg_resources.DistributionNotFound: The 'pytest' distribution was not found and is required by the application
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
The check_output function from the subprocess Python module by default
returns data as encoded bytes and leaves decoding to the application.
Given our uses of the call, it makes the most sense to immediately
decode the results.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
- In python 3 you must use raw strings for regex as other forms are
deprecated and would require further changes to the pattern here.
In one case this lets us have a simpler match pattern.
- As strings are now Unicode our complex tests (Euro symbol,
SHIFT+ALT+FN 5) we need to declare that as a bytes string and then
decode it for use.
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
In the case of some unit tests we are working with providing a fake
flash device that we have written some text strings in to. In this case
we want to tell Python to encode things to bytes for us.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
- Modern pytest is more visible in telling us about parameters that we
had not described, so describe a few more.
- ConfigParser.readfp(...) is now configparser.read_file(...)
- As part of the "strings vs bytes" conversions in Python 3, we use the
default encoding/decoding of utf-8 but in some places tell Python to
replace problematic conversions rather than throw a fatal error.
- Fix a typo noticed while doing the above ("tot he" -> "to the").
- As suggested by Stephen, re-alphabetize the import list
- Per Heinrich, replace how we write contents in test_fit.py
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
Use the 2to3 tool to perform numerous automatic conversions from Python
2 syntax to Python 3. Also fix whitespace problems that Python 3
catches that Python 2 did not.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
Fix the following spit from pytest:
u-boot/test/py/conftest.py:438: RemovedInPytest4Warning: MarkInfo objects are deprecated as they contain merged marks which are hard to deal with correctly.
Please use node.get_closest_marker(name) or node.iter_markers(name).
Docs: https://docs.pytest.org/en/latest/mark.html#updating-code
for board in mark.args:
In both cases, the later suggestion is applicable.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Igor Opaniuk <igor.opaniuk@gmail.com>
[trini: Update for current file with a few more cases, un-pin pytest in CI]
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
We inconsistently note multiple dependencies today in our tests,
sometimes with a single line that declares multiple and sometimes
multiple single lines. Current pytest seems to fail on the single line
format so change to multiple declarations.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org> [on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
Currently we set the entire PATH rather than prepend the new paths that
we need to have searched. This however breaks parts of the "virtualenv"
that was have set up and need to use as that also will be modifying
PATH. To fix this, prepend our new locations instead.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
In a number of our stanzas we had multi-line commands that were one
space short of alignment, correct this.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
- Add I2C clocks for i.MX6Q CCF driver
- Fix check in clk_set_default_parents()
- Managed API to get clock from device tree
- Fixes for core clock code (including sandbox regression tests)
'make tests' on an 32bit ARM system leads to
In file included from ../lib/efi_loader/efi_variable.c:9:
../include/malloc.h:364:7: error: conflicting types for ‘memset’
void* memset(void*, int, size_t);
^~~~~~
In file included from ../include/compiler.h:126,
from ../include/env.h:12,
from ../lib/efi_loader/efi_variable.c:8:
../include/linux/string.h:103:15:
note: previous declaration of ‘memset’ was here
extern void * memset(void *,int,__kernel_size_t);
^~~~~~
In file included from ../lib/efi_loader/efi_variable.c:9:
../include/malloc.h:365:7: error: conflicting types for ‘memcpy’
void* memcpy(void*, const void*, size_t);
^~~~~~
In file included from ../include/compiler.h:126,
from ../include/env.h:12,
from ../lib/efi_loader/efi_variable.c:8:
../include/linux/string.h:106:15:
note: previous declaration of ‘memcpy’ was here
extern void * memcpy(void *,const void *,__kernel_size_t);
^~~~~~
Use common.h as first include as recommended by the U-Boot coding style
guide.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
With this patch, when setting UEFI variable with "env set -e" command,
we will be able to
- specify vendor guid with "-guid guid",
- specify variable attributes, BOOTSERVICE_ACCESS, RUNTIME_ACCESS,
respectively with "-bs" and "-rt",
- append a value instead of overwriting with "-a",
- use memory as variable's value instead of explicit values given
at the command line with "-i address,size"
If guid is not explicitly given, default value will be used.
Meanwhile, "env print -e," will be modified so that it will NOT dump
a variable's value if '-n' is specified.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This expands current Azure Pipelines Windows host tools build
testing to cover all the CI testing in gitlab and travis CI.
Note for some unknown reason, the 'container' cannot be used for
any jobs that have buildman, for buildman does not exit properly
and hangs the job forever. As a workaround, we manually call
docker to run the image to perform the CI tasks.
A complete run on Azure Pipelines takes about 2 hours and 10
minutes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present some boards generate kwbimage.cfg in the source tree
during the build. This breaks buildman testing on some systems
where the source tree is read-only. Update makefile rules to
generate it in the build tree instead.
Note some other boards have the kwbimage.cfg file written in
advance, hence we need check if the file exists in the build
tree first, otherwise we fall back to one in the source tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the 'Make' function, the codes tries to create a directory
if current stage is 'build'. But the directory isn't used at
all anywhere.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
buildman always generates boards.cfg in the U-Boot source tree.
When '-o' is given, we should generate boards.cfg to the given
output directory.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On i.MX8, when booting from eMMC boot partition, the whole flash.bin
is stored in boot partition, however SPL switches to user partition
during the init of mmc driver:
spl_mmc_load() -> mmc_init()
Then it tries to load the container image in
spl_mmc_get_uboot_raw_sector(), but here it reads the data from user
partition and the header is not recognized as a valid header.
So we move spl_mmc_get_uboot_raw_sector after eMMC partition switch
to address this issue.
Anyway put spl_mmc_get_uboot_raw_sector before eMMC partition switch
is not correct, so let's move it after eMMC partition switch.
Reported-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
A previous patch below adding DDR mode support was actually for i.MX
platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC,
it uses different process for DDR mode, and hasn't been supported.
Let's drop DDR support code for i.MX in fsl_esdhc driver.
0e1bf61 mmc: fsl_esdhc: Add support for DDR mode
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
support it, so let's force to use it.
- Drop non-BLK support for DM_MMC introduced by below patch.
66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
- Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC).
- Use DM_MMC instead of BLK for conditional compile.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
When building U-Boot host tools for Windows from Microsoft Azure
Pipelines, the following errors were seen:
HOSTCC tools/mkenvimage.o
In file included from tools/mkenvimage.c:25:
./tools/version.h:1:1: error: expected identifier or ‘(’ before ‘.’ token
1 | ../include/version.h
| ^
tools/mkenvimage.c: In function ‘main’:
tools/mkenvimage.c:117:4: warning: implicit declaration of function ‘usage’ [-Wimplicit-function-declaration]
117 | usage(prg);
| ^~~~~
tools/mkenvimage.c:120:35: error: ‘PLAIN_VERSION’ undeclared (first use in this function)
120 | printf("%s version %s\n", prg, PLAIN_VERSION);
| ^~~~~~~~~~~~~
tools/mkenvimage.c:120:35: note: each undeclared identifier is reported only once for each function it appears in
make[2]: *** [scripts/Makefile.host:114: tools/mkenvimage.o] Error 1
It turns out tools/version.h is a symbolic link and with Windows
default settings it is unsupported hence the actual content of
tools/version.h is not what file include/version.h has, but the
the linked file path, which breaks the build.
To fix this, remove the symbolic links for tools/version.h. Instead
we perform a copy from include/version.h during the build.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When building U-Boot host tools for Windows from Microsoft Azure
Pipelines, we see tons of weird warnings and errors emitted from
every Kconfig files:
Kconfig:6:warning: ignoring unsupported character ''
Kconfig:6:warning: ignoring unsupported character ''
Kconfig:8:warning: ignoring unsupported character ''
Kconfig:9:warning: ignoring unsupported character ''
Kconfig:10:warning: ignoring unsupported character ''
Kconfig:10:warning: ignoring unsupported character ''
Kconfig:13:warning: ignoring unsupported character ''
arch/Kconfig:1:warning: ignoring unsupported character ''
arch/Kconfig:2:warning: ignoring unsupported character ''
arch/Kconfig:2:warning: ignoring unsupported character ''
arch/Kconfig:4:warning: ignoring unsupported character ''
...
After several rounds of experiments, it turns out this is caused
by line endings. Historically, Linux and macOS used linefeed (LF)
characters while Windows used a carriage return plus a linefeed
(CRLF). When Azure Pipelines checks out the U-Boot repo, Git tries
to compensate for the difference by automatically making lines end
in CRLF in the working directory on Windows, which confuses the
Kconfig file parsing logic.
Fortunately Git provides a way for repos to tell Git not to do such
automatical line endings conversion via .gitattributes file below:
* text eol=lf
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This adds a reST document for how to build U-Boot host tools,
including information for both Linux and Windows.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
'struct ustat' uses linux-specific typedefs to declare its memebers:
__kernel_daddr_t and __kernel_ino_t. It is currently not used by any
U-Boot codes, but when we build U-Boot tools for other platform like
Windows, this becomes a problem.
Let's surround it with __linux__.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
__swab32() is a Linux specific macro defined in linux/swab.h. Let's
use the compiler equivalent builtin function __builtin_bswap32() for
better portability.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
__leXX has Linux kernel specific __attribute__((bitwise)) which is
not portable. Use corresponding uintXX_t instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Use log() insted of debug() for uclass_find_device_by_seq function,
since this print is very much and we can filter it out with log()
interface.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move #define to top of file as per docs:
Signed-off-by: Simon Glass <sjg@chromium.org>
There is a contributor in Linux kernel with a comma in their name, which
confuses patman and results in invalid to- or cc- addresses on some
patches. To avoid this, let's use \0 as a separator when generating cc
file.
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is possible to enable bootstage in TPL. TPL can stash the info for SPL.
But at present this information is then lost because SPL does not read
from the stash.
Add support for SPL not being the first phase to enable bootstage.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present bootstage in TPL and SPL use the same ID so it is not possible
to see the timing of each. Separate out the IDs and use the correct one
depending on which phase we are at.
Example output:
Timer summary in microseconds (14 records):
Mark Elapsed Stage
0 0 reset
224,787 224,787 TPL
282,248 57,461 end TPL
341,067 58,819 SPL
925,436 584,369 end SPL
931,710 6,274 board_init_f
1,035,482 103,772 board_init_r
1,387,852 352,370 main_loop
1,387,911 59 id=175
Accumulated time:
196 dm_r
8,300 dm_spl
14,139 dm_f
229,121 fsp-m
262,992 fsp-s
Signed-off-by: Simon Glass <sjg@chromium.org>
At present bootstage relocation assumes that it is possible to point back
to memory available before relocation, so it does not relocate the
strings. However this is not the case on some platforms, such as x86 which
uses the cache as RAM and loses access to this when the cache is enabled.
Move the relocation step to before U-Boot relocates, expand the allocated
region to include space for the strings and relocate the strings at the
same time as the bootstage records.
This ensures that bootstage data can remain accessible from TPL through
SPL to U-Boot before/after relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present there is a single shared address for bootstage data in both
TPL and SPL. If SPL unstashs TPL bootstage info and then stashes it again
to pass it to U-Boot, the new stash overwrites the strings of the old
stash.
Fix this by duplicating the strings into the malloc() region. This should
be a small code. Fix the header-file order at the same time.
This problem doesn't happen at the next stage (SPL->U-Boot) since U-Boot
relocates the boostage data.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current code searches for empty records but these not existing with
bootstage now. This used to be needed when bootstage records were stored
in a spare array.
Drop the unnecessary code and fix a code-style nit at the same time.
Signed-off-by: Simon Glass <sjg@chromium.org>
When stashing bootstage info, store the next ID so that it can be used
when the stash is restored. This avoids the ID starting at zero and
potentially overwriting existing entries.
Signed-off-by: Simon Glass <sjg@chromium.org>
Make sure that the bloblist starts on an aligned boundary. This protects
against one of the early allocating causing the alignment to be lost.
Signed-off-by: Simon Glass <sjg@chromium.org>
With a bit of code reordering we can support %p using the existing code
for ulong.
Move the %p code up and adjust the logic accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is used in the bootstage report which may be trigged in TPL
or TPL. Add a very basic implication of this function so that it builds.
There is no attempt to get the formatting right, since this would add too
much code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
The ctype array is brought into the image, adding 256 bytes, when it is
unlikely to be needed. The extra code for %p is only present when DEBUG
is defined, so let's drop ctype as well unless DEBUG is defined.
Signed-off-by: Simon Glass <sjg@chromium.org>
The test did reads after writes but didn't check the value.
It probably was because the sandbox didn't implement the writeX/readX
functions.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Updated to use sandbox_set_enable_memio():
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This function assumes that the 'val' parameter has no masked bits set.
This is not defined by the function prototype though. Fix the function to
mask the value and update the documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This function needs a prototype so that tests can use it. Add one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function writes to its address so the address should not be declared
as const. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Quite a few tests use addresses or hex values for comparisons. Add hex
output for test failures, e.g.:
0x55ca22fa == reg: Expected 0x55ca22fa (1439310586),
got 0x55ea22fb (1441407739)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
Add the address spaces for the R5F cores in MCU domain to the ranges
property of the cbass_mcu interconnect node so that the addresses
within the R5F nodes can be translated properly by the relevant OF
address API.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.
Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.
Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Added training support for LPDDR4 and DDR3L DDRs. Also added/changed
some register configuration to support all 3 DDR types
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The current configuration of DDR on AM654 base board is for 1600MTs but
the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi.
Since 1600MHz is misleading, rename it to
k3-am654-base-board-ddr4-1600MTs.dtsi
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
U-Boot cleans and invalidate L1 and L2 caches before jumping to Linux
by set/way in cleanup_before_linux(). Additionally there is a custom
hook provided to clean and invalidate L3 cache.
Unfortunately on K3 devices(having a coherent architecture), there is no
easy way to quickly clean all the cache lines for L3. The entire address
range needs to be cleaned and invalidated by Virtual Address. This can
be implemented using the L3 custom hook but it take lot of time to clean
the entire address range. In the interest of boot time this might not be
a viable solution.
The best hit is to make sure the loaded Linux image is flushed so that
the entire image is written to DDR from L3. When Linux starts running with
caches disabled the full image is available from DDR.
Reported-by: Andrew F. Davis <afd@ti.com>
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Once the arch specific boot_prepare_linux completes, boards wants to
have a custom preparation for linux. Add support for a custom
board_prep_linux.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Expand SPL_MULTI_DTB_FIT to accommodate usb peripheral nodes being
added to support SPL_DFU bootmode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add usb peripheral and usb phy nodes in spl to enable SPL_DFU bootmode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Second set of u-boot-atmel features and fixes for 2020.01 cycle
This feature set includes Eugen's work on a new tiny flexcom driver and
eeprom mac retrieval for the sam9x60-ek board.
Some configs are selected in Kconfig and is no longer needed in the
defconfig files. Some configs (power domain, ram) are never used.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the
system, they should be always selected.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds default eth pinctrl for all boards.
There are two pinctrl nodes used for two scenarios:
ephy_iot_mode - for IOT boards which have only one port (PHY0)
ephy_router_mode - For routers which have more than one ports
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds a dts property cd-active-high for builtin-cd mode to make
it configurable instead of using hardcoded active-low.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds default p0led status and phy0 link polling for all boards.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to
prevent LAN devices from getting IP address from WAN.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
When received a packet with an invalid length recorded in rx descriptor,
we should free this rx descriptor to allow us to continue to receive
following packets.
Without doing so, u-boot will stuck in a dead loop trying to process this
invalid rx descriptor.
This patch adds a call to mt7628_eth_free_pkt() after received an invalid
packet length.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port).
Although in IOT mode only port0 is usable, the phy0 is still connected
to the switch, not the ethernet gmac directly.
This patch rewrites it and makes it optional. It can be turned on by adding
mediatek,poll-link-phy = <?> explicitly into the eth node. By default the
driver is switch mode with all 5 phy ports working without link detection.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch removes hardcoded gpio settings as they have been replaced by
pinctrl in dts, and also replaces regmap-based phy reset with a more
generic reset controller.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds slew rate calibration for mt76x8-usb-phy, removes code
which belongs to mt7620, and gets rid of using syscon and regmap by using
clock driver and reset controller.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds pinctrl support for mt7628, with a file for common pinmux
functions and a file for mt7628 which has additional support for pinconf.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Currently this driver uses a different way to implement the spi xfer,
by modifying some fields of two registers, which is incompatible with the
MTK's original SDK linux driver. This will cause the flash data being
damaged by the SDK driver.
This patch lets the mt7621_spi_set_cs() restore the original register
fields after cs deactivated.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The mt7621 spi controller supports continuous generic half-duplex spi
transaction. There is no need to cache xfer data at all.
To achieve this goal, the OPADDR register must be used as the first data
to be sent. And follows the eight generic DIDO registers. But one thing
different between OPADDR and DIDO registers is OPADDR has a reversed byte
order.
With this patch, any amount of data can be read/written in a single xfer
function call.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch lets the spi driver to use clock provided by the clk driver
since the new clk-mt7628 driver provides accurate sys clock frequency.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which
support baudrate up to 921600.
The high-speed UART is compatible with ns16550 when baudrate <= 115200.
Add compatible string to dtsi file so u-boot can use it when serial_mtk
driver is built in.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The UART of MT7628 has fixed 40MHz input clock so there is no need to put
clock-frequency in every dts files. Just put it into the common dtsi file.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds non-DM version for mtk hsuart driver and makes it
compatible with ns16550a driver in configuration.
This is needed in SPL with CONFIG_SPL_DM disabled for reducing size.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The current brcmnand driver is based on 4.18 linux kernel which uses
mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from
old kernel which does not use this new API and expect nand_chip.ecc.layout
structure to be set. This cause nand_scan_tail function running into a bug
check if the device has a different oob size than the default ones.
This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7
that supports the ecc layout struture and replaces the mtd_set_ooblayout
method
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
This adds support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
If configuration is set to skip low level init, automatic
probe of L2 cache size is not performed and the size is set to 0.
Flushing or invalidating the L2 cache will fail in this case.
Add a static configuration (SYS_DCACHE_LINE_SIZE) with default set to 0.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
it mismatches the real voltage supplied to the VCC to the PIO supply,
the PIO will work improperly.
The PIO controller also has a register that contains the status of each
VCC rail of the PIO supplies, and it has the same definition with the
configuration register. so we can just copy the content of this register
to the configuration register at startup, to ensure the configuration is
correct at startup stage.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[jagan: s/__maybe__unused/__maybe_unused]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Sync Kernel DTS for Allwinner H6 boards.
Drop /omit-if-no-ref/ keyword as it's not supported by U-boot.
commit <d45331b00ddb> Linux 5.3-rc4
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families.
PLL1 clock sets the default system clock, defined as:
sun6i: 1008000000
sun8i: 1008000000
sun50i: 816000000
With the current calculation, m = 2 and k = 3. Solving for n,
this results 28. Solving back:
(24MHz * 28 * 3) / 2 = 1008MHz
However if the requested clock is 816, n is 22.66 rounded
to 22, which results:
(24MHz * 28 * 3) / 2 = 792MHz
Changing k to 4 satisfies both system clocks:
(24E6 * 21 * 4) / 2 = 1008MHz
(24E6 * 17 * 4) / 2 = 816MHz
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
A64 OLinuXino board from Olimex has three variants with onboard eMMC:
A64-OLinuXino-1Ge16GW, A64-OLinuXino-1Ge4GW and A64-OLinuXino-2Ge8G-IND. In
addition, there are two variants without eMMC. One without eMMC and one with SPI
flash. This suggests the need for separate device tree for the three eMMC
variants.
The Linux kernel upstream has chosen to create and use a separate device tree
for the eMMC variants instead of adding eMMC support existing device tree. These
changes to Linux kernel are queued for Linux 5.4.
commit <02bb66b347ff8115f53948f86b884e008ba385b9> ("arm64: dts:
allwinner: a64: Add A64 OlinuXino board (with eMMC)")
This patch has been tested on A64-OLinuXino-1Ge16GW and is based on Linux
device-tree and a64-olinuxino_defconfig.
Signed-off-by: Sunil Mohan Adapa <sunil@medhas.org>
[jagan: updated linux-next commit details]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Half DQ configuration seems to be very rare for H6 based boards/STBs,
but exists nevertheless. Currently the only known product which needs
this support is Tanix TX6 mini.
This commit adds support for half DQ configuration. Code was tested
for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix
TX6 4 GiB/DDR3) and none were found.
Thanks to Icenowy Zheng for help with this code.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: thomas graichen <thomas.graichen@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Add an entry for the Adesto AT25SL321 SPI NOR chip.
This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in
SPL. They often rely on hacks in the board header files to include
this option conditionally. To be able to fix this, we previously
introduced a separate option SPL_SPI_FLASH_MTD.
Therefore we can now adjust the Makefile and change the code in
sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD).
We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the
header files to the according defconfigs. The affected boards are
socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6
and da850evm.
We do this all in one patch to guarantee bisectibility.
This change was tested with buildman to make sure it does not
introduce any regressions by comparing the resulting binary sizes.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status
register that indicates various errors that may be encountered during
erase/write operations. Therefore add USE_FSR flag wherever missing.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries
for the same. These flashes have bit 6 set in 5th byte of READ ID
response when compared to n25q* variants.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector
support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS.
Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Use dev_err() when reporting reason for erase/write failures so that
users can be made aware of the reason for failure.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
To allow SPI_FLASH_MTD being enabled separately in SPL we add a new
option. The only user currently is the stm32mp15_basic board.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
SoPine has winbond SPI-FLASH, so enable the same in defconfig
and add aliases for spi0 in -u-boot.dtsi
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
SPI is available in Allwinner A64 SoC, so enable it
globally in Kconfig.
- CONFIG_SPI
- CONFIG_DM_SPI
- CONFIG_DM_SPI_FLASH
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
SPI_SUNXI driver is fully dm-aware and the Allwinner
architecture kconfig would have logic to enable the
DM_SPI. So, select default spi sunxi driver for
sunxi architecture.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
DM_SPI_FLASH should require spi flash interface code for dm
version, so imply SPI_FLASH core by default if any board
enabled DM_SPI_FLASH.
This overcome the explicit enablement of CONFIG_SPI_FLASH on
respective boards when DM_SPI_FLASH being used.
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
If DM_SPI_FLASH enabled that means it is using sf command
for flash interface to access.
SPI_FLASH can be used via sf command and board/driver
functions to call spi flash ops, so mark it default only
for DM_SPI_FLASH.
This would prevent explicit adding of CONFIG_CMD_SF when
DM_SPI_FLASH being enabled.
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
We need distinguish the following two situations in various SPI APIs:
- given chip select num is invalid
- given chip select num is valid, but no device is attached
Currently -ENODEV is returned for both cases.
For the first case, it's more reasonable to return -EINVAL instead of
-ENODEV for invalid chip select numbers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
If an SPI controller driver does not implement ops->cs_info, that
probably means any chip select number could be valid, hence let's
return 0 for spi_cs_info().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
1) CONFIG_SPI_FLASH is not just a legacy code, but it has common
core code which handle both dm and non-dm spi flash code. So
fix the info text to make it clear globally.
2) Since it's flash core it shouldn't depends on legacy SPI,
so remove the 'depends on SPI'
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.
This patch only supports OTG0 with UTMI PHY.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
This fixes the issues with calculation of controller indexes in
ehci_usb_bind() for iMX7, as USB controllers on iMX7 SoCs aren't
placed next to each other, and their addresses incremented by 0x10000.
Example of USB nodes for iMX7S/D:
usbotg1: usb@30b10000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b10000 0x200>;
^^^^^^^^^^
....
usbotg2: usb@30b20000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b20000 0x200>;
^^^^^^^^^^
....
usbh: usb@30b30000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b30000 0x200>;
^^^^^^^^^^
....
Which was leading to usb enumeration issues:
Colibri iMX7 # usb start
starting USB...
Bus usb@30b10000: USB EHCI 1.00
Bus usb@30b20000: probe failed, error -22
scanning bus usb@30b10000 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Fixes: 501547cec1("usb: ehci-mx6: Fix bus enumeration for DM case")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
All platforms which are using MANUAL_RELOC are jumping back to origin
location when repeatable command is called. The reason is that cmd_rep link
is not updated properly. Issue can be reproduced by rewriting origin
U-Boot location through (for example) file download by tftp command.
Fixes: 80a48dd47e ("common: command: Rework the 'cmd is repeatable' logic")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Record two bootstages and add "Starting kernel" message to have standard
handoff message between U-Boot and OS.
Also use debug() instead of #ifdef DEBUG to clean the code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no need to show FDT message in regular flow that's why switch it
to debug level.
Fixes: 0905046050 ("microblaze: Switch to generic bootm implementation")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for System Controller available on e-a2197-00 base board.
System is very similar to p-a2197-00 board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
board_early_init_f added by commit e6cc3b25d7
("arm: zynq: Wire watchdog internals") is no longer needed that's why
remove it also with Kconfig enabling.
Fixes: ccd063e981 ("watchdog: Move watchdog_dev to data section (BSS may not be cleared)")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch removes 4K sector size support for Zynq mini qspi configuration
in favour of fast erase speed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch removes 4K sector size support for ZynqMP mini qspi
configuration in favour of fast erase speed.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There are use cases where lpd watchdog can be configured for APU use. By
design this IP should be listed in zynqmp.dtsi to make sure that node is
properly enabled by DTG.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add dt clock header which can be included by dtses. And also use zynqmp-clk
compatible string.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch increases SYS_MALLOC_F_LEN as the versal clock
driver needs to be probed before relocation itself inorder
to get required clocks before relocation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds usb host and device mode support for Xilinx
Versal virtual platform. By default USB host functionality
is enabled. To use in usb device mode, set dr_mode property
in DT to peripheral.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable device tree overlay to build all dtbs for Versal with -@ flag to
enable applying overlays.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ina226 hwmon driver is deprecated and it is recommended to use new iio
based driver. The patch is enabling iio-hwmon driver to export
functionality from IIO to hwmon interface to be able to use lm-sensors
package.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Label property is adding capability to distiguish chips from each other
when iio framework is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ina226 hwmon driver is deprecated and it is recommended to use new iio
based driver. The patch is enabling iio-hwmon driver to export
functionality from IIO to hwmon interface to be able to use lm-sensors
package.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add gpio phy reset via I2C expander TCA6416 on board ZCU102.
A warning call trace is observer in probe when this reset is called
from context that can sleep. Keep this commented until that is
resolved in phylib.
Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The DP83867 strap control workaround is already present in Linux kernel
mainline binding. All these Xilinx boards require this quirk.
Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ina226 hwmon driver is deprecated and it is recommended to use new iio
based driver. The patch is enabling iio-hwmon driver to export
functionality from IIO to hwmon interface to be able to use lm-sensors
package.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Label property is adding capability to distiguish chips from each other
when iio framework is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ina226 hwmon driver is deprecated and it is recommended to use new iio
based driver. The patch is enabling iio-hwmon driver to export
functionality from IIO to hwmon interface to be able to use lm-sensors
package.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Label property is adding capability to distiguish chips from each other
when iio framework is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ina226 hwmon driver is deprecated and it is recommended to use new iio
based driver. The patch is enabling iio-hwmon driver to export
functionality from IIO to hwmon interface to be able to use lm-sensors
package.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Currently zcu102 Rev1.0 board includes RevA sdhci dt node which has
no-1-8-v property. Since Rev1.0 has level shifters delete this
property to enable support for 1.8v.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mainline has done this switch and there is no reason not to switch it too.
Mainline U-Boot patch which has done that switch:
"dts: switch spi-flash to jedec, spi-nor compatible"
(sha1: ffd4c7c2ec)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Label property is adding capability to distiguish chips from each other
when iio framework is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ina226 hwmon driver is deprecated and it is recommended to use new iio
based driver. The patch is enabling iio-hwmon driver to export
functionality from IIO to hwmon interface to be able to use lm-sensors
package.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added tps53679 compatible string to tps53681. They are both compatible to
each other and tps53679 has Linux driver already.
Signed-off-by: Nishant Mittal <nishant.mittal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Label property is adding capability to distiguish chips from each other
when iio framework is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ina226 hwmon driver is deprecated and it is recommended to use new iio
based driver. The patch is enabling iio-hwmon driver to export
functionality from IIO to hwmon interface to be able to use lm-sensors
package.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ethernet phys based on devicetree specification should be using
ethernet-phy@ node name instead of pure phy@.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP based System controller is present on Versal boards. This patch is
aligning names with Versal to follow the spec.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DT binding was reviewed in Linux by commit b0b41af12a1b
("dt-bindings: memory: Add pl353 smc controller devicetree binding
information") that's why this fragment can be also added to U-Boot
repository.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The commit 4b0bcfa7c4 ("Kconfig: Migrate CONFIG_BOOTM_* options")
moved BOOTM_ options to Kconfig that's why align zynq defconfig with it.
Disabling NETBSD was done by commit d6f48ea5ce
("ARM: zynq: Do not enable NETBSD support by default").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable GPIO command for Xilinx Versal platform. Driver is updated that's
why it can be used directly. Driver is enabled by default through Kconfig.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fix error debug messages to be more accurate and aligned with debug message
style in the whole file.
And do not initialize ret variable because it is initialized later on and
it is just additional step.
Fixes: 1327d1678b ("firmware: zynqmp: Add zynqmp-power support")
Reported-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Remove macros which use PM_SIP_SVC offset and convert invoke_smc() to
xilinx_pm_request() which do calculation with PM_SIP_SVC already.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
versal_pm_request() and invoke_smc() are almost the same. Only one
difference is that versal_pm_request is adding PM_SIP_SVC offset to api_id.
The patch is moving platform implementation to firmware driver code for
synchronization.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
enable driver model for i2c, eeprom for mac retrieval from eeprom i2c memory,
and microchip_flexcom driver.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Those platform use the DWC2 controller for the gadget support and the
DWC3 for host-only operations.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
As the PHY driver now handles the transitions of USB power domain, we
must add this information in the node of each PHY.
Also, the phy are expected in the "phys" property, not "usb-phys".
Also add the aliases for the USB ports on boards with more than a single
port.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
KEYSTONE_USB_PHY is now required for proper USB operations.
XHCI_DWC3 can be disabled as the xhci-dwc3 is not used anymore
USB_DWC3_GADGET can also be removed, it is now selected automatically.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
There is no proper power domain support for the keystone platforms.
However we need to turn off the USB domains before jumping to linux or it
fail to boot (observed with k2e and k2l platforms).
This can be done in the PHY driver as it is dedicated only to the keystone
platforms and matches the required on/off sequence.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The mode selection for the DWC3 is kind of obsolete. The driver does not
have to be host only or gadget only. This choice is confusing.
All the remaining callers of dwc3_uboot_init() explicitly set dr_mode
before calling the function, so none rely on a default behavior.
Remove the choice menu and keep only the USB_DWC3_GADGET option. Enable it
by default if USB_GADGET and USB_DWC3 are enabled.
It must be disabled for the evb-rk3328 as it uses DWC2 for the gadget and
DWC3 for the host.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the function dwc3_get_properties() in the
linux dwc3 driver introduced in commit c5ac6116db35d.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
There is no need to fail if the maximum speed is not specified.
If the speed is not specified, do the same as linux and assume super speed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".
In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
No one is actually implementing those functions.
We could remove calls to these altogether, but it does not really hurt to
keep the empty inlined version at the moment and it satisfies a symmetry
with the gadget mode.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The xhci.h header file is currently located under drivers/usb/xhci
Move it to the include/usb folder to make it available to drivers that
are not under drivers/usb/xhci
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT so that number of flash banks
are automatically detected by CFI flash driver
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the
same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not
possible to use OSPI0 and HBMC simultaneously as they are muxed within
the Flash Subsystem hence disable HBMC by default as keep OSPI enabled.
Bootloader will fixup DT when it detects HyperFlash instead of OSPI.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
AM654/J721e has HyperBus Memory Controller that supports HyperFlash and
HyperRAM devices. It provides a memory mapped interface to interact with
these devices. Add a driver to support the same.
Driver calibrates the controller, setups up for MMIO access and probes
HyperFlash child node.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
error when CONFIG_SYS_MONITOR_BASE is not defined.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add environment variables to boot kernel from a filesystem contained in
the 2nd UFS LUN. The user can boot from a ufs filesystem just by
entering the following commands.
=> setenv boot ufs
=> boot
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add Support for commands to initialize and configure UFS devices.
TODO: Add Support for commands to resize and reconfigure LUNs
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add Support for UFS Host Controller Interface (UFSHCI) for communicating
with Universal Flash Storage (UFS) devices. The steps to initialize the
host controller interface are the following:
- Initiate the Host Controller Initialization process by writing to the
Host controller enable register.
- Configure the Host Controller base address registers by allocating a
host memory space and related data structures.
- Unipro link startup procedure
- Check for connected device
- Configure UFS host controller to process requests
Also register this host controller as a SCSI host controller.
Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported to
U-boot.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Some SCSI devices like UFS use DMA for executing scsi commands and hence
need to know the direction of transfer of the dma. Add a dma_dir element
to the command structure to facilitate this.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
The UFS SCSI device LUNs are observed to return failure the first time a
unit ready inquiry is sent and pass on the second try. Send this
inquiry 3 times to make sure device is ready.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add max_bytes_per_req to scsi_platdata to enable the host driver to limit
the number of bytes that can be read/written per request.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
With no non-DM driver using scsi_read()/_write() APIs, remove
the legacy implementations.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
[trini: Reorder slightly and mark scsi_read/write behind BLK test to
avoid warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
Make sure that the clock self-assignment works by having a clock of
clk-sbox be configured automatically when clk-sbox is probed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This fixes the case where assigned-clocks is used to define a clock
defaults inside this same clock's node. This is used sometimes to setup a
default parents and/or rate for a clock.
example:
muxed_clock: muxed_clock {
clocks = <&clk_provider 0>, <&clk_provider 1>;
#clock-cells = <0>;
assigned-clocks = <&muxed_clock>;
assigned-clock-parents = <&clk_provider 1>;
};
It doesn't work in u-boot because the assigned-clocks are setup *before*
the clock is probed. (clk_set_parent() will likely crash or fail if called
before the device probe function)
Making it work by handling "assigned-clocks" in 2 steps: first before the
clk device is probed, and then after the clk device is probed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a few more clocks the clk_sandbox clock provider and get them using
the managed API.
Make sure they are released when the device is removed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the
device-tree. The clocks is automatically released and the data structure
freed when the device is unbound.
Also add devm_clk_put() to release the clock and free the data structure
manually.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This change adds support for I2C clock modeled in CCF. This code intention
is to only enable those clocks in the I2C driver with default settings.
For that reason the "busy" versions of clocks reuse the generic approach
and would need to be updated when one wants to adjust the I2C clock
frequency in U-Boot.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
According to the documentation in clk.h, clk_set_parent() return the new
rate of the clock or a negative error code.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Select the correct USB product id used by the download gadget
for ST stm32mp1 boards.
The board stm32mp1 select the correct product id, as defined in
http://www.linux-usb.org/usb.ids for the STMicroelectronics
vendor id = 0x0483 (CONFIG_USB_GADGET_VENDOR_NUM):
- dfu = 0xdf11 : STM Device in DFU mode
it is the value used by ROM code and reused for stm32prog
command
- fasboot = 0x0afb : Android Fastboot device
- others = 0x5720 (CONFIG_USB_GADGET_PRODUCT_NUM)
Mass Storage Device
it is used for UMS command / usb_dnl_ums
This patch avoid conflict when the same USB VID/PID is used for
ums, fastboot or dfu command (two different protocols associated
to the same PID).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Network support was never added on this board, disable
CONFIG_NET flag to avoid following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Network support was never added on this board, disable
CONFIG_NET flag to avoid following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Network support was never added on this board, disable
CONFIG_NET flag to avoid following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Network support was never added on this board, disable
CONFIG_NET flag to avoid following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Network support was never added on this board, disable
CONFIG_NET flag to avoid following warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Correct the name of the define used CONFIG_IS_ENABLED which is
not aligned with Kconfig name: CONFIG_$(SPL_)PINCONF_RECURSIVE.
The recursive calls is conditional only for UCLASS_PINCONFIG
"pinconfig" driver.
It is always needed to call pinctrl_post_bind for UCLASS_PINCTRL
"pinctrl", the test CONFIG_IS_ENABLED(PINCONF_RECURSIVE) need to
be removed for this driver.
This correct a regression introduced because the same patch is
applied twice times in u-boot-dm branch:
- commit e878b53a79 ("dm: pinctrl: introduce PINCONF_RECURSIVE
option")
- commit c20851b3d8 ("dm: pinctrl: introduce PINCONF_RECURSIVE
option")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
To allow OCRAM to be used as wakeup source in
deep sleep, do not power it down.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The patch adds an errata ID A-008646 for workaround
to provide more information by errata ID.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
LX2160A/LX2120A/LX2080A SVR value should be
0x873600/0x873620/0x873602
Previous values were valid only if CAN fuse is blown.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a.
Both ls1027a and ls1017a personalities are lower functionality version
which doesn't support the multimedia subsystems, like LCD, GPU.
To disable multimedia feature on non-multimedia version,
set the status property to disabled in dts nodes.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This configuration enables picking the environment from flash before
DDR init.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and
SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write
snoop signal on LS1043A and LS1046A.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add LS1027A, LS1018A and LS1017A personalities support to
LS1028A SoC family.
LS1028A is the prime personality of LS1028A SoC family.
LS1027A is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.
The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72
core, low power versions of the QorIQ LS1028A and LS1027A
SoCs respectively.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Loading U-Boot on i.MX8QXP MEK board is broken since recent changes
in spl_mmc:
U-Boot SPL 2019.10-00162-gff5bd397e4 (Oct 18 2019 - 15:50:45 +0200)
Normal Boot
WDT: Not found!
Trying to boot from MMC2_2
Load image from MMC/SD 0x46400
spl: mmc partition switch failed
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
The newly added CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION option
is selected automatically and overrides the EXT_CSC_PART_CONFIG
configurations with default value, always selecting the eMMC boot
partition 1. Boards which place U-Boot image in other partitions
became not bootable.
Fix this by making the eMMC HW boot partition selection optional.
Fixes: 17241ea054 (spl: mmc: Add option to set eMMC HW boot partition)
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Pull request for UEFI sub-system for efi-2020-01-rc1 (2)
Install the simple file protocol only if there is a file system on the
partition.
Enable CONFIG_CMD_NVEDIT_EFI on QEMU.
- document alternative libretech-cc installation methods, including upstream TF-A and opensource tools
- add HDMI/CVBS display support for Amlogic G12A SoCs and SEI510 board
- add support for Amlogic A311D based Khadas VIM3
- add support for Amlogic S905X3 based SEI610 board, targeting Android support like SEI510
Add separate config file to handle the different eMMC size on
the sei610 board.
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Move android generic config and boot sequence in meson64_android header
and fix size of userdata to use all eMMC on SEI510.
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add support for the customer board SEI610 manufactured by SEI Robotics
with the following specifications:
- Amlogic S905X3 ARM Cortex-A55 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- 1 x USB 3.0 Host
- 1 x USB Type-C DRD
- 1 x FTDI USB Serial Debug Interface
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module
Like it's SEI510 counterpart, the boot flow is designed to boot
Android AOSP built for the Yukawa Android device.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Rename meson-g12a-u-boot.dtsi into meson-g12-common-u-boot.dtsi to
match the new DT architecture and add meson-sm1-sei610-u-boot.dtsi
to handle the U-Boot specific DT for graphics.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The GX VPU Power Domain driver has been replaced by the Everything-Else
Power Domain driver for G12A and SM1.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Based on the 54ecb8f7028c ("Linux 5.4-rc1") Everything-Else power domain
driver for Amlogic SoCs.
This driver handles the VPU Power domain and other domains from the
Everything-Else part of the SM1 and G12A SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The SM1 clock controller is almost identical to the G12A and
so far the differences don't matter.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Values imported from Linux driver, but in correct numeric order.
Khadas VIM3 prints: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
Cc: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Write SoC instead of Soc. The Linux driver is not affected.
Fixes: f41d723b9f ("ARM: meson: display Amlogic SoC Information")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In Linux meson-g12-common.dtsi was introduced as well as new g12b nodes
and headers, as dependencies of new meson-g12b-a311d-khadas-vim3.dts.
Copied from da0c9ea146cb ("Linux 5.4-rc2")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the necessary config options to support BMP display over HDMI,
and add a preboot command to load the BMP file from a predefined
eMMC partition.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Like the meson-gx support, add the U-Boot specific bits in DT
to support graphics on G12A SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
If VIDEO_MESON is enabled, we need to setup the fdt for the framebuffer.
Call meson_vpu_rsv_fb() which reserves the framebuffer memory region for
EFI, and sets up simple-framebuffer nodes if simplefb support is
enabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Finally add the Amlogic G12A SoC compatible for the VPU driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Synchronize the Amlogic Meson Video driver back with the latest
DRM misc tree, adding G12A platform support, from the latest commit:
528a25d040bc ("drm: meson: use match data to detect vpu compatibility")
The sync includes the following changes from Linux adapted to U-Boot:
- Add support for VIC alternate timings
- Switch PLL to 5.94GHz base for 297Mhz pixel clock
- Add registers for G12A SoC
- Add G12A Support for VPP setup
- Add G12A Support for VIU setup
- Add G12A support for OSD1 Plane
- Add G12A support for plane handling in CRTC driver
- Add G12A support for CVBS Encoder
- Add G12A Video Clock setup
- Add G12A support for the DW-HDMI Glue
- fix G12A HDMI PLL settings for 4K60 1000/1001 variations
- fix primary plane disabling
- fix G12A primary plane disabling
- mask value when writing bits relaxed
- crtc: drv: vpp: viu: venc: use proper macros instead of magic constants
- global clean-up
- add macro used to enable HDMI PLL
- venc: set the correct macrovision max amplitude value
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Remove getting and enabling the node power domain since it's now handled
by the dm core directly.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Add necessary clock support to set up clock for the VPU and
HDMI support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Add Amlogic G12A support for the gx-pwrc driver, aligned on the
Linux v5.2 driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
As already documented in this README, several binaries must be
glued together in order to boot the device.
Extend the documentation to cover the prebuilt binaries
(saving you the hassle of installing ancient cross-compilers),
and also mention the open source replacements for the encryption
tool (which is especially useful if you want to avoid requiring
32-bit x86 binaries in your build system).
Signed-off-by: Daniel Drake <drake@endlessm.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The released Linux boot image header in v5.3 is different from the
one present in U-Boot. Align the header with the new version. The
changes in Linux are backward compatible. Previous U-Boot releases
with older header will continue to work as well. As v5.3 kernel is
the first one to support image header, there is no compatibility
issue between new U-Boot (with this patch) and older kernel.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This patch adds a DM based driver model for gpio controller present in
FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
GPIO15 are routed to the J1 header on the board.
This implementation is ported from linux based gpio driver submitted
for review by Wesley W. Terpstra <wesley@sifive.com> and/or Atish Patra
<atish.patra@wdc.com> (many thanks !!). The linux driver can be referred
here [1]
[1]: https://lkml.org/lkml/2018/10/9/1103
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
To reduce the default image size CONFIG_CMD_NVEDIT_EFI was disabled by
default. Re-enable it on the QEMU platforms supporting the UEFI sub-system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
In the current implementation, EFI_SIMPLEFILE_SYSTEM_PROTOCOL is always
installed to all the partitions even if some of them may house no file
system.
With this patch, that protocol will be installed only if any file system
exists.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This function is a variant of fs_get_type_name() and returns a filesystem
type with which the current device is associated.
We don't want to export fs_type variable directly because we have to take
care of it consistently within fs.c.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
fs_ls(), fs_mkdir() and fs_unlink() sets fs_type to FS_TYPE_ANY
explicitly, but it is redundant as they call fs_close().
So just remove those lines.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
fs_close() closes the connection to a file system which opened with
either fs_set_blk_dev() or fs_set_dev_with_part(). Many file system
functions implicitly call fs_close(), e.g. fs_closedir(), fs_exist(),
fs_ln(), fs_ls(), fs_mkdir(), fs_read(), fs_size(), fs_write()
and fs_unlink().
So just export it.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
device_path strcuture has 2 bytes of "length" field, and so
file path length should not exceed this limit, 65535.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
ubi enhancements for 2020.01
- provide a way for skipping crc checks ported from linux, and add an
U-Boot command to set this flag on already installed systems.
- fix redundand environment management
binman enhancements:
- Dropping some test Elf files and building them from source instead
- Refactoring of x86 16-bit entries
- Support for SPL symbols within sections
- Handle the 'notes' sections and hidden symbols in recent binutils
- Improved error reporting with a tool fails
libfdt and documentation fixes
vboot required-key test
driver model power-domain controls
patman Message-Id enhancement
- Split travis jobs again so we don't have failures due to excessive
build times.
- Android image updates
- cscope bugfix, update ARM maintainers entry, drop H2200 platform.
Split the ARMv7 and AArch64 platforms into separate jobs, to avoid them
taking too long to build overall. Also rename them from "Xilinx" to
"Zynq*" to reflect slightly better what is being built and to pull in a
few more board matches.
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Split the 32bit and 64bit platforms into separate jobs, to avoid them
taking too long to build overall.
Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
- Split "tqc" and "technexion" out into their own jobs and exclude
them from the catch-all jobs
- Clarify the job labels a little more.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
cscope complains that it can't find files that appears to be symbolic links
cscope: cannot find file tools/binman/test/u_boot_binman_syms_bad.c
cscope: cannot find file tools/version.h
`find -L` tests properties, but name, and cscope can't cope with symbolic
links (a lot of bugs in upstream were simple closed as kinda invalid).
To work around the problem, exclude symbolic links from the cscope.files.
Note, it's done in two pass to speed up the process (`-exec realpath ...`
approach is not portable and introduces a 3x delay).
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
We check (with a #if defined()) the config ENV_UBI_VOLUME_REDUND
to know if there is a redundant env. But this config is a string
and is always defined with env is in ubi, so we always consider
that a redundand env is used.
To fix this issue, I've added a hidden flag ENV_UBI_IS_VOLUME_REDUND
that is true when ENV_UBI_VOLUME_REDUND is not "". Then, I check
this flag in the code, instead of the string ENV_UBI_VOLUME_REDUND.
hs: fixed typo s/condider/consider
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
U-Boot now supports the "skip_check" flag to optionally skip the CRC
check at open time. Currently its only possible to set this bit upon
UBI volume creation. But it might be very useful to also set this bit
on already installed systems (e.g. field upgrade) to make also use of
the boot-time decrease on those systems.
This patch now adds a new "ubi" command "ubi skipcheck" to set or clear
this bit in the UBI volume header:
=> ubi skipcheck rootfs0 on
Setting skip_check on volume rootfs0
BTW: This saves approx. 10 seconds Linux bootup time on a MT7688 based
target with 128MiB of SPI NAND.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Quentin Schulz <quentin.schulz@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@collabora.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Dannenberg <dannenberg@ti.com>
It might be interesting, if "skip_check" is set or not, so lets print
this flag in ubi_dump_vol_info() as well.
hs: fix typo in commit message
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Quentin Schulz <quentin.schulz@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some users of static UBI volumes implement their own integrity check,
thus making the volume CRC check done at open time useless. For
instance, this is the case when one use the ubiblock + dm-verity +
squashfs combination, where dm-verity already checks integrity of the
block device but this time at the block granularity instead of verifying
the whole volume.
Skipping this test drastically improves the boot-time.
Adapted to U-Boot by Stefan Roese.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Quentin Schulz <quentin.schulz@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
At present the 'Index' column of 'dm tree' assumes there is
two digits, this patch increase it to 3 digits.
It also aligns output of 'dm uclass', assuming the same 3 digits index.
The boards with CONFIG_PINCTRL_FULL activated have one pinconfig
by pin configuration, so they can have more than 100 devices
pinconfig (for example with stm32mp157c-ev1 board we have
106 pinconfig node).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the Linux pinctrl binding, the pin configuration nodes don't need to
be direct children of the pin controller device (may be grandchildren for
example). This behavior is managed with the pinconfig u-class which
recursively bind all the sub-node of the pin controller.
But for some binding (when pin configuration is only children of pin
controller) that is not necessary. U-Boot can save memory and reduce
the number of pinconf instance when this feature is deactivated
(for arch stm32mp for example for SPL).
This patch allows to control this feature with a new option
CONFIG_PINCONF_RECURSIVE when it is possible for each individual
pin controller device.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fixed CONFIG_IF_ENABLED() condition, added __maybe_unused:
Signed-off-by: Simon Glass <sjg@chromium.org>
The power domain associated with a device is enabled when probing,
but currently the domain remains enabled when the device is removed.
Some boards started to disable power domains for selected devices
via custom board_quiesce_devices(), but it doesn't work in many
cases, i. e. because devices still can be accessed later in
.remove() callback on behalf of dm_remove_devices_flags().
Utilize the DM core to power off the device power domain, but add a
device flag to be able to selectively let the power domain enabled
after device removal. This might be required for devices that must
remain enabled when booting OS, i. e. serial console for debug
output, etc.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add dev_power_domain_off() api to disable all the power-domains
corresponding to a device
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable DM_FLAG_DEFAULT_PD_CTRL_OFF for arm64 remote core so that
pd can be enabled after loading the image.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In some remoteproc cases, enabling the power domain of the core will
start running the core. In such cases image should be loaded before
enabling the power domain. But the current DM framework enables the
power-domain by default during probe. This is causing the remotecore
to start and crash as there is no valid image loaded.
In order to avoid this introduce a DM flag that doesn't allow for
enabling/disabling the power-domain by DM framework.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When DEVRES is not set, devm_kmalloc_array() is spelled
devm_kmaloc_array() (with one 'l' only).
Fixing it so that the name is the same with and without DEVRES.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As per the centithread on ksummit-discuss [1], there are folks who
feel that if a Change-Id is present in a developer's local commit that
said Change-Id could be interesting to include in upstream posts.
Specifically if two commits are posted with the same Change-Id there's
a reasonable chance that they are either the same commit or a newer
version of the same commit. Specifically this is because that's how
gerrit has trained people to work.
There is much angst about Change-Id in upstream Linux, but one thing
that seems safe and non-controversial is to include the Change-Id as
part of the string of crud that makes up a Message-Id.
Let's give that a try.
In theory (if there is enough adoption) this could help a tool more
reliably find various versions of a commit. This actually might work
pretty well for U-Boot where (I believe) quite a number of developers
use patman, so there could be critical mass (assuming that enough of
these people also use a git hook that adds Change-Id to their
commits). I was able to find this git hook by searching for "gerrit
change id git hook" in my favorite search engine.
In theory one could imagine something like this could be integrated
into other tools, possibly even git-send-email. Getting it into
patman seems like a sane first step, though.
NOTE: this patch is being posted using a patman containing this patch,
so you should be able to see the Message-Id of this patch and see that
it contains my local Change-Id, which ends in 2b9 if you want to
check.
[1] https://lists.linuxfoundation.org/pipermail/ksummit-discuss/2019-August/006739.html
Signed-off-by: Douglas Anderson <dianders@chromium.org>
The aes command used to segfault when accessing memory in sandbox.
The pointer accesses should be mapped.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Currently, if image verification with a required key fails, rsa_verify()
code tries to find another key to verify the FIT image. This however, is
not the intended behavior as the documentation says that required keys
"must be verified for the image / configuration to be considered valid".
This patch fixes the issue by making rsa_verify() return immediately if
the verification of a required key fails.
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@gmail.com>
This commit add a test in the vboot test to check that
when a required key is asked, only FIT signed with this
key is used/accepted by u-boot.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Skip not associated gpio phandle let register the other gpios on a group.
We need anyway to send out a warning to the user to fix their uboot-board.dtsi.
Thhe handle id can be found inside the decompiled dtb
dtc -I dtb -O dts -o devicetree.dts spl/u-boot-spl.dtb
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When multiple power domains attached to a device, need power on
them all, so use dev_power_domain_on to do that.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add this new API to power on multiple domains attached
to a device.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Changed to static inline and added a condition into C file:
Signed-off-by: Simon Glass <sjg@chromium.org>
When CONFIG_OF_PRIOR_STAGE is enabled, this workaround was needed
before device_bind_common assigned request numbers sequentially in the
absence of aliases.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
For CONFIG_OF_PRIOR_STAGE, in the absence of a device tree alias for a
given device, use the next request number for that type of device.
This allows aliases to be used when they're available, while still
allowing unaliased devices to be probed.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
The reset function sets the pin to 0 then 1 but if the pin is marked
ACTIVE_LOW in the DT it gets inverted and leaves the TPM in reset.
Let the gpio driver take care of the reset polarity.
Signed-off-by: Kayla Theil <kayla.theil@mixed-mode.de>
Default address cells value on the livetree access function
returns the wrong value. Fix this so that the value returned
corresponds to the device tree specification.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
The commit "libfdt: fdt_address_cells() and fdt_size_cells()" introduced
a bug as it consolidated code between the helpers for getting
be 0, and is frequently found so in practice for /cpus. IEEE1275 only
requires implementations to handle 1..4 for #address-cells, although one
could make a case for #address-cells == #size-cells == 0 being used to
represent a bridge with a single port.
While we're there, it's not totally obvious that the existing implicit
cast of a u32 to int will give the correct results according to strict C,
although it does work in practice. Straighten that up to cast only after
we've made our range checks.
This is based on upstream commit:
b8d6eca ("libfdt: Allow #size-cells of 0")
but misses the test cases,as we don't implement them in U-Boot.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
According to the device tree specification, the default value for
was not present.
This patch also makes fdt_address_cells() and fdt_size_cells() conform
to the behaviour documented in libfdt.h. The defaults are only returned
if fdt_getprop() returns -FDT_ERR_NOTFOUND, otherwise the actual error
is returned.
This is based on upstream commit:
aa7254d ("libfdt: return correct value if #size-cells property is not present")
but misses the test case part, as we don't implement them in U-Boot.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Add internal fdt_cells() to avoid copy and paste. Fix typo in
fdt_size_cells() documentation comment.
This is based in upstream commit:
c12b2b0 ("libfdt: fdt_address_cells() and fdt_size_cells()")
but misses the test cases, as we don't implement them in U-Boot.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When I tried to run some new efi tests with pytest, efi_smbios_register()
triggered a segmentation fault. Here is the location where it happened:
efi_init_obj_list()
efi_smbios_register()
write_smbios_table()
smbios_write_type4()
smbios_write_type4_dm()
where dev_get_parent_platdata() should return a pointer to struct
cpu_platdata, but it is actually NULL because any cpu device on
sandbox is attached to "root_driver."
With this patch, this issue will be fixed by moving all the definitions
of cpus under "cpus" node so that they have a "cpu_bus" parent.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the Linux pinctrl binding, the pin configuration nodes don't need to
be direct children of the pin controller device (may be grandchildren for
example). This behavior is managed with the pinconfig u-class which
recursively bind all the sub-node of the pin controller.
But for some binding (when pin configuration is only children of pin
controller) that is not necessary. U-Boot can save memory and reduce
the number of pinconf instance when this feature is deactivated
(for arch stm32mp for example for SPL).
This patch allows to control this feature with a new option
CONFIG_PINCONF_RECURSIVE when it is possible for each individual
pin controller device.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present the symbol information is written to binaries just before
binman exits. This is fine for entries within sections since the section
contents is calculated when it is needed, so the updated symbol values are
included in the image that is written.
However some binaries are inside entries which have already generated
their contents and do not notice that the entries have changed (e.g. Intel
IFWI).
Move the symbol writing earlier to cope with this.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Intel IFWI (Integrated Firmware Image) is effectively a section with
other entries inside it. Support writing symbol information into entries
within it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for the ProcessContents() method in this entry so that it is
possible to support entries which change after initial creation.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this class reads its entries in the constructor. This is not
how things should be done now. Update it.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Intel FSP supports initialising memory early during boot using a binary
blob called 'fspm'. Add support for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is useful to be able to access the size of an image in SPL, with
something like:
binman_sym_declare(unsigned long, u_boot_any, size);
...
ulong u_boot_size = binman_sym(ulong, u_boot_any, size);
Add support for this and update the tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present these are large enough to hold 20 bytes of symbol data. Add
four more bytes so we can add another test.
Unfortunately at present this involves changing a few test files to make
room. We could adjust the test files to not specify sizes for entries.
Then we could make the tests check the actual sizes. But for now, leave it
as it is, since the effort is minor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Entries which include a section and need to obtain its contents call
GetData(), as with any other entry. But the current implementation of this
method in entry_Section requires the size of the section to be known. If
it is unknown, an error is produced, since size is None:
TypeError: can't multiply sequence by non-int of type 'NoneType'
There is no need to know the size in advance since the code can be
adjusted to build up the section piece by piece, instead of patching each
entry into an existing bytearray.
Update the code to handle this and add a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Two of the test files somehow were not converted to three digits. Fix
them, using the next available numbers.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we only support symbols inside binaries which are at the top
level of an image. This restrictions seems unreasonable since more complex
images may want to group binaries within different sections.
Relax the restriction, adding a new _SetupTplElf() helper function.
Also fix a typo in the comment for testTpl().
Signed-off-by: Simon Glass <sjg@chromium.org>
We use the Makefile for all ELF test files now, so drop all the code that
checks whether to get the test file from the Makefile or from the git
repo.
Also add a comment to the Makefile indicating that it is run from binman.
Signed-off-by: Simon Glass <sjg@chromium.org>
Remove this file from git and instead build it using the Makefile.
With this change a few things need to be adjusted:
1. The 'notes' section no-longer appears at the start of the ELF file
(before the code), so update testSymbols to adjust the offsets.
2. The dynamic linker is disabled to avoid errors like:
"Not enough room for program headers, try linking with -N"
3. The interpreter note is moved to the end of the image, so that the
binman symbols appear first.
Signed-off-by: Simon Glass <sjg@chromium.org>
Remove this file from git and instead build it using the Makefile.
Update tools.GetInputFilename() to support reading files from an absolute
path, so that we can read the Elf test files easily. Also make sure that
the temp directory is report in ELF tests as this was commented out.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the ELF test files are checked into the U-Boot tree. This is
covenient since the files never change and can be used on non-x86
platforms. However it is not good practice to check in binaries and in
this case it does not seem essential.
Update the binman test-file Makefile to support having source in a
different directory. Adjust binman to run it to build bss_data, as a
start. We can add other files as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this command silently fails if something goes wrong. Use the
tools.Run() function instead, since it reports errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this entry does not work correctly when a FIT image is used as
the input. It updates the FIT instead of the output image. The test passed
because the FIT image happened to have the right data already.
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
A Firmware Image Table (FIT) is a data structure defined by Intel which
contains information about various things needed by the SoC, such as
microcode.
Add support for this entry as well as the pointer to it. The contents of
FIT are fixed at present. Future work is needed to support adding
microcode, etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present these two sections of code are linked together into a single
2KB chunk in a single file. Some Intel SoCs like to have a FIT (Firmware
Interface Table) in the ROM and the pointer for this needs to go at
0xffffffc0 which is in the middle of these two sections.
Make use of the new 'reset' entry and change the existing 16-bit entry to
include just the 16-bit data.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present binman has a single entry type for the 16-bit code code needed
to start up an x86 processor. This entry is intended to include both the
reset vector itself as well as the code to move to 32-bit mode.
However this is not very flexible since in some cases other data needs to
be included at the top of the SPI flash, in between these two pieces. For
example Intel requires that a FIT (Firmware Image Table) pointer be placed
0x40 bytes before the end of the ROM.
To deal with this, add a new reset entry for just the reset vector. A
subsequent change will adjust the existing 'start16' entry.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the Intel IFWI entry uses 'replace' without the 'ifwi-' prefix.
This is a fairly generic name which might conflict with the main Entry
base class at some point, if more features are added. Add a prefix.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some versions of binutils generate hidden symbols which are currently not
parsed by binman. Correct this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Recent versions of binutils add a '.note.gnu.property' into the ELF file.
This is not required and interferes with the expected output. Drop it.
Also fix testMakeElf() to use a different file for input and output.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present if libfdt is not available binman can't do anything much.
Improve the situation a little.
Ideally there should be a test to cover this, but I'm not quite sure how
to fake this.
Signed-off-by: Simon Glass <sjg@chromium.org>
(fixed up missing ReadChildData() enty test)
It is more common to use the name 'cls' for the class object of a class
method, to distinguish it from normal methods, which use 'self' Update the
binman tests accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present tools are not expected to fail. If they do an exception is
raised but there is no detail about what went wrong. This makes it hard
to debug if something does actually go wrong.
Fix this by outputting both stderr and stdout on failure.
Signed-off-by: Simon Glass <sjg@chromium.org>
In new versions of Android Boot Image next fields are added to the
header (and corresponding payloads are added to the image itself):
- v1: Recovery DTBO
- v2: DTB
Account for these new fields in next functions:
1. android_image_get_end(): as v1 and v2 have new payloads in the
image, the calculation of image end address should be extended
correspondingly; this is used e.g. by "bootm" command when booting
the kernel from Android Boot Image
2. android_print_contents(): new fields values in v1 and v2 should be
printed; the result of this function can be seen e.g. in "iminfo"
command
This commit doesn't add the means for working with new payloads in v1
and v2 images (it will be done in further commits), it only updates
existing functions w.r.t. changes in boot image v1/v2.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
As android_image.h uses types like u32, we need to include corresponding
headers in place. Otherwise the user will be forced to include those in
C file, or next build error can occur:
include/android_image.h:32:5: error: unknown type name 'u32'
u32 kernel_size; /* size in bytes */
Include required headers for data types used. While at it, remove
typedef struct, which is prohibited by kernel coding style, and fix the
comment.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
u-boot-imx-20191014
-------------------
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
- logicpd pinmux
- i.MX7ULP: imx_ddr_size
- fixes Toradex i.MX6/i.MX7
- pico-imx7d
- tpc70 converted to DM
- New Board: meerkat96
- add HAB version command
- i.MX8 :
imx8: Jump from alias to OCRAM address at SPL init
imx8qm/qxp: Set SPL TEXT base to OCRAM base
- Add sdhci driver for Broadcom iProc platform
- Add a driver callback for power-cycle for mmc
- Implement host_power_cycle callback for stm32_sdmmc2
- spl: dm_mmc: Initialize only the required mmc device
THe RVT data includes a major and minor version in its header
parameter. Add a new command to print this out.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Use imx_ddr_size() to retrieve the total DDR size instead
of passing a hardcoded memory size.
imx_ddr_size() calculates the memory size based on the actual
MMDC registers values and is useful to detect misconfigurations,
so switch to this more robust approach.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
i.MX7ULP uses the same MMDC controller IP as found on i.MX53
and i.MX6, so build mmdc_size.c for i.MX7ULP as well.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
The original imx_ddr_size() implementation had some
issues reported by checkpatch like this:
CHECK: Prefer kernel type 'u32' over 'uint32_t'
#127: FILE: arch/arm/mach-imx/mmdc_size.c:16:
+ uint32_t ctl;
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
#151: FILE: arch/arm/mach-imx/mmdc_size.c:40:
+ unsigned ctl = readl(&mem->ctl);
Fix all of them.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Place imx_ddr_size() into a separate file.
The motivation for doing this is to be able to easily reuse
imx_ddr_size() on i.MX7ULP.
Currently imx_ddr_size() is inside arch/arm/mach-imx/cpu.c, which
is not built for i.MX7ULP.
Changing the logic to allow building cpu.c for i.MX7UP would
require adding several ifdef's, leading to a not a very elegant
solution.
To allow better reuse, just place imx_ddr_size() into a common
mmdc_size.c file.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
The new class dsi host allows the management of the bridge DPI to DSI.
This bridge is embedded in the chipset mp1 (come from synopsys company).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
The new class dsi host allows the management of the bridge DPI to DSI.
This bridge is embedded in the chipset mp1 (come from synopsys company).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Support for Raydium RM68200 720p dsi 2dl video mode panel.
This rm68200 panel driver is based on the Linux Kernel driver from
drivers/gpu/drm/panel/panel-raydium-rm68200.c.
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Add a Synopsys Designware MIPI DSI host bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Display Serial Interface (DSI) host can usefully be modelled
as their own uclass.
DSI defines a serial bus and a communication protocol
between the host and the device (panel, bridge).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
This also enables mtd configs which are required by nandbcb command.
This command would be used to configure boot control block(BCB) while
writing spl image on nand device.
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Implementation of pmic_get() uses uclass_find_device_by_name(), which
behaviour was changed in 4213609cc7
("drivers: core: use strcmp when find device by name"). Now we have to
supply full node name with unit address.
Fixes boot issue:
U-Boot 2019.07-00788-g0ef6e69a1e-dirty (Jul 19 2019 - 15:27:02 +0300)
CPU: Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz)
CPU: Extended Commercial temperature grade (-20C to 105C) at 41C
Reset cause: POR
DRAM: 512 MiB
initcall sequence 9ffd3a4c failed at call 87803c61 (err=-19)
ERROR Please RESET the board
Fixes: 4213609cc7("drivers: core: use strcmp when find device by name")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
When building a FIT image for SPL to load also take into account the
configured external offset. This allows the SPL to load the u-boot FIT
image correctly when configuring SECURE_BOOT on i.mx6 is enabled
(with CONFIG_FIT_EXTERNAL_OFFSET=0x3000).
Note this doesn't allow secure booting; but it does allow an unsigned
SPL/u-boot with secure boot support eanbled to boot on open device.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Modify the SPL TEXT base from OCRAM alias to OCRAM base 0x100000, so
we can use full OCRAM not limit to 96KB
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
When running SPL on iMX8, the A core starts at address 0
which is a alias to OCRAM 0x100000.
The alias only map first 96KB of OCRAM, so this require the
SPL size can't beyond 96KB. But when using SPL DM, the size increase
significantly and may exceed 96KB.
So to fix the problem, we will change SPL linker address to OCRAM
address 0x100000. And then jump to the absolute address not the PC relative
address for entering OCRAM.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
This patch updates envs responsible for using USB pendrive as a
SWUpdate based tool for recovery and update.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch converts the TPC70 to use driver model and device tree
description in both SPL and u-boot proper.
Notable changes (DM/DTS conversion):
- PINCTRL{_IMX6}
- DM_I2C
- enable 'regulator' and 'pmic' commands
- DM_MMC and BLK (USDHC)
- DM_ETH
- DM WDT (including SYSRESET)
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit adds new file - imx6q-kp-u-boot.dtsi with a set of u-boot
specific properties for imx6q KP device.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The TPC70 can boot from SD card (debug/development) and eMMC (production).
The board_boot_order() function provides a run time check for the device
from which one wants to boot (it is selected by GPIO pins setup).
Moreover, a fallback to SD card is provided if the detection is not
possible or working properly.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
With the OCRAM expanded to 256KB and the SPL_PINCTRL enabled with
-u-boot.dtsi entries to include the pinmuxing in SPL, the manual
code setting up the pinmux can go away.
This patch removes the legacy pinmuxing code from the board file.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
With the 256KB of OCRAM available to SPL now, there should be
enough room to enable the pinmuxing in SPL from the device tree.
This patch enables SPL_PINCTRL et al and adds the serial and
usdhc pin mux references to the -u-boot.dtsi file so the pins can be
configured from the device tree.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since this board config only supports, the i.MX6D/i.MX6Q configurations,
256K of on-chip RAM is available which increases the space available
to SPL to help further reduce board code and further enable device tree
functions.
This patch enables 256K of RAM.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
So we can get rid of legacy pci config code.
PCI_PNP is not required for this board, remove it to reduce the size of the
u-boot binary.
DM_PCI does not start the host controller automatically anymore. Do so
in preboot instead.
Signed-off-by: Soeren Moch <smoch@web.de>
Both the distro boot configuration as well as the general pxe support
standardized on fdtfile as the variable to hold the dtb filename.
Adjust to follow that such that e.g. "pxe boot" will just work.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
We don't need to pull in anything from the MIPS job so exclude that from
the new bcm job and make it clear it's building only ARM.
Signed-off-by: Tom Rini <trini@konsulko.com>
When hitting an invalid FAT cluster while reading a file always print an
error message and return an error code.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
At this point, all drivers that do not use CONFIG_BLK are past their
migration deadlines, so remove this config as it's no longer helpful and
hinders enhancing block drivers.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This define indicates if DM_SPI shall be supported in SPL. This allows
proper operation of DM converted SPI drivers in SPL, which use
#if !CONFIG_IS_ENABLED(DM_SPI) to also support not yet DM/DTS converted
boards.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
If an exception occurs in a loaded image and the relocation offset is
unknown, it is helpful to know the instructions pointed to by the
program counter. This patch adds the missing output.
A possible output is:
Code: 910c4021 aa1303e0 f9400662 d63f0040 (e7f7defb)
The parentheses indicate the instruction causing the exception.
The output can be disassembled using scripts/decodecode:
echo 'Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb)' | \
ARCH=arm64 scripts/decodecode
Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb)
All code
========
0: 90000360 adrp x0, 0x6c000
4: 9100b800 add x0, x0, #0x2e
8: 94002782 bl 0x9e10
c: 17ffff8f b 0xfffffffffffffe48
10:* e7f7defb .inst 0xe7f7defb ; undefined <-- trapping instruction
Code starting with the faulting instruction
===========================================
0: e7f7defb .inst 0xe7f7defb ; undefined
We already have implemented the same for armv7.
For testing command 'exception undefined' can be used.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
readb is unconditionally defined earlier in io.h, so there's no point
checking whether it's undefined.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
No ARM board seems to define __mem_pci - and if it did, one would get tons of
./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined
warnings, because readl and friends are unconditionally defined
earlier in io.h. Moreover, the redefinitions lack the memory barriers
that the first definitions have. So I'm guessing this is practically
dead code.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
This change allows setting pre-defined eMMC boot partition for SPL eMMC
booting. It is necessary in the case when one wants to boot (through falcon
boot) from eMMC after loading SPL from other memory (like SPI-NOR).
Signed-off-by: Mans Rullgard <mans@mansr.com>
[lukma: Edit the commit message]
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Andreas Dannenberg <dannenberg@ti.com>
This fixes a wrongly indented block of code.
Signed-off-by: Mans Rullgard <mans@mansr.com>
[lukma: Make the commit message more verbose]
Signed-off-by: Lukasz Majewski <lukma@denx.de>
If there is any failure during IOdelay recalibration sequence, IOs are
not guaranteed to behave as expected. So hang on any failure during the
sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When an error is reported in __recalibrate_iodelay_start(), de-isolation
of IO doesn't happen. Because of this, undefined behaviour is observed
on many peripherals without any error. So make sure io is out of isolation
at the end of iodelay recalibration.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently "bootcmd" does not work as intended but instead prints MMC usage
information and goes directly to "nandboot".
Follow what the commit 669681104d ("configs: Fix usage of mmc rescan")
does for other boards prior to support for TechNexion TAO3530 SoM was
added.
Signed-off-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
spl_dm_init is failing as usb to be probed with the following error:
"omap_dwc3@483c0000: ret=-2"
Enable usb to make spl boot on am43xx devices
Reported-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Main uart0 is used as debug console by both R5SPL and A72 bootloader and
Linux. So mark it as shared device so that power-domain request is
successful by both cores.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM335x-ICE boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM43xx-IDK boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM57xx-IDK boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Print the board name and ver along with the DT Model.
While at it print the ver for all the detected daughter cards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Power-domain is enabled by default in device_probe. am654 mmc driver
is enabling power-domain again in probe. As the second call is
redundant, drop power_domain_on from probe.
Tested-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When running 'run_fit' the FIT file should have been loaded at
'addr_fit', although at this point they should be the same
use this variable instead of 'loadaddr'.
Signed-off-by: Andrew F. Davis <afd@ti.com>
- add BOARD_LATE_INIT function calls in board.c
- add swi_status detection in board.c
- mux: add guardian interfaces to single pinmux structure
- am33xx, kconfig: add BOARD_LATE_INIT for GUARDIAN board
Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
If the ECC is enabled over the entire memory region, we need to ensure
the printf/put calls do not modify the stack after ECC is disabled.
Moved the printf/put statements after ECC is enabled.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Before the priming begins, we need to disable RMW (Read Modify Write)
and disable ECC verification for read accesses. By default, the EMIF
tool enables RMW and read accesses in the EMIF_ECC_CTRL_REG.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
If ECC is enabled, we need to ensure interleaving is disabled for higher
address space.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr cmd driver is assuming the register
contains the start address and size of the DDR address space. Because
of this some valid ecc addresses are errored out as invalid address.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr driver is assuming the register
contains the start address and size of the DDR address space. Because
of this the ecc enabling is failing for the 2nd range of ecc addresses.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Regulator should not be enabled at probe time if regulator-boot-on
property is not in the dt node.
"enable-active-high" property is only used to indicate the GPIO
polarity.
See kernel documentation :
- Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
- Documentation/devicetree/bindings/regulator/gpio-regulator.yaml
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
In 32bits mode upper bits need to be set to 0, otherwise controller will
try to DMA into not existing memory and stops with error.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Oleksandr Rybalko <ray@ddteam.net>
This adds a document for tphy which supports physical layer
functionality for a number of controllers on MediaTek SoCs,
such as, USB2.0, USB3.0, PCIe, and SATA.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now
we just enable PCIe. As for the other functionalities will be
added gradually in upcoming days.
This is adapted from the Linux version.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
This commit add a generic function board_init_f that
only initialize some device (for example serial). It
avoid to define a board function only to launch the
serial configuration.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
The Broadcom ARM implementations do not yet have a clock framework so
one can use a fixed clock as the root clock of the hsspi block. The
fixed clock does not have an "enable" routine, since it's always
enabled. So when we hit this issue, getting an ENOSYS return, do not
bail but continue initialization.
Similarly the block might already have been out of reset, say, when
we are booting from a SPI device. So if the reset signal is not configured
in the device tree, do not bail out and instead skip deasserting the reset.
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Make the driver compatible with both big and little endian SOCs.
Replace big-endian calls with their raw equivalents, expect for
writing the command to FIFO. That still has to be in big-endian
format.
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
wait_for_bit_le32 and wait_for_bit_le16 use the raw I/O functions
which would default to big-endian on BE systems. Create the generic
equivalents to use the native endianness.
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The A72 U-Boot code loads and boots a number of remote processors
including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various
Main R5FSS Cores. In order to view the code loaded by the U-Boot by
remote cores, U-Boot should configure the memory region with right
memory attributes. Right now U-Boot carves out a memory region which
is not sufficient for all the images to be loaded. So, increase this
carve out region by 256MB.
Signed-off-by: Kedar Chitnis <kedarc@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The A53 U-Boot code can load and boot the MCU domain R5F cores (either a
single core in LockStep mode or 2 cores in Split mode) to achieve various
early system functionalities. Change the memory attributes for the DDR
regions used by the remote processors so that the cores can see and
execute the proper code loaded by U-Boot.
These regions are currently limited to 0xa0000000 to 0xa2100000 as per
the DDR carveouts assigned for these R5F cores in the overall DDR memory
map.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The A53 U-boot can support early booting of the MCU R5F remote processor(s)
from U-boot prompt to achieve various system usecases before booting the
Linux kernel. Update the default BOOTCOMMAND to provide an automatic and
easier way to start the MCU R5F cores through added environment variables.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable the R5F remoteproc driver for the AM65x GP EVM so that the
MCU domain R5F cores can be booted from A53 U-boot.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The A72 U-boot can support early booting of any of the R5F or C66x
or C71x remote processors from U-boot prompt to achieve various system
usecases before booting the Linux kernel. Update the default BOOTCOMMAND
to provide an automatic and easier way to start various remote processors
through added environment variables.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Add support to boot the MCU domain R5F Core0 remoteproc at U-boot prompt
on the AM65x EVM boards by using the 'boot_rprocs' and other env variables
defined in the common environment file k3_rproc.h, and updating the
'DEFAULT_RPROCS' macro.
The default configuration is to use the MCU R5F in Split mode, so both
the R5F Core0 and Core1 are started before loading and booting the Linux
kernel using the following firmware:
MCU R5FSS0 Core0 (Split) : 0 /lib/firmware/am65x-mcu-r5f0_0-fw
MCU R5FSS0 Core1 (Split) : 1 /lib/firmware/am65x-mcu-r5f0_1-fw
The MCU R5FSS was initially running the R5 SPL in LockStep mode with ATCM
disabled, and is actually shutdown to enable it to be reconfigured and
booted by either A53 U-Boot or Linux kernel in remoteproc mode and using
ATCM.
The MCU R5FSS would need to be reconfigured for Lockstep mode through
DT if a fault-tolerant/safety application were to be run on the cluster
with the DEFAULT_RPROCS macro updated to remove the Core1 firmware.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add support to boot some remoteprocs at U-boot prompt on the J721E EVM
boards by using the 'boot_rprocs' and other env variables defined in the
common environment file k3_rproc.h, and updating the 'DEFAULT_RPROCS'
macro.
The list of R5F cores to be started before loading and booting the Linux
kernel are as follows, and in this order:
Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7-main-r5f0_1-fw
Main R5FSS1 (LockStep) : 4 /lib/firmware/j7-main-r5f1_0-fw
The MCU R5FSS0 and Main R5FSS1 are currently in LockStep mode, so the
equivalent Core1 rprocs (rproc #1 and #5) are not included. The Main
R5FSS0 Core0 (rproc #2) is already started by R5 SPL, so is not included
in the list either.
The DSP cores are started in the following order before loading and
booting the Linux kernel:
C66_0: 6 /lib/firmware/j7-c66_0-fw
C66_1: 7 /lib/firmware/j7-c66_1-fw
C71_0: 8 /lib/firmware/j7-c71_0-fw
The order of the rprocs to boot can be changed at runtime if desired by
overwriting the 'rproc_fw_binaries' environment variable at U-boot prompt.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add a new file include/environment/ti/k3_rproc.h that defines
common environment variables useful for booting various remote
processors from U-Boot. This file is expected to be included in
the board config files with the EXTRA_ENV_RPROC_SETTINGS added
to CONFIG_EXTRA_ENV_SETTINGS and DEFAULT_RPROCS macro overwritten
to include the actual list of processors to be booted.
The 'boot_rprocs' variable just needs to be added to the board's
bootcmd to automatically boot the processors, and runtime control
can be achieved through the 'dorprocboot' variable.
The variables are currently defined to use MMC as the boot media,
and can be expanded in the future to include other boot media.
The immediate usage is intended for K3 J721E SoCs.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
The AM65x SoCs has a single dual-core Arm Cortex-R5F processor
subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster
can be configured at boot time to be either run in a LockStep mode
or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5 cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT nodes for these two MAIN domain R5F cluster/subsystems,
the two R5 cores are each added as child nodes to the corresponding
main cluster node. Configure SS0 in split mode an SS1 in lockstep mode,
with the ATCMs enabled to allow the R5 cores to execute code from DDR
with boot-strapping code from ATCM.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5 cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Certain SoCs with K3 architecture have integrated a C66 Corepac DSP
subsystem and an advanced C71 DSPs. Introduce a remoteproc driver
that that does take care of loading an elf to any of the specified
DSPs and start it.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Some Texas Instruments K3 family of SoCs have one of more Digital Signal
Processor (DSP) subsystems that are comprised of either a TMS320C66x
CorePac and/or a next-generation TMS320C71x CorePac processor subsystem.
Add the device tree bindings document for the C66x DSP devices on these
SoCs. The added example illustrates the DT nodes for the first C66x DSP
device present on the K3 J721E family of SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
SoCs with K3 architecture have an integrated Arm Cortex-R5F subsystem
that is comprised of dual-core Arm Cortex-R5F processor cores. This R5
subsytem can be configured at boot time to be either run in a LockStep
mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
This subsystem has each Tightly-Coupled Memory (TCM) internal memories
for each core split between two banks - TCMA and TCMB.
Add a remoteproc driver to support this subsystem to be able to load
and boot the R5 cores primarily in LockStep mode or split mode.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
The Texas Instruments K3 family of SoCs have one of more dual-core
Arm Cortex R5F processor subsystems/clusters (R5FSS). Add the device
tree bindings document for these R5F subsystem devices. These R5F
processors do not have an MMU, and so require fixed memory carveout
regions matching the firmware image addresses. The nodes require more
than one memory region, with the first memory region used for DMA
allocations at runtime. The remaining memory regions are reserved
and are used for the loading and running of the R5F remote processors.
The added example illustrates the DT nodes for the single R5FSS device
present on K3 AM65x family of SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Power domain for the remote cores needs to be handled in a right
sequence as mandated by the spec. Introduce tisci helper apis
that can control power-domains of remote cores. TISCI clients
can use this api and control the remote cores power domain instead
of hooking it to power-domain layer.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Introduce rproc_elf_get_boot_addr() that returns the entry point of
the elf file. This api auto detects the 64/32 bit elf file and returns
the boot addr accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Introduce a common remoteproc elf loader and checker functions that
automatically detects the 64 bit elf file or 32 bit elf file and
loads/checks the sections accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
The current rproc-elf-loader supports loading of only 32 bit elf files.
Introduce support for loading of 64 bit elf files in rproc-elf-loader.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
rproc_elf32_load_image() rely on user to send a valid address for elf loading.
Instead do a sanity check on the address passed by user. This will help
all rproc elf users to not call sanity_check explicitly before calling
elf_loading.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
Introduce a new parameter "size" that accepts size of the region to
remoteproc ops callback device_to_virt(). This can enforce more checks
on the region that device_to_virt() is dealing with.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Fabien Dessenne <fabien.dessenne@st.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
am65x ROM support booting over UART. And U-Boot built for am65x EVM
supports UART boot as well. Add the UART boot procedure into the README
also providing a corresponding example command sequence for execution
on a host PC.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Activate early console functionality on AM654x devices to allow for an
alternate serial port to be used to support UART-based boot. This is so
that System Firmware (SYSFW) can get loaded over the serial port prior
to the main console being brought up and made available.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Although we currently use the MAIN_UART0 for R5 SPL console output there
are cases where we require access to the MCU_UART0 as well for example in
case of UART-based Y-Modem boot. To support these scenarios add related
DTS definitions to be able to use that UART early on.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
In order to allow booting TI K3 family SoCs via Y-Modem add support for
loading System Firmware by tapping into the associated SPL core loader
function.
In this context also make sure a console is available and if not go
ahead and activate the early console feature which allows bringing up
an alternate full console before the main console is activated. Such
an alternate console is typically setup in a way that the associated
UART can be fully initialized prior to SYSFW services being available.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Implement an early console functionality in SPL that can be used before
the main console is being brought up. This helps in situations where the
main console is dependent on System Firmware (SYSFW) being up and running,
which is usually not the case during the very early stages of boot. Using
this early console functionality will allow for an alternate serial port
to be used to support things like UART-based boot and early diagnostic
messages until the main console is ready to get activated.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Expose SPL's Y-Modem core loader function via the common SPL header
file so it can be re-used for purposes other than loading U-Boot itself.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
During FIT reading through ymodem_read_fit() the function
xyzModem_stream_read() is being used which returns zero once the end
of a stream has been reached. This could lead to an premature exit from
ymodem_read_fit() with certain-sized FIT images reporting that zero
bytes overall were read. Such a premature exit would then result in an
-EIO failure being triggered within the spl_load_simple_fit() caller
function and ultimately lead to a boot failure.
Fix this logic by simply aborting the stream read loops and continuing
with the regular code flow which ultimately would lead to returning
the number of bytes to be read ('size') as expected by the callers of
ymodem_read_fit().
Fixes: fa715193c0 ("spl: Add an option to load a FIT containing U-Boot from UART")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
The doc currently uses sandbox_defconfig as examples of enabling
debug/verbose output of binman. However during a sandbox build it
does not call binman at all. Change it to qemu-x86_defconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present this produces a 16-byte file. It is intended to start 16 bytes
before the end of ROM and pads with zeroes to readh the end.
But binman sometimes wants to add an image-header at the very end of ROM.
Furthermore binman automatically pads the data if it is finishes early.
Drop the padding in resetvec and let binman handle it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Many of the Kconfig options do not apply to FSP2. Update them to use the
FSP_VERSION1 condition instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Move the code to determine the size of a cache record into a function so
we can use it elsewhere in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The write functions do actually change the contents of memory so it is not
correct to use 'const'. Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a field to the PCI emulator per-device data which records which device
is being emulated. This is useful when the emulator needs to check the
device for something.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present when these fail to boot there is no message, just a hang. Add a
panic so it is obvious that something when wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For the correct power cycle sequence with stm32_sdmmc2, the write of the
power cycle value in PWRCTL field of SDMMC_POWER register is now done in
stm32_sdmmc2_host_power_cycle() and no more in stm32_sdmmc2_pwrcycle().
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Some MMC peripherals require specific power cycle sequence, where some
registers need to be written between the regulator is turned off and then
back on. This is the case for the MMC IP embedded in STM32MP1 SoC.
In STM32MP157 reference manual [1], the power cycle sequence is:
1. Reset the SDMMC with the RCC.SDMMCxRST register bit. This will reset
the SDMMC to the reset state and the CPSM and DPSM to the Idle state.
2. Disable the Vcc power to the card.
3. Set the SDMMC in power-cycle state. This will make that the
SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low, to prevent the card
from being supplied through the signal lines.
4. After minimum 1ms enable the Vcc power to the card.
5. After the power ramp period set the SDMMC to the power-off state for
minimum 1ms. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are set to
drive “1”.
6. After the 1ms delay set the SDMMC to power-on state in which the
SDMMC_CK clock will be enabled.
7. After 74 SDMMC_CK cycles the first command can be sent to the card.
The step 3. cannot be handled by the current framework implementation.
A new callback (host_power_cycle) is created, and called in
mmc_power_cycle(), after mmc_power_off().
The incorrect power cycle sequence has shown some boot failures on
STM32MP1 with some SD-cards, especially on cold boots when the input
frequency is low (<= 25MHz).
Those failures are no more seen with this correct power cycle sequence.
[1] https://www.st.com/resource/en/reference_manual/DM00327659.pdf
Signed-off-by: Yann Gautier <yann.gautier@st.com>
In SPL, all the available mmc devices gets initialized during boot.
This might not work in cases where clocks are not available for
certain mmc devices(other than boot device) and the support for
enabling device might not be ready.
Texas Instruments' K3 J721E device having a central system controller
(dmsc) is one such example falling in this category. Below is the
sequence for the failing scenario:
- ROM comes up in SD mode and loads SPL by just initialing SD card.
- SPL loads dmsc firmware from SD Card.
Since ROM has enabled SD, SPL need not enable the SD, just need
to re initialize the card. But SPL is trying to initialize other MMC
instances which are in disabled state. Since dmsc firmware is not yet
available, devices cannot be enabled. So in SPL, initialize only the
mmc device that is needed.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Build the keystone 3 platforms with the keystone 2 platforms, in order
to get back more room in the "catch-all" build jobs.
Signed-off-by: Tom Rini <trini@konsulko.com>
As both "catch-all" ARM jobs are nearing their time limit, move all of
the bcm SoC boards into a single job.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Rename existing FSP code to fsp1
- Add fsp2 directory in preparation to support FSP 2.0
- Various x86 platform codes update
- Various bug fixes and updates in dm core, sandbox and spl
First set of u-boot-atmel features and fixes for 2020.01 cycle
The feature set includes support for two new boards from Microchip AT91:
The sama5d27_wlsom1_ek , an evaluation kit which includes the SAMA5D2
SOC packaged in a 256 MB LPDDR2 SIP, on a SOM including wireless, which
is placed on evaluation kit with sd-card, ethernet, LCD, Camera sensor,
QSPI, etc
The sam9x60ek, an evaluation kit for the new SoC based on ARM926j , the
SAM9X60 . The evaluation kit includes NAND flash, QSPI, Ethernet, Audio,
Camera sensor connector, etc.
The full support for sam9x60ek will come at a later time. There are
still missing bits regarding the clock support and power management
controller.
Pull request for UEFI sub-system for efi-2020-01-rc1
The major corrections in this pull request are:
Fixes for the SetVariable() boot service.
Device path node for NVMe drives.
Disable CONFIG_CMD_NVEDIT by default.
- Python3 conversion of genboardscfg.py
- Resync Kconfiglib.py
- Switch to running CI on Ubuntu "bionic" to facilitate Python 3.6 being
the minimum we use and test.
In order to run all filesystem tests we need to have newer ext4 tools,
move up to Ubuntu 18.04 'bionic' for our base. We need to change
slightly how we invoke the provided grub-mkimage. This will also make
future python3 work easier.
Signed-off-by: Tom Rini <trini@konsulko.com>
When running as another user we might not be able to use '..' for
certain directories and this is the default for buildman. Specify an
output directory instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
We may not always be able to write to the default output directory so
have a temporary directory for our output be created.
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Suggested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
With the reverting of a previous change to spl_boot_device,
this board needs a new solution to determining if we're booting
from MMC1 or MMC2.
This patch creates board_boot_order function which overrides the
standard, and returns not only MMC1, or MMC2, but also can fall
back to NAND or the serial downloader should other boot options
fail.
Signed-off-by: Adam Ford <aford173@gmail.com>
Apologies to everyone whose board I broke by attempting to return
MMC1 or MMC2. I misunderstood how the MMC indexing worked.
This reverts commit 14d319b185.
Signed-off-by: Adam Ford <aford173@gmail.com>
With upcoming patches u-boot.kwb gets too large.
Save 3740 bytes in u-boot.kwb by disabling Unicode support in the UEFI
sub-system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross
architecture purposes. If Secure Boot is required for imx, this means to
enable and use the HAB processor in the soc.
Signed-off-by: Stefano Babic <sbabic@denx.de>
For NXP SoCs we have to set pinmux configuration ASAP (ideally
before relocation) to get serial console working. Without this we miss
almost the half of output (U-boot version, CPU defails, Reset cause,
DRAM details etc.).
To achieve this we need to force appropriate pinctrl drivers to get
probed before relocation.
Fixes: cd69e8ef9b ("colibri-imx6ull: migrate pinctrl and regulators to dtb/dm")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
1. Commit 3a7c45f6a7 ("simple-bus: add DM_FLAG_PRE_RELOC flag to
simple-bus driver") causes some i.MX boards that were converted
to DM, such as warp7, to fail to boot.
As explained by Lukas Auer:
"With the patch, U-Boot probes the drivers for devices under simple-bus
device tree nodes in the pre-relocation device model. The default value
of CONFIG_SYS_MALLOC_F_LEN (0x4000) leaves U-Boot with not enough memory to
do this, causing it to hang."
Fix this problem by providing a convenient default value for
CONFIG_SYS_MALLOC_F_LEN.
2. CONFIG_SPL_TEXT_BASE was moved to Kconfig, so added in defconfig
"configs: move CONFIG_SPL_TEXT_BASE to Kconfig"
(sha1: f89d6133ee)
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
In order to call preloader_console_init from board_init_f when
DM_SERIAL is enabled, it neesd to call spl_early_init() to get early access
to DM and device tree.
This patch calls spl_early_init just before preloader_console_init()
and enables DM_SERIAL and SPL_DM_SERIAL.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Per the workflow found in crt0.S, we don't need to clear BSS in
board_init_f nor do we need to call board_init_r since that will be
done for us from main when we return from board_init_f.
This patch removes the unneeded function calls from board_init_f.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add instructions on how to boot mx6ul_14x14_evk_defconfig target
using the Serial Download Protocol.
Add examples from uuu and imx_usb_loader tools.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
On, i.MX8MQ, the PLL config must be done when ddrmix
isolation is released. So move the dram pll init after
iso config done. For other i.MX8M SOC, either init pll
before or after isolation is ok.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Refine the ddr init driver to make it more reusable for different
DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
code.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
Since the parameter of dram_pll_init is changed, update to use new.
Also remove non-existed header file.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The write data size can be overwritten by writing to the IDATSZ
field of IPCR register. Since the driver always updates the IDATSZ
in page program operation. Set the LUT data size to 0 to align
the codes with iMX.
Signed-off-by: Ye Li <ye.li@nxp.com>
On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller
is updated to have TDH field in FLSHCR register. According to reference
manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX
DDR delay logic won't be enabled.
Another issue in DDR mode is the MCR register will be overwritten in
every read/write/erase operation. This causes DDR_EN been cleared while
TDH=1, then no clk2x output for TX data shift and all operations will
fail.
Signed-off-by: Ye Li <ye.li@nxp.com>
board early initialize fec ethernet controller pinmux
only when FEC is enabled
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
boot order was added to handle both SD and eMMC. But commit
14d319b1 introduced to handle both eMMC and SD globally.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
After u-boot.cnt is padded to flash.bin automatically by script,
no need to burn the image mannually, so drop the step.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To avoid hardcoded offset when adding u-boot.cnt to flash.bin, we use
flexible offset which is calculated based on the size of the container
image generated int the first stage. And pad u-boot.cnt at 1KB
alignment.
So add code to get the offset when SPL loading u-boot.cnt.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Import i.MX8MM pin func from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Import i.MX8MM dtsi from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Because we need to get cpu freq in print_cpuinfo at very early stage,
so we need to make sure the ccm be probed.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When DM_MMC enabled, the USDHC index in U-Boot is the USDHC port.
To directly return devno, we could avoid add board specific code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Introduce clk implementation for i.MX8MM, including pll configuration,
ccm configuration. Mostly will be done clk dm driver,
but such as DRAM part, we still use non clk dm driver, because we
have limited sram.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To i.MX8MM SCTR clock is disabled by ROM, so before timer init
need to enable it.
To i.MX8MQ, it does not hurt the clock is enabled again.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Set trustzone region 0 to allow both non-secure and secure access
when trust zone is enabled. We found USB controller fails to access
DDR if the default region 0 is secure access only.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE
memory from its settings. So ARM speculative prefetch in u-boot may access
that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory
is set to secure access, then the speculative prefetch will fail and cause
various memory issue in u-boot.
The fail address register and int_status register in trustzone has logged
that speculative access from u-boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and register layout change.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There is no HDMI on i.MX8MM, so we need to remove HDMI entry, then
we could not reuse imximage.cfg, so create a new one.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
With CONFIG_SPL_OF_CONTROL, the device tree will be padded to
end of the u-boot-spl-nodtb.bin, however we also put
the ddr firmware file to this location, so need to adapt
the code with SPL OF and align to 4 bytes to ease copy firmware.
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The loader for the DDR firmware in drivers/ddr/imx/imx8m/helper.c uses a
4-byte-aligned address to load the firmware. In cases where OF is
enabled in SPL the dtb will be appended to the SPL binary and can result
in a binary that is not aligned correctly. If OF is not enabled in SPL,
`_end` is already aligned correctly, but this patch does not hurt.
To ensure the correct alignment we use dd to create a temporary file
u-boot-spl-pad.bin with the correct padding.
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fix the FIT image metadata for i.MX8 to result in the intended boot
order (SPL -> ATF -> U-Boot).
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Use BUILD_TARGET to automatically build "u-boot-with-spl.imx" on MX6
targets with SPL.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Similar to "spl_sd.cfg", this patch introduces "spl_qspi.cfg" so that
all i.MX6 based boards can use it, when they use SPL and QSPI boot
mode.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
This patch adds the missing boot mode detection for QSPI boot on
i.MX6UL/ULL. Without it, booting with SPL from QSPI NOR does not work.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Since recent splash changes common code for splashscreen logo
should be used instead of adding duplicated code under board
directories. mx6ul_9x9_evk and mx6ul_14x14_evk configurations
used old board specific logo code and do not link, fix them.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
The default CSF_SIZE defined in Kconfig is too high and SPL cannot
fit into the OCRAM in certain cases.
The CSF cannot achieve 0x2000 length when using RSA 4K key which is
the largest key size supported by HABv4.
According to AN12056 "Encrypted Boot on HABv4 and CAAM Enabled Devices"
it's recommended to pad CSF binary to 0x2000 and append DEK blob to
deploy encrypted boot images.
As the maximum DEK blob size is 0x58 we can reduce CSF_SIZE to 0x2060
which should cover both CSF and DEK blob length.
Update default_image.c and image.c to align with this change and avoid
a U-Boot proper authentication failure in HAB closed devices:
Authenticate image from DDR location 0x877fffc0...
bad magic magic=0x32 length=0x6131 version=0x38
bad length magic=0x32 length=0x6131 version=0x38
bad version magic=0x32 length=0x6131 version=0x38
spl: ERROR: image authentication fail
Fixes: 96d27fb218 (Revert "habv4: tools: Avoid hardcoded CSF size for SPL targets")
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Add support for the reset controller that's used on the i.MX7D
and i.MX8MQ. This will be needed to be able to assert the PCIe
reset pins. Bindings taken from Linux, driver implementation
mostly taken from Linux and adjusted to U-Boot infrastructure.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add support for the power domain controller that's used on the
i.MX8MQ. This will be needed to be able to power on the PCIe
controller. Bindings taken from Linux, driver implementation
taken from the i.MX8 power domain controller and adjusted for
the i.MX8M SoC.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
doc/README.mxs no longer exists. It has been renamed doc/imx/common/mxs.txt,
so fix the mx28evk README accordingly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
After this patch the mxs_gpio.c DM/DTS driver can be used at early SPL to
read states of gpio pins (and for example alter the boot flow).
It was necessary to adjust its name to 'fsl_imx_2{38}_gpio' to match
requirements for SPL_OF_PLATDATA usage.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change replaces printf() with debug() for the notification about
commands timeouts.
This is done on purpose (also other drivers use such approach - dw_mmc.c,
mvebu_mmc.c), as the mmc core code (mmc.c) uses timeouts to assess if one
is using sd card or eMMC device.
In such situation timeout is a some kind of a "normal" behavior and there
shall not be any output to the console.
There is no impact on boot time for boards using this driver (even in SPL)
when two extra timeouts are returned (no SD card present, only eMMC
available).
Boot time tested with grabserial:
sudo grabserial -b 115200 -d /dev/ttyUSB1 -e 30 -t -m "^U-Boot SPL*"
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch converts the mxsmmc driver to support DM/DTS.
Moreover, it is also possible to use it in early SPL with
SPL_OF_PLATDATA enabled.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After this patch the mxs_spi.c DM/DTS driver can be used at early SPL to
read payload from SPI-NOR memories.
It was necessary to adjust its name to 'fsl_imx_2{38}_spi' to match
requirements for SPL_OF_PLATDATA usage.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Without this change the DM/DTS version of mxs_spi driver doesn't reset the
SPI IP block in probe.
As a result this driver (when used solely on U-Boot proper) relies on reset
performed by mxs spi driver in SPL.
In the use case where eMMC is used in SPL as a boot primary device, the
mxs_reset_block() is not called at all and DM/DTS aware SPI driver in
U-Boot proper is malfunctioning.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change initializes proper member of struct driver -
platdata_auto_alloc_size instead of priv_auto_alloc_size, which is setup
twice.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After this change it is possible to use imx28-<board>-u-boot.dtsi with
the imx28-u-boot.dtsi explicitly included without breaking setup from
imx28-<board>.dts file.
The problem is that the imx28.dtsi included in a wrong place overrides the
changes made in imx28-<board>.dts. As a result some devices are "disabled"
in the final DTB.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change tries to fix the following problem:
- The board boots (to be more precise - ROM loads SPL) from a slow SPI-NOR
memory.
As a result the spl_boot_device() will return SPI-NOR as a boot device
(which is correct).
- The problem is that in 'falcon boot' the eMMC is used as a boot medium to
load kernel from its partition.
Calling spl_boot_device() will break things as it returns SPI-NOR device.
To fix this issue the new CONFIG_SPL_FORCE_MMC_BOOT Kconfig flag is
introduced to handle this special use case. By default it is not defined,
so there is no change in the legacy code flow.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The get_board_id() function was using the old gpio_* compatibility layer
to read HW and SW ID numbers encoded on the PCB board.
After this change the new dm_gpio* API is used for this purpose.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After this change the display5's emergency gpio use dm_gpio* functions
instead of legacy ones (gpio*) to read its state.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit updates the display5_factory_defconfig file after the switch
to DM/DTS for this board.
Moreover, the VID and PID for SPL running SDP gadget have been updated to
allow seamless work with 'uuu' utility from NXP (the imx_usb doesn't work
properly after embedding the u-boot proper into fitImage - problem with IVT
embedding in FIT).
Example to use 'uuu' session:
cat << EOF > display5_recovery.lst
uuu_version 1.2.135
SDP: boot -f /srv/tftp/SPL
SDPU: write -f /srv/tftp/u-boot-dtb.img -addr 0x10000000
SDPU: jump -addr 0x10000000
SDPU: done
EOF
sudo ./uuu/uuu display5_recovery.lst
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The common.c file content can be safely moved to spl.c file after
performing the DM/DTS conversion for the U-Boot proper.
It contains the non DM/DTS setup code, which now is only used by SPL.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit enables support for CONFIG_WDT in the U-Boot proper. Moreover,
the SYSRESET_WATCHDOG driver is used to support 'reset' command.
As SPL is not yet ready for DM conversion, the CONFIG_HW_WATCHDOG is
enabled for it. This allows the legacy SPL code to work properly.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The DM/DTS support for SPI is disabled on purpose for SPL, as it is not
supported as of time of this conversion.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After this commit the display5 device would use I2C driver supporting
driver model (DM_I2C).
The 'i2c' and 'eeprom' commands now use DM I2C drivers and initialize
on-bus devices according to device tree description.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change fixes issue with building display5 "factory" U-Boot variant
when the display5 board gains DM/DTS support.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This code uses HW difference on the USB_RESET pin (added PULL UP resistor
on the L333 rev) to distinguish between two BK4 HW revisions.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add Falcon mode support, which allows the SPL to load and
jump to the Linux kernel directly, without the need of loading
U-Boot proper.
CONFIG_SPL_OS_BOOT=y needs to be passed in the defconfig
in order to use Falcon mode.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
We should use a common script to allow booting the U-Boot console as
fallback so we ended using a 'default_boot' and 'base_boot'
environment scripts to accomplish that.
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Allow enable_ipu_clock() to be built for SPL code. This is done
in preparation for configuring the NoC registers on i.MX6QP in SPL.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.
Running "saveenv" causes U-Boot to hang because of this overlap.
Fix this problem by increasing the CONFIG_ENV_OFFSET size.
Also, in order to prevent this same problem in the future, use
CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time.
CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare
CONFIG_ENV_OFFSET with its direct value instead.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Default value is too high and it covers the worst case. SPL for
imx6dl_mamoj becomes too big and cannot fit into the OCRAM, but CSF size
can be reduced.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Breno Lima <breno.lima@nxp.com>
This syncs all baseboard specific defconfig using the
pico-imx7d_defconfig as base. It changes:
- pico-dwarf-imx7d_defconfig
- pico-hobbit-imx7d_defconfig
- pico-nymph-imx7d_defconfig
- pico-pi-imx7d_defconfig
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Remove CONFIG_SPL_DRIVERS_MISC_SUPPORT since it is already defined
in include/configs/mx6_common.h for SPL builds. When this option
is in defconfig, we get build warnings (or errors when building
with -Werror).
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add the TechNexion's logo from their internal U-Boot tree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
When CONFIG_SPL_OS_BOOT is selected, it is still convenient to be able
to escape from Falcon mode and boot to U-Boot proper.
Add a mechanism that allows booting in U-Boot proper when the
key 'c' is entered on console at boot time.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Improve the README by adding instructions on how to boot using
Falcon mode, which allows the SPL to load the kernel directly,
without using U-Boot proper.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This add the boot menu option for the NYMPH baseboard as well as a
specific config file for users which wish to use it as a pre-defined
board.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This add the boot menu option for the DWARF baseboard as well as a
specific config file for users which wish to use it as a pre-defined
board.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Update pico-hobbit-imx7d_defconfig using pico-imx7d_defconfig as base
to fix device tree file generation. With this all pico-imx7d are
creating u-boot-dtb.img files.
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
When CONFIG_SPL_OS_BOOT is selected, it is still convenient to be able
to escape from Falcon mode and boot to U-Boot proper.
Add a mechanism that allows booting in U-Boot proper when the
key 'c' is entered on console at boot time.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Sync the Falcon mode instructions with the ones fro pico-imx7d.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Add support for the VXT VL050-8048NT-C01 panel connected through
the 24 bit parallel LCDIF interface.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.
Running "saveenv" causes U-Boot to hang because of this overlap.
Fix this problem by increasing the CONFIG_ENV_OFFSET size.
Also, in order to prevent this same problem in the future, use
CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time.
CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare
CONFIG_ENV_OFFSET with its direct value instead.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This add the boot menu option for the DWARF baseboard as well as a
specific config file for users which wish to use it as a pre-defined
board.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Currently it's not possible to authenticate the U-Boot proper of
mx6ul_14x14_evk_defconfig target:
Authenticate image from DDR location 0x877fffc0...
bad magic magic=0x0 length=0x00 version=0x3
bad length magic=0x0 length=0x00 version=0x3
bad version magic=0x0 length=0x00 version=0x3
spl: ERROR: image authentication fail
Commit 0633e13478 ("imx: hab: Increase CSF_SIZE for i.MX6 and
i.MX7 devices") has increased CSF_SIZE to avoid a possible issue
when booting encrypted boot images.
Commit d21bd69b6e ("tools: mkimage: add firmware-ivt image type
for HAB verification") is hardcoding the CSF and IVT sizes, the
new CSF size is not being considered and u-boot-ivt.img fails to
boot.
Avoid hardcoded CSF and IVT size to fix this issue.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add sc_pm_is_partition_started to check whether a partition
has been started. This will be used to detect M4 partition booted up or
not, then we could choose which dtb to use. If M4 is up, we need
use dtb, such as imx8qm-mek-rpmsg.dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add OP-TEE device tree node for Linux according to args passed from ATF.
If ATF has been built with OP-TEE running, boot_pointer[1] will indicate
that.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On i.MX8QM, sid is programmable, so we could program sid according the
value encoded in device tree.
This patch support legacy bindings which are still being used by XEN
and new bindings used by Linux Kernel.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Enable CONFIG_OF_SYSTEM_SETUP to let U-Boot could disable
device tree nodes that could not be used by Linux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When resource is not assigned to non-secure Linux, if linux continue
to use the node, linux may crash or hang. So need to set the node
status to disabled for not owned resources.
The resource id is in the power-domains property in device tree,
so parse the power-domains property to get the resource id and
use scfw api to check whether it is owned by current partition.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Since SCU MU driver has been bound in dm_init, so we don't need to
bind it again. Just replace by using uclass function to probe it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Because FIT could not be used for AHAB secure boot on i.MX8,
so switch to use container image that could let SPL verify
ATF and U-Boot with AHAB.
Enable HUSH_PARSER in defconfig to make run netboot could work.
Note: The AHAB related code has not been added.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Because FIT could not be used for AHAB secure boot on i.MX8,
so switch to use container image that could let SPL verify
ATF and U-Boot with AHAB.
Note: The AHAB related code has not been added.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To support SPL loading container file, add a new Makefile target,
and introduce a new Kconfig file to source the cfg file which
will be parsed by mkimage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add parsing i.MX8 Container file support, this is to let
SPL could load images in a container file to destination address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The first stage of flash.bin is larger than 584 * 512, so when
writting u-boot.itb, some data will be override. Enlarge the
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to fix boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The changes were added by following patch:
commit <9002e735e717> ("imx: mx6sabresd: fix boot hang with video")
commit <f45ec8fcfb86> ("imx6: dts: add 'u-boot, dm-pre-reloc' to soc and ipu nodes")
Let's move the U-Boot specific change to imx6qdl-u-boot.dtsi
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Since commit 6e1f4d2652 ("arm: imx-common: add SECURE_BOOT option
to Kconfig") the SECURE_BOOT option is selected through Kconfig.
Cleanup comments in code to align with this change.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
In case CONFIG_SECURE_BOOT is enabled we need to limit the SPL size to
avoid a possible HAB failure event:
--------- HAB Event 1 -----------------
event data:
0xdb 0x00 0x14 0x42 0x33 0x22 0x33 0x00
0x00 0x00 0x00 0x0f 0x00 0x90 0x70 0x00
0x00 0x01 0x10 0x00
STS = HAB_FAILURE (0x33)
RSN = HAB_INV_ADDRESS (0x22)
CTX = HAB_CTX_TARGET (0x33)
ENG = HAB_ENG_ANY (0x00)
As explained in Commit 23612534fe ("spl: imx6: Provide a SPL_SIZE_LIMIT
default") the i.MX6 SPL size limit is 68KB.
The ROM code is copying the image size defined in boot data to its
respective load address, in case we exceed the OCRAM free region a
HAB invalid address failure event is generated.
The maximum CSF size is defined in CONFIG_CSF_SIZE, reduce SPL size
limit based on this configuration.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Move CONFIG_CSF_SIZE to Kconfig and define default value as 0x4000.
mx8mqevk requires 0x2000 add this configuration in imx8mq_evk_defconfig
file.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Currently the SPL binary is 67 kB, which leaves only 1 kB of free
internal RAM space.
The following options can be safely removed to save some precious
SPL space:
- CONFIG_SPL_FS_EXT4: u-boot-dtb.img is stored in raw sector via dd
command (at offset 69 kB)
- CONFIG_SPL_I2C_SUPPORT: I2C is not used during SPL
- CONFIG_SPL_OS_BOOT: no need to make Falcon mode supported
by default
After this change the SPL binary size gets down to 51 kB.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
On i.MX7ULP B0, there is change in NIC clock dividers architecture.
On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but
on B0 they are parallel with NIC1 DIV. So now the dividers are independent.
This patch modifies the scg_nic_get_rate function according to this change.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
The normal target frequency for ULP A7 core is 500Mhz, but now ROM
set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider
set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU
is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28)
to workaround the problem. The correct fix should let GPU handle the
clock rate in kernel.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The num/denom is a float value, but in the calculation it is convert
to integer 0, and cause the result wrong.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Wrong I2c driver configuration name is used in codes, so I2c driver is
not built. Correct it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Since many drivers need this CONFIG_MX7ULP to distiguish the settings
for i.MX7ULP only. Add this entry to cpu's kconfig.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The offset for FRAC and the mask for PCD are not correct.
If we set FRAC, we can't get the right frequency. Fix them
to correct value.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The board will reboot if A7 core enter mem mode by rtc, then M4 core
enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
to fix this issue.
Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access
it. So check the CPU rev and not apply the settings for B0.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Since the SD3.0 kernel driver needs M4 image support, this causes
problem for usb boot booting into kernel. To decouple the relationship,
we modify the FDT file in u-boot to disable SD3.0.
So the kernel won't depend on M4 image.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add CONFIG_DM_GPIO to all defconfigs whose board is
nitrogen6x.
mx6qsabrelite_defconfig
nitrogen6dl2g_defconfig
nitrogen6dl_defconfig
nitrogen6q2g_defconfig
nitrogen6q_defconfig
nitrogen6s1g_defconfig
This is in preparation for adding CONFIG_DM_SPI.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
This prevents messages like
gpio@20a0000: get_value: error: gpio GPIO2_2 not reserved
when CONFIG_DM_GPIO is enabled.
Also, when CONFIG_DM_GPIO is enabled, checkboard is too
early to use gpio_get_value, so read it directly on failure.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Add DM_MMC to all defconfigs whose board is
nitrogen6x.
mx6qsabrelite_defconfig
nitrogen6dl2g_defconfig
nitrogen6dl_defconfig
nitrogen6q2g_defconfig
nitrogen6q_defconfig
nitrogen6s1g_defconfig
This commit is adding multiple configs, but
seems to be the minimum change to not lose features
and still compile fine.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Previously the SPL size on all iMX6 platforms was restricted to 68KB
because the OCRAM size on iMX6SL/DL parts is only 128KB. However, the
other iMX6 variants have 256KB of OCRAM. Add an option
CONFIG_MX6_OCRAM_256KB which allows using the full size on boards which
don't need to support the SL/DL variants. This allows for an SPL size of
196KB, which makes it much easier to use configurations such as SPL with
driver model and FDT control.
Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Tested-by: Adam Ford <aford173@gmail.com> #imx6q_logic
There is no need to use HAB for FIT signature validation when
SPL_FIT_SIGNATURE is also enabled, as that will be validated via the
normal U-Boot signed FIT image flow.
This allows having SPL validated by HAB and the payloads to follow
being validated with FIT signatures only.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Toradex Apalis iMX6 modules are available in the iMX6D and iMX6Q
variants, which are quite similar and already managed via only one
dtb in u-boot (imx6-apalis.dtb). Select MX6Q via Kconfig by default in
order to automatically enable the HAS_CAAM and MX6_SMP features.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Commit e37ac717d7 ("Convert to use fsl_esdhc_imx for i.MX platforms")
converted FSL_ESDHC to FSL_ESDHC_IMX, but the config check for
apalis_imx6 wasn't updated accordantly.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
The gpio command currently uses equal bank names "GPIO0_"
for all existing gpio banks, i. e.:
U-Boot# gpio status -a
Bank GPIO0_:
GPIO0_0: input: 0 [ ]
GPIO0_1: input: 0 [ ]
...
Bank GPIO0_:
GPIO0_0: input: 0 [ ]
GPIO0_1: input: 0 [ ]
...
So the command is broken, it is not possible to address
a desired bank. Add gpio aliases to fix this.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
i.MX7 and i.MX8M use mxc uart driver, so let's make the SoC could
use MXC_UART kconfig.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Add missed break for HDMI entry.
And moving FIT parsing earlier, because it does not have parameter,
it will not runs into CFG_REG_SIZE.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
fdtdec_get_addr_size could not parse addr/size correctly is
using address-cells 2 and size-cells 2 on an ARM32 SoC.
So switch to use devfdt_get_addr_size_index.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To support DM_VIDEO,
Add display node for lcdif
Drop board iomuxc settings.
Enable DM_VIDEO
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
When booting SPL on the board, met boot failure:
"
Trying to boot from MMC2
MMC Device 1 not found
spl: could not find mmc device 1. error: -19
SPL: failed to boot from all boot devices
"
Let's register the two mmc controllers in SPL stage to
avoid boot failure.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add i.MX6ULZ board support. the i.MX6ULZ is SW compatible
with i.MX6ULL. so most code of i.MX6ULL can be reused
by i.MX6ULZ.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Import kernel dts for i.MX6ULZ from
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Sync kernel dts for i.MX6ULL from
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Sync kernel dts for i.MX6UL from
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
A large number of changes have happened upstream since our last sync
which was to 375506d. The reason to do the upgrade at this point is for
improved Python 3 support.
As part of this upgrade we need to update moveconfig.py and
genboardscfg.py the current API. This is:
- Change "kconfiglib.Config" calls to "kconfiglib.Kconfig"
- Change get_symbol() calls to syms.get().
- Change get_value() to str_value.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Convert this tool to requiring Python 3. The bulk of this is done with
the 2to3 tool In addition, we need to use the '//' operator to have our
division result return an int rather than a float and ensure that we use
UTF-8 when reading/writing files.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add virtual defconfig for Zynq architecture using of_board dtb.
This defconfig should become generic config for all Zynq boards.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add virtual defconfig for ZynqMP architecture using of_board dtb.
This defconfig should become generic config for all ZynqMP boards.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Modify the configuration naming to be generic to xilinx rather than
specific to Versal. The offset value is different for Zynq and ZynqMP
to avoid overlapping with FSBL.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
With new mailbox driver PMUFW configuration object can be loaded via the
same interface and there is no need to have pmu_ipc.c completely.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
U-Boot running in EL3 can't use SMC that's why there is a need to talk to
PMUFW directly via mailbox. The same logic is applied to all functions
which need to talk to PMUFW that's why move this logic to separate function
to avoid code duplication.
Also SMC request ID can be composed from PM_SIP_SVC offset that's why
ZYNQMP_SIP_SVC_GET_API_VERSION macro can be removed completely.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Probe ZynqMP firmware driver on the board initialization phase and
ensure that firmware is in place to continue execution. The probing is
done on board_init so it can be used for both SPL and U-Boot proper.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
New firmware header to place firmware specific macro and function
declarations. The patch also moves the macros defining PM operations as
well as some helper macros.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Implements the function to get PMU Firmware version using the mailbox
driver or smc call based on if running SPL or not. Additionally gets
version as part of the ZynqMP Firmware driver probing
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynqmp-power driver for ZynqMP to handle the communication with the PMU
firmware. Firmware driver just probes subnodes and power driver handles
communication with PMU using the IPI mailbox driver.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP mailbox driver implementing IPI communication with PMU. This would
allow U-Boot SPL to communicate with PMUFW to request privileged
operations.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The following patch allows the mailbox node in DT to host subnodes with
mailbox definitions. If the client phandle to the mailbox is not the
mailbox driver node, just checks parents as well.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There were several changes in past in this file without removing headers
(watchdog cleanup, soft reset, etc). That's why remove additional useless
headers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Setup initrd_high and fdt_high to be placed in lowmem space for kernel to
be able to reach it. Values are setup at run time to ensure that the same
setting can be used on different memory setup. Do this setting only when
variables are not
Similar run time detection was done for Zynqmp and Versal.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The whole cache code needs to be redesign to read information about cache
from DT instead of macro selection. Enable caches by default because
systems have caches on by default for Linux.
Also enable CMD_CACHE to be able to disable cache if there is any issue.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no reason to use private code for standard bootm command.
Current implementation is also broken and don't support image relocation
properly. Switching to generic bootm implementation is fixing these issues.
cmdline and bdt bootm subcommands are returning -1 because they are not
implemented.
Similar change was done long time ago by for example commit 2bb5b63879
("MIPS: bootm: rework and fix broken bootm code")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch_lmb_reserve() protects U-Boot relocated code with stack not to be used
for image relocation.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Microblaze as Arm is using multiple memory banks which are read from DT
that's why there is a need to initialized LMB based on bd->bi_dram[].
Without this fix memory base/size is all the time 0 and image relocation is
not possible.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
All boards are using the same prompt that's why add it as default value to
Kconfig to simplify defconfigs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
All boards are using the same prompt that's why add it as default value to
Kconfig to simplify defconfigs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CONFIG_SYS_BOOT_RAMDISK_HIGH is already defined in
arch/arm/include/asm/config.h:10:#define CONFIG_SYS_BOOT_RAMDISK_HIGH
that's why there is no reason to define it again in board file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Similar SCs but different wiring.
- dc_i2c is connected to X-PRC cards that's why label is required to have
an option to hook up some devices.
- Exactly identify i2c devices on x-prc boards.
In case of missing i2c connection devices won't be accessible.
- USB 0 should be device mode with super speed.
- USB 1 should be host mode.
- Fix i2c mux reset pin entry - commented, not verified.
- Fix i2c1 eeprom compatible string - it is an ST 128Kbit device.
Need to use atmel fallback.
- Fix si570 I2C slave address and add corresponding part numbers.
- Enable AMS for system monitoring.
- phy reset property should be commented because it will throw a
warning dump when called from context that can sleep.
No support for phys property (zynqmp phy driver) with SGMII.
Add is-internal-pcspma property required by uboot.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
This patch assings the phynode pointer to the phydev node as it is needed
later in the corresponding phy driver to read phy properties from DT.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixes zynq_gpio_direction() to call driver specific
zynq_gpio_set_value function rather than top level gpio_set_value.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The PSCI_RESET and EXPERT are not needed for mini configurations so remove
them to save space.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds default offset & sector size values for environment
variables to save in qspi/ospi flash for versal.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Phy setup should be done before dwc3 soft core reset as it is done
in linux & this fixes unreliable detection of usb cable on host side.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Devicetree bindings are already specified in Linux kernel documentation.
Instead of maintaining same dt bindings in U-Boot doc specify path to dt
bindings in Linux kernel & documenting specific changes that are in U-Boot.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The zynq_sdhci drivers depends on DM_MMC in Kconfig so no need to check for
DM_MMC in the driver so this patch removes it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change has been done across the whole tree only zynqmp-mini-qspi hasn't
been fixed.
Origin changed done by commit ffd4c7c2ec
("dts: switch spi-flash to jedec, spi-nor compatible")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support for gmiitorgmii converter.
This converter sits between the MAC and the external phy
MAC <==> GMII2RGMII <==> RGMII_PHY.
The ethernet driver probes this bridge and this bridge driver
probes real phy driver and invokes the real phy functionalities
as requested. This bridge just needs to be configured based on
real phy negotiated speed and duplex.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
All platforms have been moved to distro boot that's why remove the rest of
configurations to have unified boot flow.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Follow conventions and used {} around variables.
Fixes: 90e97ab31e ("arm: zynq: Define distro boot commnads for qspi, nand and nor")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There are two typos in this command that's why it couldn't work properly.
This bootmode is almost unused from the beggining on this SoC.
Fixes: 90e97ab31e ("arm: zynq: Define distro boot commnads for qspi, nand and nor")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Xilinx Zynq SoC has two sdhci controllers but boot is only possible from
the first one. That's why there is a need to specify controller number.
mmc1 is supposed to be secondary boot device and should be also listed in
distribution boot.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch define init routine for generic phy driver and registers it
using phy_register as this generic phy driver also needs to be relocated
incase of manual reloc.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add zu48dr and zu49dr to the list of zynqmp devices. The zu48dr and zu49dr
are the new RFSoC silicons with id values of 0x7b and 0x7e.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch reduces the console buffer size from 2048 to 1024, thus fixes
OCM overwriting issue.
Differences are in bss section as is shown from output:
xilinx_versal_mini: all -2056 bss -2048 text -8
u-boot: add: 0/0, grow: 0/-3 bytes: 0/-2056 (-2056)
function old new delta
cli_simple_run_command 340 332 -8
static.lastcommand 2049 1025 -1024
console_buffer 2049 1025 -1024
Better would be to use PPU RAM but this change is also aligned with changes
done in ZynqMP mini configurations.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP and Versal is using 2k that's why aligned all platform together to
be able to use the same scripts.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Increase init ram size by 4K such that more stack space will be available
during initialization as the present stackspace is not sufficient if DEBUG
option is enabled and causes system hang. Increasing init ram size provides
sufficient stack space during init even if DEBUG enabled and solves the
hang issue.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This option is disable in Xilinx tree for quite a long time that's why
let's disable it in mainline. If there is anybody who requires this options
then it should be moved to Kconfig first and should be removed from this
config.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds clock driver support for Versal platform. The clock driver
queries and performs clock operations using PLM firmware by communicating
with it using SMC calls.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds new jtag distro boot command to look for bootscript file in
DDR and execute it first incase of jtag bootmode.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch updates scriptaddr value to 512MB as having it at 32MB has high
chance of script corruption incase of bigger kernel.
Be aware that 512MB is used for SPL malloc area that's why images should be
loaded after SPL (the best after u-boot relocation).
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
With the current boot script offset address in qspi is being overlaped
by BOOT.BIN as it is over 90MB with fpga included. So moving the script
offset address to end of flash after "bootenv" mtd partition. Here we
are considering qspi flash size >= 128Mbytes on versal and left
512Kbytes space to save boot.scr script.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds new dfu usb distro boot command to look for bootscript
from dfu-util and runs it.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
This patch adds new jtag distro boot command to look for bootscript file
in DDR and execute it first incase of jtag bootmode.
This patch also updates scriptaddr to 512MB as there is high of script
corruption incase of bigger kernel image.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add simple ZynqMP firmware drive to populate child nodes under
zynqmp_firmware DT node.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch provides an option to enable/disable OCM and TCM memory into MMU
table with corresponding memory attributes.
The same change was done for ZynqMP by commit 189bec47ab
("arm64: zynqmp: Provide a Kconfig option to define OCM and TCM in MMU")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Code reads DT and setup MMU table based on memory node. This will ensure
that only DT needs to be changed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is setting up the initrd_high to as high as possible by leaving
max stack size for u-boot so that bigger rootfs can also be loaded by
u-boot for booting kernel.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is setting up the initrd_high to as high as possible by leaving
max stack size for u-boot so that bigger rootfs can also be loaded by
u-boot for booting kernel.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define board_late_init which performs bootmode detection
and prepares corresponding distro boot commaand sequence.
Also disable it for mini platforms because simply there is no need to have
it enabled.
But also disable it for virtual platform because Qemu is not modelling this
register space that's why travis testing would fail. This configuration
should be reverted when mainline Qemu is updated.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This node is used by qspi driver for supporting qspi boot mode in SPL.
Similar changes have beeen done by commit a9022b017a
("ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodes")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds sdboot command script for reference.
This can be converetd into uboot script using mkimage and
use for booting.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Thsi patch adds qspiboot command script for reference.
This can be converetd into uboot script using mkimage and
use for booting.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define default address via Kconfig. There is no need to change this address
for most of the boards but it is also possible. This one line save a lot of
lines in defconfigs that's why make sense to do it.
The similar change has been done by commit 9340d8fe8b
("sunxi: move CONFIG_SPL_TEXT_BASE from *_defconfig to Kconfig")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Boot from QSPI nor flash.
The at91bootstrap, u-boot, u-boot env redundant, u-boot env,
device tree and kernel will reside in the QSPI nor flash.
The rootfs will reside in the NAND flash.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.
Enable the qspi node together with the SST26VF064B qspi nor flash
memory. Booting from the QSPI NOR flash is now possible.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
- EBI Chip Select Register is now in SFR,
- the pins are set to default values,
- timings are matching MT29F4G08BABWP's nand flash requirements.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
sama5's SFR has at offset 0x04 the DDR Configuration Register,
while sam9x60's SFR contains the EBI Chip Select Register. Add
a union to reconcile both boards.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
add sam9x60ek_mmc_defconfig and for now only supports booting from
sdcard.
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[nicolas.ferre@microchip.com: split patch, add Ethernet controller,
phy and tools]
[claudiu.beznea@microchip.com: add CONFIG_OF_LIBFDT_OVERLAY]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
[tudor.ambarus@microchip.com: Fix number of DRAM banks:
One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Add new board SAM9X60-EK using the ARM926 SAM9X60 SoC.
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
[tudor.ambarus@microchip.com:
- fix number of DRAM banks:
One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks]
- drop SPL related macros
- drop memtest macros
- drop CONFIG_SPI_BOOT, CONFIG_SYS_USE_DATAFLASH related macros
- drop inclusion of asm/arch/at91sam9_smc.h]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Add Ethernet controller to dtsi file and enable it on sam9x60ek
platform connected with rmii.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
add device tree files for sam9x60ek board with below changes.
- Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit)
- Add the reg property for the pinctrl node.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
are used by the board_init_f stage.
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
[prasanthi.chellakumar@microchip.com: fix style/whitespace issues]
Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com>
[nicolas.ferre@microchip.com:
- fix gclk,
- fix pio/pinctrl controller definition and allow to have more
than only PIOA for this SoC,
- removing pinctrl address]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[claudiu.beznea@microchip.com:
- use SAM9X60's compatible for pinctrl
- add drive strength and slew rate options for SDMMC0 pins.]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
[tudor.ambarus@microchip.com:
- u-boot,dm-pre-reloc property in dedicated file,
- fix pit len, starts from 0xFFFFFE40 and it is of len 0x10]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Fixes redefinition of CONFIG_SYS_SPI_U_BOOT_OFFS
This is now a Kconfig
Fixes: e40a9ba6d2d5 ("board: atmel: sama5d2_wlsom1_ek: add qspi support and qspi boot config")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This board has an external oscillator as MCK that does not need driving.
Bypass the driving for the main oscillator in SPL.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Remove 2017 from being printed at boot video console.
This is outdated.
To avoid this situation, remove the year completely.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add node for hlcld for u-boot logo display at boot.
This is compatible with the Precision Design Associates (PDA) TM5000 screen.
Timings are compatible with simple panel from Linux, panel name is
pda_91_00156_a0
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add support for qspi memory on board. Created boot support for QSPI
for both u-boot proper and SPL.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
qspi1 does not have an alias/seq number. This is required for
SPL default SF bus booting for the boards that have this SoC
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add a function in SFR implementation that will open the DDR input
buffers.
This can be called at DRAM initialization time.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip
WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
With FSP2 we use MTRRs in U-Boot proper even though the 32-bit init
happens in TPL. Enable this, using a variable to try to make the
conditions more palatable.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need this driver very early in boot and it adds code size. Drop
it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Normally U-Boot handles MTRRs through an add/commit process which
overwrites all MTRRs. But in very early boot it is not desirable to clear
the existing MTRRs since they may be in use and it can cause a hang.
Add a new mtrr_set_next_var() function which sets up the next available
MTRR to the required region.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: pass 'type' to set_var_mtrr() in mtrr_set_next_var()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Move the code that actually sets up the MTRR into another function so it
can be used elsewhere in the file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present these uclasses assumes that they are used with a device tree.
Update them to support of-platdata as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove inclusion of <asm/test.h> in pci_sandbox.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This function ise effectively replaced by ofnode_read_pci_addr() which
works with flat tree. Delete it to avoid code duplication.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a few more CPU functions that are common on Intel CPUs. Also add
attribution for the code source.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist();
fix 2 typos in cpu_get_burst_mode_state() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Some MSR registers are defined twice in different parts of the file. Move
them together and remove the duplicates. Also drop some thermal defines
which are not used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These functions are the same on modern Intel CPUs, so use common code to
set them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: return false instead of 0 in cpu_ivybridge_config_tdp_levels();
fix 'muiltiplier' and 'desgn' typos]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Modern Intel CPUs use a standard bus clock value of 100MHz, so put this in
a common file and tidy up the copies.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code appears in a few places, so move it to a common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This parameter is needed by the PCI driver-mode interface but is always
NULL on x86. There are a number of calls to this function so it makes
sense to minimise the parameters.
Adjust the x86 function to omit the first parameter, and introduce stub
functions to handle the conversion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present this hedaer is only available on x86. To allow sandbox to use
it for testing, move it to a common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot has two distinct phases: before and after relocation. These are
commonly referred to as F (running from Flash) and R (Relocated and
running from RAM). Some drivers want to do different things in these
phases so update the SPL phase function to return a different value for
each.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is currently a decimal value which is not as convenient or
meaningful. Also U-Boot tends to use hex everywhere.
Convert this option to hex and add a comment for the size_check macro.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct the typo in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present there is only one control for this and it is used for both SPL
and TPL. But SPL might have a lot more space than TPL so the extra cost of
a full printf() might be acceptable.
Split the option into two, providing separate SPL and TPL controls. The
TPL setting defaults to the same as SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this is defined in Kconfig but there is a separate one in the
CONFIG whitelist. It looks like these are duplicates.
Rename the non-Kconfig one and remove it from the whitelist.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the 'iod' command differs from 'md' in that it only shows a
single value. It is useful to see a dump of multiple values, particularly
when x86 peripherals contain register sets accessible via I/O ports.
Enhance the command to match md.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct multi-line comment format style]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
If a log statement includes a variable and logging is disabled, this can
generate warnings about unused variables. Add a bit more complexity to the
macros to avoid this for the common case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The image-header currently sets it offset assuming that skip-at-start is
zero. This does not work on x86 where offsets end at 4GB. Add in this
value so that the offset is correct.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Some x86 sections have special offsets which currently result in empty
data being returned from the 'extract' command. Fix this by taking account
of the skip-at-start property.
Add a little more debugging while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
At present this function is not present in the Entry base class so it is
hard to find the documentation for it. Move the docs from the section
class and expand it a little.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the verbose flag only works for the 'build' command. This is
not intended, nor is it useful. Update the code to support the verbose
flag and make use of a command exception handler.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When this UART is used early in boot (before PCI is set up) it is
convenient to store the PCI BDF of the UART so that it can be manually
configured. This is useful when it is used as a debug UART, for example.
Add a new field to hold this information, so that drivers can simply use
the existing platform data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present PCI address transaction is not supported so drivers must
manually read the correct BAR after reading the device tree info. The
ns16550 has a suitable implementation, so move this code into the core
DM support.
Note that there is no live-tree equivalent at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct the unclear comments in test.dts]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present this fails silently which can be confusing since some devices
on the PCI bus may not work correctly. Show a message in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add a '\n' in the PCI autoconfig fail message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
If PCI auto-config runs out of memory, show a few more details to help
diagnose the problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: change %x to %llx to avoid build warnings on some platforms]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Fix these spelling errors the header file and documentation.
Fix a small typo in the PCI documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present U-Boot runs autoconfig in SPL but this is best left to U-Boot
proper. For TPL and SPL we can normally used fixed BARs and save code size
and time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update the debugging info a little to show the result of trying to bind
a PCI device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present PCI emulation devices are not probed before use, since they
used to be children of the device that used them, and children cannot be
probed before their parents.
Now that PCI emulation devices are attached to the root node, we can
simply probe them, and avoid using the internal function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Sandbox pci works using emulation drivers which are currently children of
the pci device:
pci-controller {
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
emul@1f,0 {
compatible = "sandbox,swap-case";
};
};
};
In this case the emulation device is attached to pci device on address
f800 (device 1f, function 0) and provides the swap-case functionality.
However this is not ideal, since every device on a PCI bus has a child
device. This is only really the case for sandbox, but we want to avoid
special-case code for sandbox.
Worse, child devices cannot be probed before their parents. This forces
us to use 'find' rather than 'get' to obtain the emulator device. In fact
the emulator devices are never probed. There is code in
sandbox_pci_emul_post_probe() which tries to track when emulators are
active, but at present this does not work.
A better approach seems to be to add a separate node elsewhere in the
device tree, an 'emulation parent'. This could be given a bogus address
(such as -1) to hide the emulators away from the 'pci' command, but it
seems better to keep it at the root node to avoid such hacks.
Then we can use a phandle to point from the device to the correct
emulator, and only on sandbox. The code to find an emulator does not
interfere with normal pci operation.
Add a new UCLASS_PCI_EMUL_PARENT uclass which allows finding an emulator
given a bus, and finding a bus given an emulator. Update the existing
device trees and the code for finding an emulator.
This brings PCI emulators more into line with I2C.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix 3 typos in the commit message;
encode bus number in the labels of swap_case_emul nodes;
mention commit 4345998ae9 in sandbox_pci_get_emul()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present these functions are stubbed out. For more comprehensive testing
with PCI devices it is useful to be able to fully emulate I/O access. Add
simple implementations for these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: change to use 'const void *' in sandbox_write();
cast 'addr' in read/write macros in arch/sandbox/include/asm/io.h;
remove the unnecessary cast in readq/writeq in nvme.h]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Increase the memory space so we can support the p2sb bus which needs
multiples of 1MB.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot already supports using -D to indicate that it should use the normal
device tree. It is sometimes useful to run with the test device tree, e.g.
when running a test. Add a -T option for this along with some
documentation.
It can be used like this:
/tmp/b/sandbox/u-boot -T -c "ut dm pci_busdev"
(this will use /tmp/b/sandbox/arch/sandbox/dts/test.dtb as the DT)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This function is useful in PCI emulators. More it into the header file to
avoid duplicating it in other drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This method is not used anymore since the bus/device/function of PCI
devices can be obtained from their (parent's per-child) platform data.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some functions and a struct should be marked static since they are not
used outside this file. Update them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These functions are available on x86 but not sandbox. They are useful
shortcuts and clarify the code, so add them to sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Rename this ID to SANDBOX_PCI_SWAP_CASE_EMUL_ID since it is more
descriptive and allows us to add new PCI emulators without any conflict or
confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present running sandbox with valgrind produces some warnings due to the
MMC emulator not filling in all the expected fields. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: use sizeof() instead of hardcoded 16]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present address translation does not work since there is no ranges
property in the spmi nodes. Add empty ranges properties and a little more
logging so that this shows the error:
/tmp/b/sandbox/u-boot -d /tmp/b/sandbox/arch/sandbox/dts/test.dtb \
-c "ut dm spmi_access_peripheral" -L7 -v
...
pm8916_gpio_probe() bad address: returning err=-22
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This should perhaps be a period.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add the ending period and reword the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
We have a 'safe' version of this function but sometimes it is not needed.
Add a normal version too and update a few places that can use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function returns -ENODEV when there is no device. This is
inconsistent with other functions, such as uclass_find_next_device(),
which returns 0.
Update it and tidy up the incorrect '-1' values in the comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present this function is never called when of-platdata is enabled since
we never have a device tree. However, this function is responsible for
copying over the of-platdata, so we must call it. Otherwise the probe()
method would have to be used.
Correct this and fix the sandbox serial driver to not read from the device
tree and try to write to what is read-only platdata on some platforms.
Fixes: 396e343b3d (dm: core: Allow binding a device from a live tree)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present tests that are marked as only for livetree fail when executed
on sandbox_flattree. They cannot actually be executed, but we should not
resport them as 'not found', since this causes errors. Instead, they
should be silently skipped.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present when multiple 'ut dm' commands are executed, all but the first
is run with a flat tree, even if live tree is enabled. This is because the
live tree node pointer is set to NULL and never restored.
This does not affect normal test running, which just runs all the test in
one go, but can be confusing when several individual tests are run during
the same U-Boot run.
Correct this by restoring the pointer.
Fixes: c166c47ba3 (dm: test: Add support for running tests with livetree)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Sometimes devices don't appear and it can be confusing. Add a few notes to
help with this situation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix 2 issues in the doc and include the doc in the index.rst]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Two functions in this file return early for no good reason. Adjust the
code to match the standard DM style of returning 0 at the end of the
function on success.
Oddly enough this save 12 bytes of code size on ARM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The pr_debug() functions do not response to setting the log level and in
fact have their own separate log level. Use U-Boot logging instead.
Perhaps we should make these options redirect to log_debug(), etc.?
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This MSR number is used on most modern Intel processors, so drop the
confusing NHM prefix (which might mean Nehalem).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: drop MSR_IVT_TURBO_RATIO_LIMIT as no code uses it]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add some new MTRRs used by Apollolake as well as a mask for the MTRR
type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The full start-up sequence (TPL->SPL->U-Boot) can be a bit confusing since
each phase has its own 'start' file. Add comments to explain this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we assume that CAR (Cache-as-RAM) is used if HOBs (Hand-off
blocks) are not, since HOBs typically indicate that an FSP is in use, and
FSPs handle the CAR init.
However this is a bit indirect, and for FSP2 machines which use their own
CAR implementation (such as apollolake) but use the FSP for other
functions, the logic is wrong.
To fix this, add a dedicated Kconfig option to indicate when CAR is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix a typo in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The useable RAM is calculated when the RAM is inited. Save this value so
that it can be easily used in U-Boot proper.
Also save a pointer to the hob list so that it is accessible (before
relocation only) in U-Boot proper. This avoids having to scan it in SPL,
for everything U-Boot proper might need later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: guard handoff_arch_save() with IS_ENABLED(CONFIG_USE_HOB)]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When TPL is running, broadwell needs to do different init from SPL. There
is no need for this code to be in the generic x86 SPL file, so move it to
arch_cpu_init().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This image loader works on systems where the flash is directly mapped to
the last part of the 32-bit address space. On recent Intel systems (such
as apollolake) this is not the case.
Reduce the priority of this loader so that another one can override it.
While we are here, rename the loader to BOOT_DEVICE_SPI_MMAP since
BOOT_DEVICE_BOARD is not very descriptive.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use the standard hang() function when booting fails since this implements
the defined U-Boot behaviour for this situation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the x86 pre-DM equivalent of pci_bus_clrset_config32() does not
exist. Add it to simplify PCI init code on x86.
Also add the missing functions to this header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is useful in SPL and TPL to access symbols from binman, such as the
position and size of an entry in the ROM. Collect these symbols together
in the SPL binaries.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add cpu_intel_get_info() to find out the CPU info on modern Intel CPUs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add parameter and return value descriptions]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
With FSP2 the non-volatile storage used by the FSP to init memory can be
split into a fixed piece (determined at compile time) and a variable piece
(determined at run time). Add support for reading the latter.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present these two functions are defined in efi_loader.h but only if
CONFIG_EFI_LOADER is enabled. But these are functions that are useful to
other code, such as that which deals with Intel Handoff Blocks (HOBs).
Move these to the top of the function.
Possibly ascii2unicode() should not be an inline function, since this
might impact code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some of this file can be shared between FSP1 and FSP2. Move it into a
shared file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Some of this file can be shared between FSP1 and FSP2. Move it into a
shared file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Most of the DRAM functionality can be shared between FSP1 and FSP2. Move
it into a shared file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The comments in the FSP code use a different style from the rest of the
x86 code. I am not sure it this is intentional.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix 2 comment style issues]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Update a few #ifdefs to if() to improve build coverage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: recover the codes that got wrongly deleted in dram_init()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Many support functions are common between FSP1 and FSP2. Add a new header
to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove forward declarations in fsp_support.h]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Given these exported function an fsp_ prefix since they are declared in an
fsp.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present this driver is always included in SPL and TPL, if U-Boot proper
enables it. Update the Makefile to provide full control using the existing
Kconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: make the Kconfig help text a little bit clearer]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot is built in three phases: TPL, SPL and U-Boot proper. Sometimes
it is necessary to use different init code depending on the phase. For
example, TPL might do very basic CPU init, SPL might do a little more
and U-Boot proper might bring the CPU up to full speed and enable all
cores.
Add a function which allows easy determination of the current phase being
built.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the bloblist is set up in spl_common_init() which can be called
from spl_early_init(), i.e. before SDRAM is ready. This prevents the
bloblist from being located in SDRAM, which is useful on some platforms
where SRAM is inaccessible after U-Boot relocates (e.g. x86 CAR region).
It doesn't serve much purpose to have the bloblist available early, since
very little is known about the platform then, and the handoff info is
written when SPL is about to jump to U-Boot.
Move the code to board_init_r() to avoid any restrictions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present there is an arch-specific area in the SPL handoff area intended
for use by arch-specific code, but there is no explicit call to fill in
this data. Add a hook for this.
Also use the hook to remove the sandbox-specific test code from
write_spl_handoff().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present these options can be enabled when bloblist is not enabled for
SPL or TPL. This is incorrect as SPL handoff requires bloblist. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't have a console in SPL so it doesn't make sense to check for
Ctrl-C when printing a memory dump. Skip this so that print_buffer() can
be used in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this driver uses the wrong condition for including the code and
drivers in SPL/TPL. Update it so that the code is only included if
DM_SERIAL is enabled for SPL/TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present spi_flash is defined to be spi_nor which is confusing since it
is not possible to find the 'spi_flash' by normal text search. Add a
comment to help with this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Support a new BINMAN_VERBOSE option to the build, to allow passing the
-v flag to binman.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Pass in the toolpath in case binman needs to use tools compiled in the
U-Boot tools/ directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This include file is only used for FSP v1. Avoid including it from
fdt_support.h so we can use the latter with FSP v2.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This header file is the same for FSP v1 and v2, although there may be
some additions to come. Move it into the generic fsp directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This header file is the same for FSP v1 and v2. Move it into the general
fsp directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: move rename of fsp_infoheader.h from previous patch to this one]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This header file is the same for FSP v1 and v2. Move it into the general
fsp directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove inclusion of fsp_hob.h in fsp_support.h]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This header file is the same for FSP v1 and v2. Move it into the general
fsp directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This header file is the same for FSP v1 and v2. Move it into the general
fsp directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This header file is different for each version of FSP. Move it into the
fsp_arch.h header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present fsp_support.h includes fsp_vpd.h which is an FPSv1 concept
(VPD means Vital Product Data). For FSPv2 only UPD (Updatable Product
Data) is used.
To avoid mangling header files, put these two includes in a separate
header which we can adjust as necessary for FSPv2.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This header file is the same for FSP v1 and v2. Move it into the general
fsp directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove forward declarations in fsp_support.h]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Since there is now a new version of the FSP and it is incompatible with
the existing version, move the code into an fsp1 directory. This will
allow us to put FSP v2 code into an fsp2 directory.
Add a Kconfig which defines which version is in use.
Some of the code in this new fsp1/ directory is generic across both FSPv1
and FSPv2. Future patches will address this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The commit
642b80d256 ("net: designware: drop compatible altr, socfpga-stmmac")
breaks designware ethernet for all ARC boards. It removes
"altr, socfpga-stmmac" compatible from "drivers/net/designware.c"
without changing compatible in the boards which use it.
Fix that by adding "snps,arc-dwmac-3.70a" compatible string to
"drivers/net/designware.c" and using it in ARC boards device tree.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
With the patch below applied, host_block_dev structure was switched
to be placed in platdata rather than priv. The command "host info"
must be aligned with this change. Otherwise, we will see "Segmentation
Fault."
Fixes: 8f994c860d ("sandbox: blk: Switch to use platdata_auto_alloc_size for the driver data")
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
These boards don't have a watchdog enabled in SPL, so make sure
CONFIG_SPL_WDT is not enabled.
Fixes: commit 6874cb7220 ("watchdog: Split WDT from SPL_WDT")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The growth of the UEFI sub-system leads to build failures for systems with
strict limits on the U-Boot image size.
CMD_NVEDIT_EFI supports displaying and editing of UEFI variables. The
setting is not needed for booting. Disabling it by default reduces the
size of the U-Boot image by 2 KiB.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This allows our EFI API to create a device path node for NVMe
devices. It adds the necessary device path struct, uses the
nvme namespace accessor to retrieve the id and eui64, and also
provides support for the device path text protocol.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This adds a function which can be used by e.g. EFI to retrieve
the namespace identifier and EUI64. For that it adds the EUI64
to its driver internal namespace structure and copies the EUI64
during namespace identification.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A wrong function name is referred to in a comment of do_env_set_efi().
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This reverts commit 0797f7f0b7.
Tegra specific solution is not required any more as efi core has been
made aware of ram_top with the following commit:
7b78d6438a efi_loader: Reserve unaccessible memory
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
The UEFI spec has this sentence:
"Variables that have runtime access but that are not nonvolatile are
read-only data variables once ExitBootServices() is performed."
At least EDK2 therefore treats variable PlatformLangCodes only as read-only
at runtime. Nowhere do we make this variable read-only in U-Boot.
Do not use variable PlatformLangCodes for testing if the read only
attribute of variables is observed before ExitBootServices().
Fixes: 5a24239c95 ("efi_loader: selftest: enable APPEND_WRITE tests")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Errors should not only be announced as text but should also result in
EFI_ST_FAILURE being returned.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Appending to a non-existent variable must result in an error of type
EFI_NOT_FOUND.
Fixes: 09c76b79a9db ("efi_loader: SetVariable() deleting variables")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
- Assorted TI platform fixes
- Revert the change that broke environment flag validation
- Assorted typo fixes
- Assorted Kconfig dependency fixes
- Other minor bug fixes
This reverts commit 7d4776545b. The
changes here break environment validation and furthermore do not seem to
be required.
Signed-off-by: Tom Rini <trini@konsulko.com>
The SPL device tree is missing the entires for gpio1, uart1, usdhc1 and
usdhc2. This creates the missing imx6q-logicpd-u-boot.dtsi file
which will enable these functions so SPL can properly setup UART, detect
microSD card, and startup.
Fixes: 8f4691e31a ("ARM: imx6q_logic: With SPL_OF_CONTROL enabled,
remove MMC init")
Signed-off-by: Adam Ford <aford173@gmail.com>
Existing debug output is mixed with the function name:
initcall_run_list() initcall: 25263initcall_run_list() (relocated to 425263)
Turn it to:
initcall_run_list() initcall: 25263 (relocated to 425263)
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
At this point we are using part number sub-command to retrieve UUID
of the partition using it's name.
e.g.:
part number mmc $mmcdev system_a system_a_index
part uuid mmc $mmcdev:${system_a_index} system_a_uuid
Since 'part uuid' sub-command expects partition index in hex format and
'part number' returns decimal value, 'part uuid' command will provide
wrong UUID or fail.
Fixes: be683756f6 ("cmd: part: Add 'number' sub-command")
Cc: Dirk Behme <dirk.behme@de.bosch.com>
Reported-by: Pontus Fuchs <pontus.fuchs@se.bosch.com>
Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
To accommodate the growth of u-boot, we need to shift the location of the
secure monitor. Moving it 64kB further.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
On HS devices the access to TRNG is restricted on the non-secure
ARM side, disable the node in DT to prevent firewall violations.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This updates MAINTAINERS and git-mailrc to add me as maintainer for
socfpga.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
*.pyc files contain compiled Python bytecode. 'make mrproper' should remove
them.
Removing *.pyc files helps for instance sometimes when running into an
error "binman: Unknown entry type 'blob' in node '/binman/blob'".
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
This was 269000 bytes but now needs to be grown to 276000 to make room
for the signatures attached to the board configuration data on High
Security devices.
Signed-off-by: Andrew F. Davis <afd@ti.com>
At present this code passes an fdt_addr_t pointer as a u64 pointer which
is not safe, since sizeof(fdt_addr_t) may be 4, e.g. with sandbox. Correct
this to avoid a stack corruption problem.
Fixes: e679d03b08 (core: ofnode: Add ofnode_get_addr_size_index)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct one typo in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This reads the low cell of the PCI address from the wrong cell. Fix it.
Also fix the function that this code came from.
Fixes: 9e51204527 (dm: core: Add operations on device tree references)
Fixes: 4ea5243a3a (fdt: fix fdtdec_get_pci_addr() for CONFIG_PHYS_64BIT)
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is reincarnation of the U-Boot
commit 3469bf4274
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Wed Jan 10 19:40:15 2018 +0200
x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters
after upstream got eventually the Linux kernel
commit e6e094e053af75cbc164e950814d3d084fb1e698
Author: Juergen Gross <jgross@suse.com>
Date: Tue Nov 20 08:25:29 2018 +0100
x86/acpi, x86/boot: Take RSDP address from boot params if available
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When booting through the efi stub, the memory map get's created by
reading the dram bank information. Depending on the version of the RPi4
this information changes. Read the device tree to initialize the dram
bank data structure. This way the kernel is able to access the whole
range of available memory.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
First set of u-boot-atmel fixes for 2019.10 cycle:
This includes only tiny cleanups on env changes related to 2019.10 new
features: removal of duplicate env settings (otherwise there may be
warnings in building..) and a small fix for flashes on Gardena smart
gateway (requires nand bad block tables).
'commit a9221f3ebd ("at91, omap2plus: configs: migrate CONFIG_ENV_ to defconfigs")'
migrated CONFIG_ENV_ macros to defconfigs but did not remove the
identical redefinition of these macros in include/configs/.
Since the duplicated macros have the same value as the ones in defconfigs,
no "redefined" warnings were raised. Remove duplicated macros for all
sama5 and sam9x5ek boards.
While verifying that the removal of the macros from include/configs did
not change the same macros in defconfigs, overwrite the old defconfig by
saving them with the output from "make arch=ARM savedefconfig". This
resulted in the movement of some macros in the defconfig files.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This patch enables the BBT in NAND on the AT91SAM based GARDENA smart
Gateway. This is especially important, since the Linux driver also
enables this option and uses the BBT table pages. Without setting this
option, U-Boot will try to re-use these pages again (e.g. UBI).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Tom Rini <trini@konsulko.com>
This patch restores commit c49d0ac38a ("ARM: dts: rmobile: Increase off-on
delay on the SD Vcc regulator"), which was accidentally dropped during DT
resync in commit 317d13ac63 ("ARM: dts: rmobile: Synchronize Gen3 DTs with
Linux 5.0").
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Fixes: 317d13ac63 ("ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0")
The commit 619f002db8 ("rockchip: make_fit_atf.py: fix loadables property
set error") fixed the double-loading of the primary atf-image, but didn't
take into account that there may be rare atf images with only that main
section present.
Right now this will result in a broken its due to the loadables section not
getting closed correctly, so fix that by adapting the guards around the loop.
The guards now protect against 0 segments when the bl31 binary doesn't
contain any section and 1 segment when only a core atf section is present.
Fixes: 619f002db8 ("rockchip: make_fit_atf.py: fix loadables property set error")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Originally the cpuid var the value gets read into was defined as
u8 cpuid[RK3399_CPUID_LEN];
hence the sizeof(cpuid) would return the correct the correct number
of array elements.
With the move to a separate function cpuid becomes a pointer and
sizeof(cpuid) hence returns the pointer size - 8 in the arm64 case.
We do have the actual id length available as function param so use
it for actual amount of bytes to read.
Fixes: 0482538499 ("rockchip: rk3399: derive ethaddr from cpuid")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
This commit add envtools suppport to CI to verify if there
is no build issues.
Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since commit af95f20 ("env: Create a new file for environment functions"),
a new header file exists.
So, this commit add a missing header file.
Fixes:
include/env.h:158:1: error: unknown type name ‘ulong’; did you mean ‘long’?
ulong env_get_ulong(const char *name, int base, ulong default_val);
^~~~~
long
include/env.h:158:49: error: unknown type name ‘ulong’; did you mean ‘long’?
ulong env_get_ulong(const char *name, int base, ulong default_val);
Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Tested-by: Joris Offouga <offougajoris@gmail.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Since commit d3716dd ("env: Rename the redundancy flags"), the
definitions of ENV_REDUND_OBSOLETE & ENV_REDUND_ACTIVE was moved
to env.h.
Fixes:
tools/env/fw_env.c:122:22: error: ‘ENV_REDUND_ACTIVE’ redeclared as different kind of symbol
static unsigned char ENV_REDUND_ACTIVE = 1;
^~~~~~~~~~~~~~~~~
In file included from tools/env/fw_env.c:13:
include/env.h:63:2: note: previous definition of ‘ENV_REDUND_ACTIVE’ was here
ENV_REDUND_ACTIVE = 1,
^~~~~~~~~~~~~~~~~
tools/env/fw_env.c:127:22: error: ‘ENV_REDUND_OBSOLETE’ redeclared as different kind of symbol
static unsigned char ENV_REDUND_OBSOLETE;
^~~~~~~~~~~~~~~~~~~
In file included from tools/env/fw_env.c:13:
include/env.h:62:2: note: previous definition of ‘ENV_REDUND_OBSOLETE’ was here
ENV_REDUND_OBSOLETE = 0,
Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Tested-by: Joris Offouga <offougajoris@gmail.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
APPEND_WRITE with data length zero is allowable according to the UEFI
specification.
The EDK2 interpretation of no access attributes is attributes = 0. As
the UEFI specification is vague in this respect let's stick to EDK2 here.
Fixes: commit 6d2f27c5fd ("efi_loader: variable: support APPEND_WRITE")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
We always have to return via EFI_EXIT() from EFIAPI functions.
Coverity reported an unreachable line and a resource leak.
Fixes: commit 6d2f27c5fd ("efi_loader: variable: support APPEND_WRITE")
Reported-by: Coverity Scan CID 253575, CID 184095
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Remove outdated TODO for efi_stri_coll(). efi_stri_coll() is already using
the Unicode capitalization table.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Pull request for UEFI sub-system for v2019.10-rc4 (5)
This patch set fixes errors in the UEFI sub-system and adds a function to
compare u16 strings which is prerequisite for further patches.
Currently we may end up with an LCD clock divider that differs from
the HDMI PHY clock divider if we can't exactly match the pixel clock.
Fix this by using DIV_ROUND_UP to calculate the divider. This works
since the PLL is chosen such that the resulting pixel clock is
never higher than the requested pixel clock.
Fixes: 1feed358ed ("sunxi: video: HDMI: Fix clock setup")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Old splash code in cfb_console driver displayed U-Boot version
string by default. Restore this behaviour for DM_VIDEO enabled
configurations.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Fabio Estevam <festevam@gmail.com>
Define "splashimage" variable in the default environment
and enable BMP code. Also configure white on black for
video console.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
After mxc_ipuv3 DM_VIDEO conversion showing splash image
doesn't work. Fix this. Also enable white on black console
configuration as it used to be with cfb_console driver.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
After mxc_ipuv3 DM_VIDEO conversion showing splash image
doesn't work. Fix this. Also enable white on black console
configuration as it used to be with cfb_console driver.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
After mxc_ipuv3 DM_VIDEO conversion board configs with enabled
CONFIG_VIDEO_LOGO do not show splash screen (previosly drawing
splash screen worked via cfb_console driver with CONFIG_VIDEO_LOGO
enabled). Use splash_source library for loading splash images
when CONFIG_SPLASH_SOURCE is selected, otherwise prepare built-in
video logo for drawing.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
New seven test cases for u16_str<n>cmp() are added under Unicode unit test,
which should be executed by "ut unicode" command.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
u16 version of strcmp(): u16_strncmp() works like u16_strcmp() but only
at most n characters (in u16) are compared.
This function will be used in my UEFI secure boot patch.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Now that APPEND_WRITE is supported,
the result check for the only existing test case should be changed to
'todo' to 'error', while two more test cases are added.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
If EFI_VARIABLE_APPEND_WRITE is specified in attributes at
efi_set_variable(), specified data will be appended to the variable's
original value. Attributes other than APPEND_WRITE should not be
modified.
With this patch, APPEND_WRITE test in 'variables' selftest will pass.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
DisconnectController() should never return EFI_NOT_FOUND.
If EFI_DRIVER_BINDING_PROTOCOL.Stop() fails, return EFI_DEVICE_ERROR.
If the driver handle does not expose the EFI_DRIVER_BINDING_PROTOCOL
return EFI_INVALID_PARAMETER.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Sandbox's "host" devices are currently described as UCLASS_ROOT udevice
with DEV_IF_HOST block device. As the current implementation of
efi_device_path doesn't support such a type, any "host" device
on sandbox cannot be seen as a distinct object.
For example,
=> host bind 0 /foo/disk.img
=> efi devices
Scanning disk host0...
Found 1 disks
Device Device Path
================ ====================
0000000015c19970 /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)
0000000015c19d70 /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)
=> efi dh
Handle Protocols
================ ====================
0000000015c19970 Device Path, Device Path To Text, Device Path Utilities, Unicode Collation 2, HII String, HII Database, HII Config Routing
0000000015c19ba0 Driver Binding
0000000015c19c10 Simple Text Output
0000000015c19c80 Simple Text Input, Simple Text Input Ex
0000000015c19d70 Block IO, Device Path, Simple File System
As you can see here, efi_root (0x0000000015c19970) and host0 device
(0x0000000015c19d70) have the same representation of device path.
This is not only inconvenient, but also confusing since two different
efi objects are associated with the same device path and
efi_dp_find_obj() will possibly return a wrong result.
Solution:
Each "host" device should be given an additional device path node
of "vendor device path" to make it distinguishable.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
- Coding style corrections in some RTC drivers.
- Small doc updates.
- Regression fix in part_test_dos()
- Regression fix on TI OMAP WDTs.
- Document deadline for CONFIG_DM migration.
- Switch Travis-CI to "xenial" release.
For many sub-systems we already require the driver model to be used. Yet
there is still a handful of boards that do not have CONFIG_DM enabled.
We should make CONFIG_DM compulsory with release v2020.01
Conversion dates for CONFIG_DM_SPL and CONFIG_DM_TPL are yet to be defined.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
AM335X based beaglebone black target gets reset by DM converted watchdog
if booted from emmc around 60sec. Fixed this by moving driver's private struct
variable initialization at different places in the driver to driver's probe.
Tested on Beaglebone Black.
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Fixes: 7659ea32 ("watchdog: omap_wdt: Convert watchdog driver to use DT and DM")
Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
The README.scrapyard file has been inconsistently updated. While well
intentioned, bad data is worse than no data, and in this case a pointer
to use the history that git provides. Remove the current content and
the script that would update it from time to time as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
The blk_dread() following the mbr allocation reads one block from the
device. This will lead to overflow if block size is greater than the
size of legacy_mbr. Fix this by allocating at least one block size.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
The of-plat.rst file till this change has been using
This is at best misleading as SPL_OF_PLATDATA is always defined when we
want to use this SPL tinification feature (also in U-Boot proper).
As a result the OF_PLATDATA SPL specific code is also compiled in when
U-Boot proper is build.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We need a new STACK in SDRAM instead of SRAM so that the EMMC controller
can work properly. The EMMC/SD controller's master is not able to access
SRAM area, it can only access DRAM area.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
SPL_TEXT_BASE is 0x0 by default, based on the kconfig
definition move in below commit.
"configs: move CONFIG_SPL_TEXT_BASE to Kconfig"
(sha1: f89d6133ee)
So, don't define it explicitly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tinker board needs to mux all the sdmmc gpio and
activate the regulator connected to bank 7. Remove
all the bank that are not in use and mark them as dm,spl
so-that it would initialize at SPL.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
SPL sets up SDRAM while in its board_init_f()
function, it is possible for the stack to move
there before board_init_r() is reached.
So it is required to reserve the stack for SDRAM,
with a proper location and size otherwise any
operations during SPL handoff would leads to failure.
On, this particular context tinker-rk3288 SPL is
failing to launch U-Boot proper on SDRAM due to
lack of stack.
U-Boot SPL 2019.10-rc3-00297-g5ba8b12543 (Sep 12 2019 - 08:50:36 +0530)
Trying to boot from MMC1
spl: mmc init failed with error: -110
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
So, enable SPL_STACK_R_ADDR and it's related-config
items for SDRAM, SPL stack to setup properly.
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
SPL_TEXT_BASE is 0x0 by default, based on the kconfig
definition move in below commit.
"configs: move CONFIG_SPL_TEXT_BASE to Kconfig"
(sha1: f89d6133ee)
So, don't define it explicitly.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Few of the rk3288 boards like tinker, vyasa are using
TPL, SPL bootchain so the dram initialization must needed
during TPL stage. So add proper ifconstruct to satisfy
both TPL, SPL and SPL-only bootchain boards.
This eventually fixing TPL to SPL handoff, otherwise missing
dram initilaztion at TPL stage would leads to SPL hang.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
The initial Vyasa-rk3288 TPL implementation is to reuse the
SPL_TEXT_BASE for TPL and SPL as 0x0 and 0xff704000 respectively.
But the below commit implements the reverse way of using TEXT_BASE's
like 0xff704000 for TPL and 0x0 for SPL and which indeed update
the SPL_TEXT_BASE for vyasa-rk3288 board.
"rockchip: Kconfig: enable TPL support for rk3328"
(sha1: 3f47db0275)
So, fix by dropping the legacy SPL_TEXT_BASE and it will
reassign 0x0 by default based on Kconfig definition.
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
ROCKCHIP_BROM_HELPER is selected as if TPL/SPL ROCKCHIP_BACK_TO_BROM
has been defined, so drop the explicit enablement for vyasa board.
This change is supposed to missed during config move to
other locations, and missed to drop the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
This enables reading the cpuid from e-fuse, and deriving a static
MAC address from it. Without this, the ethernet interface on the
rockpro64 can't be used to boot.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Commit c4e8862308 (mtd: spi: Switch to new SPI NOR framework)
performs switch from previous 'spi_flash' infrastructure without
proper testing/investigations which results in a regressions for
SST26 flash series.
Enable protection ops for SST26 flash series which were
previously enabled by
Commit 3d4fed87a5 (mtd: sf: Add support of sst26wf* flash ICs
protection ops)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Commit c4e8862308 (mtd: spi: Switch to new SPI NOR framework)
performs switch from previous 'spi_flash' infrastructure without
proper testing/investigations which results in a regressions for
SST26 flash series.
Add missing SST26* flash IC protection ops which were introduced
previously by
Commit 3d4fed87a5 (mtd: sf: Add support of sst26wf* flash ICs
protection ops)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
spi_write_then_read, will manage to do the respective
spi_xfer based on the tx_buf, rx_buf so drop the
legacy spi_flash_read/write/cm code.
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for SPI synchronous write followed by read,
this is common interface call from spi-nor to spi drivers.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
MXS_SPI driver now partially converted into driver-model,
so unmark the DEPRECATED option for the same.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
[jagan: update the commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
In case spi_get_bus_and_cs callback is used, spi bus is first probed
then slave devices are probed. To avoid a data abort in soft_spi probe
function, we need to check that (slave != NULL).
If slave is NULL, cs_flags and clk_flags will be initialized with
respectively GPIOD_ACTIVE_LOW and 0.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The prescaler value computation can yield wrong result if given 0x1f at
the beginning: the value is computed to be 0x20, but the maximum value
the register can hold 0x1f, so the actual stored value in this case is
0, which is obviously wrong.
Set the upper bound of the value to 0x1f with the min macro.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add missing PCI range for translating DRAM to bus addresses.
This fixes e.g. PCI NIC interface and allows network to work
in QEMU.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since binutils 2.30 , the resulting U-Boot binary was incorrectly linked
against address 0 instead of text base, fix it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
HS devices use the FIT post processing step to authenticate boot images.
Set the configured boot command to load FIT by default.
Signed-off-by: Andrew F. Davis <afd@ti.com>
API get_ti_sci_handle() is relying on the device-tree node name
to be "dmsc" for probing the ti_sci device. But with the introduction
of debug messages for dmsc, the node name changed to dmsc@44083000.
Because of this ti_sci is never probed cause a boot failure. Instead
of relying on device-tree node name, use the first available firmware
node for probing ti_sci.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The da8xx GPIO driver is available with DM_GPIO support. This
patch enables the CMD_GPIO, CMD_DM, and DM_GPIO and DA8XX_GPIO.
Signed-off-by: Adam Ford <aford173@gmail.com>
The USB was just recently enabled, so it is unlikely anyone is
using it in SPL, so this patch removes it from SPL to further
reduce the SPL code size.
Signed-off-by: Adam Ford <aford173@gmail.com>
The header it littered with #ifdefs and #defines and that appear
to be legacy associations to the older da850-evm and in some cases
obsolete with either Kconfig or DM migrations. This patch removes
these legacy references.
Signed-off-by: Adam Ford <aford173@gmail.com>
Enable driver model for USB, MMC, SPI and SPI_FLASH. Also enable BLK.
This will remove the following compile warnings:
===================== WARNING ======================
This board does not use CONFIG_DM_MMC. Please update
the board to use CONFIG_DM_MMC before the v2019.04 release.
====================================================
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
====================================================
===================== WARNING ======================
This board does not use CONFIG_DM_SPI_FLASH. Please update
the board to use CONFIG_SPI_FLASH before the v2019.07 release.
====================================================
Target was compile tested, build was clean.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Add device tree from Linux for driver model conversion
and enable OF_CONTROL. This will remove the following compile
warning:
==================================================
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument
===================================================
Target was compile tested, build was clean.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
In case dma_ring_reset_quirk is not set the k3_ringacc_ring_reset_dma will
just exit without ring reset. Fix it, by adding ring reset call in case
dma_ring_reset_quirk is not.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Pull request for UEFI sub-system for v2019.10-rc4 (4)
Fixes for the EFI_FILE_PROTOCOL:
* correctly iterate over directories
* correct Unicode conversion of file names
* parameter checks
In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2
Fixes: 36f50b7523 ("armv8: ls1028a: Add other serdes
protocal support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The correct config entry is CONFIG_PCIE_LAYERSCAPE and this
typo results in skipping the fixup of Linux PCIe DT nodes.
Also enable the fixup when Layerscape Gen4 controller driver
is enabled.
Fixes: 4da0e52c9d (armv8: fsl-layerscape: fix config dependency
for layerscape pci code)
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add SerDes1 protocol 14 in the list of supported protocols.
This configuration enables one high-speed 100G port and PCIe x4.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The code that generates the compatible property concatenates the
ethernet phy id and clause-compatible information without
separating them with a comma, resulting into no ethernet phy driver
getting loaded by Linux kernel.
Suffix phy_id_compatible_str with comma to fix this
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
lx2160a rev1 and rev2 SoC has different pcie controller.
The pcie controller device tree node fields "compatible"
and registers names needs to be updated accordingly
This change in device tree is handled as part of
fdt fixups. These changes would only be applied
if the soc revision is not rev1.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
By default, i2c input clock is programmed at
platform clk / 2 in u-boot, but this is not
correct for all the platforms,
Update I2C clock divider's default values as per
SoC (LS1012A, LS1028A, LX2160A and LS1088A).
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The SP805-WDT module on LS1028A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the device-tree structure describing the MUX in board dts.
QDS board has an on-board RGMII PHY and 4 slots for extension cards.
All these can be accessed over MDIO through a MDIO MUX controlled
over I2C.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
During boot, u-boot reads MC, DPL, DPC firmware from SD card
and copies to DDR. Update DDR addresses to which these firmwares
are copied as per memory map of these firmwares on SD-card
so that isolation between the regions of various firmwares
is maintained to avoid geting overwritten.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add eMMC hs200 mode for ls1028a, ls1012a, lx2160a.
This increases eMMC performance.
Tuning procedure is currently not supported.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
NXP fsl_esdhc controller supports two reference clocks:
platform clock and peripheral clock
Peripheral clock can provide higher clock frequency
which is required to be used for tuning of SD UHS mode
and eMMC HS200/HS400 modes.
Peripheral clock is enabled by default by defining config
option FSL_ESDHC_USE_PERIPHERAL_CLK if eMMC HS200/HS400 modes
are supported.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
- add idbloader.img target for rockchip tpl+spl;
- usb ehci/ohci: go on process if clock driver don't have clk_enable();
- remove clk_enable() for rockchip clock drivers;
- add boot order for rockpro64
We do not support volume label changes. No parameter checks are needed
here.
When the info for as file is changed the buffer must always contain a file
name.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Many Rockchip platforms require the same u-boot deploy procedure
when TPL and SPL both enabled.
The following examples are taken from doc/README.rockchip
and board/theobroma-systems/lion_rk3368/README:
RK3288:
./tools/mkimage -n rk3288 -T rksd -d ./tpl/u-boot-tpl.bin out
cat ./spl/u-boot-spl-dtb.bin >> out
sudo dd if=out of=/dev/mmcblk0 seek=64
RK3328:
./tools/mkimage -n rk3328 -T rksd -d ./tpl/u-boot-tpl.bin idbloader.img
cat ./spl/u-boot-spl.bin >> idbloader.img
sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64
RK3368:
./tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img
cat spl/u-boot-spl-dtb.bin >> spl-3368.img
dd if=spl-3368.img of=/dev/sdb seek=64
RK3399:
./tools/mkimage -n rk3399 -T rksd -d ./tpl/u-boot-tpl-dtb.bin out
cat ./spl/u-boot-spl-dtb.bin >> out
sudo dd if=out of=/dev/sdc seek=64
Here, we introduce generic idbloader.img target
which is the TPL image followed by the SPL binary.
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Use obj-$(config) instead of #ifdef $config to make the code looks
clean, and move the misc_init for U-Boot proper only.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The rk3188/Makefile already depends on !TPL_BUILD, so no need to add
this again in parent Makefile, remove it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk()
do not return fail if ret value is '-ENOSYS'
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk()
do not return fail if ret value is '-ENOSYS'
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
commit 65c1f9820c8f79f "usb: Add nonblock argument to submit_int_msg"
breaks the musb_hcd driver.
Fixing it by adding the missing argument
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
An USB 1.1 keyboard connected to dwc2 through a high-speed hub does not
report status until it changes. With this patch you can enable keyboard
by pressing a key while USB devices are probed. Without a keypress no
state is reported and the probe times out. We don't want to wait for a
keypress or timeout while polling for keypresses so implement an int_msg
nonblock variant that exits early on error.
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
- Tangier ACPI table fixes
- Support getting high memory size on QEMU x86
- Show UEFI images involved in crash for x86
- EFI loader conventional memory map fix
- Add support for dis_u2_susphy_quirk in the xhci-dwc3 driver to fix boot when
a device is plugged only in the OTG capable port for libretech-ac and libretech-cc
Intel iDMA 32-bit controller has 17 bits for the maximum block size value.
Due to nature of the binary number representation the maximum value is
2^17 - 1. The original code misses the latter part in equation.
Fixes: 5e99fde34a ("x86: tangier: Populate CSRT for shared DMA controller")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Per PCI firmware specification the ACPI has to reserve the memory
which is defined as PCI ECAM.
Fixes: 39665beed6 ("x86: tangier: Enable ACPI support for Intel Tangier")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
GCC 9.2 starts complaining about possible pointer misalignment of
pointers to the unpacked (alignment=4) structures in the packed
(alignment=1) ones:
CC arch/x86/cpu/tangier/acpi.o
arch/x86/cpu/tangier/acpi.c: In function ‘acpi_create_fadt’:
arch/x86/cpu/tangier/acpi.c:22:37: warning: taking address of packed
member of ‘struct acpi_fadt’ may result in an unaligned pointer value
[-Waddress-of-packed-member]
22 | struct acpi_table_header *header = &(fadt->header);
CC arch/x86/lib/acpi_table.o
arch/x86/lib/acpi_table.c: In function ‘acpi_create_spcr’:
arch/x86/lib/acpi_table.c:366:37: warning: taking address of packed
member of ‘struct acpi_spcr’ may result in an unaligned pointer value
[-Waddress-of-packed-member]
366 | struct acpi_table_header *header = &(spcr->header);
Fix the potential issues by annotating embedded structures with
__packed even though they are packed naturally.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add GCC version number in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This quirk is necessary for the Amlogic GXL SoCs otherwise the
Port 2 PHY doesn't get out of suspend and U-Boot resets the board after:
XHCI timeout on event type 33... cannot recover.
BUG: failure at drivers/usb/host/xhci-ring.c:474/xhci_wait_for_event()!
BUG!
This quirk is also handled in the dwc3 core code, but until the
xhci-dwc3 driver uses the dwc3 core, the quirk must be handled here
to fix USB support on the Amlogic libretech-cc and libretech-ac board
when a device is only plugged in the OTG port.
Cc: Yuri Frolov <crashing.kernel@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Fixes: dc9cdf859e ("usb: dwc3: Add DWC3 controller driver support")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use efi_add_conventional_memory_map() to configure EFI conventional memory
properly with ram_top value. This will give 32-bit mode U-Boot proper
conventional memory regions even if e820 has an entry which is greater than
32-bit address space.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[bmeng: fixed some typos in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
If a crash occurs, show the loaded UEFI images to facilitate analysis.
This is an example output:
=> bootefi 0x1000000
Found 0 disks
Hello world of bugs!
Invalid Opcode (Undefined Opcode)
EIP: 0010:[<06ceb06e>] EFLAGS: 00010206
Original EIP :[<fec9906e>]
EAX: 00000000 EBX: 06cec000 ECX: 00000fd0 EDX: 00000001
ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0
DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: ffff0ff0 DR7: 00000400
Stack:
0x07d0fde8 : 0x00000000
0x07d0fde4 : 0x06ced040
--->0x07d0fde0 : 0x07fe27a0
0x07d0fddc : 0x00010206
0x07d0fdd8 : 0x00000010
0x07d0fdd4 : 0x06ceb06e
UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi'
### ERROR ### Please RESET the board ###
With the additional information provided by this patch we know that the
problem occurred 0x106e after the load address of bug-i386.efi.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Now that we are able to get the size of high memory from QEMU,
report its memory range as usable ram.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
At present only size of memory that is below 4GiB is retrieved from
QEMU. Add a function that gets size of memory that is above 4GiB.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
This extracts getting memory size logic in dram_init() to a separate
routine qemu_get_low_memory_size(). No functional changes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Every x86 platform provides board_get_usable_ram_top(), hence there
is no need to provide a weak version board_get_usable_ram_top(), not
to mention there is another weak version board_get_usable_ram_top()
in common/board_f.c.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Using ACPI predefined macros, such as Zero or One, will reduce a binary
size of resulting ACPI tables.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: manually fixed the conflicts when applying]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
While the original patch to fix a regression in distro boot for mmc on
these platforms had the correct syntax, I broke the change while
applying. Add back in the missing "=" here so that the syntax is
correct.
Reported-by: Andre Heider <a.heider@gmail.com>
Fixes: 27e0f3bcf0 ("arm: ti: Fix regression in distro boot for mmc")
Signed-off-by: Tom Rini <trini@konsulko.com>
Check the parameters of EFI_FILE_PROTOCOL.GetInfo() to avoid possible NULL
dereference.
Check the buffer size for EFI_FILE_SYSTEM_INFO.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
We cannot determine the volume name in U-Boot. Instead of providing a dummy
volume name in case of EFI_FILE_SYSTEM_INFO and EFI_UNSUPPORTED in case of
EFI_FILE_SYSTEM_VOLUME_LABEL consistently return an empty string.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The UEFI specification requires to implement version 2 of the
EFI_FILE_PROTOCOL. Provide the missing functions as stubs.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The file size has to be determined in multiple places. Factor out a common
function.
If on entry into EFI_FILE_PROTOCOL.Read() the current position is beyond
the end of the file, return EFI_DEVICE_ERROR.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
EFI_FILE_PROTOCOL.Read() is used both to read files and directories.
When reaching the end of a directory we always have to return buffer size
zero irrespective of the incoming buffer size. (The described scenario for
a Shim quirk cannot arise because every directory has at least '.' and '..'
as entries.)
Even when the buffer_size is too small multiple times we have to keep a
reference to our last read directory entry.
When we return to the start of the directory via SetPosition() we must
remove the reference to a previously kept directory entry.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
ascii2unicode() can only convert characters 0x00-0x7f from UTF-8 to UTF-16.
Use utf8_utf16_strcpy() instead.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Check the parameters passed to Write():
* cannot write to directories (UEFI SCT 2017, 5.7.3.5.15)
* cannot write to file opened read only (UEFI SCT 2017, 5.7.3.5.16)
Add missing comments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
- fix mailbox status register used for polling
- fix bcm2835_sdhost to wait long enough for a transfer to complete
- increase kernel image size from 8 MB to 64 MB on arm64
- add support for RPi4
- add prefixes for raspberry pi related stuff to git-mailrc
Define the memory map for the BCM2711 based on the dt configuration
available in the Raspberry Pi kernel fork.
Signed-off-by: Andrei Gherzan <andrei@balena.io>
[mb: BCM2838 -> BCM2711]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
The bcm2711 has two emmc controllers. The difference is the clocks
they use. Add support for the second emmc controller.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Andrei Gherzan <andrei@balena.io>
This clock has a different mbox ID so have this included in the relevant
header file.
Signed-off-by: Andrei Gherzan <andrei@balena.io>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
The Raspebrry Pi 4 uses the new revision code scheme as documented by
the foundation. This change adds an entry for this board as well.
Signed-off-by: Andrei Gherzan <andrei@balena.io>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Define two target configs for Raspberry Pi 4 (32 and 64bit) and the
corresponding BCM2838* configs.
Be aware of the current limitation in firmware which requires an
explicit configuration to force the arm in 64bit mode when the
respective target is used.
Signed-off-by: Andrei Gherzan <andrei@balena.io>
[mb: rename BCM2838 -> BCM2711]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Devices of bcm283x have different base address, depending if they are on
bcm2835 or bcm2836/7. Use BCM283x_BASE depending on the SoC you want to
build and only add the offset in the header files.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Andrei Gherzan <andrei@balena.io>
This defines a minimum defconfig for each of the two Raspberry Pi 4
variants. One notable difference is that we don't have a embedded dt for
this board given that the fw supplies us with one which we can reuse.
Furthermore, the ram size is not queryable through mbox interface as the
maximum reported size is 1G. The fw patches the dt with the right
memory configuration and uboot uses it as it is. We avoid u-boot
touching this configuration by making sure CONFIG_ARCH_FIXUP_FDT_MEMORY
is deactivated.
Signed-off-by: Andrei Gherzan <andrei@balena.io>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
On AArch64, kernel images are not self-decompressing and easily exceed
the 8MB limit.
Signed-off-by: Laurent Bonnans <laurent.bonnans@here.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Function bcm_2835_wait_transfer_complete() is not waiting long enough.
The previous code was claiming to wait for ~1 seconds, but as it depends
on register reads it's time actually varies.
Some cards require wait times of up to ~56 ms to perform
the command 'saveenv' on an EXT4 partition.
Re-implement the loop exit condition to use get_timer() which allows
to specify the wait time in more reliable manner. Set the maximum wait
time to the originally intended 1 second.
Signed-off by: Raul Benet <raul.benet_at_kaptivo.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Before we can send a message to the mailbox we have to check that there
is space to do so. Therefore we poll the status register. But up to now
the wrong status register, the one of mailbox 0, was checked. Fix this
by polling the status regiser of mailbox 1.
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
[mb: rename registers and update commit message]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Pull request for UEFI sub-system for v2019.10-rc4 (3)
This includes the patches from
Pull request for UEFI sub-system for v2019.10-rc4 (2)
Fix UEFI specification compliance issues in the simple network protocol:
* Correctly set and reset the interrupt status.
* Support filling the header in the Transmit() service.
* Correct the checking and setting of the network state.
* Implement the MCastIPtoMAC() service.
* Adjust the simple network protocol unit test.
Fix UEFI specification compliance issues in the protocol.
Fix UEFI specification compliance issues in the simple text output protocol:
* Avoid out of bounds cursor position.
* Do not set illegal screen mode.
Fix UEFI specification compliance issues in the block IO protocol:
* Check parameters.
* Return correct status code if buffer is unaligned.
Refactor initialization of EFI memory in preparation of support for
> 3GB memory on x86.
The sdhci capabilities registers can be incorrect. The
sdhci-caps-mask and sdhci-caps dt properties specify which bits of
the registers are incorrect and what their values should be. This
patch makes the sdhci driver use those properties to correct the caps.
Also use "dev_read_u64_default" instead of "dev_read_u32_array" for
caps mask.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We cannot do anything in EFI_BLOCK_IO_PROTOCOL.Reset() but this does not
justify to return an error.
Let EFI_BLOCK_IO_PROTOCOL.Reset() return EFI_SUCCESS.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
EFI_PRINT() offers indention of debug messages. Adjust the debug messages
of the BLOCK_IO_PROTOCOL.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Check parameters of ReadBlocks() and WriteBlocks().
If the buffer size is not a multiple of the block size, we have to return
EFI_BAD_BUFFER_SIZE.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetMode() should return EFI_UNDEFINED if a
screen mode is not available.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@csgraf.de>
When backspacing in column 0 do no set the column index to ULONG_MAX.
Ensure that the row number is not set to ULONG_MAX even if the row count is
advertised as 0.
Ignore control characters other the 0x08, 0x0a, 0x0d when updating the
column.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Correct the name of the partition size component in struct
efi_device_path_cdrom_path.
Render entry, start, and size when converting a CD-ROM device path node to
text.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Vendor device paths may contain data. When converting vendor device paths
to text this binary data has to be rendered.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Adding a conventional memory region to the memory map may require ram_top
limitation and it can be also commonly used. Extract adding a conventional
memory to the memory map in a separate routine for generic use.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Implement the MCastIPtoMAC service of the simple network protocol.
It converts an multicast IPv4 (or IPv6) address to a multicast Ethernet
address.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The network should start in status EfiSimpleNetworkStopped.
Add and correct status checks in the simple network protocol.
Correct the unit test:
* Shutdown() and Stop() during setup if needed
* invoke Shutdown() before Stop() when tearing down
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Fill the media header in EFI_SIMPLE_NETWORK.Transmit().
Check that the buffer size is large enough for the header.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Check that when the WaitForPacket event occurs
EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT is set.
Check the return value of Receive().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
GetStatus() must clear the interrupt status.
Transmit() should set the TX interrupt.
Receive() should clear the RX interrupt.
Initialize() and Start() should clear the interrupt status.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Enable CONFIG_CMD_BOOTEFI_SELFTEST for the QEMU RISC-V boards.
Travis CI QEMU testing has been enabled for qemu-riscv64_defconfig. With
this patch we will test the UEFI sub-system on the board.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The mmc_spi driver's priv is not available in its bind phase(). Use
platdata instead.
Fixes: 05e35d4297 ("mmc: mmc_spi: Re-write driver using DM framework")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
There are two cases not been considered:
- use uint for timeout, it will overflow when size bigger than 512KB for
it *8*1000 at the beginning, but we may use size up to 32MB; The
'timeout' will overflow if size bigger than 51.2MB after this fix, which
should be enough for U-Boot;
- The timeout is using clock speed for data rate, but the device may not
have such high speed, eg. clock is 52MHz while the device write speed may
be less than 10MB/s, and we may use up to 150MHz clock.
Fix them in this patch, the max timeout is about 6500 when size is 32MB
after fix.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Add nodes for the Aspeed SD controllers with their necessary properties.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Enable the MMC subsystem and the Aspeed SD controller. Also enable the
use of the device tree for probing the controller.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
It's quite hard to figure out time units for various function that have
timeout parameters. This leads to possible errors when one forgets to
convert ms to us, for example. Let's rename those parameters
correspondingly to 'timeout_us' and 'timeout_ms' to prevent such issues
further.
While at it, add time units info as comments to struct mmc fields.
This commit doesn't change the behavior, only renames parameters names.
Buildman should report no changes at all.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
mmc_wait_dat0() expects timeout argument to be in usec units. But some
overlying functions operate on timeout in msec units. Convert timeout
from msec to usec when passing it to mmc_wait_dat0().
This fixes 'avb' commands on BeagleBoard X15, because next chain was
failing:
get_partition() -> mmc_switch_part() -> __mmc_switch() ->
mmc_wait_dat0()
when passing incorrect timeout from __mmc_switch() to mmc_wait_dat0().
Fixes: bb98b8c5c0 ("mmc: During a switch, poll on dat0 if available and check the final status")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Tested-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
When look through the code, I found this bare metal
drives is not used, so remove it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With GCC 9.2.1 net/nfs.c leads to multiple errors of type
address-of-packed-member.
net/nfs.c: In function ‘rpc_req’:
net/nfs.c:199:18: error: taking address of packed member of
‘struct rpc_t’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
199 | p = (uint32_t *)&(rpc_pkt.u.call.data);
| ^~~~~~~~~~~~~~~~~~~~~~
net/nfs.c: In function ‘nfs_readlink_reply’:
net/nfs.c:631:46: error: taking address of packed member of
‘struct rpc_t’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
631 | nfs3_get_attributes_offset(rpc_pkt.u.reply.data);
| ~~~~~~~~~~~~~~~^~~~~
LD drivers/block/built-in.o
net/nfs.c: In function ‘nfs_read_reply’:
net/nfs.c:692:46: error: taking address of packed member of
‘struct rpc_t’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
692 | nfs3_get_attributes_offset(rpc_pkt.u.reply.data);
| ~~~~~~~~~~~~~~~^~~~~
struct rpc_t is only used as local variable. It is naturally packed. So
there is no need for the attribute packed.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
rpc_pkt.u.call.data is an array of uint32_t. There is no need to convert
it to uint32_t *.
memcpy() expects void * as it 1st and 2nd argument. There is no point in
converting pointers to char * before passing them to memcpy().
In ntohl(data[1]) != 0 calling ntohl() is superfluous. If the value is
zero, does not depend on the byte order.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Some environment variables are relevant for networking. For these
U_BOOT_ENV_CALLBACKs have been defined. When the corresponding environment
variable is updated the callback updates the state of the network
sub-system.
In the UEFI subsystem we can use the network even if CONFIG_CMD_NET is not
defined.
Let the usage of the U_BOOT_ENV_CALLBACKs depend on CONFIG_NET and not on
CONFIG_CMD_NET.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds a check to nfs_handler to fix buffer overflow for CVE-2019-14197,
CVE-2019-14200, CVE-2019-14201, CVE-2019-14202, CVE-2019-14203 and CVE-2019-14204.
Signed-off-by: Cheng Liu <liucheng32@huawei.com>
Reported-by: Fermín Serna <fermin@semmle.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The net_random_ethaddr() tries to get some entropy from different
startup times of a board. The seed is initialized with get_timer() which
has only a granularity of milliseconds. We can do better if we use
get_ticks() which returns the raw timer ticks. Using this we have a
higher chance of getting different values at startup.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
With commit c6d07bf440 ("net/macb: increase RX buffer size for GEM")
ethernet support does not work any more with d-cache enabled on the
AT91SAM. The reason is, that MACB_RX_BUFFER_SIZE was changed from 4096
to 128 but this change was not refected in the rx_buffer flush and
invalidate functions, as these also use this macro.
This patch now fixes this by calculating the rx buffer size correctly
again in those functions. With this change, ethernet works again
reliably on my AT91SAM board.
Signed-off-by: Stefan Roese <sr@denx.de>
Fixes: c6d07bf440 ("net/macb: increase RX buffer size for GEM")
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The same compatible = "altr,socfpga-stmmac" appears in both
drivers/net/designware.c and drivers/net/dwmac_socfgpa.c,
creating ambiguity in which driver will be bound.
For Intel/Altera SoC devices, dwmac_socfpga.c is the correct driver.
So drop the compatible string from designware.c.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This reverts commit 1b0c9914cc.
Commit 1b0c9914cc ("net: macb: Fixed reading MII_LPA register")
causes 100Mbps does not work any more with SiFive FU540 GEM on the
HiFive Unleashed board. Revert it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The driver model has been supported for network drivers since 2015. It is
time to convert the remaining boards. Set July 2020 as a timeline.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
It was missing in the original submission and not having it in place causes
issues with probing of PCI devices.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Align the board and driver prototype for board_interface_eth_init
to avoid execution issue (the interface_type parameter is defined
as int or phy_interface_t).
To have a generic weak function (it should be reused by other driver)
I change the prototype to use directly udevice.
This prototype is added in netdev.h to allow compilation check
and avoid warning when compiling with W=1 on file
board/st/stm32mp1/stm32mp1.c
warning: no previous prototype for 'board_interface_eth_init'\
[-Wmissing-prototypes]
int board_interface_eth_init(int interface_type, ....
^~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Do not use random value from stack as return value of pfe_phy_write().
Indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
SANDBOX_PHY_REG_CNT is not an allowable index for the array
u16 reg[SANDBOX_PHY_REG_CNT].
Identified by cppcheck.
Fixes: b47edf8069 ("test: dm_mdio: add a 2nd register to the emulated PHY")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
mvpp2 already has support for setting MAC addresses but this
functionality was not exposed to the ethernet core. This commit exposes
this functionality so that MAC address assignments stored in U-Boot's
environment are correctly applied before Linux boots.
Signed-off-by: Matt Pelland <mpelland@starry.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Implicitly Marvell MDIO driver uses DT node names for devices, but in this
case that is not unique. Set MDIO device names for master/slave to
cpm/cps.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds a separate driver for the MDIO interface of the
Marvell Ethernet controllers based on driver model. There are two
reasons to have a separate driver rather than including it inside
the MAC driver itself:
*) The MDIO interface is shared by all Ethernet ports, so a driver
must guarantee non-concurrent accesses to this MDIO interface. The
most logical way is to have a separate driver that handles this
single MDIO interface, used by all Ethernet ports.
*) The MDIO interface is the same between the existing mv643xx_eth
driver and the new mvneta/mvpp2 driver. Even though it is for now
only used by the mvneta/mvpp2 driver, it will in the future be
used by the mv643xx_eth driver as well.
This driver supports SMI IEEE for 802.3 Clause 22 and XSMI for IEEE
802.3 Clause 45.
This patch also adds device tree binding for marvell MDIO driver.
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adds a binding document for mdio. A notable deviation from corresponding
Linux binding is the introduction of device-name optional property, which
can be used to name MDIO buses. Two reset optional properties described
by Linux binding are also not present as they don't seem to be used in
U-Boot at this time.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use the optional property device-name to name the MDIO bus. This works
around limitations with using the DT node name on devices such as
Armada-8040, which integrates two cp100 cores, both featuring MDIOs at the
same relative offsets and with the same DT node names.
The concept was originally proposed by Marvell as a custom property called
mdio-name specific to Marvell driver. This patch uses the more generic
property device-name and moves this into MDIO class code so other can use
it as well.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for capturing ethernet packets and storing
them in memory in PCAP(2.4) format, later to be analyzed by
any PCAP viewer software (IE. Wireshark)
This feature greatly assist debugging network issues such
as detecting dropped packets, packet corruption etc.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Tested-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs
from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This driver is used for MDIO muxes driven over I2C. This is currently
used on Freescale LS1028A QDS board, on which the physical MDIO MUX is
controlled by an on-board FPGA which in turn is configured through I2C.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These are some very late changes mostly required to get 64-bit
division working on ARC boards.
For that we had to import missing parts of libgcc and add compiler
flags to EMSDP which otherwise used very simple profile for compliation.
And while at it another fix for EM SDP initialization is inluded as well.
Even though EM SDP is FPGA-based board and different FPGA
images (known as .bit-files) are awailable for the board still
there's a common subset of options we may rely on for all configs.
These are:
* Normalizer
* Swap instructions
* Simple multiplier
* Barrel-shifter
* Floating-point unit
* Shorter instructions (code density)
This among other improvements allows to compile code with
64-bit divisions, see [1].
[1] https://patchwork.ozlabs.org/patch/1156541/
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
If the "Page Mode" is not enabled on the device,
read operations from PSRAM may result in incorrect data.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
- Skip unavailable hart in the get_count().
- fu540 set serial env from otp.
- fu540 add mmc0 as a boot target device.
- Update fix_rela_dyn and add absolute reloc addend.
- Andestech PLIC driver will skip unavailable hart.
- Support Andestech V5L2 cache driver.
When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.
Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().
This way can support to skip some harts which maybe marked as
unavailable, but the cpu node exists indeed.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The addend is now added for RELOC_TYPE relocs. Also, changed the loop
structure so that all the R_RISCV_RELATIVE relocs are not required to
be at the beginning of the list.
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>
Previously the handling of R_RISCV_32 and R_RISCV_64 would simply
insert the value of the symbol and ignore any addend. However, there
exist relocs where the addend is non-zero:
0000000080250900 R_RISCV_64 efi_runtime_services+0x0000000000000068
0000000080250910 R_RISCV_64 efi_runtime_services+0x0000000000000038
0000000080250920 R_RISCV_64 efi_runtime_services+0x0000000000000018
0000000080250930 R_RISCV_64 efi_runtime_services+0x0000000000000020
0000000080250980 R_RISCV_64 efi_runtime_services+0x0000000000000048
0000000080250990 R_RISCV_64 efi_runtime_services+0x0000000000000050
00000000802509a0 R_RISCV_64 efi_runtime_services+0x0000000000000058
0000000080250940 R_RISCV_64 systab+0x0000000000000030
0000000080250950 R_RISCV_64 systab+0x0000000000000040
0000000080250960 R_RISCV_64 systab+0x0000000000000050
0000000080250970 R_RISCV_64 systab+0x0000000000000060
In these cases the addend needs to be added to the symbol value to get
the correct value for the reloc.
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>
Add DT entry for the DM PCI driver, update board configs
and drop ad-hoc board init code for the PCI bus. Instead,
let the DM PCI driver initialize and operate the hardware.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Enable OF control for SH4 R2Dplus board. This is necessary, because
the PCI uclass is designed in a way that makes it depend on DT and
disallows instanciating devices without DT (e.g. with platdata).
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Enable driver model support for SH4 R2Dplus board. Thus far, no
drivers are bound via the DM. The PCI drivers have yet to be
converted to DM_PCI.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
If the OF_SEPARATE is enabled, the DT is appended past the _end symbol.
The current code however clears BSS very early, which overwrites the DT
blob with zeroes. Moreover, the early code relocates U-Boot into RAM to
the correct location, but does not relocate the DT.
This patch adds code to relocate the DT and avoids clearing BSS too
early, thus addressing both problems with OF_SEPARATE on SH.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Some of the DM functions depend on OF_CONTROL, which is incorrect.
DM and DT are orthogonal. Add macro guards around such functions to
avoid compiling them in when DM is enabled, while OF_CONTROL is not.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
When CONFIG_CLK enabled, use CLK UCLASS for clk related settings.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
hs: removed hunk in mxc_i2c_probe() as not longer in code
I wanted this to be compatible with mkenvimage, including the ability
to embed newlines in variables by escaping them. But I failed to check
that it works more than once.
Fixes: f3d8f7dd73 (Allow providing default environment from file)
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Enable CONFIG_DM_USB to remove compile warning for
am43xx based targets:
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
TI AM65x platforms (evm and HS) generate an SPL image
'tispl.bin*' and there is no rule for cleanup.
Added entry for cleanup in clean target.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
eMMC device has multiple hw partitions both address from zero. However the
mmc driver lacks block cache invalidation for switch hwpart. This causes a
problem that data of current hw partition is cached before switching to
another hw partition. And the following read operation of the latter hw
partition will get wrong data when reading from the addresses that have
been cached previously.
To solve this problem, invalidate block cache after a successful
mmc_switch_part() operation.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Felix Brack <fb@ltec.ch>
This reverts commit 0ebe112d09.
Most block devices have only one hwpart. Multiple hwparts only found used
by eMMC devices in u-boot. The mmc driver do blk_dselect_hwpart() at the
beginning of mmc_bread() which causes block cache being invalidated too
frequently and makes block cache useless.
So it's not a good idea to put blkcache_invalidate() in the common
functions. It should be called inside mmc_select_hwpart().
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Felix Brack <fb@ltec.ch>
The current code in reserve_noncached() has two issues:
1) The first update of gd->start_addr_sp always rounds down to a section
start. However, the equivalent calculation in cache.c:noncached_init()
always first rounds up to a section start, then subtracts a section size.
These two calculations differ if the initial value is already rounded to
section alignment.
2) The second update of gd->start_addr_sp subtracts exactly
CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in
cache.c:noncached_init() rounds the noncached size up to section
alignment before subtracting it. The two calculations differ if the
noncached region size is not a multiple of the MMU section size.
In practice, one/both of those issues causes a practical problem on
Jetson TX1; U-Boot triggers a synchronous abort during initialization,
likely due to overlapping use of some memory region.
This change fixes both these issues by duplicating the exact calculations
from noncached_init() into reserve_noncached().
However, this fix assumes that gd->start_addr_sp on entry to
reserve_noncached() exactly matches mem_malloc_start on entry to
noncached_init(). I haven't traced the code to see whether it absolutely
guarantees this in all (or indeed any!) cases. Consequently, I added some
comments in the hope that this condition will continue to be true.
Fixes: 5f7adb5b1c ("board_f: reserve noncached space below malloc area")
Cc: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Pull request for UEFI sub-system for v2019.10-rc4
Enable the unit test for UEFI runtime service Exit() on x86_64.
Use as standalone UEFI binary for testing the handling of exceptions.
To fully demonstrate crash outputs for UEFI images provide a standalone
UEFI application that tries to invoke an illegal opcode.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Compile the legacy PCIe initialization routines for P2041RDB,
P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is
not enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Compile the legacy PCIe initialization routines for P1020,
P1021, P1024, P1025 and P2020 RDB boards only when DM_PCI
is not enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
T104x integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Remove the macro CONFIG_ARCH_T1040 from the T102xRDB.h and
the PCIE4 related macros, as there are only 3 PCIe controllers
on T102x SoCs.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
T102x integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
T4240 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The PCIe controller register address in CCSR is different
on various platforms, the current code erroneously use
the hardcoded address (0xffe240000) and stride (0x10000)
to calculate the controller's index.
Fix it by adding the related info to the driver data
structure.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The Class Code fixup method was changed from PCIe block
revision 3.0, the current fixup is only valid for the
revision 3.0 and the later ones.
So add the Class Code fixup for the block revision < 3.0.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This can avoid build error:
The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only
defined on the platforms that select the CONFIG_FOO, while
it's not defined on platforms that do not select the
CONFIG_FOO.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The G12B clock controller is almost identical to the G12A and
so far the differences don't matter. Adding the G12B compatible
makes USB work on the Odroid-N2.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Support of device tree model for T2080RDB, T4240RDB, T1024RDB,
T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, P5040DS and
MPC8548CDS. Also support of i2c dm model.
i2c bugfixes for 2019.10
- misc: i2c_eeprom: verify that the chip is functional at probe()
- i2c: mxc_i2c: Remove i2c_idle_bus from probe
- i2c-mux-gpio: Fix GPIO request flag issue
Add example of its files to generate FIT to start kernel
on ev1 or dk2 board with
- only kernel and dtb = fit_copro_kernel_dtb.its
- kernel, M4 copro firmware and dtb = it_copro_kernel_dtb.its
Add extlinux example to manage config in generated FIT.
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Implements copro image loading with FIT.
Once image is loaded with remoteproc,
the M4 coprocessor is automatically started.
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Define new image type for coprocessor images.
It is used in FIT to identify the files loaded
with remoteproc command (elf or bin).
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RCC driver have no operation so the new NOP uclass
is more appropriate. It only used as parent for clock and reset driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Update management of misc_read, which now return length of data
after the commit 8729b1ae2c ("misc: Update read() and write()
methods to return bytes xfered")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Update management of misc_read in sysconf_init, which now return
length of data after the commit 8729b1ae2c ("misc: Update read()
and write() methods to return bytes xfered")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Update the stm32mp1 baord after the commit 8729b1ae2c
("misc: Update read() and write() methods to return bytes xfered")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Use MISC u-class to export the NVM register (starting at 0xF8 offset)
and avoid specific API.
- SHADOW have offset < 0.
- NVM have register > 0
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Since the commit 8729b1ae2c ("misc: Update read() and
write() methods to return bytes xfered"); The misc bsec driver
need to be adapted to reflect the number of transferred bytes.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Use existing gd structure to store frequency information
which can be used in drivers or arch without new request.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add pattern for infinite test_read and test_write, that
allow to change the pattern to test without recompilation;
default pattern is 0xA5A5AA55.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reduce verbosity of the infinite tests to avoid CubeMX issue.
test and display loop by 1024*1024 accesses: read or write.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
If user choose to test memory size is 1GByte (0x40000000),
memory address would overflow in test "Random" and
test "FrequencySelectivePattern".
Thus the system would hangs up when running DDR test.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Bossen WU <bossen.wu@st.com>
The "serial_stm32.h" is only used by drivers/serial/serial_stm32.c
and it is the file ./drivers/serial/serial_stm32.h
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add management of Bit 1 of USART_ISR = FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise
or a break character is detected. It is cleared by software, writing 1
to the FECF bit in the USART_ICR register (for stm32 after f4).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Due to kernel DT alignment, pwr-supply is renamed to vdd-supply
and is a subnode of pwr-regulators.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
As for Audio codec IC, HDMI IC is not "IO safe".
HDMI regulators (v3v3 and v1v2) must be enabled to allow
I2C1 bus usage. HDMI IC must be under reset during power up
and keep HDMI and AUDIO devices in reset while they are not
used in U-Boot to keep them in low power mode
(each device can be kept in reset independently keeping their
power supplies ON until kernel).
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add the boot for NOR, SPL load U-Boot.img at offset
CONFIG_SYS_SPI_U_BOOT_OFFS = 0x80000.
It is the start address of mtd partition ssbl in nor.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This allows to display splashcreen without waiting
an extra delay of 2 seconds due to default value of bootdelay.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add altbootcmad as it is used for
- bootcountlimit
- in mach-stm32mp/cpu.c for BOOT_RECOVERY mode
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Backlight of panel raydium RM68200 is controlled by a simple gpio,
thus we activate the support for the needed driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add imply for FDT overlay that can be usefuill for kernel device tree
management but it is not mandatory (can be removed to gain space)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
for the moment basic and trusted configuration must
start CPU in Supervisor mode and not in Hypervisor
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Depending on backup register value, we maintain the debug unit
powered-on for debugging purpose.
Only BUCK1 is required for powering the debug unit, so revert
the setting for all the other power lanes, except BUCK3 that
has to be always on.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Avoid U-Boot auto-boot interruption for line break detection
on console when the RX line connected to STLINK is floating
(-IO error in getc cause by framing error and testc return 1)
Same workaround is applied on all the STMicroelectonics board.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The pre-relocation probe is needed to reserve video frame buffer
in video_reserve() for all the board;
LDTC must be tagged prereloc in SOC U-Boot dtsi file.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add node in DT and avoid error to search UCLASS_SYSRESET in
board_f.c::print_resetinfo() and lost 1.6s in U-Boot
for the trusted boot chain.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch adds independent watchdog support for stm32mp157c
in SPL.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Update DDR configuration with the latest update:
- Change DQSGE to 1 for DDR3, to cure missing DQS preamble.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Alignment with kernel driver.
According to the following tab (coming from STMFX datasheet), updates
have to done in stmfx_pinctrl_conf_set function:
-"type" has to be set when "bias" is configured as "pull-up or pull-down"
-PIN_CONFIG_DRIVE_PUSH_PULL should only be used when gpio is configured as
output. There is so no need to check direction.
DIR | TYPE | PUPD | MFX GPIO configuration
----|------|------|---------------------------------------------------
1 | 1 | 1 | OUTPUT open drain with internal pull-up resistor
----|------|------|---------------------------------------------------
1 | 1 | 0 | OUTPUT open drain with internal pull-down resistor
----|------|------|---------------------------------------------------
1 | 0 | 0/1 | OUTPUT push pull no pull
----|------|------|---------------------------------------------------
0 | 1 | 1 | INPUT with internal pull-up resistor
----|------|------|---------------------------------------------------
0 | 1 | 0 | INPUT with internal pull-down resistor
----|------|------|---------------------------------------------------
0 | 0 | 1 | INPUT floating
----|------|------|---------------------------------------------------
0 | 0 | 0 | analog (GPIO not used, default setting)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
STM32 RTC manages only 2 digits for YEAR
(Year tens and units in BCD format in RTC_DR register).
With this patch, RTC driver assumes that tm->tm_years is between
2000 and 2099; tm->tm_year - 2000 have only 2 digit
(0 > and <= 99).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
host->mmc, host->mmc->dev and host->mmc->priv must be set
before calling sdhci_setup_cfg() to avoid hang during mmc
initialization.
Thanks to commit 3d296365e4
("mmc: sdhci: Add support for sdhci-caps-mask") which put
this issue into evidence.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Increase SDMMC_BUSYD0END_TIMEOUT_US from 1s to 2s to
avoid timeout error during blocks erase on some sdcard
Issue seen on Kingston 16GB :
Device: STM32 SDMMC2
Manufacturer ID: 27
OEM: 5048
Name: SD16G
Bus Speed: 50000000
Mode: SD High Speed (50MHz)
card capabilities: widths [4, 1] modes [SD Legacy, SD High Speed (50MHz)]
host capabilities: widths [4, 1] modes [MMC legacy, SD Legacy, MMC High Speed (26MHz), SD High Speed (50MHz), MMC High Speed (52MHz)]
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
Issue reproduced with following command:
STM32MP> mmc erase 0 100000
MMC erase: dev # 0, block # 0, count 1048576 ... mmc erase failed
16384 blocks erased: ERROR
By setting SDMMC_BUSYD0END_TIMEOUT_US at 2 seconds and by adding
time measurement in stm32_sdmmc2_end_cmd() as shown below:
+start = get_timer(0);
/* Polling status register */
ret = readl_poll_timeout(priv->base + SDMMC_STA,
status, status & mask,
SDMMC_BUSYD0END_TIMEOUT_US);
+printf("time = %ld ms\n", get_timer(start));
We get the following trace:
STM32MP> mmc erase 0 100000
MMC erase: dev # 0, block # 0, count 1048576 ...
time = 17 ms
time = 1 ms
time = 1025 ms
time = 54 ms
time = 56 ms
time = 1021 ms
time = 57 ms
time = 56 ms
time = 1020 ms
time = 53 ms
time = 57 ms
time = 1021 ms
time = 53 ms
time = 57 ms
time = 1313 ms
time = 54 ms
time = 56 ms
time = 1026 ms
time = 54 ms
time = 56 ms
time = 1036 ms
time = 54 ms
time = 56 ms
time = 1028 ms
time = 53 ms
time = 56 ms
time = 1027 ms
time = 54 ms
time = 56 ms
time = 1024 ms
time = 54 ms
time = 56 ms
time = 1020 ms
time = 54 ms
time = 57 ms
time = 1023 ms
time = 54 ms
time = 56 ms
time = 1033 ms
time = 53 ms
time = 57 ms
....
time = 53 ms
time = 57 ms
time = 1021 ms
time = 56 ms
time = 56 ms
time = 1026 ms
time = 54 ms
time = 56 ms
1048576 blocks erased: OK
We see that 1 second timeout is not enough, we also see one measurement
up to 1313 ms. Set the timeout to 2 second to keep a security margin.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Read a single byte from EEPROM to verify that it is actually there.
This is equivalent to Linux kernel commit 00f0ea70d2b8 ("eeprom: at24:
check if the chip is functional in probe()").
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
hs: fixed style check prefer kernel type 'u8' over 'uint8_t'
i2c_idle_bus is already used in i2c_init_transfer. So before each transfer
if the bus is not ready, the i2c_idle_bus will be used to force idle.
It is unnecessary to call it again in probe.
We found a issue when enabling i2c mux with the mxc_i2c. The mxc_i2c is probed
after mux probing. However, at this moment the mux is still in idle state not
select any port. So if we call i2c_idle_bus in probe, it will fail and cause
mxc_i2c probe failed.
Signed-off-by: Ye Li <ye.li@nxp.com>
When requesting GPIO, the GPIOD_IS_OUT is missed in flag, so the GPIO
is set the input mode not output and cause mux not work.
Signed-off-by: Ye Li <ye.li@nxp.com>
Add device tree for MPC8548CDS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add CONFIG_RESET_VECTOR_ADDRESS definition with the default value
in u-boot.dtsi to fix the build error below. In the configuration
header file of some MPC85xx boards, there is not the definition
of CONFIG_RESET_VECTOR_ADDRESS, while CONFIG_SYS_MPC85XX_NO_RESETVEC
is also not defined. In this case, it will lack of definition of
CONFIG_RESET_VECTOR_ADDRESS in u-boot.dtsi, and the address
0xfffffffc will be used as the boot page by default.
Error log:
DTC arch/powerpc/dts/mpc8548cds.dtb
DTC arch/powerpc/dts/mpc8548cds_36b.dtb
Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error
FATAL ERROR: Unable to parse input tree
Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:308: recipe for target
'arch/powerpc/dts/mpc8548cds.dtb' failed
make[2]: *** [arch/powerpc/dts/mpc8548cds.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
scripts/Makefile.lib:308: recipe for target
'arch/powerpc/dts/mpc8548cds_36b.dtb' failed
make[2]: *** [arch/powerpc/dts/mpc8548cds_36b.dtb] Error 1
dts/Makefile:38: recipe for target 'arch-dtbs' failed
make[1]: *** [arch-dtbs] Error 2
Makefile:1038: recipe for target 'dts/dt.dtb' failed
make: *** [dts/dt.dtb] Error 2
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P5040DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P4080DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P3041DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P1041RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for T1042D4RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for T1024RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for T4240RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add device tree for T2080RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
include/video_logo.h once was created via the tool easylogo and than used
in cpu/mpc8xx/video.c to display Tux. video_logo.h has been replaced by
include/linux_logo.h and is not needed anymore.
Delete the include and the tool,
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Found accidentally in omap3_logic, CONFIG_USB_EHCI_OMAP adds some
code size to SPL, so this patch disables it on the am3517-evm to
reduce the code a bit since it's tight for space.
Signed-off-by: Adam Ford <aford173@gmail.com>
The SPI and NAND variants enable DM_GPIO, so this patch enables
DM_GPIO for the NOR / XIP version of the da850-evm.
Signed-off-by: Adam Ford <aford173@gmail.com>
The NAND configuration has had the ethernet missing, so this patch
enables the on-board ethernet interface.
Signed-off-by: Adam Ford <aford173@gmail.com>
Several options are presenting themselves on a various boards
where the options are clearly not used. (ie, SPL/TPL options
when SPL or TPL are not defined)
This patch is not attempting to be a complete list of items, but
more like low hanging fruit. In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.
This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.
Signed-off-by: Adam Ford <aford173@gmail.com>
The current Makefile always use u-boot.bin to generate
PBL boot image (u-boot.pbl), this patch changes it to
use u-boot-with-dtb.bin to support device tree when
CONFIG_OF_SEPARATE is enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
To address the following warning message:
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
CONFIG_DM_USB is enabled, this resulted in SPL build errors:
drivers/built-in.o: In function 'xhci_dwc3_probe':
u-boot/drivers/usb/host/xhci-dwc3.c:155: undefined reference to 'usb_get_dr_mode'
scripts/Makefile.spl:404: recipe for target 'spl/u-boot-spl' failed
make[1]: *** [spl/u-boot-spl] Error 1
Makefile:1721: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2
Enabling usb common library and usb ethernet drivers in SPL
does the job. Target was compile tested, build was clean.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
When large writes take place I saw a Samsung EVO 970+ return a status
value of 0x13, PRP Offset Invalid. I tracked this down to the
improper handling of PRP entries. The blocks the PRP entries are
placed in cannot cross a page boundary and thus should be allocated
on page boundaries. This is how the Linux kernel driver works.
With this patch, the PRP pool is allocated on a page boundary and
other than the very first allocation, the pool size is a multiple of
the page size. Each page can hold (4096 / 8) - 1 entries since the
last entry must point to the next page in the pool.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The command "pci bar" and "pci region" display the address and size in
16 characters including "0x", so the command can only display
14 hexadecimal digits if the number of digits in the address and size is
less than 14.
ID Base Size Width Type
----------------------------------------------------------
0 0x00000020000000 0x00000000100000 64 MEM Prefetchable
1 0xffff000080000000 0x00000000100000 64 MEM Prefetchable
The 64-bit address and size should be displayed in 18(= 16+2) digits,
so this patch adjusts them.
Cc: Yehuda Yitschak <yehuday@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some of the USB code is still being built into SPL even when the
SPL menu options have it explicitly disabled for SPL. Unit there is
a better solution, This patch undefines CONFIG_USB_EHCI_OMAP when
building SPL which reduces the code and lets the board boot again.
Fixes: 25e4ff45b1 ("ARM: omap3_logic: Enable OMAP EHCI support
for SOM-LV Boards")
Signed-off-by: Adam Ford <aford173@gmail.com>
The assigned value NULL is overwritten before being used. Remove the
assignment.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
File was found on specified location. Info about file was read,
but then immediately destroyed using 'free' call. As a result
file size was set to 0, hence fat process didn't read any data.
Premature 'free' call removed. Resources are freed right before
function return. File is read correctly.
Signed-off-by: Martin Vystrcil <martin.vystrcil@m-linux.cz>
The scsi_scan_dev() is looping over the number of uc_plat->max_id.
The number of actual ports a AHCI controller has can be greater than
max_id. Update uc_plat->max_id to make SCSI scan all detected ports.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When the pinmux configuration was added, it was accidentally placed into
the omap3_pmx_wkup node when it should have been placed into the
omap3_pmx_core. This error was accidentally propagated to U-Boot by
me when I blindly copied the device tree from Linux.
This patch moves the i2c2_pins and i2c3_pins to the correct node
which should eliminate i2c bus errors and timeouts due to the fact
the bootloader uses the save device tree that no longer properly
assigns these pins.
Signed-off-by: Adam Ford <aford173@gmail.com>
Noncached area at present is being initialized to random space after malloc
area. It works in most the cases as it goes to stack area & stack is not
overwriting it being far from it.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
When devnum was changed to a local variable in distro_bootcmd we ran
into a problem on TI platforms (confirmed on Beaglebone) as we had been
using 'setenv devnum' there as well and it needs to match the other
usage.
Fixes: 13dd6665ed ("distro: not taint environment variables if possible")
[trini: Review other platforms, re-word commit message]
Signed-off-by: Tom Rini <trini@konsulko.com>
When 'make qemu-riscv64_defconfig', there is a build warning:
board/emulation/qemu-riscv/Kconfig:24:
warning: config symbol defined without type
Fix it by specifying the config symbol type to 'hex'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
The available defconfigs for RISC-V QEMU have changed. We now have
configurations to compile U-Boot to run in supervisor mode and for
U-Boot SPL. Update the QEMU RISC-V documentation to reflect these
changes.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
configurations are meant to help the development of SPL on RISC-V.
The configurations enable RAM as the only SPL boot device. Images must
be loaded at address 0x80200000. In the default boot flow, U-Boot SPL
starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
then started in supervisor mode by OpenSBI.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Now that we have a generic FIT generator script for RISC-V, set it as
the default. To also build the FIT image by default, set the default
build target to "u-boot.itb" if CONFIG_SPL_LOAD_FIT is enabled.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Add a generic FIT generator script for RISC-V to generate images
containing U-Boot, OpenSBI FW_DYNAMIC firmware, and optionally one or
more device trees. The location of the OpenSBI firmware binary can be
specified with the OPENSBI environment variable. By default, it is
assumed to be "fw_dynamic.bin", located in the U-Boot top-level. Device
trees are passed as arguments to the generator script. A separate
configuration entry is created for each device tree.
The load addresses of U-Boot and OpenSBI are parsed from the U-Boot
configuration. They can be overwritten with the UBOOT_LOAD_ADDR and
OPENSBI_LOAD_ADDR environment variables.
The script is based on the i.MX (arch/arm/mach-imx/mkimage_fit_atf.sh)
and Allwinner sunxi (board/sunxi/mksunxi_fit_atf.sh) FIT generator
scripts.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
To support relocation of the stack and global data on RISC-V, the
secondary harts must be notified of the change using IPIs. We can reuse
the hart relocation code for this purpose. It uses global data to store
the new stack pointer and global data pointer for the secondary harts.
This means that we cannot update the global data pointer of the main
hart in spl_relocate_stack_gd(), because the secondary harts have not
yet been relocated at this point. It is updated after the secondary
harts have been notified.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.
To be able to use SPL, boards have to provide a supported SPL boot
device.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
RISC-V OpenSBI is an open-source implementation of the RISC-V Supervisor
Binary Interface (SBI) specification. It is required by Linux and U-Boot
running in supervisor mode. This patch adds support for booting via the
OpenSBI FW_DYNAMIC firmware. It supports OpenSBI version 0.4 and higher.
In this configuration, U-Boot SPL starts in machine mode. After loading
OpenSBI and U-Boot proper, it will start OpenSBI. All necessary
parameters are generated by U-Boot SPL and are passed to OpenSBI. U-Boot
proper is started in supervisor mode by OpenSBI. Support for OpenSBI is
enabled with CONFIG_SPL_OPENSBI. An additional configuration entry,
CONFIG_SPL_OPENSBI_LOAD_ADDR, is used to specify the load address of the
OpenSBI firmware binary. It is not used directly in U-Boot and instead
is intended to make the value available to scripts such as FIT
configuration generators.
The header file include/opensbi.h is based on header files from the
OpenSBI project. They are recent, as of commit bae54f764570 ("firmware:
Add fw_dynamic firmware").
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.
Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
As part of the SPL FIT boot flow, the device tree is appended to U-Boot
proper. The device tree is used to record information on the loadables
to make them available to the SPL framework and U-Boot proper. Depending
on the U-Boot device tree provider, the FIT image might not include a
device tree. Information on the loadables is missing in this case.
When booting via firmware bundled with the FIT image, U-Boot SPL loads
the firmware binary and U-Boot proper before starting the firmware. The
firmware, in turn, is responsible for starting U-Boot proper.
Information on the memory location of the U-Boot proper loadable must be
available to the SPL framework so that it can be passed to the firmware
binary. To support this use case when no device tree is found in the FIT
image, fall back to the U-Boot device tree in this situation.
At the same time, update the comment to remove the note that the
destination address must be aligned to ARCH_DMA_MINALIGN. Alignment is
only required as an intermediate step when reading external data. This
is automatically handled by spl_fit_append_fdt(). After reading the
external data, it is copied to the specified address, which does not
have to be aligned to ARCH_DMA_MINALIGN.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
When building a U-Boot FIT image, the device trees specified by the
board are unconditionally built for inclusion in the FIT image. However,
not all device tree providers, such as CONFIG_OF_PRIOR_STAGE, require a
device tree to be built and bundled with the U-Boot binary. They rely on
other mechanisms to provide the device tree to U-Boot. Compilation on
boards with these device tree providers fails, because they do not
specify a device tree.
Change the makefile rules to conditionally build the device trees if
CONFIG_OF_SEPARATE, CONFIG_OF_EMBED, or CONFIG_OF_HOSTFILE is selected
as device tree provider.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
The current preprocessor logic prevents CONFIG_OF_PRIOR_STAGE from being
used in U-Boot SPL. Change the logic to also make it available in U-Boot
SPL.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This converts the following to Kconfig:
CONFIG_SYS_SPI_U_BOOT_OFFS
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
[trini: Expose this for SPL_SPI_SUNXI for now]
Signed-off-by: Tom Rini <trini@konsulko.com>
Exact two boards are referencing CONFIG_SYS_SPI_U_BOOT_OFFS to another
define, we replace this manually with the value for having a clean run
of moveconfig.py afterwards.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
some boards have common headers for several individual build-targets
where CONFIG_SYS_SPI_U_BOOT_OFFS is defined even it is not needed (only
needed if CONFIG_SPL_SPI_LOAD is defined also). Take this define here
under '#ifdef CONFIG_SPL_SPI_LOAD' for having a clean run of
moveconfig.py
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Some boards have coded this offset with formula or bitshifts in their
board-config. Manually convert these things into hex-values to be able
using moveconfig.py afterwards.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Convert CONFIG_SYS_NAND_USE_FLASH_BBT to Kconfig, update defconfigs,
headers and whitelist.
Please note that this symbol already was used in Kconfig
(imply in CONFIG_NAND_ATMEL) which did not work, since this symbol was
not available in Kconfig. This changes now with this patch and all
boards with CONFIG_NAND_ATMEL will have BBT enabled. Which is what
I also need on my GARDENA AT91SAM based board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
[trini: Rework such that the configs are unchanged to start with]
Signed-off-by: Tom Rini <trini@konsulko.com>
- remove rk3288 fennec board
- remove SPL raw image support for Rockchip SoCs
- add common misc_init_r() for ethaddr from cpuid
- enable USB HOST support for rk3328
- unify code for finding a valid gpt in part driver
This converts the following to Kconfig:
CONFIG_FSL_USDHC
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add IMX8M, TARGET_S32V234EVB to FSL_USDHC list]
Signed-off-by: Tom Rini <trini@konsulko.com>
Several options are presenting themselves on a various boards
where the options are clearly not used. (ie, arm64 options on
arm9, or SPL/TPL options when SPL or TPL are not defined)
This patch is not attempting to be a complete list of items, but
more like low hanging fruit.
This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.
Signed-off-by: Adam Ford <aford173@gmail.com>
Some ChromeOS devices (atleast veyron speedy) have the first 8MiB of
the eMMC write protected and equipped with a dummy 'IGNOREME' GPT
header - instead of spewing error messages about it, just silently
try the backup GPT.
Note: this does not touch the gpt cmd writing/verifying functions,
those will still complain.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.
The MAC address is only generated and set if there is no ethaddr
present in the saved environment.
This is based off of Klaus Goger's work in 8adc9d
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
According to rock64 schemetic, both VCC_HOST1_5V and VCC_HOST_5V are
controlled by USB20_HOST_DRV(GPIO0A2), fix it so that we can get correct
power supply for USB HOST ports.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We need to store all the ram related cap/map info back to register
for each channel after all the init has been done in case some of register
was reset during the process.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Enable USB host support on GR Peach board.
To use USB host on GR Peach, it might be necessary to solder JP3 header
onto the board first and then short it. Shorting JP3 is mandatory to let
the U5 regulator to supply VBUS to the CN3 USB port.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Add DM regulator support for toggling VBUS, this is useful on boards
which control the VBUS e.g. through GPIO.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Convert the R8A66597 USB driver to DM and add support for DT probing.
Drop support for legacy non-DM and non-DT probing, since there are no
platform using that.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
While the USB controller can work both in LE and BE modes, there is
no user for the BE mode, so drop it. If there ever is a user for it,
it can be easily re-added back.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Replace in{bwl}()/out{bwl}() IO accessors with read{bwl}()/write{bwl}(),
to make the driver compile both on SH and ARM.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
No other platforms use this r8a66597 controller but RZ/A1,
make RZ/A1 support the default and drop all the other SoC
support to remove ifdeffery.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
By default, i2c input clock is platform clk / 2, but some of the
platform of i2c clock divider does not meet this kind of circumstance,
so alone to set default values for these platforms.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
BRDCFG4[USBOSC] and BRDCFG5[SPR] register field of Qixis device is used
to control SPI and other IP signal routing.
USBOSC:
0= SPI_CLK used as external USB REFCLK input driven with 24.000 MHz.
SPI devices are unusable in this mode.
1= SPI_CLK used as SPI clock.
SPI devices are usable in this mode. USB block is clocked from
internal sources
SPR[3:2]:
SPI_CS / SDHC_DAT4:7 Routing (schematic net CFG_SPI_ROUTE[3:2]):
00= SDHC/eMMC 8-bit
01= SD Card Rev 2.0/3.0
10= SPI on-board memory
11= TDM Riser / SPI off-board connector.
The default value is 00 if an SDCard/eMMC card is selected as the boot
device.
SPR[1:0]:
SPI_SIN/SOUT/SCK Routing (schematic net CFG_SPI_ROUTE[1:0]):
00= SDHC Sync loop
01= TDM Riser / SPI off-board connector.
10= SPI on-board memory.
11= SPI off-board connector.
By default, the SPI feature is not available, so we need to configure
the above register fields to select the route to the SPI feature.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Defines CONFIG_ENV_ADDR for QSPI Boot which specifies the start
address of the flash sector containing the environment. It fixes
the issue that bootcmd is always set as default at bootup.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Flexcan in LX2160ARDB is controlled by FPGA register boardcfg4
bit 5. enable this bit so that flexcan is enabled in LX2160ARDB.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Enable related configs on all ls1088aqds boards to support pcf2127
rtc DM function.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add the pcf2127-rtc node under the i2c0->i2c-mux@77->i2c@3 for ls1088aqds boards.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This patch adds some slave nodes to support the i2c dm on the device
side under the i2c0 controller.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
One ls1088a, there are four I2C controllers. So add all I2C node
for ls1088a in device tree.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls1088a.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM
I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch
solves the problem that the i2c-related api of the ls1088a platform
does not support dm.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Enable related configs on all ls2088aqds boards to support ds3231
rtc DM function.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add the ds3232-rtc node under the i2c0->i2c-mux@77->i2c@0 for ls2088aqds
boards.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add an implementation of the rtc_enable_32khz_output() that uses the
driver model i2c APIs.
Also put code related to rtc_enable_32khz_output
under CONFIG_RTC_ENABLE_32KHZ_OUTPUT.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add some slave nodes to support the i2c dm on the device side under the i2c0.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
One ls2088a, there are four I2C controllers. So add I2C nodes in dts
for ls2088a.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls2080a.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM
I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch
solves the problem that the i2c-related api of the ls2088a platform
does not support dm.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Since i2c uses dm mode, i2c controller will be initialized when reading
and writing devices on i2c bus. So there is no need for the original
non-dm mode i2c early initialization function call, this patch removed
the definition of CONFIG_SYS_I2C_EARLY_INIT.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls1028a.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM
I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch
solves the problem that the i2c-related api of the ls1028a platform
does not support dm.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Enable related configs on all lx2160ardb boards to support pcf2127
rtc DM feature.
Also remove SYS_I2C_MXC_I2Cx, where x is from 1 to 8 from
Kconfig.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add the pcf2127-rtc node under the i2c0->i2c-mux@77->i2c@3 in dts for
lx2160aqds boards.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Lx2160ardb need to use i2c0 before relocation, so we also need to set
u-boot, dm-pre-reloc to initialize node before relocation.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
In lx2160a soc, there are eight i2c controllers, this patch adds i2c
nodes for lx2160a, and the gpio2 nodes on which the i2c4 controller
depends.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch ls2160a.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
I2C dm mode enablemenet causes below compilation errors:
In file included from include/config.h:8:0,
from include/common.h:20:
include/config_fallbacks.h:51:4: error: #error "Cannot define
CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
^~~~~
In file included from include/config.h:8:0,
from include/common.h:20:
include/config_fallbacks.h:51:4: error: #error "Cannot define
CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
^~~~~
board/freescale/lx2160a/lx2160a.c: In function 'board_early_init_f':
board/freescale/lx2160a/lx2160a.c:108:2: warning: implicit declaration
of function 'i2c_early_init_f'; did you mean 'arch_early_init_r'?
[-Wimplicit-function-declaration]
i2c_early_init_f();
^~~~~~~~~~~~~~~~
arch_early_init_r
drivers/i2c/mxc_i2c.c: In function 'mxc_i2c_probe':
drivers/i2c/mxc_i2c.c:824:8: warning: implicit declaration of function
'enable_i2c_clk';
did you mean 'enable_irq_wake'? [-Wimplicit-function-declaration]
ret = enable_i2c_clk(1, bus->seq);
^~~~~~~~~~~~~~
enable_irq_wake
So fix these compilation errors.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch solves
the problem that the i2c-related api of the lx2160a platform does not
support dm.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Move CONFIG_FSL_QSPI from header file to defconfigs,
consequently unset imply config(CONFIG_SPI_FLASH_BAR) which
is not valid for LS series.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Select BOARD_LATE_INIT for ls1028ardb and ls1028aqds targets
so that late init work can be done.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This driver needs modification to work with new soc,
like ls1028, since bitmap of RCFG is changed to
RESV[7:5] LIVE[4] WDEN[3] RESV[2:1] GO[0]
000 1 0 00 0
Also the RCW location is moved to only dutcfg0.
RESV[7:4] RCWSRC[3:0]
1111 configurable
Following commands are functional now
qixis_reset
qixis_reset sd
qixis_reset qspi
qixis_reset emmc
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved.
But MC support to work with 128MB or 256MB DDR memory also, in this
case, rest of the memory is not usable.
So reporting this extra memory to Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Since we added clk enable_count and prograte clk child enabling
operation to clk parent, so add a new function sandbox_clk_enable_count
to get enable_count for test usage.
And add test code to get the enable_count after we enable/disable
the device clk.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On i.MX8MM, thinking such as clk path
OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device
Only enabling CCGR GATE is not enough, we also need to enable PLL GATE
to make sure the clk path work. So when enabling CCGR GATE,
we could prograte to enabling PLL GATE to make life easier.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
As what Linux Kernel 5.3.0 provides when enable/disable clk,
there is an enable_count in clk_core_disable/enable. Introduce
enable_count to track the clk enable/disable count when
clk_enable/disable for CCF. And Initialize enable_count to 0 when
register the clk.
And clk tree dump with enable_count will be supported, it will
be easy for us to check the clk status with enable_count
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Based on discussion with Stephen Warren there was recommendation to list
both memory and random command dependencies just in case that dependency is
not properly handled by Kconfig.
Fixes: a09c1f7e1c ("test/py: Fix MMC/SD block write test dependency")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Building easylogo with `HOST_TOOLS_ALL=y make tools` results in a build
warning due to a possible buffer overrun:
tools/easylogo/easylogo.c:453:4: note: ‘sprintf’ output between 7 and
262 bytes into a destination of size 256
sprintf (str, "%s, 0x%02x", app, *dataptr++);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Truncate the output to fit into the destination buffer.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Looking at the contents of file .mailmap it seems that some editors assumed
that translation is done by entering multiple lines into the file and the
last one replaces the others. This is not how it works. The translation
occurs according to entries in single lines as described in the
git-check-mailmap man-page.
Add a description of the file format.
Add an entry for Alexander Graf as his old email address is not valid
anymore.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The earlier commit....
commit a5a5d997b4 ("spl: Allow performing BSS init early before board_init_f()")
...introduced the ability to use BSS from SPL's board_init_f() as it may
be required in certain exceptional use cases so go ahead and update the
README to reflect this change. Note that as highlighted with the changes
the use of the associated CONFIG option is generally not recommended.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Based on discussion with Stephen Warren there was recommendation to list
both memory and random command dependencies just in case that dependency is
not properly handled by Kconfig.
Fixes: a09c1f7e1c ("test/py: Fix MMC/SD block write test dependency")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Building easylogo with `HOST_TOOLS_ALL=y make tools` results in a build
warning due to a possible buffer overrun:
tools/easylogo/easylogo.c:453:4: note: ‘sprintf’ output between 7 and
262 bytes into a destination of size 256
sprintf (str, "%s, 0x%02x", app, *dataptr++);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Truncate the output to fit into the destination buffer.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Looking at the contents of file .mailmap it seems that some editors assumed
that translation is done by entering multiple lines into the file and the
last one replaces the others. This is not how it works. The translation
occurs according to entries in single lines as described in the
git-check-mailmap man-page.
Add a description of the file format.
Add an entry for Alexander Graf as his old email address is not valid
anymore.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The earlier commit....
commit a5a5d997b4 ("spl: Allow performing BSS init early before board_init_f()")
...introduced the ability to use BSS from SPL's board_init_f() as it may
be required in certain exceptional use cases so go ahead and update the
README to reflect this change. Note that as highlighted with the changes
the use of the associated CONFIG option is generally not recommended.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
With DM_MMC enabled, enable CONFIG_BLK to remove this
compile warning for am43xx based targets:
===================== WARNING ======================
This board does not use CONFIG_DM_MMC. Please update
the board to use CONFIG_DM_MMC before the v2019.04 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
Targets were compile tested, build was clean.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
TI HS platforms generate *dtb_HS binary blobs and there is no
rule for cleanup. Added entry for cleanup in clean-files target.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The commit 1b42ab3eda ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") updates the kernel device-tree blob to adjust
the DSP, IVA and GPU DPLL clocks based on a one-time OPP choice selected
in U-Boot. All these DPLL clocks are children of the cm_core_aon clocks
DT node.
The hierarchy of this clocks DT node has changed in newer Linux kernels
starting from v5.0, and this results in a failure in ft_fixup_clocks()
function to update the clock rates on these newer kernels. Fix this by
updating the lookup logic to look through both the newer and older
DT hierarchy paths for the cm_core_aon clocks node.
Signed-off-by: Suman Anna <s-anna@ti.com>
The Kconfig file calls to ti/common/Kconfig twice which makes
several of the menu items repeat themselves. In an effort to
clean this up, this patch removes the second call which eliminates
the duplicate menu items.
Signed-off-by: Adam Ford <aford173@gmail.com>
Now that SPL supports DM_SERIAL and the direct NOR boot supports
DM_SERIAL, the check to see if DM_SERIAL is defined can go away,
because all da850evm variants now support DM_SERIAL. This patch
simply removes some dead precompiler defines.
Signed-off-by: Adam Ford <aford173@gmail.com>
With SPL now supporting DM_SPI, the need for compiler directives
and hard-coded addresses is obsolete. This patch removes some
dead legacy code defining the SPI base address
Signed-off-by: Adam Ford <aford173@gmail.com>
Sorry for the noise, but there appears to be a regression with older
hardware. Since it broke the direct_nor boot option, it should be
reverted until a better solution is available.
This reverts commit 51cd1e2373.
Like we did with 'fit_loadaddr' to 'addr_fit', the variable
'fit_bootfile' contains a name and so should be prefixed with
name_. Make this change here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
This is the first part of a larger effort I would like to propose to
unify and simplify the default set of environment variables.
When many early environment variables were named there were fewer images
being loaded, usually just a kernel. At this time names like 'loadaddr'
would suffice. Now we have more images and many more commands that act on
them, often re-using the same variable for several different uses. The
contents of a variable are also not immediately known causing one to have
to look up a chain of variables to understand what a command is actually
doing. I suggest the following.
To start, all variables containing names should be prefixed with name_
and addresses with addr_. This is like how K2 already does things and
allows for simple universal commands like:
get_fdt_nfs=nfs ${addr_fdt} /boot/${name_fdt}
Which is very clear on what is intended here and would work across all
board that using the this naming convention.
We can do this one variable at a time, start here with addr_fit.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Andreas Dannenberg <dannenberg@ti.com>
The variable 'name_overlays' serves the same purpose. Remove
'overlay_files' and use 'name_overlays' everywhere.
Signed-off-by: Andrew F. Davis <afd@ti.com>
The full path has changed in the recent kernels so that it is
not possible to load them. Aliases "ethernet0" and "ethernet1"
are still present in both legacy and new kernels.
Also, fix error messages to correspond to the taken actions.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
- Add ROC-RK3399-PC board support
- Move CONFIG_SPI_FLASH_GIGADEVICE and CONFIG_CMD_USB_MASS_STORAGE to
Kconfig
- using SYSRESET_POWER_OFF for poweroff
(Note that patch for rk8xx pmic is droped for it can not pass Travis
build)
- fix ofnode_get_name() assert
This is a generic implementation. Add CONFIG_SYSRESET_CMD_POWEROFF
to signal when we need it. Enable it from the STPMIC1 config and in
sandbox.
The config flag is transitionary, that is it can be removed after all
poweroff implementations use sysreset, and just have CMD_POWEROFF depend
on sysreset.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
It seems that SYSRESET_POWER_OFF was added recently, and all previous code
used SYSRESET_POWER for poweroff. SYSRESET_POWER is supposed to be a
PMIC-level power cycle, not a poweroff.
(Comment by Simon Glass)
SYSRESET_POWER means to do a power reset (removing and reinstating all power)
SYSRESET_POWER_OFF means to turn the device off and leave it off
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
(Update comment to help understand the patch)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Updates jerry, mickey, minnie and speedy defconfigs to:
- fit the SPL in 32k
- boot from SPI (only)
- remove gadget support (these have no OTG port)
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Rebase on top of tree)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This affects RK3036, RK322X and RK3288 - the defconfig changes done by
moveconfig.py for the veyrons were left out on purpose because they dont
have an OTG port, and will get their config updated in the next commit.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In some case with LIVE DT, some node always not valid, or not have
a valid name, eg. blk driver add by mmc.
Return fail instead of Assert for this kind of ofnode, and this
help with assert happen from time to time when of_live is enabled
and DEBUG is enabled.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the removal of the x86 specific GD flags, there are no arch-
specific GD flags any more. Let's remove the comment about reserving the
upper 16 bits for arch-specific flags in the common header. This gives
us more flexibility with the usage of the GD flags.
As a matter of fact, we are already using more than 16 bits for common
GD flags (with the addition of GD_FLG_WDT_READY).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch removes the x86 architecture specific GD flags
(GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only
GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S.
But the coreboot target does not use start16.S at all and boots directly
from the 32-bit start code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Rename some camel-case variables to match U-Boot style.
Camel case is not generally allowed in U-Boot. Rename this variable to fit
in with the style.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Sometimes an image has multiple CBFS. The current CBFS API is limited to
handling only one at time. Also it keeps track of the CBFS internally in
BSS, which does not work before relocation, for example.
Add a few new functions to overcome these limitations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Move the result variable into the struct also, so that it can be used when
BSS is not available. Add a function to read it.
Note that all functions sill use the BSS version of the data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present there are a number of static variables in BSS. This cannot work
with SPL, at least until BSS is available in board_init_r().
Move the variables into a struct, so it is possible to malloc() it and use
it before BSS is available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present this file has a function at the top, above declarations. This
is normally avoided, so fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a new Kconfig option to enable CBFS in SPL. This can be useful when
the memory-init code is in CBFS.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Avoid a warning when building the 'make htmldocs' target:
doc/board/intel/slimbootloader.rst:90: WARNING: Title underline too short.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Use DISTRO_BOOTENV to decouple BOOTENV from CONFIG_DISTRO_DEFAULTS.
Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Pull request for UEFI sub-system for v2019.10-rc3
This pull request provides corrections for the SetVirtualAddress runtime
service and avoids possible calls to NULL by consumers of the
EFI_PXE_BASE_CODE_PROTOCOL.
Commit 7f95104d91 ("efi_loader: detach runtime in ExitBootServices()")
added a call to efi_runtime_detach() to ExitBootServices() but did not
remove the call in SetVirtualAddressMap().
Remove the superfluous function call.
Correct a comment referring to efi_runtime_detach().
Fixes: 7f95104d91 ("efi_loader: detach runtime in ExitBootServices()")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Check the parameters DescriptorSize and DescriptiorVersion of
SetVirtualAddressMap() as prescribed by the UEFI specification.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
U-Boot implements the EFI_PXE_BASE_CODE_PROTOCOL because GRUB uses the mode
information for booting via PXE. All function pointers in the protocol were
NULL up to now which will cause immediate crashes when the services of the
protocol are called.
Create function stubs for all services of the protocol returning
EFI_UNSUPPORTED.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the
DDR driver does not use bss any more, bss is not used before board_init_r()
and we can remove this hack.
bss is normally zeroed by crt0.S, but after board_init_f(), before
board_init_r(). socfpga just had this double-zeroing because it invalidly
used bss in board_init_f() already (during DDR initialization).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Bring cyclone5 / arria5 / arria10 in line with convention and use
u-boot.img as CONFIG_SPL_FS_LOAD_PAYLOAD_NAME.
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
All ELF fields whose values are inspected by the code are converted to
CPU byteorder first. Values which are copied verbatim (relocation
fixups) are not swapped to CPU byteorder and back as it is not needed.
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
We should explicitly load DTB from TFTP server or MMC/SD card
for Linux booting. This will allow us:
1. To use different Linux DTB for SiFive Unleashed board with
expansion board connected.
2. Avoid re-flashing OpenSBI firmware whenever board connections
change.
This patch updates reference bootlog in SiFive FU540 README
as-per above.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
We should prefer accessing CSRs using their CSR numbers
because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR
numbers as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not
recognize newly added CSRs by name.
This commit is inspired from Linux kernel commit a3182c91ef4e
("RISC-V: Access CSRs using CSR numbers").
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
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