x86: Add chromebook_coral
Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
2153e8fbfc
commit
a1d6dc3f84
@ -2,6 +2,7 @@
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dtb-y += bayleybay.dtb \
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cherryhill.dtb \
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chromebook_coral.dtb \
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chromebook_link.dtb \
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chromebox_panther.dtb \
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chromebook_samus.dtb \
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831
arch/x86/dts/chromebook_coral.dts
Normal file
831
arch/x86/dts/chromebook_coral.dts
Normal file
@ -0,0 +1,831 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/dts-v1/;
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#include <dt-bindings/gpio/x86-gpio.h>
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/include/ "skeleton.dtsi"
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/include/ "keyboard.dtsi"
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/include/ "reset.dtsi"
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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#ifdef CONFIG_CHROMEOS
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#include "chromeos-x86.dtsi"
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#include "flashmap-x86-ro.dtsi"
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#include "flashmap-16mb-rw.dtsi"
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#endif
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#include <asm/intel_pinctrl_defs.h>
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#include <asm/arch-apollolake/cpu.h>
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#include <asm/arch-apollolake/gpio.h>
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#include <asm/arch-apollolake/iomap.h>
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#include <asm/arch-apollolake/pm.h>
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/ {
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model = "Google Coral";
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compatible = "google,coral", "intel,apollolake";
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aliases {
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cros-ec0 = &cros_ec;
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fsp = &fsp_s;
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spi0 = &spi;
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};
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config {
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silent_console = <0>;
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};
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chosen {
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stdout-path = &serial;
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};
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cpus {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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u-boot,dm-pre-reloc;
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device_type = "cpu";
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compatible = "intel,apl-cpu";
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reg = <0>;
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intel,apic-id = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "intel,apl-cpu";
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reg = <1>;
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intel,apic-id = <2>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "intel,apl-cpu";
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reg = <2>;
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intel,apic-id = <4>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "intel,apl-cpu";
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reg = <3>;
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intel,apic-id = <6>;
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};
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};
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keyboard {
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intel,duplicate-por;
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};
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pci {
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compatible = "pci-x86";
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#address-cells = <3>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
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0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
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0x01000000 0x0 0x1000 0x1000 0 0xefff>;
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u-boot,skip-auto-config-until-reloc;
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host_bridge: host-bridge@0,0 {
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u-boot,dm-pre-reloc;
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reg = <0x00000000 0 0 0 0>;
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compatible = "intel,apl-hostbridge";
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pciex-region-size = <0x10000000>;
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/*
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* Parameters used by the FSP-S binary blob. This is
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* really unfortunate since these parameters mostly
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* relate to drivers but we need them in one place. We
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* could put them in the driver nodes easily, but then
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* would have to scan each node to find them. So just
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* dump them here for now.
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*/
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fsp_s: fsp-s {
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};
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};
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punit@0,1 {
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u-boot,dm-pre-reloc;
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reg = <0x00000800 0 0 0 0>;
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compatible = "intel,apl-punit";
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};
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p2sb: p2sb@d,0 {
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u-boot,dm-pre-reloc;
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reg = <0x02006810 0 0 0 0>;
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compatible = "intel,apl-p2sb";
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early-regs = <IOMAP_P2SB_BAR 0x100000>;
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n {
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compatible = "intel,apl-pinctrl";
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u-boot,dm-pre-reloc;
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intel,p2sb-port-id = <PID_GPIO_N>;
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gpio_n: gpio-n {
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compatible = "intel,gpio";
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u-boot,dm-pre-reloc;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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nw {
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u-boot,dm-pre-reloc;
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compatible = "intel,apl-pinctrl";
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intel,p2sb-port-id = <PID_GPIO_NW>;
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#gpio-cells = <2>;
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gpio_nw: gpio-nw {
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compatible = "intel,gpio";
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u-boot,dm-pre-reloc;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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w {
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u-boot,dm-pre-reloc;
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compatible = "intel,apl-pinctrl";
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intel,p2sb-port-id = <PID_GPIO_W>;
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#gpio-cells = <2>;
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gpio_w: gpio-w {
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compatible = "intel,gpio";
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u-boot,dm-pre-reloc;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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sw {
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u-boot,dm-pre-reloc;
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compatible = "intel,apl-pinctrl";
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intel,p2sb-port-id = <PID_GPIO_SW>;
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#gpio-cells = <2>;
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gpio_sw: gpio-sw {
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compatible = "intel,gpio";
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u-boot,dm-pre-reloc;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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itss {
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u-boot,dm-pre-reloc;
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compatible = "intel,apl-itss";
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intel,p2sb-port-id = <PID_ITSS>;
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intel,pmc-routes = <
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PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
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PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
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PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
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PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
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PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
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PMC_GPE_N_31_0 GPIO_GPE_N_31_0
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PMC_GPE_N_63_32 GPIO_GPE_N_63_32
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PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
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};
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};
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pmc@d,1 {
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u-boot,dm-pre-reloc;
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reg = <0x6900 0 0 0 0>;
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/*
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* Values for BAR0, BAR2 and ACPI_BASE for when PCI
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* auto-configure is not available
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*/
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early-regs = <0xfe042000 0x2000
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0xfe044000 0x2000
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IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
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compatible = "intel,apl-pmc";
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gpe0-dwx-mask = <0xf>;
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gpe0-dwx-shift-base = <4>;
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/*
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* GPE configuration
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* Note that GPE events called out in ASL code rely on
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* this route, i.e., if this route changes then the
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* affected GPE * offset bits also need to be changed.
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* This sets the PMC register GPE_CFG fields.
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*/
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gpe0-dw = <PMC_GPE_N_31_0
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PMC_GPE_N_63_32
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PMC_GPE_SW_31_0>;
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gpe0-sts = <0x20>;
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gpe0-en = <0x30>;
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};
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spi: fast-spi@d,2 {
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u-boot,dm-pre-reloc;
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reg = <0x02006a10 0 0 0 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,fast-spi";
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early-regs = <IOMAP_SPI_BASE 0x1000>;
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intel,hardware-seq = <1>;
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fwstore_spi: spi-flash@0 {
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#size-cells = <1>;
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#address-cells = <1>;
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u-boot,dm-pre-reloc;
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reg = <0>;
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compatible = "winbond,w25q128fw",
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"jedec,spi-nor";
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rw-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x008e0000 0x00010000>;
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u-boot,dm-pre-reloc;
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};
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rw-var-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x008f0000 0x0001000>;
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u-boot,dm-pre-reloc;
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};
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};
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};
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serial: serial@18,2 {
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reg = <0x0200c210 0 0 0 0>;
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u-boot,dm-pre-reloc;
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compatible = "intel,apl-ns16550";
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early-regs = <0xde000000 0x20>;
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reg-shift = <2>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pch: pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,apl-pch";
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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lpc {
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compatible = "intel,apl-lpc";
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cros_ec: cros-ec {
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u-boot,dm-pre-reloc;
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compatible = "google,cros-ec-lpc";
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reg = <0x204 1 0x200 1 0x880 0x80>;
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/*
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* Describes the flash memory within
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* the EC
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*/
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#address-cells = <1>;
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#size-cells = <1>;
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flash@8000000 {
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reg = <0x08000000 0x20000>;
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erase-value = <0xff>;
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};
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};
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};
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};
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};
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};
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&host_bridge {
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/*
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* PL1 override 12000 mW: the energy calculation is wrong with the
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* current VR solution. Experiments show that SoC TDP max (6W) can be
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* reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
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*/
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tdp-pl-override-mw = <12000 15000>;
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early-pads = <
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/* These two are for the debug UART */
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GPIO_46 /* UART2 RX */
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(PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
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(PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
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GPIO_47 /* UART2 TX */
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(PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
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(PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
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GPIO_75 /* I2S1_BCLK -- PCH_WP */
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(PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
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(PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
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/* I2C2 - TPM */
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GPIO_128 /* LPSS_I2C2_SDA */
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(PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
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(PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
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GPIO_129 /* LPSS_I2C2_SCL */
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(PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
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(PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
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GPIO_28 /* TPM IRQ */
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(PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
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PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
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PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
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(PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
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/*
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* WLAN_PE_RST - default to deasserted just in case FSP
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* misbehaves
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*/
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GPIO_122 /* SIO_SPI_2_RXD */
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(PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
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PAD_CFG0_RX_DISABLE | 0)
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(PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
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/* LPC */
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PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
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PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
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PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
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PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
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PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
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PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
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PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
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PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
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PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
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>;
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lpddr4-swizzle = /bits/ 8 <
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/* LP4_PHYS_CH0A */
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/* DQA[0:7] pins of LPDDR4 module */
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6 7 5 4 3 1 0 2
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/* DQA[8:15] pins of LPDDR4 module */
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12 10 11 13 14 8 9 15
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/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
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16 22 23 20 18 17 19 21
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/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
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30 28 29 25 24 26 27 31
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/* LP4_PHYS_CH0B */
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/* DQA[0:7] pins of LPDDR4 module */
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7 3 5 2 6 0 1 4
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/* DQA[8:15] pins of LPDDR4 module */
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9 14 12 13 10 11 8 15
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/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
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20 22 23 16 19 17 18 21
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/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
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28 24 26 27 29 30 31 25
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/* LP4_PHYS_CH1A */
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/* DQA[0:7] pins of LPDDR4 module */
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2 1 6 7 5 4 3 0
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/* DQA[8:15] pins of LPDDR4 module */
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11 10 8 9 12 15 13 14
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/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
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17 23 19 16 21 22 20 18
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/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
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31 29 26 25 28 27 24 30
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/* LP4_PHYS_CH1B */
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/* DQA[0:7] pins of LPDDR4 module */
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4 3 7 5 6 1 0 2
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/* DQA[8:15] pins of LPDDR4 module */
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15 9 8 11 14 13 12 10
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||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
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20 23 22 21 18 19 16 17
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/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
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||||
25 28 30 31 26 27 24 29>;
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};
|
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|
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&fsp_s {
|
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u-boot,dm-pre-proper;
|
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|
||||
/* Disable unused clkreq of PCIe root ports */
|
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pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */
|
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CLKREQ_DISABLED
|
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CLKREQ_DISABLED
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CLKREQ_DISABLED
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CLKREQ_DISABLED
|
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CLKREQ_DISABLED>;
|
||||
|
||||
/*
|
||||
* GPIO for PERST_0
|
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* If the Board has PERST_0 signal, assign the GPIO
|
||||
* If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
|
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*
|
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* This are not used yet, so comment them out for now.
|
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*
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* prt0-gpio = <GPIO_122>;
|
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*
|
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* GPIO for SD card detect
|
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* sdcard-cd-gpio = <GPIO_177>;
|
||||
*/
|
||||
|
||||
/*
|
||||
* Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
|
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* emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
|
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*
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||||
* EMMC TX DATA Delay 1
|
||||
* Refer to EDS-Vol2-22.3
|
||||
* [14:8] steps of delay for HS400, each 125ps
|
||||
* [6:0] steps of delay for SDR104/HS200, each 125ps
|
||||
|
||||
/*
|
||||
* EMMC TX DATA Delay 2
|
||||
* Refer to EDS-Vol2-22.3.
|
||||
* [30:24] steps of delay for SDR50, each 125ps
|
||||
* [22:16] steps of delay for DDR50, each 125ps
|
||||
* [14:8] steps of delay for SDR25/HS50, each 125ps
|
||||
* [6:0] steps of delay for SDR12, each 125ps
|
||||
*/
|
||||
|
||||
/*
|
||||
* EMMC RX CMD/DATA Delay 1
|
||||
* Refer to EDS-Vol2-22.3.
|
||||
* [30:24] steps of delay for SDR50, each 125ps
|
||||
* [22:16] steps of delay for DDR50, each 125ps
|
||||
* [14:8] steps of delay for SDR25/HS50, each 125ps
|
||||
* [6:0] steps of delay for SDR12, each 125ps
|
||||
*/
|
||||
|
||||
/*
|
||||
* EMMC RX CMD/DATA Delay 2
|
||||
* Refer to EDS-Vol2-22.3.
|
||||
* [17:16] stands for Rx Clock before Output Buffer
|
||||
* [14:8] steps of delay for Auto Tuning Mode, each 125ps
|
||||
* [6:0] steps of delay for HS200, each 125ps
|
||||
*/
|
||||
emmc = <0x0c16 0x28162828 0x00181717 0x10008>;
|
||||
|
||||
/* Enable DPTF */
|
||||
dptf-enable;
|
||||
|
||||
/* Enable Audio Clock and Power gating */
|
||||
hdaudio-clk-gate-enable;
|
||||
hdaudio-pwr-gate-enable;
|
||||
hdaudio-bios-config-lockdown;
|
||||
|
||||
/* Enable lpss s0ix */
|
||||
lpss-s0ix-enable;
|
||||
|
||||
/*
|
||||
* TODO(sjg@chromium.org): Move this to the I2C nodes
|
||||
* Intel Common SoC Config
|
||||
*+-------------------+---------------------------+
|
||||
*| Field | Value |
|
||||
*+-------------------+---------------------------+
|
||||
*| I2C0 | Audio |
|
||||
*| I2C2 | TPM |
|
||||
*| I2C3 | Touchscreen |
|
||||
*| I2C4 | Trackpad |
|
||||
*| I2C5 | Digitizer |
|
||||
*+-------------------+---------------------------+
|
||||
*
|
||||
common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise-time-ns = 104,
|
||||
.fall-time-ns = 52,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise-time-ns = 57,
|
||||
.fall-time-ns = 28,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise-time-ns = 76,
|
||||
.fall-time-ns = 164,
|
||||
},
|
||||
.i2c[4] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise-time-ns = 114,
|
||||
.fall-time-ns = 164,
|
||||
.data_hold_time_ns = 350,
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise-time-ns = 152,
|
||||
.fall-time-ns = 30,
|
||||
},
|
||||
}"
|
||||
*/
|
||||
|
||||
/* Minimum SLP S3 assertion width 28ms */
|
||||
slp-s3-assertion-width-usecs = <28000>;
|
||||
|
||||
pads = <
|
||||
/* PCIE_WAKE[0:3]_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
|
||||
PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */
|
||||
PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */
|
||||
PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */
|
||||
|
||||
/* EMMC interface */
|
||||
PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
|
||||
PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
|
||||
|
||||
/* SDIO -- unused */
|
||||
PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */
|
||||
PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */
|
||||
/* Configure SDIO to enable power gating */
|
||||
PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
|
||||
PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */
|
||||
PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */
|
||||
PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */
|
||||
|
||||
/* SDCARD */
|
||||
/* Pull down clock by 20K */
|
||||
PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
|
||||
PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
|
||||
PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
|
||||
PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
|
||||
PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
|
||||
/* Card detect is active LOW with external pull up */
|
||||
PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
|
||||
PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
|
||||
/* CLK feedback, internal signal, needs 20K pull down */
|
||||
PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
|
||||
/* No h/w write proect for uSD cards, pull down by 20K */
|
||||
PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
|
||||
/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
|
||||
PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */
|
||||
|
||||
/* SMBus -- unused */
|
||||
PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */
|
||||
PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */
|
||||
PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */
|
||||
|
||||
/* LPC */
|
||||
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
|
||||
PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
|
||||
PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
|
||||
PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
|
||||
PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
|
||||
PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
|
||||
PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
|
||||
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
|
||||
PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
|
||||
|
||||
/* I2C0 - Audio */
|
||||
PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
|
||||
PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
|
||||
|
||||
/* I2C1 - NFC with external pulls */
|
||||
PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
|
||||
PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
|
||||
|
||||
/* I2C2 - TPM */
|
||||
PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
|
||||
PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
|
||||
|
||||
/* I2C3 - touch */
|
||||
PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
|
||||
PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
|
||||
|
||||
/* I2C4 - trackpad */
|
||||
/* LPSS_I2C4_SDA */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
|
||||
/* LPSS_I2C4_SCL */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
|
||||
|
||||
/* I2C5 -- pen with external pulls */
|
||||
PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
|
||||
PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
|
||||
|
||||
/* I2C6-7 -- unused */
|
||||
PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */
|
||||
PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */
|
||||
PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */
|
||||
PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */
|
||||
|
||||
/* Audio Amp - I2S6 */
|
||||
PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
|
||||
PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
|
||||
PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */
|
||||
PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
|
||||
|
||||
/* NFC Reset */
|
||||
PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */
|
||||
|
||||
PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */
|
||||
|
||||
/* Touch enable */
|
||||
PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */
|
||||
|
||||
PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */
|
||||
PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */
|
||||
PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */
|
||||
|
||||
/* PCIE_CLKREQ[0:3]_N */
|
||||
PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */
|
||||
PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */
|
||||
|
||||
/* OSC_CLK_OUT_[0:4] -- unused */
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
|
||||
|
||||
/* PMU Signals */
|
||||
PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
|
||||
PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
|
||||
PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
|
||||
PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
|
||||
PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
|
||||
PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
|
||||
PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
|
||||
PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
|
||||
PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
|
||||
PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */
|
||||
PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
|
||||
PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
|
||||
|
||||
/* DDI[0:1] SDA and SCL -- unused */
|
||||
PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */
|
||||
PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */
|
||||
PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */
|
||||
PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */
|
||||
|
||||
/* MIPI I2C -- unused */
|
||||
PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */
|
||||
PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */
|
||||
|
||||
/* Panel 0 control */
|
||||
PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
|
||||
PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
|
||||
PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
|
||||
|
||||
/* Panel 1 control -- unused */
|
||||
PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
|
||||
PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
|
||||
PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
|
||||
|
||||
/* Hot plug detect */
|
||||
PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
|
||||
PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
|
||||
|
||||
/* MDSI signals -- unused */
|
||||
PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */
|
||||
PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */
|
||||
|
||||
/* USB overcurrent pins */
|
||||
PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
|
||||
PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
|
||||
|
||||
/* PMC SPI -- almost entirely unused */
|
||||
PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
|
||||
PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
|
||||
PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
|
||||
|
||||
/* PMIC Signals Unused signals related to an old PMIC interface */
|
||||
PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
|
||||
PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */
|
||||
PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
|
||||
PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
|
||||
PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
|
||||
PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
|
||||
|
||||
/* I2S1 -- largely unused */
|
||||
PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */
|
||||
PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */
|
||||
PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */
|
||||
PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */
|
||||
PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
|
||||
|
||||
/* DMIC or I2S4 */
|
||||
/* AVS_DMIC_CLK_A1 */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
|
||||
PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
|
||||
PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */
|
||||
PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */
|
||||
PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
|
||||
|
||||
/* I2S2 -- Headset amp */
|
||||
PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */
|
||||
PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */
|
||||
PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */
|
||||
PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */
|
||||
PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */
|
||||
|
||||
/* I2S3 -- largely unused */
|
||||
PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */
|
||||
PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */
|
||||
PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */
|
||||
|
||||
/* Fast SPI */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
|
||||
PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */
|
||||
PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
|
||||
PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */
|
||||
PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */
|
||||
|
||||
/* SIO_SPI_0 - Used for FP */
|
||||
PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */
|
||||
PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */
|
||||
PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */
|
||||
PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */
|
||||
|
||||
/* SIO_SPI_1 -- largely unused */
|
||||
PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */
|
||||
PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */
|
||||
PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */
|
||||
/* Headset interrupt */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
|
||||
PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */
|
||||
|
||||
/* SIO_SPI_2 -- unused */
|
||||
PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */
|
||||
PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */
|
||||
PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */
|
||||
PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */
|
||||
/* WLAN_PE_RST - default to deasserted */
|
||||
PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */
|
||||
PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */
|
||||
|
||||
/* Debug tracing */
|
||||
PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
|
||||
PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */
|
||||
PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
|
||||
PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
|
||||
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
|
||||
PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */
|
||||
PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */
|
||||
PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
|
||||
PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
|
||||
PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */
|
||||
PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
|
||||
PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
|
||||
PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
|
||||
PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */
|
||||
PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
|
||||
PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
|
||||
PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */
|
||||
PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
|
||||
PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */
|
||||
PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */
|
||||
PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */
|
||||
PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */
|
||||
|
||||
/* LPSS_UART[0:2] */
|
||||
PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
|
||||
/* Next 2 are straps */
|
||||
PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */
|
||||
PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */
|
||||
PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */
|
||||
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */
|
||||
PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */
|
||||
PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */
|
||||
PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
|
||||
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
|
||||
PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */
|
||||
PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
|
||||
|
||||
/* Camera interface -- completely unused */
|
||||
PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */
|
||||
PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */
|
||||
PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */
|
||||
PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */
|
||||
PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */
|
||||
PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */
|
||||
PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */
|
||||
PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */
|
||||
PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */
|
||||
PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */
|
||||
PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */
|
||||
PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */
|
||||
>;
|
||||
};
|
||||
@ -8,6 +8,20 @@ choice
|
||||
prompt "Mainboard model"
|
||||
optional
|
||||
|
||||
config TARGET_CHROMEBOOK_CORAL
|
||||
bool "Chromebook coral"
|
||||
help
|
||||
This is a range of Intel-based laptops released in 2018. They use an
|
||||
Intel Apollo Lake SoC. The design supports WiFi, 4GB to 16GB of
|
||||
LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB),
|
||||
up two cameras (front-facing 720p and another 5MP option), USB SD
|
||||
reader, microphone and speakers. It also includes two USB 3 Type A and
|
||||
two Type C ports. The latter are used as power input and can also
|
||||
charge external devices as well as a 4K external display. There is a
|
||||
Chrome OS EC connected on LPC, a Cr50 secure chip from Google and
|
||||
various display options. OEMs products include Acer Chromebook 11
|
||||
(e.g. C732, CB11, CP311) and Lenovo Chromebook (100e, 300e, 500e).
|
||||
|
||||
config TARGET_CHROMEBOOK_LINK
|
||||
bool "Chromebook link"
|
||||
help
|
||||
@ -62,6 +76,7 @@ config TARGET_CHROMEBOOK_SAMUS_TPL
|
||||
|
||||
endchoice
|
||||
|
||||
source "board/google/chromebook_coral/Kconfig"
|
||||
source "board/google/chromebook_link/Kconfig"
|
||||
source "board/google/chromebox_panther/Kconfig"
|
||||
source "board/google/chromebook_samus/Kconfig"
|
||||
|
||||
43
board/google/chromebook_coral/Kconfig
Normal file
43
board/google/chromebook_coral/Kconfig
Normal file
@ -0,0 +1,43 @@
|
||||
if TARGET_CHROMEBOOK_CORAL
|
||||
|
||||
config SYS_BOARD
|
||||
default "chromebook_coral"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "google"
|
||||
|
||||
config SYS_SOC
|
||||
default "apollolake"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "chromebook_coral"
|
||||
|
||||
config SYS_TEXT_BASE
|
||||
default 0xffe00000
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select X86_RESET_VECTOR
|
||||
select INTEL_APOLLOLAKE
|
||||
select BOARD_ROMSIZE_KB_16384
|
||||
|
||||
config PCIE_ECAM_BASE
|
||||
default 0xf0000000
|
||||
|
||||
config EARLY_POST_CROS_EC
|
||||
bool "Enable early post to Chrome OS EC"
|
||||
help
|
||||
Allow post codes to be sent to the Chroem OS EC early during boot,
|
||||
to enable monitoring of the boot and debugging when things go wrong.
|
||||
With this option enabled, the EC console can be used to watch post
|
||||
codes the first part of boot.
|
||||
|
||||
config SYS_CAR_ADDR
|
||||
hex
|
||||
default 0xfef00000
|
||||
|
||||
config SYS_CAR_SIZE
|
||||
hex
|
||||
default 0xc0000
|
||||
|
||||
endif
|
||||
6
board/google/chromebook_coral/MAINTAINERS
Normal file
6
board/google/chromebook_coral/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
||||
CHROMEBOOK_CORAL_BOARD
|
||||
M: Simon Glass <sjg@chromium.org>
|
||||
S: Maintained
|
||||
F: board/google/chromebook_coral/
|
||||
F: include/configs/chromebook_coral.h
|
||||
F: configs/chromebook_coral_defconfig
|
||||
5
board/google/chromebook_coral/Makefile
Normal file
5
board/google/chromebook_coral/Makefile
Normal file
@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2019 Google LLC
|
||||
|
||||
obj-y += coral.o
|
||||
19
board/google/chromebook_coral/coral.c
Normal file
19
board/google/chromebook_coral/coral.c
Normal file
@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2019 Google LLC
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This function is needed if CONFIG_CMDLINE is not enabled */
|
||||
int board_run_command(const char *cmdline)
|
||||
{
|
||||
printf("No command line\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
102
configs/chromebook_coral_defconfig
Normal file
102
configs/chromebook_coral_defconfig
Normal file
@ -0,0 +1,102 @@
|
||||
CONFIG_X86=y
|
||||
CONFIG_SYS_TEXT_BASE=0x1110000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x3d00
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
|
||||
CONFIG_NR_DRAM_BANKS=8
|
||||
CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000
|
||||
CONFIG_DEBUG_UART_BOARD_INIT=y
|
||||
CONFIG_DEBUG_UART_BASE=0xde000000
|
||||
CONFIG_DEBUG_UART_CLOCK=1843200
|
||||
CONFIG_VENDOR_GOOGLE=y
|
||||
CONFIG_TARGET_CHROMEBOOK_CORAL=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FSP_VERSION2=y
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_INTEL_CAR_CQOS=y
|
||||
CONFIG_X86_OFFSET_U_BOOT=0xffe00000
|
||||
CONFIG_X86_OFFSET_SPL=0xffe80000
|
||||
CONFIG_SPL_TEXT_BASE=0xfef10000
|
||||
CONFIG_BOOTSTAGE=y
|
||||
CONFIG_SPL_BOOTSTAGE=y
|
||||
CONFIG_TPL_BOOTSTAGE=y
|
||||
CONFIG_BOOTSTAGE_REPORT=y
|
||||
CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10
|
||||
CONFIG_BOOTSTAGE_STASH=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro earlyprintk console=tty0 console=ttyS0,115200"
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
CONFIG_SPL_LOG=y
|
||||
CONFIG_LOG_DEFAULT_LEVEL=7
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_LAST_STAGE_INIT=y
|
||||
CONFIG_BLOBLIST=y
|
||||
# CONFIG_TPL_BLOBLIST is not set
|
||||
CONFIG_BLOBLIST_ADDR=0x100000
|
||||
CONFIG_HANDOFF=y
|
||||
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_CPU_SUPPORT=y
|
||||
CONFIG_SPL_PCI=y
|
||||
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_CPU=y
|
||||
CONFIG_CMD_PMC=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_SATA=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_SOUND=y
|
||||
CONFIG_CMD_BOOTSTAGE=y
|
||||
CONFIG_CMD_TPM=y
|
||||
CONFIG_CMD_TPM_TEST=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
# CONFIG_SPL_MAC_PARTITION is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_ISO_PARTITION=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral"
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_DW=y
|
||||
CONFIG_TPL_MISC=y
|
||||
CONFIG_CROS_EC=y
|
||||
CONFIG_CROS_EC_LPC=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_X86_PCH7 is not set
|
||||
# CONFIG_X86_PCH9 is not set
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_SPL_PINCTRL_FULL is not set
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SOUND_I8254=y
|
||||
CONFIG_SOUND_RT5677=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ICH_SPI=y
|
||||
CONFIG_TPL_SYSRESET=y
|
||||
CONFIG_TPM_TIS_LPC=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_KEYBOARD=y
|
||||
CONFIG_SPL_FS_CBFS=y
|
||||
# CONFIG_SPL_USE_TINY_PRINTF is not set
|
||||
CONFIG_TPL_USE_TINY_PRINTF=y
|
||||
CONFIG_CMD_DHRYSTONE=y
|
||||
CONFIG_TPM=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
241
doc/board/google/chromebook_coral.rst
Normal file
241
doc/board/google/chromebook_coral.rst
Normal file
@ -0,0 +1,241 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Simon Glass <sjg@chromium.org>
|
||||
|
||||
Chromebook Coral
|
||||
================
|
||||
|
||||
Coral is a Chromebook (or really about 20 different Chromebooks) which use the
|
||||
Intel Apollo Lake platform (APL). The 'reef' Chromebooks use the same APL SoC so
|
||||
should also work. Some later ones based on Glacier Lake (GLK) need various
|
||||
changes in GPIOs, etc. but are very similar.
|
||||
|
||||
It is hoped that this port can enable ports to embedded APL boards which are
|
||||
starting to appear.
|
||||
|
||||
Note that booting U-Boot on APL is already supported by coreboot and
|
||||
Slim Bootloader. This documentation refers to a 'bare metal' port.
|
||||
|
||||
|
||||
Boot flow - TPL
|
||||
---------------
|
||||
|
||||
Apollo Lake boots via an IFWI (Integrated Firmware Image). TPL is placed in
|
||||
this, in the IBBL entry.
|
||||
|
||||
On boot, an on-chip microcontroller called the CSE (Converged Security Engine)
|
||||
sets up some SDRAM at ffff8000 and loads the TPL image to that address. The
|
||||
SRAM extends up to the top of 32-bit address space, but the last 2KB is the
|
||||
start16 region, so the TPL image must be 30KB at most, and CONFIG_TPL_TEXT_BASE
|
||||
must be ffff8000. Actually the start16 region is small and it could probably
|
||||
move from f800 to fe00, providing another 1.5KB, but TPL is only about 19KB so
|
||||
there is no need to change it at present. The size limit is enforced by
|
||||
CONFIG_TPL_SIZE_LIMIT to avoid producing images that won't boot.
|
||||
|
||||
TPL (running from start.S) first sets up CAR (Cache-as-RAM) which provides
|
||||
larger area of RAM for use while booting. CAR is mapped at CONFIG_SYS_CAR_ADDR
|
||||
(fef00000) and is 768KB in size. It then sets up the stack in the botttom 64KB
|
||||
of this space (i.e. below fef10000). This means that the stack and early
|
||||
malloc() region in TPL can be 64KB at most.
|
||||
|
||||
TPL operates without CONFIG_TPL_PCI enabled so PCI config access must use the
|
||||
x86-specific functions pci_x86_write_config(), etc. SPL creates a simple-bus
|
||||
device so that PCI devices are bound by driver model. Then arch_cpu_init_tpl()
|
||||
is called to early init on various devices. This includes placing PCI devices
|
||||
at hard-coded addresses in the memory map. PCI auto-config is not used.
|
||||
|
||||
Most of the 16KB ROM is mapped into the very top of memory, except for the
|
||||
Intel descriptor (first 4KB) and the space for SRAM as above.
|
||||
|
||||
TPL does not set up a bloblist since at present it does not have anything to
|
||||
pass to SPL.
|
||||
|
||||
Once TPL is done it loads SPL from ROM using either the memory-mapped SPI or by
|
||||
using the Intel fast SPI driver. SPL is loaded into CAR, at the address given
|
||||
by CONFIG_SPL_TEXT_BASE, which is normally fef10000.
|
||||
|
||||
Note that booting using the SPI driver results in an TPL image that is about
|
||||
26KB in size instead of 19KB. Also boot speed is worse by about 340ms. If you
|
||||
really want to use the driver, enable CONFIG_APL_SPI_FLASH_BOOT and set
|
||||
BOOT_FROM_FAST_SPI_FLASH to true[2].
|
||||
|
||||
|
||||
Boot flow - SPL
|
||||
---------------
|
||||
|
||||
SPL (running from start_from_tpl.S) continues to use the same stack as TPL.
|
||||
It calls arch_cpu_init_spl() to set up a few devices, then init_dram() loads
|
||||
the FSP-M binary into CAR and runs to, to set up SDRAM. The address of the
|
||||
output 'HOB' list (Hand-off-block) is stored into gd->arch.hob_list for parsing.
|
||||
There is a 2GB chunk of SDRAM starting at 0 and the rest is at 4GB.
|
||||
|
||||
PCI auto-config is not used in SPL either, but CONFIG_SPL_PCI is defined, so
|
||||
proper PCI access is available and normal dm_pci_read_config() calls can be
|
||||
used. However PCI auto-config is not used so the same static memory mapping set
|
||||
up by TPL is still active.
|
||||
|
||||
SPL on x86 always runs with CONFIG_SPL_SEPARATE_BSS=y and BSS is at 120000
|
||||
(see u-boot-spl.lds). This works because SPL doesn't access BSS until after
|
||||
board_init_r(), as per the rules, and DRAM is available then.
|
||||
|
||||
SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper.
|
||||
This includes a pointer to the HOB list as well as DRAM information. See
|
||||
struct arch_spl_handoff. The bloblist address is set by CONFIG_BLOBLIST_ADDR,
|
||||
normally 100000.
|
||||
|
||||
SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent
|
||||
boots. Be warned that SPL can take 30 seconds without this cache! This is a
|
||||
known issue with Intel SoCs with modern DRAM and apparently cannot be improved.
|
||||
The MRC caches are used to work around this.
|
||||
|
||||
Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which
|
||||
is normally 1110000. Note that CAR is still active.
|
||||
|
||||
|
||||
Boot flow - U-Boot pre-relocation
|
||||
---------------------------------
|
||||
|
||||
U-Boot (running from start_from_spl.S) starts running in RAM and uses the same
|
||||
stack as SPL. It does various init activities before relocation. Notably
|
||||
arch_cpu_init_dm() sets up the pin muxing for the chip using a very large table
|
||||
in the device tree.
|
||||
|
||||
PCI auto-config is not used before relocation, but CONFIG_PCI of course is
|
||||
defined, so proper PCI access is available. The same static memory mapping set
|
||||
up by TPL is still active until relocation.
|
||||
|
||||
As per usual, U-Boot allocates memory at the top of available RAM (a bit below
|
||||
2GB in this case) and copies things there ready to relocate itself. Notably
|
||||
reserve_arch() does not reserve space for the HOB list returned by FSP-M since
|
||||
this is already located in RAM.
|
||||
|
||||
U-Boot then shuts down CAR and jumps to its relocated version.
|
||||
|
||||
|
||||
Boot flow - U-Boot post-relocation
|
||||
---------------------------------
|
||||
|
||||
U-Boot starts up normally, running near the top of RAM. After driver model is
|
||||
running, arch_fsp_init_r() is called which loads and runs the FSP-S binary.
|
||||
This updates the HOB list to include graphics information, used by the fsp_video
|
||||
driver.
|
||||
|
||||
PCI autoconfig is done and a few devices are probed to complete init. Most
|
||||
others are started only when they are used.
|
||||
|
||||
Note that FSP-S is supposed to run after CAR has been shut down, which happens
|
||||
immediately before U-Boot starts up in its relocated position. Therefore we
|
||||
cannot run FSP-S before relocation. On the other hand we must run it before
|
||||
PCI auto-config is done, since FSP-S may show or hide devices. The first device
|
||||
that probes PCI after relocation is the serial port, in initr_serial(), so FSP-S
|
||||
must run before that. A corollary is that loading FSP-S must be done without
|
||||
using the SPI driver, to avoid probing PCI and causing an autoconfig, so
|
||||
memory-mapped reading is always used for FSP-S.
|
||||
|
||||
It would be possible to tear down CAR in SPL instead of U-Boot. The SPL handoff
|
||||
information could make sure it does not include any pointers into CAR (in fact
|
||||
it doesn't). But tearing down CAR in U-Boot allows the initial state used by TPL
|
||||
and SPL to be read by U-Boot, which seems useful. It also matches how older
|
||||
platforms start up (those that don't use SPL).
|
||||
|
||||
|
||||
Performance
|
||||
-----------
|
||||
|
||||
Bootstage is used through all phases of U-Boot to keep accurate timimgs for
|
||||
boot. Use 'bootstage report' in U-Boot to see the report, e.g.:
|
||||
|
||||
Timer summary in microseconds (16 records):
|
||||
Mark Elapsed Stage
|
||||
0 0 reset
|
||||
155,325 155,325 TPL
|
||||
204,014 48,689 end TPL
|
||||
204,385 371 SPL
|
||||
738,633 534,248 end SPL
|
||||
739,161 528 board_init_f
|
||||
842,764 103,603 board_init_r
|
||||
1,166,233 323,469 main_loop
|
||||
1,166,283 50 id=175
|
||||
|
||||
Accumulated time:
|
||||
62 fast_spi
|
||||
202 dm_r
|
||||
7,779 dm_spl
|
||||
15,555 dm_f
|
||||
208,357 fsp-m
|
||||
239,847 fsp-s
|
||||
292,143 mmap_spi
|
||||
|
||||
CPU performance is about 3500 DMIPS:
|
||||
|
||||
=> dhry
|
||||
1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS
|
||||
|
||||
|
||||
Partial memory map
|
||||
------------------
|
||||
|
||||
ffffffff Top of ROM (and last byte of 32-bit address space)
|
||||
ffff8000 TPL loaded here (from IFWI)
|
||||
ff000000 Bottom of ROM
|
||||
fefc000 Top of CAR region
|
||||
fef96000 Stack for FSP-M
|
||||
fef40000 59000 FSP-M
|
||||
fef11000 SPL loaded here
|
||||
fef10000 CONFIG_BLOBLIST_ADDR
|
||||
fef10000 Stack top in TPL, SPL and U-Boot before relocation
|
||||
fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR
|
||||
fef00000 Base of CAR region
|
||||
|
||||
f0000 CONFIG_ROM_TABLE_ADDR
|
||||
120000 BSS (defined in u-boot-spl.lds)
|
||||
200000 FSP-S (which is run after U-Boot is relocated)
|
||||
1110000 CONFIG_SYS_TEXT_BASE
|
||||
|
||||
|
||||
Supported peripherals
|
||||
---------------------
|
||||
|
||||
- UART
|
||||
- SPI flash
|
||||
- Video
|
||||
- MMC (dev 0) and micro-SD (dev 1)
|
||||
- Chrome OS EC
|
||||
- Keyboard
|
||||
- USB
|
||||
|
||||
|
||||
To do
|
||||
-----
|
||||
|
||||
- Finish peripherals
|
||||
- left-side USB
|
||||
- USB-C
|
||||
- Cr50 (security chip: a basic driver is running but not included here)
|
||||
- I2C (driver exists but not enabled in device tree)
|
||||
- Sound (Intel I2S support exists, but need da7219 driver)
|
||||
- RTC (driver exists but not enabled in device tree)
|
||||
- Various minor features supported by LPC, etc.
|
||||
- Booting Chrome OS, e.g. with verified boot
|
||||
- Integrate with Chrome OS vboot
|
||||
- Improvements to booting from coreboot (i.e. as a coreboot target)
|
||||
- Use FSP-T binary instead of our own CAR implementation
|
||||
- Use the official FSP package instead of the coreboot one
|
||||
- Enable all CPU cores
|
||||
- Suspend / resume
|
||||
- ACPI
|
||||
|
||||
|
||||
Credits
|
||||
-------
|
||||
|
||||
This is a spare-time project conducted slowly over a long period of time.
|
||||
|
||||
Much of the code for this port came from Coreboot, an open-source firmware
|
||||
project similar to U-Boot's SPL in terms of features.
|
||||
|
||||
Also see [2] for information about the boot flow used by coreboot. It is
|
||||
similar, but has an extra postcar stage. U-Boot doesn't need this since it
|
||||
supports relocating itself in memory.
|
||||
|
||||
|
||||
[2] Intel PDF https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf
|
||||
@ -6,5 +6,6 @@ Google
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
chromebook_coral
|
||||
chromebook_link
|
||||
chromebook_samus
|
||||
|
||||
32
include/configs/chromebook_coral.h
Normal file
32
include/configs/chromebook_coral.h
Normal file
@ -0,0 +1,32 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 Google LLC
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board-specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"fatload mmc 1:c 1000000 syslinux/vmlinuz.A; zboot 1000000"
|
||||
|
||||
#include <configs/x86-common.h>
|
||||
#include <configs/x86-chromebook.h>
|
||||
|
||||
#undef CONFIG_STD_DEVICES_SETTINGS
|
||||
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
|
||||
"stdout=vidconsole,serial\0" \
|
||||
"stderr=vidconsole,serial\0"
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x1000
|
||||
#define CONFIG_ENV_OFFSET 0x003f8000
|
||||
|
||||
#define CONFIG_TPL_TEXT_BASE 0xffff8000
|
||||
|
||||
#define CONFIG_SYS_NS16550_MEM32
|
||||
#undef CONFIG_SYS_NS16550_PORT_MAPPED
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user