pmu: stpmic1: change specific NVM api to MISC
Use MISC u-class to export the NVM register (starting at 0xF8 offset) and avoid specific API. - SHADOW have offset < 0. - NVM have register > 0 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay
Patrice Chotard
parent
0c8620d2ff
commit
234a60244c
@ -40,8 +40,17 @@ int fuse_read(u32 bank, u32 word, u32 *val)
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#ifdef CONFIG_PMIC_STPMIC1
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case STM32MP_NVM_BANK:
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stpmic1_nvm),
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&dev);
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if (ret)
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return ret;
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*val = 0;
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ret = stpmic1_shadow_read_byte(word, (u8 *)val);
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ret = misc_read(dev, -word, val, 1);
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if (ret != 1)
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ret = -EINVAL;
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else
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ret = 0;
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break;
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#endif /* CONFIG_PMIC_STPMIC1 */
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@ -76,7 +85,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
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#ifdef CONFIG_PMIC_STPMIC1
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case STM32MP_NVM_BANK:
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ret = stpmic1_nvm_write_byte(word, (u8 *)&val);
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stpmic1_nvm),
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&dev);
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if (ret)
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return ret;
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ret = misc_write(dev, word, &val, 1);
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if (ret != 1)
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ret = -EINVAL;
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else
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ret = 0;
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break;
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#endif /* CONFIG_PMIC_STPMIC1 */
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@ -110,8 +128,17 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
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#ifdef CONFIG_PMIC_STPMIC1
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case STM32MP_NVM_BANK:
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stpmic1_nvm),
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&dev);
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if (ret)
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return ret;
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*val = 0;
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ret = stpmic1_nvm_read_byte(word, (u8 *)val);
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ret = misc_read(dev, word, val, 1);
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if (ret != 1)
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ret = -EINVAL;
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else
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ret = 0;
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break;
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#endif /* CONFIG_PMIC_STPMIC1 */
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@ -146,7 +173,16 @@ int fuse_override(u32 bank, u32 word, u32 val)
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#ifdef CONFIG_PMIC_STPMIC1
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case STM32MP_NVM_BANK:
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ret = stpmic1_shadow_write_byte(word, (u8 *)&val);
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stpmic1_nvm),
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&dev);
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if (ret)
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return ret;
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ret = misc_write(dev, -word, &val, 1);
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if (ret != 1)
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ret = -EINVAL;
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else
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ret = 0;
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break;
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#endif /* CONFIG_PMIC_STPMIC1 */
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@ -7,6 +7,7 @@
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <misc.h>
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#include <sysreset.h>
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#include <dm/device.h>
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#include <dm/lists.h>
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@ -69,6 +70,7 @@ static int stpmic1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
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static int stpmic1_bind(struct udevice *dev)
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{
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int ret;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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ofnode regulators_node;
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int children;
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@ -86,6 +88,13 @@ static int stpmic1_bind(struct udevice *dev)
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dev_dbg(dev, "no child found\n");
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#endif /* DM_REGULATOR */
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if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
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ret = device_bind_driver(dev, "stpmic1-nvm",
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"stpmic1-nvm", NULL);
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if (ret)
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return ret;
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}
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if (CONFIG_IS_ENABLED(SYSRESET))
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return device_bind_driver(dev, "stpmic1-sysreset",
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"stpmic1-sysreset", NULL);
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@ -113,32 +122,38 @@ U_BOOT_DRIVER(pmic_stpmic1) = {
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};
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#ifndef CONFIG_SPL_BUILD
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static int stpmic1_nvm_rw(u8 addr, u8 *buf, int buf_len, enum pmic_nvm_op op)
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static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len,
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enum pmic_nvm_op op)
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{
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struct udevice *dev;
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unsigned long timeout;
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u8 cmd = STPMIC1_NVM_CMD_READ;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_PMIC,
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DM_GET_DRIVER(pmic_stpmic1), &dev);
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if (ret)
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/* No PMIC on power discrete board */
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return -EOPNOTSUPP;
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int ret, len = buf_len;
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if (addr < STPMIC1_NVM_START_ADDRESS)
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return -EACCES;
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if (addr + buf_len > STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE)
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len = STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE - addr;
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if (op == SHADOW_READ)
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return pmic_read(dev, addr, buf, buf_len);
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if (op == SHADOW_READ) {
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ret = pmic_read(dev, addr, buf, len);
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if (ret < 0)
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return ret;
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else
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return len;
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}
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if (op == SHADOW_WRITE)
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return pmic_write(dev, addr, buf, buf_len);
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if (op == SHADOW_WRITE) {
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ret = pmic_write(dev, addr, buf, len);
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if (ret < 0)
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return ret;
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else
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return len;
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}
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if (op == NVM_WRITE) {
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cmd = STPMIC1_NVM_CMD_PROGRAM;
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ret = pmic_write(dev, addr, buf, buf_len);
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ret = pmic_write(dev, addr, buf, len);
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if (ret < 0)
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return ret;
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}
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@ -168,51 +183,50 @@ static int stpmic1_nvm_rw(u8 addr, u8 *buf, int buf_len, enum pmic_nvm_op op)
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return -ETIMEDOUT;
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if (op == NVM_READ) {
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ret = pmic_read(dev, addr, buf, buf_len);
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ret = pmic_read(dev, addr, buf, len);
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if (ret < 0)
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return ret;
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}
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return 0;
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return len;
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}
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int stpmic1_shadow_read_byte(u8 addr, u8 *buf)
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static int stpmic1_nvm_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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return stpmic1_nvm_rw(addr, buf, 1, SHADOW_READ);
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enum pmic_nvm_op op = NVM_READ;
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if (offset < 0) {
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op = SHADOW_READ;
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offset = -offset;
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}
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return stpmic1_nvm_rw(dev->parent, offset, buf, size, op);
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}
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int stpmic1_shadow_write_byte(u8 addr, u8 *buf)
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static int stpmic1_nvm_write(struct udevice *dev, int offset,
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const void *buf, int size)
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{
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return stpmic1_nvm_rw(addr, buf, 1, SHADOW_WRITE);
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enum pmic_nvm_op op = NVM_WRITE;
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if (offset < 0) {
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op = SHADOW_WRITE;
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offset = -offset;
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}
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return stpmic1_nvm_rw(dev->parent, offset, (void *)buf, size, op);
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}
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int stpmic1_nvm_read_byte(u8 addr, u8 *buf)
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{
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return stpmic1_nvm_rw(addr, buf, 1, NVM_READ);
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}
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static const struct misc_ops stpmic1_nvm_ops = {
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.read = stpmic1_nvm_read,
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.write = stpmic1_nvm_write,
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};
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int stpmic1_nvm_write_byte(u8 addr, u8 *buf)
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{
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return stpmic1_nvm_rw(addr, buf, 1, NVM_WRITE);
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}
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int stpmic1_nvm_read_all(u8 *buf, int buf_len)
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{
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if (buf_len != STPMIC1_NVM_SIZE)
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return -EINVAL;
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return stpmic1_nvm_rw(STPMIC1_NVM_START_ADDRESS,
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buf, buf_len, NVM_READ);
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}
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int stpmic1_nvm_write_all(u8 *buf, int buf_len)
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{
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if (buf_len != STPMIC1_NVM_SIZE)
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return -EINVAL;
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return stpmic1_nvm_rw(STPMIC1_NVM_START_ADDRESS,
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buf, buf_len, NVM_WRITE);
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}
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U_BOOT_DRIVER(stpmic1_nvm) = {
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.name = "stpmic1-nvm",
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.id = UCLASS_MISC,
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.ops = &stpmic1_nvm_ops,
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};
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#endif /* CONFIG_SPL_BUILD */
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#ifdef CONFIG_SYSRESET
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@ -108,11 +108,4 @@ enum {
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STPMIC1_PWR_SW2,
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STPMIC1_MAX_PWR_SW,
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};
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int stpmic1_shadow_read_byte(u8 addr, u8 *buf);
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int stpmic1_shadow_write_byte(u8 addr, u8 *buf);
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int stpmic1_nvm_read_byte(u8 addr, u8 *buf);
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int stpmic1_nvm_write_byte(u8 addr, u8 *buf);
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int stpmic1_nvm_read_all(u8 *buf, int buf_len);
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int stpmic1_nvm_write_all(u8 *buf, int buf_len);
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#endif
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