ARM: socfpga: vining_fpga: Rename VINING|FPGA
The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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@ -8,7 +8,7 @@
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#include <dt-bindings/input/input.h>
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/ {
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model = "samtec VIN|ING FPGA";
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model = "Softing VIN|ING FPGA";
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compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
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chosen {
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@ -100,8 +100,8 @@ config TARGET_SOCFPGA_IS1
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bool "IS1 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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bool "samtec VIN|ING FPGA (Cyclone V)"
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config TARGET_SOCFPGA_SOFTING_VINING_FPGA
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bool "Softing VIN|ING FPGA (Cyclone V)"
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select BOARD_LATE_INIT
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select TARGET_SOCFPGA_CYCLONE5
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@ -145,7 +145,7 @@ config SYS_BOARD
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default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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default "sr1500" if TARGET_SOCFPGA_SR1500
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default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
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default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
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config SYS_VENDOR
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default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
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@ -155,7 +155,7 @@ config SYS_VENDOR
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default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
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default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
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default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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@ -178,6 +178,6 @@ config SYS_CONFIG_NAME
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default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
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default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
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default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
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endif
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@ -1,6 +1,6 @@
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CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
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CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y
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CONFIG_SPL_TEXT_BASE=0xFFFF0000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_FIT=y
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@ -35,7 +35,7 @@ CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);"
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CONFIG_CMD_UBI=y
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# CONFIG_ISO_PARTITION is not set
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# CONFIG_EFI_PARTITION is not set
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@ -86,7 +86,7 @@ CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_MANUFACTURER="samtec"
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CONFIG_USB_GADGET_MANUFACTURER="softing"
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CONFIG_USB_GADGET_VENDOR_NUM=0x0525
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CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
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CONFIG_USB_GADGET_DWC2_OTG=y
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@ -1,9 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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* Copyright (C) 2015-2019 Marek Vasut <marex@denx.de>
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*/
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#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__
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#define __CONFIG_SAMTEC_VINING_FPGA_H__
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#ifndef __CONFIG_SOFTING_VINING_FPGA_H__
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#define __CONFIG_SOFTING_VINING_FPGA_H__
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#include <asm/arch/base_addr_ac5.h>
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@ -50,8 +50,8 @@
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"1m(u-boot)," \
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"64k(env1)," \
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"64k(env2)," \
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"256k(samtec1)," \
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"256k(samtec2)," \
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"256k(softing1)," \
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"256k(softing2)," \
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"-(rcvrfs)\0" /* Recovery */ \
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"mtdparts_1=ff705000.spi.1:" \
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"32m(rootfs)," \
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@ -150,4 +150,4 @@
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/* The rest of the configuration is shared */
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#include <configs/socfpga_common.h>
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#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */
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#endif /* __CONFIG_SOFTING_VINING_FPGA_H__ */
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