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riscv: andes_plic: Fix some wrong configurations

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Fix two wrong settings of andes plic driver as below:

1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
   int can help to fix wrong plic enabling setting in RV64.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
This commit is contained in:
Rick Chen 2019-11-14 13:52:24 +08:00 committed by Andes
parent 7e24518c90
commit 43a0832ba0
1 changed files with 7 additions and 4 deletions
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11
arch/riscv/lib/andes_plic.c
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@ -19,7 +19,7 @@
#include <cpu.h>
/* pending register */
#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8)
#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
/* enable register */
#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
/* claim register */
@ -46,7 +46,7 @@ static int init_plic(void);
static int enable_ipi(int hart)
{
int en;
unsigned int en;
en = ENABLE_HART_IPI >> hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
@ -94,10 +94,13 @@ static int init_plic(void)
int riscv_send_ipi(int hart)
{
unsigned int ipi;
PLIC_BASE_GET();
writel(SEND_IPI_TO_HART(hart),
(void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
return 0;
}