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clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()

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Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
This commit is contained in:
Giulio Benetti 2020-01-17 13:06:40 +01:00 committed by Lukasz Majewski
parent 90cbfa50c2
commit 3391e77729
1 changed files with 8 additions and 2 deletions
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10
drivers/clk/imx/clk-pllv3.c
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@ -121,10 +121,16 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
unsigned long parent_rate = clk_get_parent_rate(clk);
unsigned long min_rate = parent_rate * 54 / 2;
unsigned long max_rate = parent_rate * 108 / 2;
unsigned long min_rate;
unsigned long max_rate;
u32 val, div;
if (parent_rate == 0)
return -EINVAL;
min_rate = parent_rate * 54 / 2;
max_rate = parent_rate * 108 / 2;
if (rate < min_rate || rate > max_rate)
return -EINVAL;