leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm: zynq: Remove low level UART setting

Browse Source 
There is no reason to do serial initializationin low level code. Uart
driver does it already based on DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2019-12-06 09:33:25 +01:00
parent 84d2bbf082
commit 47446a3c66
18 changed files with 0 additions and 1046 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
View File

@ -220,10 +220,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
EMIT_WRITE(0XF8000004, 0x0000767BU),
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),

8
board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
View File

@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0XF8F00200, 1),

8
board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
View File

@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),

8
board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
View File

@ -171,14 +171,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0XF8F00200, 1),

12
board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
View File

@ -227,10 +227,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0XF8F00200, 1),
@ -474,10 +470,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0XF8F00200, 1),
@ -714,10 +706,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0XF8F00200, 1),

4
board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
View File

@ -219,10 +219,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),

186
board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
View File

@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U
@ -7894,70 +7836,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. IRMODE = 0x0
// .. ==> 0XE0001004[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// .. UCLKEN = 0x0
// .. ==> 0XE0001004[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U
@ -12094,70 +11972,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. IRMODE = 0x0
// .. ==> 0XE0001004[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// .. UCLKEN = 0x0
// .. ==> 0XE0001004[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U

186
board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
View File

@ -3666,64 +3666,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U
@ -8046,70 +7988,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. IRMODE = 0x0
// .. ==> 0XE0001004[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// .. UCLKEN = 0x0
// .. ==> 0XE0001004[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U
@ -12359,70 +12237,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. IRMODE = 0x0
// .. ==> 0XE0001004[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// .. UCLKEN = 0x0
// .. ==> 0XE0001004[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U

186
board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
View File

@ -3635,64 +3635,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U
@ -7984,70 +7926,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. IRMODE = 0x0
// .. ==> 0XE0001004[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// .. UCLKEN = 0x0
// .. ==> 0XE0001004[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U
@ -12266,70 +12144,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. IRMODE = 0x0
// .. ==> 0XE0001004[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// .. UCLKEN = 0x0
// .. ==> 0XE0001004[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U

12
board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
View File

@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),
@ -461,10 +457,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),
@ -699,10 +691,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),

12
board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
View File

@ -212,10 +212,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@ -446,10 +442,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@ -678,10 +670,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),

12
board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
View File

@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@ -442,10 +438,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@ -672,10 +664,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),

12
board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
View File

@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
@ -467,10 +463,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
@ -711,10 +703,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),

12
board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
View File

@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),
@ -439,10 +435,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),
@ -666,10 +658,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKDELAY(0xF8F00200, 1),

186
board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
View File

@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U
@ -7860,70 +7802,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. IRMODE = 0x0
// .. ==> 0XE0001004[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// .. UCLKEN = 0x0
// .. ==> 0XE0001004[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U
@ -12026,70 +11904,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. FINISH: LOCK IT BACK
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
// .. BDIV = 0x6
// .. ==> 0XE0001034[7:0] = 0x00000006U
// .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
// .. CD = 0x3e
// .. ==> 0XE0001018[15:0] = 0x0000003EU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. STTBRK = 0x0
// .. ==> 0XE0001000[7:7] = 0x00000000U
// .. ==> MASK : 0x00000080U VAL : 0x00000000U
// .. RSTTO = 0x0
// .. ==> 0XE0001000[6:6] = 0x00000000U
// .. ==> MASK : 0x00000040U VAL : 0x00000000U
// .. TXDIS = 0x0
// .. ==> 0XE0001000[5:5] = 0x00000000U
// .. ==> MASK : 0x00000020U VAL : 0x00000000U
// .. TXEN = 0x1
// .. ==> 0XE0001000[4:4] = 0x00000001U
// .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. RXDIS = 0x0
// .. ==> 0XE0001000[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. RXEN = 0x1
// .. ==> 0XE0001000[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. TXRES = 0x1
// .. ==> 0XE0001000[1:1] = 0x00000001U
// .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. RXRES = 0x1
// .. ==> 0XE0001000[0:0] = 0x00000001U
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
// ..
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
// .. IRMODE = 0x0
// .. ==> 0XE0001004[11:11] = 0x00000000U
// .. ==> MASK : 0x00000800U VAL : 0x00000000U
// .. UCLKEN = 0x0
// .. ==> 0XE0001004[10:10] = 0x00000000U
// .. ==> MASK : 0x00000400U VAL : 0x00000000U
// .. CHMODE = 0x0
// .. ==> 0XE0001004[9:8] = 0x00000000U
// .. ==> MASK : 0x00000300U VAL : 0x00000000U
// .. NBSTOP = 0x0
// .. ==> 0XE0001004[7:6] = 0x00000000U
// .. ==> MASK : 0x000000C0U VAL : 0x00000000U
// .. PAR = 0x4
// .. ==> 0XE0001004[5:3] = 0x00000004U
// .. ==> MASK : 0x00000038U VAL : 0x00000020U
// .. CHRL = 0x0
// .. ==> 0XE0001004[2:1] = 0x00000000U
// .. ==> MASK : 0x00000006U VAL : 0x00000000U
// .. CLKS = 0x0
// .. ==> 0XE0001004[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
// .. FINISH: UART REGISTERS
// .. START: QSPI REGISTERS
// .. Holdb_dr = 1
// .. ==> 0XE000D000[19:19] = 0x00000001U

8
board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
View File

@ -222,14 +222,6 @@ static unsigned long ps7_peripherals_init_data[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),

4
board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
View File

@ -235,10 +235,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),

186
board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
View File

@ -3647,64 +3647,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
/* .. FINISH: LOCK IT BACK */
/* .. START: SRAM/NOR SET OPMODE */
/* .. FINISH: SRAM/NOR SET OPMODE */
/* .. START: UART REGISTERS */
/* .. BDIV = 0x6 */
/* .. ==> 0XE0001034[7:0] = 0x00000006U */
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
/* .. CD = 0x7c */
/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
/* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
/* .. STTBRK = 0x0 */
/* .. ==> 0XE0001000[7:7] = 0x00000000U */
/* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
/* .. RSTTO = 0x0 */
/* .. ==> 0XE0001000[6:6] = 0x00000000U */
/* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
/* .. TXDIS = 0x0 */
/* .. ==> 0XE0001000[5:5] = 0x00000000U */
/* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
/* .. TXEN = 0x1 */
/* .. ==> 0XE0001000[4:4] = 0x00000001U */
/* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
/* .. RXDIS = 0x0 */
/* .. ==> 0XE0001000[3:3] = 0x00000000U */
/* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
/* .. RXEN = 0x1 */
/* .. ==> 0XE0001000[2:2] = 0x00000001U */
/* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
/* .. TXRES = 0x1 */
/* .. ==> 0XE0001000[1:1] = 0x00000001U */
/* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
/* .. RXRES = 0x1 */
/* .. ==> 0XE0001000[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. */
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
/* .. CHMODE = 0x0 */
/* .. ==> 0XE0001004[9:8] = 0x00000000U */
/* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
/* .. NBSTOP = 0x0 */
/* .. ==> 0XE0001004[7:6] = 0x00000000U */
/* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
/* .. PAR = 0x4 */
/* .. ==> 0XE0001004[5:3] = 0x00000004U */
/* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
/* .. CHRL = 0x0 */
/* .. ==> 0XE0001004[2:1] = 0x00000000U */
/* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
/* .. CLKS = 0x0 */
/* .. ==> 0XE0001004[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@ -7944,70 +7886,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
/* .. FINISH: LOCK IT BACK */
/* .. START: SRAM/NOR SET OPMODE */
/* .. FINISH: SRAM/NOR SET OPMODE */
/* .. START: UART REGISTERS */
/* .. BDIV = 0x6 */
/* .. ==> 0XE0001034[7:0] = 0x00000006U */
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
/* .. CD = 0x7c */
/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
/* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
/* .. STTBRK = 0x0 */
/* .. ==> 0XE0001000[7:7] = 0x00000000U */
/* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
/* .. RSTTO = 0x0 */
/* .. ==> 0XE0001000[6:6] = 0x00000000U */
/* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
/* .. TXDIS = 0x0 */
/* .. ==> 0XE0001000[5:5] = 0x00000000U */
/* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
/* .. TXEN = 0x1 */
/* .. ==> 0XE0001000[4:4] = 0x00000001U */
/* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
/* .. RXDIS = 0x0 */
/* .. ==> 0XE0001000[3:3] = 0x00000000U */
/* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
/* .. RXEN = 0x1 */
/* .. ==> 0XE0001000[2:2] = 0x00000001U */
/* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
/* .. TXRES = 0x1 */
/* .. ==> 0XE0001000[1:1] = 0x00000001U */
/* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
/* .. RXRES = 0x1 */
/* .. ==> 0XE0001000[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. */
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
/* .. IRMODE = 0x0 */
/* .. ==> 0XE0001004[11:11] = 0x00000000U */
/* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
/* .. UCLKEN = 0x0 */
/* .. ==> 0XE0001004[10:10] = 0x00000000U */
/* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
/* .. CHMODE = 0x0 */
/* .. ==> 0XE0001004[9:8] = 0x00000000U */
/* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
/* .. NBSTOP = 0x0 */
/* .. ==> 0XE0001004[7:6] = 0x00000000U */
/* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
/* .. PAR = 0x4 */
/* .. ==> 0XE0001004[5:3] = 0x00000004U */
/* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
/* .. CHRL = 0x0 */
/* .. ==> 0XE0001004[2:1] = 0x00000000U */
/* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
/* .. CLKS = 0x0 */
/* .. ==> 0XE0001004[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@ -12172,70 +12050,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
/* .. FINISH: LOCK IT BACK */
/* .. START: SRAM/NOR SET OPMODE */
/* .. FINISH: SRAM/NOR SET OPMODE */
/* .. START: UART REGISTERS */
/* .. BDIV = 0x6 */
/* .. ==> 0XE0001034[7:0] = 0x00000006U */
/* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
/* .. */
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
/* .. CD = 0x7c */
/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
/* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
/* .. */
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
/* .. STPBRK = 0x0 */
/* .. ==> 0XE0001000[8:8] = 0x00000000U */
/* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
/* .. STTBRK = 0x0 */
/* .. ==> 0XE0001000[7:7] = 0x00000000U */
/* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
/* .. RSTTO = 0x0 */
/* .. ==> 0XE0001000[6:6] = 0x00000000U */
/* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
/* .. TXDIS = 0x0 */
/* .. ==> 0XE0001000[5:5] = 0x00000000U */
/* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
/* .. TXEN = 0x1 */
/* .. ==> 0XE0001000[4:4] = 0x00000001U */
/* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
/* .. RXDIS = 0x0 */
/* .. ==> 0XE0001000[3:3] = 0x00000000U */
/* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
/* .. RXEN = 0x1 */
/* .. ==> 0XE0001000[2:2] = 0x00000001U */
/* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
/* .. TXRES = 0x1 */
/* .. ==> 0XE0001000[1:1] = 0x00000001U */
/* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
/* .. RXRES = 0x1 */
/* .. ==> 0XE0001000[0:0] = 0x00000001U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
/* .. */
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
/* .. IRMODE = 0x0 */
/* .. ==> 0XE0001004[11:11] = 0x00000000U */
/* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
/* .. UCLKEN = 0x0 */
/* .. ==> 0XE0001004[10:10] = 0x00000000U */
/* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
/* .. CHMODE = 0x0 */
/* .. ==> 0XE0001004[9:8] = 0x00000000U */
/* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
/* .. NBSTOP = 0x0 */
/* .. ==> 0XE0001004[7:6] = 0x00000000U */
/* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
/* .. PAR = 0x4 */
/* .. ==> 0XE0001004[5:3] = 0x00000004U */
/* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
/* .. CHRL = 0x0 */
/* .. ==> 0XE0001004[2:1] = 0x00000000U */
/* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
/* .. CLKS = 0x0 */
/* .. ==> 0XE0001004[0:0] = 0x00000000U */
/* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
/* .. */
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
/* .. FINISH: UART REGISTERS */
/* .. START: QSPI REGISTERS */
/* .. Holdb_dr = 1 */
/* .. ==> 0XE000D000[19:19] = 0x00000001U */