video: add support of STM32 MIPI DSI controller driver
Add the STM32 DSI controller driver that uses the Synopsys DesignWare MIPI DSI host controller bridge. Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
This commit is contained in:
Yannick Fertré
Anatolij Gustschin
parent
d4f7ea83fc
commit
18b6ca5c5a
@ -13,6 +13,15 @@ menuconfig VIDEO_STM32
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DSI. This option enables these supports which can be used on
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devices which have RGB TFT or DSI display connected.
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config VIDEO_STM32_DSI
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bool "Enable STM32 DSI video support"
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depends on VIDEO_STM32
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select VIDEO_BRIDGE
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select VIDEO_DW_MIPI_DSI
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help
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This option enables support DSI internal bridge which can be used on
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devices which have DSI devices connected.
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config VIDEO_STM32_MAX_XRES
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int "Maximum horizontal resolution (for memory allocation purposes)"
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depends on VIDEO_STM32
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@ -6,3 +6,4 @@
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# Yannick Fertre <yannick.fertre@st.com>
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obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
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obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
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490
drivers/video/stm32/stm32_dsi.c
Normal file
490
drivers/video/stm32/stm32_dsi.c
Normal file
@ -0,0 +1,490 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 STMicroelectronics - All Rights Reserved
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* Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
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* Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
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*
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* This MIPI DSI controller driver is based on the Linux Kernel driver from
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* drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dsi_host.h>
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#include <mipi_dsi.h>
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#include <panel.h>
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#include <reset.h>
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#include <video.h>
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#include <video_bridge.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <dm/device-internal.h>
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#include <linux/iopoll.h>
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#include <power/regulator.h>
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#define HWVER_130 0x31333000 /* IP version 1.30 */
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#define HWVER_131 0x31333100 /* IP version 1.31 */
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/* DSI digital registers & bit definitions */
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#define DSI_VERSION 0x00
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#define VERSION GENMASK(31, 8)
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/*
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* DSI wrapper registers & bit definitions
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* Note: registers are named as in the Reference Manual
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*/
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#define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
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#define WCFGR_DSIM BIT(0) /* DSI Mode */
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#define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */
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#define DSI_WCR 0x0404 /* Wrapper Control Reg */
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#define WCR_DSIEN BIT(3) /* DSI ENable */
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#define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
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#define WISR_PLLLS BIT(8) /* PLL Lock Status */
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#define WISR_RRS BIT(12) /* Regulator Ready Status */
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#define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
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#define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
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#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
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#define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
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#define WRPCR_PLLEN BIT(0) /* PLL ENable */
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#define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
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#define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
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#define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
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#define WRPCR_REGEN BIT(24) /* REGulator ENable */
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#define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
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#define IDF_MIN 1
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#define IDF_MAX 7
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#define NDIV_MIN 10
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#define NDIV_MAX 125
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#define ODF_MIN 1
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#define ODF_MAX 8
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/* dsi color format coding according to the datasheet */
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enum dsi_color {
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DSI_RGB565_CONF1,
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DSI_RGB565_CONF2,
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DSI_RGB565_CONF3,
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DSI_RGB666_CONF1,
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DSI_RGB666_CONF2,
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DSI_RGB888,
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};
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#define LANE_MIN_KBPS 31250
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#define LANE_MAX_KBPS 500000
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/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
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#define TIMEOUT_US 200000
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struct stm32_dsi_priv {
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struct mipi_dsi_device device;
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void __iomem *base;
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struct udevice *panel;
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u32 pllref_clk;
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u32 hw_version;
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int lane_min_kbps;
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int lane_max_kbps;
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struct udevice *vdd_reg;
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struct udevice *dsi_host;
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};
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static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
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{
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writel(val, dsi->base + reg);
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}
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static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
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{
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return readl(dsi->base + reg);
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}
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static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
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{
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dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
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}
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static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
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{
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dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
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}
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static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg,
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u32 mask, u32 val)
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{
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dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
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}
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static enum dsi_color dsi_color_from_mipi(u32 fmt)
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{
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switch (fmt) {
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case MIPI_DSI_FMT_RGB888:
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return DSI_RGB888;
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case MIPI_DSI_FMT_RGB666:
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return DSI_RGB666_CONF2;
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case MIPI_DSI_FMT_RGB666_PACKED:
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return DSI_RGB666_CONF1;
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case MIPI_DSI_FMT_RGB565:
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return DSI_RGB565_CONF1;
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default:
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pr_err("MIPI color invalid, so we use rgb888\n");
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}
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return DSI_RGB888;
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}
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static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
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{
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int divisor = idf * odf;
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/* prevent from division by 0 */
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if (!divisor)
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return 0;
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return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
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}
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static int dsi_pll_get_params(struct stm32_dsi_priv *dsi,
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int clkin_khz, int clkout_khz,
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int *idf, int *ndiv, int *odf)
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{
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int i, o, n, n_min, n_max;
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int fvco_min, fvco_max, delta, best_delta; /* all in khz */
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/* Early checks preventing division by 0 & odd results */
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if (clkin_khz <= 0 || clkout_khz <= 0)
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return -EINVAL;
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fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
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fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
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best_delta = 1000000; /* big started value (1000000khz) */
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for (i = IDF_MIN; i <= IDF_MAX; i++) {
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/* Compute ndiv range according to Fvco */
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n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
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n_max = (fvco_max * i) / (2 * clkin_khz);
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/* No need to continue idf loop if we reach ndiv max */
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if (n_min >= NDIV_MAX)
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break;
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/* Clamp ndiv to valid values */
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if (n_min < NDIV_MIN)
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n_min = NDIV_MIN;
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if (n_max > NDIV_MAX)
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n_max = NDIV_MAX;
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for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
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n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
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/* Check ndiv according to vco range */
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if (n < n_min || n > n_max)
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continue;
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/* Check if new delta is better & saves parameters */
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delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
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clkout_khz;
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if (delta < 0)
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delta = -delta;
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if (delta < best_delta) {
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*idf = i;
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*ndiv = n;
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*odf = o;
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best_delta = delta;
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}
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/* fast return in case of "perfect result" */
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if (!delta)
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return 0;
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}
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}
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return 0;
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}
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static int dsi_phy_init(void *priv_data)
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{
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struct mipi_dsi_device *device = priv_data;
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struct udevice *dev = device->dev;
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struct stm32_dsi_priv *dsi = dev_get_priv(dev);
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u32 val;
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int ret;
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debug("Initialize DSI physical layer\n");
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/* Enable the regulator */
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dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
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ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
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TIMEOUT_US);
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if (ret) {
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debug("!TIMEOUT! waiting REGU\n");
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return ret;
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}
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/* Enable the DSI PLL & wait for its lock */
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dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
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ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
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TIMEOUT_US);
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if (ret) {
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debug("!TIMEOUT! waiting PLL\n");
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return ret;
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}
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return 0;
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}
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static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
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{
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struct mipi_dsi_device *device = priv_data;
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struct udevice *dev = device->dev;
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struct stm32_dsi_priv *dsi = dev_get_priv(dev);
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debug("Set mode %p enable %ld\n", dsi,
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mode_flags & MIPI_DSI_MODE_VIDEO);
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if (!dsi)
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return;
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/*
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* DSI wrapper must be enabled in video mode & disabled in command mode.
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* If wrapper is enabled in command mode, the display controller
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* register access will hang.
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*/
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if (mode_flags & MIPI_DSI_MODE_VIDEO)
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dsi_set(dsi, DSI_WCR, WCR_DSIEN);
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else
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dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
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}
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static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
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u32 lanes, u32 format, unsigned int *lane_mbps)
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{
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struct mipi_dsi_device *device = priv_data;
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struct udevice *dev = device->dev;
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struct stm32_dsi_priv *dsi = dev_get_priv(dev);
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int idf, ndiv, odf, pll_in_khz, pll_out_khz;
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int ret, bpp;
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u32 val;
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/* Update lane capabilities according to hw version */
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dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
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dsi->lane_min_kbps = LANE_MIN_KBPS;
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dsi->lane_max_kbps = LANE_MAX_KBPS;
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if (dsi->hw_version == HWVER_131) {
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dsi->lane_min_kbps *= 2;
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dsi->lane_max_kbps *= 2;
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}
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pll_in_khz = dsi->pllref_clk / 1000;
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/* Compute requested pll out */
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bpp = mipi_dsi_pixel_format_to_bpp(format);
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pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes;
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/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
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pll_out_khz = (pll_out_khz * 12) / 10;
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if (pll_out_khz > dsi->lane_max_kbps) {
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pll_out_khz = dsi->lane_max_kbps;
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dev_warn(dev, "Warning max phy mbps is used\n");
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}
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if (pll_out_khz < dsi->lane_min_kbps) {
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pll_out_khz = dsi->lane_min_kbps;
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dev_warn(dev, "Warning min phy mbps is used\n");
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}
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/* Compute best pll parameters */
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idf = 0;
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ndiv = 0;
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odf = 0;
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ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
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&idf, &ndiv, &odf);
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if (ret) {
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dev_err(dev, "Warning dsi_pll_get_params(): bad params\n");
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return ret;
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}
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/* Get the adjusted pll out value */
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pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
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/* Set the PLL division factors */
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dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
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(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
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/* Compute uix4 & set the bit period in high-speed mode */
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val = 4000000 / pll_out_khz;
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dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
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/* Select video mode by resetting DSIM bit */
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dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
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/* Select the color coding */
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dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
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dsi_color_from_mipi(format) << 1);
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*lane_mbps = pll_out_khz / 1000;
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debug("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
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pll_in_khz, pll_out_khz, *lane_mbps);
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return 0;
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}
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static const struct mipi_dsi_phy_ops dsi_stm_phy_ops = {
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.init = dsi_phy_init,
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.get_lane_mbps = dsi_get_lane_mbps,
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.post_set_mode = dsi_phy_post_set_mode,
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};
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static int stm32_dsi_attach(struct udevice *dev)
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{
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struct stm32_dsi_priv *priv = dev_get_priv(dev);
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struct mipi_dsi_device *device = &priv->device;
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struct mipi_dsi_panel_plat *mplat;
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struct display_timing timings;
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int ret;
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ret = uclass_first_device(UCLASS_PANEL, &priv->panel);
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if (ret) {
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dev_err(dev, "panel device error %d\n", ret);
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return ret;
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}
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mplat = dev_get_platdata(priv->panel);
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mplat->device = &priv->device;
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ret = panel_get_display_timing(priv->panel, &timings);
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if (ret) {
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ret = fdtdec_decode_display_timing(gd->fdt_blob,
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dev_of_offset(priv->panel),
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0, &timings);
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if (ret) {
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dev_err(dev, "decode display timing error %d\n", ret);
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return ret;
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}
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}
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ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
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if (ret) {
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dev_err(dev, "No video dsi host detected %d\n", ret);
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return ret;
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}
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ret = dsi_host_init(priv->dsi_host, device, &timings, 2,
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&dsi_stm_phy_ops);
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if (ret) {
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dev_err(dev, "failed to initialize mipi dsi host\n");
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return ret;
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}
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return 0;
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}
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static int stm32_dsi_set_backlight(struct udevice *dev, int percent)
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{
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struct stm32_dsi_priv *priv = dev_get_priv(dev);
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int ret;
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ret = panel_enable_backlight(priv->panel);
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if (ret) {
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dev_err(dev, "panel %s enable backlight error %d\n",
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priv->panel->name, ret);
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return ret;
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}
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ret = dsi_host_enable(priv->dsi_host);
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if (ret) {
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dev_err(dev, "failed to enable mipi dsi host\n");
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return ret;
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}
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return 0;
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}
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static int stm32_dsi_probe(struct udevice *dev)
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{
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struct stm32_dsi_priv *priv = dev_get_priv(dev);
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struct mipi_dsi_device *device = &priv->device;
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struct reset_ctl rst;
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struct clk clk;
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int ret;
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device->dev = dev;
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priv->base = (void *)dev_read_addr(dev);
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if ((fdt_addr_t)priv->base == FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "dsi dt register address error\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
|
||||
ret = device_get_supply_regulator(dev, "phy-dsi-supply",
|
||||
&priv->vdd_reg);
|
||||
if (ret && ret != -ENOENT) {
|
||||
dev_err(dev, "Warning: cannot get phy dsi supply\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (ret != -ENOENT) {
|
||||
ret = regulator_set_enable(priv->vdd_reg, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(device->dev, "pclk", &clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "peripheral clock get error %d\n", ret);
|
||||
goto err_reg;
|
||||
}
|
||||
|
||||
ret = clk_enable(&clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "peripheral clock enable error %d\n", ret);
|
||||
goto err_reg;
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "ref", &clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "pll reference clock get error %d\n", ret);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
priv->pllref_clk = (unsigned int)clk_get_rate(&clk);
|
||||
|
||||
ret = reset_get_by_index(device->dev, 0, &rst);
|
||||
if (ret) {
|
||||
dev_err(dev, "missing dsi hardware reset\n");
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
/* Reset */
|
||||
reset_deassert(&rst);
|
||||
|
||||
return 0;
|
||||
err_clk:
|
||||
clk_disable(&clk);
|
||||
err_reg:
|
||||
if (IS_ENABLED(CONFIG_DM_REGULATOR))
|
||||
regulator_set_enable(priv->vdd_reg, false);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct video_bridge_ops stm32_dsi_ops = {
|
||||
.attach = stm32_dsi_attach,
|
||||
.set_backlight = stm32_dsi_set_backlight,
|
||||
};
|
||||
|
||||
static const struct udevice_id stm32_dsi_ids[] = {
|
||||
{ .compatible = "st,stm32-dsi"},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stm32_dsi) = {
|
||||
.name = "stm32-display-dsi",
|
||||
.id = UCLASS_VIDEO_BRIDGE,
|
||||
.of_match = stm32_dsi_ids,
|
||||
.bind = dm_scan_fdt_dev,
|
||||
.probe = stm32_dsi_probe,
|
||||
.ops = &stm32_dsi_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct stm32_dsi_priv),
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user