x86: Add a generic Intel GPIO driver
Add a GPIO driver which uses the pinctrl driver to access the pad information. This driver relies on the GPIO nodes being subnodes to the pinctrl device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
74749f1e84
commit
7e589bc19b
55
doc/device-tree-bindings/gpio/intel,apl-gpio.txt
Normal file
55
doc/device-tree-bindings/gpio/intel,apl-gpio.txt
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@ -0,0 +1,55 @@
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Intel Apollo Lake GPIO controller
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The Apollo Lake (APL) GPIO controller is used to control GPIO functions of
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the pins.
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Required properties:
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- compatible: "intel,apl-gpio"
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- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
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nodes should be the following with values derived from the SoC user manual.
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<[phandle of the gpio controller node]
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[pin number within the gpio controller]
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[flags]>
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Values for gpio specifier:
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- Pin number: is a GPIO pin number between 0 and 244
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- Flags: GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW
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- gpio-controller: Specifies that the node is a gpio controller.
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Example:
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...
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{
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p2sb: p2sb@d,0 {
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reg = <0x02006810 0 0 0 0>;
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compatible = "intel,apl-p2sb";
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early-regs = <IOMAP_P2SB_BAR 0x100000>;
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north {
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compatible = "intel,apl-pinctrl";
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intel,p2sb-port-id = <PID_GPIO_N>;
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gpio_n: gpio-n {
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compatible = "intel,gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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i2c_2: i2c2@16,2 {
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compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
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reg = <0x0200b210 0 0 0 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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tpm@50 {
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reg = <0x50>;
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compatible = "google,cr50";
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u-boot,i2c-offset-len = <0>;
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ready-gpio = <&gpio_n GPIO_28 GPIO_ACTIVE_LOW>;
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};
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};
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};
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...
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@ -104,6 +104,15 @@ config INTEL_BROADWELL_GPIO
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driver from the common Intel ICH6 driver. It supports a total of
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95 GPIOs which can be configured from the device tree.
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config INTEL_GPIO
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bool "Intel generic GPIO driver"
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depends on DM_GPIO
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help
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Say yes here to select Intel generic GPIO driver. This controller
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supports recent chips (e.g. Apollo Lake). It permits basic GPIO
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control including setting pins to input/output. It makes use of its
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parent pinctrl driver to actually effect changes.
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config INTEL_ICH6_GPIO
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bool "Intel ICH6 compatible legacy GPIO driver"
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depends on DM_GPIO
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@ -17,6 +17,7 @@ endif
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obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
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obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
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obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o
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obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o
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obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
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obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
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obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
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161
drivers/gpio/intel_gpio.c
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161
drivers/gpio/intel_gpio.c
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@ -0,0 +1,161 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <p2sb.h>
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#include <pch.h>
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#include <pci.h>
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#include <syscon.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/intel_pinctrl_defs.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/gpio.h>
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#include <dt-bindings/gpio/x86-gpio.h>
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static int intel_gpio_direction_input(struct udevice *dev, uint offset)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
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pcr_clrsetbits32(pinctrl, config_offset,
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PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
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PAD_CFG0_RX_DISABLE,
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PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE);
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return 0;
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}
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static int intel_gpio_direction_output(struct udevice *dev, uint offset,
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int value)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
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pcr_clrsetbits32(dev, config_offset,
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PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
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PAD_CFG0_TX_DISABLE,
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PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE |
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(value ? PAD_CFG0_TX_STATE : 0));
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return 0;
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}
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static int intel_gpio_get_value(struct udevice *dev, uint offset)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint mode, rx_tx;
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u32 reg;
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reg = intel_pinctrl_get_config_reg(pinctrl, offset);
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mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
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if (!mode) {
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rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
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if (rx_tx == PAD_CFG0_TX_DISABLE)
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return mode & PAD_CFG0_RX_STATE_BIT ? 1 : 0;
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else if (rx_tx == PAD_CFG0_RX_DISABLE)
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return mode & PAD_CFG0_TX_STATE_BIT ? 1 : 0;
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}
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return 0;
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}
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static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
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pcr_clrsetbits32(dev, config_offset, PAD_CFG0_TX_STATE,
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value ? PAD_CFG0_TX_STATE : 0);
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return 0;
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}
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static int intel_gpio_get_function(struct udevice *dev, uint offset)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint mode, rx_tx;
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u32 reg;
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reg = intel_pinctrl_get_config_reg(pinctrl, offset);
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mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
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if (!mode) {
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rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
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if (rx_tx == PAD_CFG0_TX_DISABLE)
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return GPIOF_INPUT;
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else if (rx_tx == PAD_CFG0_RX_DISABLE)
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return GPIOF_OUTPUT;
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}
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return GPIOF_FUNC;
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}
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static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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struct udevice *pinctrl, *dev;
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int gpio, ret;
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/*
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* GPIO numbers are global in the device tree so it doesn't matter
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* which one is used
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*/
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gpio = args->args[0];
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ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
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if (ret)
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return log_msg_ret("bad", ret);
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device_find_first_child(pinctrl, &dev);
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if (!dev)
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return log_msg_ret("no child", -ENOENT);
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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desc->dev = dev;
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return 0;
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}
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static int intel_gpio_probe(struct udevice *dev)
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{
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return 0;
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}
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static int intel_gpio_ofdata_to_platdata(struct udevice *dev)
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{
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struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
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struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
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const struct pad_community *comm = pinctrl_priv->comm;
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upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
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upriv->bank_name = dev->name;
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return 0;
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}
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static const struct dm_gpio_ops gpio_intel_ops = {
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.direction_input = intel_gpio_direction_input,
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.direction_output = intel_gpio_direction_output,
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.get_value = intel_gpio_get_value,
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.set_value = intel_gpio_set_value,
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.get_function = intel_gpio_get_function,
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.xlate = intel_gpio_xlate,
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};
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static const struct udevice_id intel_intel_gpio_ids[] = {
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{ .compatible = "intel,gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_intel) = {
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.name = "gpio_intel",
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.id = UCLASS_GPIO,
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.of_match = intel_intel_gpio_ids,
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.ops = &gpio_intel_ops,
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.ofdata_to_platdata = intel_gpio_ofdata_to_platdata,
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.probe = intel_gpio_probe,
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};
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