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watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig

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Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
accordingly, no functional change. The S10 enables the WDT only in
SPL, but does not enable it in U-Boot itself, hence disable it in
the config again.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Marek Vasut 2019-06-27 00:26:34 +02:00
parent 707c36e2af
commit 8941f8414d
6 changed files with 13 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
configs/socfpga_stratix10_defconfig
View File

@ -59,3 +59,4 @@ CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_DESIGNWARE_WATCHDOG=y

1
configs/socfpga_vining_fpga_defconfig
View File

@ -97,3 +97,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
# CONFIG_SPL_WDT is not set
CONFIG_DESIGNWARE_WATCHDOG=y

7
drivers/watchdog/Kconfig
View File

@ -45,6 +45,13 @@ config ULP_WATCHDOG
help
Say Y here to enable i.MX7ULP watchdog driver.
config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"
select HW_WATCHDOG
help
Enable this to support Designware Watchdog Timer IP, present e.g.
on Altera SoCFPGA SoCs.
config WDT
bool "Enable driver model for watchdog timer drivers"
depends on DM

3
include/configs/socfpga_common.h
View File

@ -104,11 +104,8 @@
/*
* L4 Watchdog
*/
#ifdef CONFIG_HW_WATCHDOG
#define CONFIG_DESIGNWARE_WATCHDOG
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
#endif
/*
* MMC Driver

6
include/configs/socfpga_soc64_common.h
View File

@ -152,7 +152,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*/
#ifdef CONFIG_SPL_BUILD
#define CONFIG_HW_WATCHDOG
#define CONFIG_DESIGNWARE_WATCHDOG
#else
#undef CONFIG_HW_WATCHDOG
#undef CONFIG_DESIGNWARE_WATCHDOG
#endif
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
#ifndef __ASSEMBLY__
@ -162,7 +165,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
#else
#define CONFIG_DW_WDT_CLOCK_KHZ 100000
#endif
#endif
/*
* SPL memory layout

1
scripts/config_whitelist.txt
View File

@ -311,7 +311,6 @@ CONFIG_DEFAULT_IMMR
CONFIG_DEF_HWCONFIG
CONFIG_DELAY_ENVIRONMENT
CONFIG_DESIGNWARE_ETH
CONFIG_DESIGNWARE_WATCHDOG
CONFIG_DEVELOP
CONFIG_DEVICE_TREE_LIST
CONFIG_DFU_ALT