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Merge tag 'u-boot-rockchip-20191118' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
- Add support for rockchip SoC: PX30, RK3308
- Add and migrate to use common dram driver: PX30, RK3328, RK3399
- Add rk3399 board Tinker-s support
- Board config update for Rock960, Rockpro64
This commit is contained in:
Tom Rini 2019-11-17 21:15:57 -05:00
commit d64efd920e
168 changed files with 16846 additions and 1815 deletions
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2
arch/arm/Kconfig
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@ -1604,7 +1604,6 @@ config ARCH_ROCKCHIP
select OF_CONTROL
select SPI
select SPL_DM if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL
select SYS_MALLOC_F
select SYS_THUMB_BUILD if !ARM64
imply ADC
@ -1614,6 +1613,7 @@ config ARCH_ROCKCHIP
imply FAT_WRITE
imply SARADC_ROCKCHIP
imply SPL_SYSRESET
imply SPL_SYS_MALLOC_SIMPLE
imply SYS_NS16550
imply TPL_SYSRESET
imply USB_FUNCTION_FASTBOOT

8
arch/arm/dts/Makefile
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@ -67,6 +67,9 @@ dtb-$(CONFIG_KIRKWOOD) += \
dtb-$(CONFIG_ARCH_OWL) += \
bubblegum_96.dtb
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
@ -87,12 +90,17 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-popmetal.dtb \
rk3288-rock2-square.dtb \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
dtb-$(CONFIG_ROCKCHIP_RK3308) += \
rk3308-evb.dtb \
rk3308-roc-cc.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-rock64.dtb

81
arch/arm/dts/px30-evb-u-boot.dtsi Normal file
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@ -0,0 +1,81 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&dmc {
u-boot,dm-pre-reloc;
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart5 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
/* temporary till I find out why dma mode doesn't work */
fifo-mode;
};
&emmc {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&xin24m {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
status = "okay";
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};

530
arch/arm/dts/px30-evb.dts Normal file
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@ -0,0 +1,530 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "px30.dtsi"
#include "px30-evb-u-boot.dtsi"
/ {
model = "Rockchip PX30 EVB";
compatible = "rockchip,px30-evb", "rockchip,px30";
chosen {
stdout-path = "serial2:115200n8";
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
esc-key {
label = "esc";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <1310000>;
};
home-key {
label = "home";
linux,code = <KEY_HOME>;
press-threshold-microvolt = <624000>;
};
menu-key {
label = "menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <987000>;
};
vol-down-key {
label = "volume down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <300000>;
};
vol-up-key {
label = "volume up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <17000>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 25000 0>;
power-supply = <&vcc3v3_lcd>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
};
vcc5v0_sys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&display_subsystem {
status = "okay";
};
&dsi {
status = "okay";
ports {
mipi_out: port@1 {
reg = <1>;
mipi_out_panel: endpoint {
remote-endpoint = <&mipi_in_panel>;
};
};
};
panel@0 {
compatible = "sitronix,st7703";
reg = <0>;
backlight = <&backlight>;
iovcc-supply = <&vcc_1v8>;
vci-supply = <&vcc3v3_lcd>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipi_in_panel: endpoint {
remote-endpoint = <&mipi_out_panel>;
};
};
};
};
};
&dsi_dphy {
status = "okay";
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v0>;
vqmmc-supply = <&vccio_flash>;
status = "okay";
};
&gmac {
clock_in_out = "output";
phy-supply = <&vcc_rmii>;
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
status = "okay";
};
&i2c0 {
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <0>;
clock-output-names = "xin32k";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
regulators {
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: vcc_rmii: DCDC_REG4 {
regulator-name = "vcc_3v0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_sys: DCDC_REG5 {
regulator-name = "vcc3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v0: LDO_REG1 {
regulator-name = "vcc_1v0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 {
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_1v0: LDO_REG3 {
regulator-name = "vdd_1v0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-name = "vcc3v0_pmu";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-name = "vcc2v8_dvp";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-name = "vcc1v8_dvp";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v5_dvp: LDO_REG9 {
regulator-name = "vcc1v5_dvp";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcc3v3_lcd: SWITCH_REG1 {
regulator-name = "vcc3v3_lcd";
regulator-boot-on;
};
vcc5v0_host: SWITCH_REG2 {
regulator-name = "vcc5v0_host";
regulator-always-on;
regulator-boot-on;
};
};
};
};
&i2s1_2ch {
status = "okay";
};
&io_domains {
status = "okay";
vccio1-supply = <&vccio_sdio>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_3v0>;
vccio4-supply = <&vcc3v0_pmu>;
vccio5-supply = <&vcc_3v0>;
vccio6-supply = <&vccio_flash>;
};
&pinctrl {
headphone {
hp_det: hp-det {
rockchip,pins =
<2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
emmc {
emmc_reset: emmc-reset {
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
soc_slppin_gpio: soc_slppin_gpio {
rockchip,pins =
<0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
};
soc_slppin_slp: soc_slppin_slp {
rockchip,pins =
<0 RK_PA4 1 &pcfg_pull_none>;
};
soc_slppin_rst: soc_slppin_rst {
rockchip,pins =
<0 RK_PA4 2 &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins =
<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v0_pmu>;
pmuio2-supply = <&vcc3v0_pmu>;
};
&pwm1 {
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <800>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
};
&sdio {
bus-width = <4>;
cap-sd-highspeed;
keep-power-in-suspend;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
sd-uhs-sdr104;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&uart5 {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

2068
arch/arm/dts/px30.dtsi Normal file
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File diff suppressed because it is too large Load Diff

34
arch/arm/dts/rk3288-tinker-s-u-boot.dtsi Normal file
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@ -0,0 +1,34 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Amarula Solutions SRO
*/
#include "rk3288-u-boot.dtsi"
#include "rk3288-tinker-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = \
"same-as-spl", &sdmmc, &emmc;
};
};
&emmc {
u-boot,dm-spl;
};
&emmc_clk {
u-boot,dm-spl;
};
&emmc_cmd {
u-boot,dm-spl;
};
&emmc_pwr {
u-boot,dm-spl;
};
&emmc_bus8 {
u-boot,dm-spl;
};

29
arch/arm/dts/rk3288-tinker-s.dts Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rk3288-tinker.dtsi"
/ {
model = "Rockchip RK3288 Asus Tinker Board S";
compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
chosen {
stdout-path = &uart2;
};
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
max-frequency = <150000000>;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
status = "okay";
};

12
arch/arm/dts/rk3288-tinker-u-boot.dtsi
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@ -5,6 +5,18 @@
#include "rk3288-u-boot.dtsi"
&dmc {
u-boot,dm-pre-reloc;
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x2>;
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

12
arch/arm/dts/rk3288-tinker.dts
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@ -15,18 +15,6 @@
};
};
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x2>;
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
&pinctrl {
usb {
host_vbus_drv: host-vbus-drv {

17
arch/arm/dts/rk3308-evb-u-boot.dtsi Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
*/
#include "rk3308-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &emmc;
};
};
&uart4 {
u-boot,dm-pre-reloc;
clock-frequency = <24000000>;
status = "okay";
};

230
arch/arm/dts/rk3308-evb.dts Normal file
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@ -0,0 +1,230 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
*
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3308.dtsi"
/ {
model = "Rockchip RK3308 EVB";
compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
chosen {
stdout-path = "serial4:1500000n8";
};
adc-keys0 {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
func-key {
linux,code = <KEY_FN>;
label = "function";
press-threshold-microvolt = <18000>;
};
};
adc-keys1 {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
esc-key {
linux,code = <KEY_MICMUTE>;
label = "micmute";
press-threshold-microvolt = <1130000>;
};
home-key {
linux,code = <KEY_MODE>;
label = "mode";
press-threshold-microvolt = <901000>;
};
menu-key {
linux,code = <KEY_PLAY>;
label = "play";
press-threshold-microvolt = <624000>;
};
vol-down-key {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <300000>;
};
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <18000>;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power {
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
wakeup-source;
debounce-interval = <100>;
};
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vdd_core: vdd-core {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 1>;
regulator-name = "vdd_core";
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
};
vdd_log: vdd-log {
compatible = "regulator-fixed";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&vcc5v0_sys>;
};
vdd_1v0: vdd-1v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
vin-supply = <&vcc5v0_sys>;
};
vccio_sdio: vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_io>;
};
vcc_ddr: vcc-ddr {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vccio_flash: vccio-flash {
compatible = "regulator-fixed";
regulator-name = "vccio_flash";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc5v0_host: vcc5v0-host {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_drv>;
regulator-name = "vbus_host";
vin-supply = <&vcc5v0_sys>;
};
};
&cpu0 {
cpu-supply = <&vdd_core>;
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
buttons {
pwr_key: pwr-key {
rockchip,pins = <0 RK_PA6 0 &pcfg_pull_up>;
};
};
usb {
usb_drv: usb-drv {
rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA2 0 &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_pin_pull_down>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer>;
status = "okay";
};

17
arch/arm/dts/rk3308-roc-cc-u-boot.dtsi Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
*/
#include "rk3308-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &emmc;
};
};
&uart2 {
u-boot,dm-pre-reloc;
clock-frequency = <24000000>;
status = "okay";
};

190
arch/arm/dts/rk3308-roc-cc.dts Normal file
View File

@ -0,0 +1,190 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include "rk3308.dtsi"
/ {
model = "Firefly ROC-RK3308-CC board";
compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
chosen {
stdout-path = "serial2:1500000n8";
};
ir_rx {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ir_recv_pin>;
};
ir_tx {
compatible = "pwm-ir-tx";
pwms = <&pwm5 0 25000 0>;
};
leds {
compatible = "gpio-leds";
power {
label = "firefly:red:power";
linux,default-trigger = "ir-power-click";
default-state = "on";
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
};
user {
label = "firefly:blue:user";
linux,default-trigger = "ir-user-click";
default-state = "off";
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
};
};
typec_vcc5v: typec-vcc5v {
compatible = "regulator-fixed";
regulator-name = "typec_vcc5v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&typec_vcc5v>;
};
vdd_core: vdd-core {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 1>;
regulator-name = "vdd_core";
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
regulator-init-microvolt = <1015000>;
regulator-always-on;
regulator-boot-on;
regulator-settling-time-up-us = <250>;
pwm-supply = <&vcc5v0_sys>;
};
vdd_log: vdd-log {
compatible = "regulator-fixed";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vcc_sdmmc: vcc-sdmmc {
compatible = "regulator-gpio";
regulator-name = "vcc_sdmmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0
3300000 0x1>;
vin-supply = <&vcc5v0_sys>;
};
vcc_sd: vcc-sd {
compatible = "regulator-fixed";
gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vim-supply = <&vcc_io>;
};
};
&cpu0 {
cpu-supply = <&vdd_core>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
#clock-cells = <0>;
};
};
&pwm5 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm5_pin_pull_down>;
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
ir-receiver {
ir_recv_pin: ir-recv-pin {
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
pwr_key: pwr-key {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_pin_pull_down>;
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
supports-sd;
card-detect-delay = <300>;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vcc_sdmmc>;
status = "okay";
};
&uart2 {
status = "okay";
};

25
arch/arm/dts/rk3308-u-boot.dtsi Normal file
View File

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*(C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
&cru {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
status = "okay";
};

1829
arch/arm/dts/rk3308.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
View File

@ -14,6 +14,8 @@
0x0
0x10
0x10
0x10
0x10
0
0x9028b189
@ -26,6 +28,8 @@
333
3
1
0
0
0x00000000

4
arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
View File

@ -14,6 +14,8 @@
0x0
0x10
0x10
0x10
0x10
0
0x98899459
@ -27,6 +29,8 @@
800
6
1
0
1
0x00000000
0x43041008

4
arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
View File

@ -14,6 +14,8 @@
0x0
0x10
0x10
0x10
0x10
0
0x0c48a18a
@ -26,6 +28,8 @@
333
6
1
0
0
0x00000000

6
arch/arm/dts/rk3399-evb-u-boot.dtsi
View File

@ -5,3 +5,9 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
/ {
chosen {
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
};

2
arch/arm/dts/rk3399-evb.dts
View File

@ -15,8 +15,6 @@
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = \
&sdhci, &sdmmc;
};
vdd_center: vdd-center {

6
arch/arm/dts/rk3399-firefly-u-boot.dtsi
View File

@ -5,3 +5,9 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};

1
arch/arm/dts/rk3399-firefly.dts
View File

@ -14,7 +14,6 @@
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
backlight: backlight {

4
arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
View File

@ -11,3 +11,7 @@
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};
&vdd_log {
regulator-init-microvolt = <950000>;
};

4
arch/arm/dts/rk3399-orangepi-u-boot.dtsi
View File

@ -5,3 +5,7 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1333.dtsi"
&vdd_log {
regulator-init-microvolt = <950000>;
};

32
arch/arm/dts/rk3399-roc-pc.dts
View File

@ -57,9 +57,9 @@
* should be placed inside mp8859, but not until mp8859 has
* its own dt-binding.
*/
vcc12v_sys: mp8859-dcdc1 {
dc_12v: mp8859-dcdc1 {
compatible = "regulator-fixed";
regulator-name = "vcc12v_sys";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
@ -85,7 +85,7 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc12v_sys>;
vin-supply = <&vcc_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
@ -118,7 +118,7 @@
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_sys>;
vin-supply = <&dc_12v>;
};
vdd_log: vdd-log {
@ -129,7 +129,7 @@
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
vin-supply = <&vcc3v3_sys>;
vin-supply = <&vcc_sys>;
};
};
@ -202,16 +202,16 @@
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
@ -385,7 +385,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc3v3_sys>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@ -404,7 +404,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc3v3_sys>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;

4
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
View File

@ -11,3 +11,7 @@
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};
&vdd_log {
regulator-init-microvolt = <950000>;
};

13
arch/arm/dts/rk3399-rock960-u-boot.dtsi
View File

@ -10,4 +10,17 @@
chosen {
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <950000>;
vin-supply = <&vcc5v0_sys>;
};
};

5
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
View File

@ -11,6 +11,11 @@
};
};
&vdd_center {
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
};
&vdd_log {
regulator-init-microvolt = <950000>;
};

57
arch/arm/dts/rk3399-rockpro64.dts
View File

@ -58,6 +58,13 @@
};
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
fan-supply = <&vcc12v_dcin>;
pwms = <&pwm1 0 50000 0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
@ -166,7 +173,7 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-max-microvolt = <1700000>;
vin-supply = <&vcc5v0_sys>;
};
};
@ -222,6 +229,10 @@
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@ -236,8 +247,8 @@
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
@ -504,11 +515,25 @@
status = "okay";
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcca1v8_codec>;
audio-supply = <&vcc_3v0>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
&pcie0 {
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_perst>;
vpcie12v-supply = <&vcc12v_dcin>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
@ -538,6 +563,10 @@
};
pcie {
pcie_perst: pcie-perst {
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
@ -545,7 +574,7 @@
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
@ -580,6 +609,10 @@
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
@ -591,7 +624,6 @@
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
@ -603,12 +635,21 @@
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
&tcphy0 {
status = "okay";
};

4
arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
View File

@ -13,6 +13,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x80120e12
0x11030802
@ -28,6 +30,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x80120e12
0x11030802

4
arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
View File

@ -13,6 +13,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x80151015
0x14040902
@ -28,6 +30,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x80151015
0x14040902

4
arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
View File

@ -13,6 +13,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x80181219
0x17050a03
@ -28,6 +30,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x80181219
0x17050a03

4
arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
View File

@ -14,6 +14,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x1d191519
0x14040808
@ -29,6 +31,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x1d191519
0x14040808

4
arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
View File

@ -13,6 +13,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x1d191519
0x14040808
@ -28,6 +30,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x1d191519
0x14040808

4
arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
View File

@ -13,6 +13,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x801d181e
@ -30,6 +32,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x801d181e

4
arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
View File

@ -15,6 +15,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x80241d22
0x15050f08
@ -30,6 +32,8 @@
0x0
0xf
0xf
0xf
0xf
1
0x80241d22
0x15050f08

48
arch/arm/dts/rk3399-u-boot.dtsi
View File

@ -3,10 +3,50 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
&cic {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pmu {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&pmu {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&pmusgrf {
u-boot,dm-pre-reloc;
};
&sdhci {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
@ -22,3 +62,11 @@
&uart2 {
u-boot,dm-pre-reloc;
};
&vopb {
u-boot,dm-pre-reloc;
};
&vopl {
u-boot,dm-pre-reloc;
};

11
arch/arm/dts/rk3399.dtsi
View File

@ -275,7 +275,6 @@
};
sdhci: sdhci@fe330000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
reg = <0x0 0xfe330000 0x0 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
@ -1072,7 +1071,6 @@
};
pmugrf: syscon@ff320000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff320000 0x0 0x1000>;
@ -1083,7 +1081,6 @@
};
pmusgrf: syscon@ff330000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pmusgrf", "syscon";
reg = <0x0 0xff330000 0x0 0xe3d4>;
};
@ -1204,7 +1201,6 @@
};
cic: syscon@ff620000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-cic", "syscon";
reg = <0x0 0xff620000 0x0 0x100>;
};
@ -1219,7 +1215,6 @@
};
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
@ -1268,7 +1263,6 @@
};
pmucru: pmu-clock-controller@ff750000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
rockchip,grf = <&pmugrf>;
@ -1279,7 +1273,6 @@
};
cru: clock-controller@ff760000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
@ -1310,7 +1303,6 @@
};
grf: syscon@ff770000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x10000>;
#address-cells = <1>;
@ -1520,7 +1512,6 @@
};
vopl: vop@ff8f0000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-vop-lit";
reg = <0x0 0xff8f0000 0x0 0x3efc>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
@ -1578,7 +1569,6 @@
};
vopb: vop@ff900000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-vop-big";
reg = <0x0 0xff900000 0x0 0x3efc>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
@ -1818,7 +1808,6 @@
};
pinctrl: pinctrl {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;

11
arch/arm/include/asm/arch-px30/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-px30/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

11
arch/arm/include/asm/arch-rk3308/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

290
arch/arm/include/asm/arch-rk3308/cru_rk3308.h Normal file
View File

@ -0,0 +1,290 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
*/
#ifndef _ASM_ARCH_CRU_RK3308_H
#define _ASM_ARCH_CRU_RK3308_H
#include <common.h>
#define MHz 1000000
#define OSC_HZ (24 * MHz)
#define APLL_HZ (816 * MHz)
#define CORE_ACLK_HZ 408000000
#define CORE_DBG_HZ 204000000
#define BUS_ACLK_HZ 200000000
#define BUS_HCLK_HZ 100000000
#define BUS_PCLK_HZ 100000000
#define PERI_ACLK_HZ 200000000
#define PERI_HCLK_HZ 100000000
#define PERI_PCLK_HZ 100000000
#define AUDIO_HCLK_HZ 100000000
#define AUDIO_PCLK_HZ 100000000
#define RK3308_PLL_CON(x) ((x) * 0x4)
#define RK3308_MODE_CON 0xa0
/* RK3308 pll id */
enum rk3308_pll_id {
APLL,
DPLL,
VPLL0,
VPLL1,
PLL_COUNT,
};
struct rk3308_clk_info {
unsigned long id;
char *name;
};
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3308_clk_priv {
struct rk3308_cru *cru;
ulong armclk_hz;
ulong dpll_hz;
ulong vpll0_hz;
ulong vpll1_hz;
};
struct rk3308_cru {
struct rk3308_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
unsigned int con4;
unsigned int reserved0[3];
} pll[4];
unsigned int reserved1[8];
unsigned int mode;
unsigned int misc;
unsigned int reserved2[2];
unsigned int glb_cnt_th;
unsigned int glb_rst_st;
unsigned int glb_srst_fst;
unsigned int glb_srst_snd;
unsigned int glb_rst_con;
unsigned int pll_lock;
unsigned int reserved3[6];
unsigned int hwffc_con0;
unsigned int reserved4;
unsigned int hwffc_th;
unsigned int hwffc_intst;
unsigned int apll_con0_s;
unsigned int apll_con1_s;
unsigned int clksel_con0_s;
unsigned int reserved5;
unsigned int clksel_con[74];
unsigned int reserved6[54];
unsigned int clkgate_con[15];
unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
unsigned int ssgtbl[32];
unsigned int softrst_con[10];
unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
unsigned int sdmmc_con[2];
unsigned int sdio_con[2];
unsigned int emmc_con[2];
};
enum {
/* PLLCON0*/
PLL_BP_SHIFT = 15,
PLL_POSTDIV1_SHIFT = 12,
PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
PLL_FBDIV_SHIFT = 0,
PLL_FBDIV_MASK = 0xfff,
/* PLLCON1 */
PLL_PDSEL_SHIFT = 15,
PLL_PD1_SHIFT = 14,
PLL_PD_SHIFT = 13,
PLL_PD_MASK = 1 << PLL_PD_SHIFT,
PLL_DSMPD_SHIFT = 12,
PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
PLL_LOCK_STATUS_SHIFT = 10,
PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
PLL_POSTDIV2_SHIFT = 6,
PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
PLL_REFDIV_SHIFT = 0,
PLL_REFDIV_MASK = 0x3f,
/* PLLCON2 */
PLL_FOUT4PHASEPD_SHIFT = 27,
PLL_FOUTVCOPD_SHIFT = 26,
PLL_FOUTPOSTDIVPD_SHIFT = 25,
PLL_DACPD_SHIFT = 24,
PLL_FRAC_DIV = 0xffffff,
/* CRU_MODE */
PLLMUX_FROM_XIN24M = 0,
PLLMUX_FROM_PLL,
PLLMUX_FROM_RTC32K,
USBPHY480M_MODE_SHIFT = 8,
USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
VPLL1_MODE_SHIFT = 6,
VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT,
VPLL0_MODE_SHIFT = 4,
VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT,
DPLL_MODE_SHIFT = 2,
DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
APLL_MODE_SHIFT = 0,
APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
/* CRU_CLK_SEL0_CON */
CORE_ACLK_DIV_SHIFT = 12,
CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT,
CORE_DBG_DIV_SHIFT = 8,
CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT,
CORE_CLK_PLL_SEL_SHIFT = 6,
CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT,
CORE_CLK_PLL_SEL_APLL = 0,
CORE_CLK_PLL_SEL_VPLL0,
CORE_CLK_PLL_SEL_VPLL1,
CORE_DIV_CON_SHIFT = 0,
CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
/* CRU_CLK_SEL5_CON */
BUS_PLL_SEL_SHIFT = 6,
BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT,
BUS_PLL_SEL_DPLL = 0,
BUS_PLL_SEL_VPLL0,
BUS_PLL_SEL_VPLL1,
BUS_ACLK_DIV_SHIFT = 0,
BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
/* CRU_CLK_SEL6_CON */
BUS_PCLK_DIV_SHIFT = 8,
BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT,
BUS_HCLK_DIV_SHIFT = 0,
BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
/* CRU_CLK_SEL7_CON */
CRYPTO_APK_SEL_SHIFT = 14,
CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
CRYPTO_PLL_SEL_DPLL = 0,
CRYPTO_PLL_SEL_VPLL0,
CRYPTO_PLL_SEL_VPLL1 = 0,
CRYPTO_APK_DIV_SHIFT = 8,
CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
CRYPTO_PLL_SEL_SHIFT = 6,
CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
CRYPTO_DIV_SHIFT = 0,
CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
/* CRU_CLK_SEL8_CON */
DCLK_VOP_SEL_SHIFT = 14,
DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT,
DCLK_VOP_SEL_DIVOUT = 0,
DCLK_VOP_SEL_FRACOUT,
DCLK_VOP_SEL_24M,
DCLK_VOP_PLL_SEL_SHIFT = 10,
DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT,
DCLK_VOP_PLL_SEL_DPLL = 0,
DCLK_VOP_PLL_SEL_VPLL0,
DCLK_VOP_PLL_SEL_VPLL1,
DCLK_VOP_DIV_SHIFT = 0,
DCLK_VOP_DIV_MASK = 0xff,
/* CRU_CLK_SEL25_CON */
/* CRU_CLK_SEL26_CON */
/* CRU_CLK_SEL27_CON */
/* CRU_CLK_SEL28_CON */
CLK_I2C_PLL_SEL_SHIFT = 14,
CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT,
CLK_I2C_PLL_SEL_DPLL = 0,
CLK_I2C_PLL_SEL_VPLL0,
CLK_I2C_PLL_SEL_24M,
CLK_I2C_DIV_CON_SHIFT = 0,
CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT,
/* CRU_CLK_SEL29_CON */
CLK_PWM_PLL_SEL_SHIFT = 14,
CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT,
CLK_PWM_PLL_SEL_DPLL = 0,
CLK_PWM_PLL_SEL_VPLL0,
CLK_PWM_PLL_SEL_24M,
CLK_PWM_DIV_CON_SHIFT = 0,
CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
/* CRU_CLK_SEL30_CON */
/* CRU_CLK_SEL31_CON */
/* CRU_CLK_SEL32_CON */
CLK_SPI_PLL_SEL_SHIFT = 14,
CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT,
CLK_SPI_PLL_SEL_DPLL = 0,
CLK_SPI_PLL_SEL_VPLL0,
CLK_SPI_PLL_SEL_24M,
CLK_SPI_DIV_CON_SHIFT = 0,
CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
/* CRU_CLK_SEL34_CON */
CLK_SARADC_DIV_CON_SHIFT = 0,
CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT,
/* CRU_CLK_SEL36_CON */
PERI_PLL_SEL_SHIFT = 6,
PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT,
PERI_PLL_DPLL = 0,
PERI_PLL_VPLL0,
PERI_PLL_VPLL1,
PERI_ACLK_DIV_SHIFT = 0,
PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
/* CRU_CLK_SEL37_CON */
PERI_PCLK_DIV_SHIFT = 8,
PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT,
PERI_HCLK_DIV_SHIFT = 0,
PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
/* CRU_CLKSEL41_CON */
EMMC_CLK_SEL_SHIFT = 15,
EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
EMMC_CLK_SEL_EMMC = 0,
EMMC_CLK_SEL_EMMC_DIV50,
EMMC_PLL_SHIFT = 8,
EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT,
EMMC_SEL_DPLL = 0,
EMMC_SEL_VPLL0,
EMMC_SEL_VPLL1,
EMMC_SEL_24M,
EMMC_DIV_SHIFT = 0,
EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
/* CRU_CLKSEL43_CON */
MAC_CLK_SPEED_SEL_SHIFT = 15,
MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT,
MAC_CLK_SPEED_SEL_10M = 0,
MAC_CLK_SPEED_SEL_100M,
MAC_CLK_SOURCE_SEL_SHIFT = 14,
MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT,
MAC_CLK_SOURCE_SEL_INTERNAL = 0,
MAC_CLK_SOURCE_SEL_EXTERNAL,
MAC_PLL_SHIFT = 6,
MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT,
MAC_SEL_DPLL = 0,
MAC_SEL_VPLL0,
MAC_SEL_VPLL1,
MAC_DIV_SHIFT = 0,
MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT,
/* CRU_CLK_SEL45_CON */
AUDIO_PCLK_DIV_SHIFT = 8,
AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT,
AUDIO_PLL_SEL_SHIFT = 6,
AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT,
AUDIO_PLL_VPLL0 = 0,
AUDIO_PLL_VPLL1,
AUDIO_PLL_24M,
AUDIO_HCLK_DIV_SHIFT = 0,
AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT,
};
check_member(rk3308_cru, emmc_con[1], 0x494);
#endif

11
arch/arm/include/asm/arch-rk3308/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

197
arch/arm/include/asm/arch-rk3308/grf_rk3308.h Normal file
View File

@ -0,0 +1,197 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
*Copyright 2019 Rockchip Electronics Co., Ltd.
*/
#ifndef _ASM_ARCH_GRF_rk3308_H
#define _ASM_ARCH_GRF_rk3308_H
#include <common.h>
struct rk3308_grf {
unsigned int gpio0a_iomux;
unsigned int reserved0;
unsigned int gpio0b_iomux;
unsigned int reserved1;
unsigned int gpio0c_iomux;
unsigned int reserved2[3];
unsigned int gpio1a_iomux;
unsigned int reserved3;
unsigned int gpio1bl_iomux;
unsigned int gpio1bh_iomux;
unsigned int gpio1cl_iomux;
unsigned int gpio1ch_iomux;
unsigned int gpio1d_iomux;
unsigned int reserved4;
unsigned int gpio2a_iomux;
unsigned int reserved5;
unsigned int gpio2b_iomux;
unsigned int reserved6;
unsigned int gpio2c_iomux;
unsigned int reserved7[3];
unsigned int gpio3a_iomux;
unsigned int reserved8;
unsigned int gpio3b_iomux;
unsigned int reserved9[5];
unsigned int gpio4a_iomux;
unsigned int reserved33;
unsigned int gpio4b_iomux;
unsigned int reserved10;
unsigned int gpio4c_iomux;
unsigned int reserved11;
unsigned int gpio4d_iomux;
unsigned int reserved34;
unsigned int gpio0a_p;
unsigned int gpio0b_p;
unsigned int gpio0c_p;
unsigned int reserved12;
unsigned int gpio1a_p;
unsigned int gpio1b_p;
unsigned int gpio1c_p;
unsigned int gpio1d_p;
unsigned int gpio2a_p;
unsigned int gpio2b_p;
unsigned int gpio2c_p;
unsigned int reserved13;
unsigned int gpio3a_p;
unsigned int gpio3b_p;
unsigned int reserved14[2];
unsigned int gpio4a_p;
unsigned int gpio4b_p;
unsigned int gpio4c_p;
unsigned int gpio4d_p;
unsigned int reserved15[(0x100 - 0xec) / 4 - 1];
unsigned int gpio0a_e;
unsigned int gpio0b_e;
unsigned int gpio0c_e;
unsigned int reserved16;
unsigned int gpio1a_e;
unsigned int gpio1b_e;
unsigned int gpio1c_e;
unsigned int gpio1d_e;
unsigned int gpio2a_e;
unsigned int gpio2b_e;
unsigned int gpio2c_e;
unsigned int reserved17;
unsigned int gpio3a_e;
unsigned int gpio3b_e;
unsigned int reserved18[2];
unsigned int gpio4a_e;
unsigned int gpio4b_e;
unsigned int gpio4c_e;
unsigned int gpio4d_e;
unsigned int gpio0a_sr;
unsigned int gpio0b_sr;
unsigned int gpio0c_sr;
unsigned int reserved19;
unsigned int gpio1a_sr;
unsigned int gpio1b_sr;
unsigned int gpio1c_sr;
unsigned int gpio1d_sr;
unsigned int gpio2a_sr;
unsigned int gpio2b_sr;
unsigned int gpio2c_sr;
unsigned int reserved20;
unsigned int gpio3a_sr;
unsigned int gpio3b_sr;
unsigned int reserved21[2];
unsigned int gpio4a_sr;
unsigned int gpio4b_sr;
unsigned int gpio4c_sr;
unsigned int gpio4d_sr;
unsigned int gpio0a_smt;
unsigned int gpio0b_smt;
unsigned int gpio0c_smt;
unsigned int reserved22;
unsigned int gpio1a_smt;
unsigned int gpio1b_smt;
unsigned int gpio1c_smt;
unsigned int gpio1d_smt;
unsigned int gpio2a_smt;
unsigned int gpio2b_smt;
unsigned int gpio2c_smt;
unsigned int reserved23;
unsigned int gpio3a_smt;
unsigned int gpio3b_smt;
unsigned int reserved35[2];
unsigned int gpio4a_smt;
unsigned int gpio4b_smt;
unsigned int gpio4c_smt;
unsigned int gpio4d_smt;
unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1];
unsigned int soc_con0;
unsigned int soc_con1;
unsigned int soc_con2;
unsigned int soc_con3;
unsigned int soc_con4;
unsigned int soc_con5;
unsigned int soc_con6;
unsigned int soc_con7;
unsigned int soc_con8;
unsigned int soc_con9;
unsigned int soc_con10;
unsigned int reserved25[(0x380 - 0x328) / 4 - 1];
unsigned int soc_status0;
unsigned int reserved26[(0x400 - 0x380) / 4 - 1];
unsigned int cpu_con0;
unsigned int cpu_con1;
unsigned int cpu_con2;
unsigned int reserved27[(0x420 - 0x408) / 4 - 1];
unsigned int cpu_status0;
unsigned int cpu_status1;
unsigned int reserved28[(0x440 - 0x424) / 4 - 1];
unsigned int pvtm_con0;
unsigned int pvtm_con1;
unsigned int pvtm_status0;
unsigned int pvtm_status1;
unsigned int reserved29[(0x460 - 0x44C) / 4 - 1];
unsigned int tsadc_tbl;
unsigned int tsadc_tbh;
unsigned int reserved30[(0x480 - 0x464) / 4 - 1];
unsigned int host0_con0;
unsigned int host0_con1;
unsigned int otg_con0;
unsigned int host0_status0;
unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1];
unsigned int mac_con0;
unsigned int upctrl_con0;
unsigned int upctrl_status0;
unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1];
unsigned int os_reg0;
unsigned int os_reg1;
unsigned int os_reg2;
unsigned int os_reg3;
unsigned int os_reg4;
unsigned int os_reg5;
unsigned int os_reg6;
unsigned int os_reg7;
unsigned int os_reg8;
unsigned int os_reg9;
unsigned int os_reg10;
unsigned int os_reg11;
unsigned int reserved38[(0x600 - 0x52c) / 4 - 1];
unsigned int soc_con12;
unsigned int reserved39;
unsigned int soc_con13;
unsigned int soc_con14;
unsigned int soc_con15;
unsigned int reserved40[(0x800 - 0x610) / 4 - 1];
unsigned int chip_id;
};
check_member(rk3308_grf, gpio0a_p, 0xa0);
struct rk3308_sgrf {
unsigned int soc_con0;
unsigned int soc_con1;
unsigned int con_tzma_r0size;
unsigned int con_secure0;
unsigned int reserved0;
unsigned int clk_timer_en;
unsigned int clkgat_con;
unsigned int fastboot_addr;
unsigned int fastboot_en;
unsigned int reserved1[(0x30 - 0x24) / 4];
unsigned int srst_con;
};
check_member(rk3308_sgrf, fastboot_en, 0x20);
#endif

82
arch/arm/include/asm/arch-rockchip/clock.h
View File

@ -9,6 +9,7 @@
/* define pll mode */
#define RKCLK_PLL_MODE_SLOW 0
#define RKCLK_PLL_MODE_NORMAL 1
#define RKCLK_PLL_MODE_DEEP 2
enum {
ROCKCHIP_SYSCON_NOC,
@ -33,6 +34,81 @@ enum rk_clk_id {
CLK_COUNT,
};
#define PLL(_type, _id, _con, _mode, _mshift, \
_lshift, _pflags, _rtable) \
{ \
.id = _id, \
.type = _type, \
.con_offset = _con, \
.mode_offset = _mode, \
.mode_shift = _mshift, \
.lock_shift = _lshift, \
.pll_flags = _pflags, \
.rate_table = _rtable, \
}
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
_postdiv2, _dsmpd, _frac) \
{ \
.rate = _rate##U, \
.fbdiv = _fbdiv, \
.postdiv1 = _postdiv1, \
.refdiv = _refdiv, \
.postdiv2 = _postdiv2, \
.dsmpd = _dsmpd, \
.frac = _frac, \
}
struct rockchip_pll_rate_table {
unsigned long rate;
unsigned int nr;
unsigned int nf;
unsigned int no;
unsigned int nb;
/* for RK3036/RK3399 */
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
pll_rk3328,
pll_rk3366,
pll_rk3399,
};
struct rockchip_pll_clock {
unsigned int id;
unsigned int con_offset;
unsigned int mode_offset;
unsigned int mode_shift;
unsigned int lock_shift;
enum rockchip_pll_type type;
unsigned int pll_flags;
struct rockchip_pll_rate_table *rate_table;
unsigned int mode_mask;
};
struct rockchip_cpu_rate_table {
unsigned long rate;
unsigned int aclk_div;
unsigned int pclk_div;
};
int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
void __iomem *base, ulong clk_id,
ulong drate);
ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
void __iomem *base, ulong clk_id);
const struct rockchip_cpu_rate_table *
rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
ulong rate);
static inline int rk_pll_id(enum rk_clk_id clk_id)
{
return clk_id - 1;
@ -43,12 +119,6 @@ struct sysreset_reg {
unsigned int glb_srst_snd_value;
};
struct softreset_reg {
void __iomem *base;
unsigned int sf_reset_offset;
unsigned int sf_reset_num;
};
/**
* clk_get_divisor() - Calculate the required clock divisior
*

432
arch/arm/include/asm/arch-rockchip/cru_px30.h Normal file
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@ -0,0 +1,432 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*/
#ifndef _ASM_ARCH_CRU_PX30_H
#define _ASM_ARCH_CRU_PX30_H
#include <common.h>
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24 * MHz)
#define APLL_HZ (600 * MHz)
#define GPLL_HZ (1200 * MHz)
#define NPLL_HZ (1188 * MHz)
#define ACLK_BUS_HZ (200 * MHz)
#define HCLK_BUS_HZ (150 * MHz)
#define PCLK_BUS_HZ (100 * MHz)
#define ACLK_PERI_HZ (200 * MHz)
#define HCLK_PERI_HZ (150 * MHz)
#define PCLK_PMU_HZ (100 * MHz)
/* PX30 pll id */
enum px30_pll_id {
APLL,
DPLL,
CPLL,
NPLL,
GPLL,
PLL_COUNT,
};
struct px30_clk_priv {
struct px30_cru *cru;
ulong gpll_hz;
};
struct px30_pmuclk_priv {
struct px30_pmucru *pmucru;
ulong gpll_hz;
};
struct px30_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
unsigned int con4;
unsigned int reserved0[3];
};
struct px30_cru {
struct px30_pll pll[4];
unsigned int reserved1[8];
unsigned int mode;
unsigned int misc;
unsigned int reserved2[2];
unsigned int glb_cnt_th;
unsigned int glb_rst_st;
unsigned int glb_srst_fst;
unsigned int glb_srst_snd;
unsigned int glb_rst_con;
unsigned int reserved3[7];
unsigned int hwffc_con0;
unsigned int reserved4;
unsigned int hwffc_th;
unsigned int hwffc_intst;
unsigned int apll_con0_s;
unsigned int apll_con1_s;
unsigned int clksel_con0_s;
unsigned int reserved5;
unsigned int clksel_con[60];
unsigned int reserved6[4];
unsigned int clkgate_con[18];
unsigned int reserved7[(0x280 - 0x244) / 4 - 1];
unsigned int ssgtbl[32];
unsigned int softrst_con[12];
unsigned int reserved8[(0x380 - 0x32c) / 4 - 1];
unsigned int sdmmc_con[2];
unsigned int sdio_con[2];
unsigned int emmc_con[2];
unsigned int reserved9[(0x400 - 0x394) / 4 - 1];
unsigned int autocs_con[8];
};
check_member(px30_cru, autocs_con[7], 0x41c);
struct px30_pmucru {
struct px30_pll pll;
unsigned int pmu_mode;
unsigned int reserved1[7];
unsigned int pmu_clksel_con[6];
unsigned int reserved2[10];
unsigned int pmu_clkgate_con[2];
unsigned int reserved3[14];
unsigned int pmu_autocs_con[2];
};
check_member(px30_pmucru, pmu_autocs_con[1], 0xc4);
struct pll_rate_table {
unsigned long rate;
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
struct cpu_rate_table {
unsigned long rate;
unsigned int aclk_div;
unsigned int pclk_div;
};
enum {
/* PLLCON0*/
PLL_BP_SHIFT = 15,
PLL_POSTDIV1_SHIFT = 12,
PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
PLL_FBDIV_SHIFT = 0,
PLL_FBDIV_MASK = 0xfff,
/* PLLCON1 */
PLL_PDSEL_SHIFT = 15,
PLL_PD1_SHIFT = 14,
PLL_PD_SHIFT = 13,
PLL_PD_MASK = 1 << PLL_PD_SHIFT,
PLL_DSMPD_SHIFT = 12,
PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
PLL_LOCK_STATUS_SHIFT = 10,
PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
PLL_POSTDIV2_SHIFT = 6,
PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
PLL_REFDIV_SHIFT = 0,
PLL_REFDIV_MASK = 0x3f,
/* PLLCON2 */
PLL_FOUT4PHASEPD_SHIFT = 27,
PLL_FOUTVCOPD_SHIFT = 26,
PLL_FOUTPOSTDIVPD_SHIFT = 25,
PLL_DACPD_SHIFT = 24,
PLL_FRAC_DIV = 0xffffff,
/* CRU_MODE */
PLLMUX_FROM_XIN24M = 0,
PLLMUX_FROM_PLL,
PLLMUX_FROM_RTC32K,
USBPHY480M_MODE_SHIFT = 8,
USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
NPLL_MODE_SHIFT = 6,
NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT,
DPLL_MODE_SHIFT = 4,
DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
CPLL_MODE_SHIFT = 2,
CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT,
APLL_MODE_SHIFT = 0,
APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
/* CRU_CLK_SEL0_CON */
CORE_ACLK_DIV_SHIFT = 12,
CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT,
CORE_DBG_DIV_SHIFT = 8,
CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT,
CORE_CLK_PLL_SEL_SHIFT = 7,
CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
CORE_CLK_PLL_SEL_APLL = 0,
CORE_CLK_PLL_SEL_GPLL,
CORE_DIV_CON_SHIFT = 0,
CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
/* CRU_CLK_SEL3_CON */
ACLK_VO_PLL_SHIFT = 6,
ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT,
ACLK_VO_SEL_GPLL = 0,
ACLK_VO_SEL_CPLL,
ACLK_VO_SEL_NPLL,
ACLK_VO_DIV_SHIFT = 0,
ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT,
/* CRU_CLK_SEL5_CON */
DCLK_VOPB_SEL_SHIFT = 14,
DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT,
DCLK_VOPB_SEL_DIVOUT = 0,
DCLK_VOPB_SEL_FRACOUT,
DCLK_VOPB_SEL_24M,
DCLK_VOPB_PLL_SEL_SHIFT = 11,
DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT,
DCLK_VOPB_PLL_SEL_CPLL = 0,
DCLK_VOPB_PLL_SEL_NPLL,
DCLK_VOPB_DIV_SHIFT = 0,
DCLK_VOPB_DIV_MASK = 0xff,
/* CRU_CLK_SEL8_CON */
DCLK_VOPL_SEL_SHIFT = 14,
DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT,
DCLK_VOPL_SEL_DIVOUT = 0,
DCLK_VOPL_SEL_FRACOUT,
DCLK_VOPL_SEL_24M,
DCLK_VOPL_PLL_SEL_SHIFT = 11,
DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT,
DCLK_VOPL_PLL_SEL_NPLL = 0,
DCLK_VOPL_PLL_SEL_CPLL,
DCLK_VOPL_DIV_SHIFT = 0,
DCLK_VOPL_DIV_MASK = 0xff,
/* CRU_CLK_SEL14_CON */
PERI_PLL_SEL_SHIFT = 15,
PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
PERI_PLL_GPLL = 0,
PERI_PLL_CPLL,
PERI_HCLK_DIV_SHIFT = 8,
PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
PERI_ACLK_DIV_SHIFT = 0,
PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
/* CRU_CLKSEL15_CON */
NANDC_CLK_SEL_SHIFT = 15,
NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT,
NANDC_CLK_SEL_NANDC = 0,
NANDC_CLK_SEL_NANDC_DIV50,
NANDC_DIV50_SHIFT = 8,
NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT,
NANDC_PLL_SHIFT = 6,
NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT,
NANDC_SEL_GPLL = 0,
NANDC_SEL_CPLL,
NANDC_SEL_NPLL,
NANDC_DIV_SHIFT = 0,
NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT,
/* CRU_CLKSEL20_CON */
EMMC_PLL_SHIFT = 14,
EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
EMMC_SEL_GPLL = 0,
EMMC_SEL_CPLL,
EMMC_SEL_NPLL,
EMMC_SEL_24M,
EMMC_DIV_SHIFT = 0,
EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
/* CRU_CLKSEL21_CON */
EMMC_CLK_SEL_SHIFT = 15,
EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
EMMC_CLK_SEL_EMMC = 0,
EMMC_CLK_SEL_EMMC_DIV50,
EMMC_DIV50_SHIFT = 0,
EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT,
/* CRU_CLKSEL22_CON */
GMAC_PLL_SEL_SHIFT = 14,
GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT,
GMAC_PLL_SEL_GPLL = 0,
GMAC_PLL_SEL_CPLL,
GMAC_PLL_SEL_NPLL,
CLK_GMAC_DIV_SHIFT = 8,
CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT,
SFC_PLL_SEL_SHIFT = 7,
SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
SFC_DIV_CON_SHIFT = 0,
SFC_DIV_CON_MASK = 0x7f,
/* CRU_CLK_SEL23_CON */
BUS_PLL_SEL_SHIFT = 15,
BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT,
BUS_PLL_SEL_GPLL = 0,
BUS_PLL_SEL_CPLL,
BUS_ACLK_DIV_SHIFT = 8,
BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
RMII_CLK_SEL_SHIFT = 7,
RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT,
RMII_CLK_SEL_10M = 0,
RMII_CLK_SEL_100M,
RMII_EXTCLK_SEL_SHIFT = 6,
RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
RMII_EXTCLK_SEL_INT = 0,
RMII_EXTCLK_SEL_EXT,
PCLK_GMAC_DIV_SHIFT = 0,
PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT,
/* CRU_CLK_SEL24_CON */
BUS_PCLK_DIV_SHIFT = 8,
BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT,
BUS_HCLK_DIV_SHIFT = 0,
BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
/* CRU_CLK_SEL25_CON */
CRYPTO_APK_SEL_SHIFT = 14,
CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
CRYPTO_PLL_SEL_GPLL = 0,
CRYPTO_PLL_SEL_CPLL,
CRYPTO_PLL_SEL_NPLL = 0,
CRYPTO_APK_DIV_SHIFT = 8,
CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
CRYPTO_PLL_SEL_SHIFT = 6,
CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
CRYPTO_DIV_SHIFT = 0,
CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
/* CRU_CLK_SEL30_CON */
CLK_I2S1_DIV_CON_MASK = 0x7f,
CLK_I2S1_PLL_SEL_MASK = 0X1 << 8,
CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8,
CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8,
CLK_I2S1_SEL_MASK = 0x3 << 10,
CLK_I2S1_SEL_I2S1 = 0x0 << 10,
CLK_I2S1_SEL_FRAC = 0x1 << 10,
CLK_I2S1_SEL_MCLK_IN = 0x2 << 10,
CLK_I2S1_SEL_OSC = 0x3 << 10,
CLK_I2S1_OUT_SEL_MASK = 0x1 << 15,
CLK_I2S1_OUT_SEL_I2S1 = 0x0 << 15,
CLK_I2S1_OUT_SEL_OSC = 0x1 << 15,
/* CRU_CLK_SEL31_CON */
CLK_I2S1_FRAC_NUMERATOR_SHIFT = 16,
CLK_I2S1_FRAC_NUMERATOR_MASK = 0xffff << 16,
CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0,
CLK_I2S1_FRAC_DENOMINATOR_MASK = 0xffff,
/* CRU_CLK_SEL34_CON */
UART1_PLL_SEL_SHIFT = 14,
UART1_PLL_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
UART1_PLL_SEL_GPLL = 0,
UART1_PLL_SEL_24M,
UART1_PLL_SEL_480M,
UART1_PLL_SEL_NPLL,
UART1_DIV_CON_SHIFT = 0,
UART1_DIV_CON_MASK = 0x1f << UART1_DIV_CON_SHIFT,
/* CRU_CLK_SEL35_CON */
UART1_CLK_SEL_SHIFT = 14,
UART1_CLK_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
UART1_CLK_SEL_UART1 = 0,
UART1_CLK_SEL_UART1_NP5,
UART1_CLK_SEL_UART1_FRAC,
UART1_DIVNP5_SHIFT = 0,
UART1_DIVNP5_MASK = 0x1f << UART1_DIVNP5_SHIFT,
/* CRU_CLK_SEL37_CON */
UART2_PLL_SEL_SHIFT = 14,
UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
UART2_PLL_SEL_GPLL = 0,
UART2_PLL_SEL_24M,
UART2_PLL_SEL_480M,
UART2_PLL_SEL_NPLL,
UART2_DIV_CON_SHIFT = 0,
UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT,
/* CRU_CLK_SEL38_CON */
UART2_CLK_SEL_SHIFT = 14,
UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
UART2_CLK_SEL_UART2 = 0,
UART2_CLK_SEL_UART2_NP5,
UART2_CLK_SEL_UART2_FRAC,
UART2_DIVNP5_SHIFT = 0,
UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT,
/* CRU_CLK_SEL46_CON */
UART5_PLL_SEL_SHIFT = 14,
UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
UART5_PLL_SEL_GPLL = 0,
UART5_PLL_SEL_24M,
UART5_PLL_SEL_480M,
UART5_PLL_SEL_NPLL,
UART5_DIV_CON_SHIFT = 0,
UART5_DIV_CON_MASK = 0x1f << UART5_DIV_CON_SHIFT,
/* CRU_CLK_SEL47_CON */
UART5_CLK_SEL_SHIFT = 14,
UART5_CLK_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
UART5_CLK_SEL_UART5 = 0,
UART5_CLK_SEL_UART5_NP5,
UART5_CLK_SEL_UART5_FRAC,
UART5_DIVNP5_SHIFT = 0,
UART5_DIVNP5_MASK = 0x1f << UART5_DIVNP5_SHIFT,
/* CRU_CLK_SEL49_CON */
CLK_I2C_PLL_SEL_GPLL = 0,
CLK_I2C_PLL_SEL_24M,
CLK_I2C_DIV_CON_MASK = 0x7f,
CLK_I2C_PLL_SEL_MASK = 1,
CLK_I2C1_PLL_SEL_SHIFT = 15,
CLK_I2C1_DIV_CON_SHIFT = 8,
CLK_I2C0_PLL_SEL_SHIFT = 7,
CLK_I2C0_DIV_CON_SHIFT = 0,
/* CRU_CLK_SEL50_CON */
CLK_I2C3_PLL_SEL_SHIFT = 15,
CLK_I2C3_DIV_CON_SHIFT = 8,
CLK_I2C2_PLL_SEL_SHIFT = 7,
CLK_I2C2_DIV_CON_SHIFT = 0,
/* CRU_CLK_SEL52_CON */
CLK_PWM_PLL_SEL_GPLL = 0,
CLK_PWM_PLL_SEL_24M,
CLK_PWM_DIV_CON_MASK = 0x7f,
CLK_PWM_PLL_SEL_MASK = 1,
CLK_PWM1_PLL_SEL_SHIFT = 15,
CLK_PWM1_DIV_CON_SHIFT = 8,
CLK_PWM0_PLL_SEL_SHIFT = 7,
CLK_PWM0_DIV_CON_SHIFT = 0,
/* CRU_CLK_SEL53_CON */
CLK_SPI_PLL_SEL_GPLL = 0,
CLK_SPI_PLL_SEL_24M,
CLK_SPI_DIV_CON_MASK = 0x7f,
CLK_SPI_PLL_SEL_MASK = 1,
CLK_SPI1_PLL_SEL_SHIFT = 15,
CLK_SPI1_DIV_CON_SHIFT = 8,
CLK_SPI0_PLL_SEL_SHIFT = 7,
CLK_SPI0_DIV_CON_SHIFT = 0,
/* CRU_CLK_SEL55_CON */
CLK_SARADC_DIV_CON_SHIFT = 0,
CLK_SARADC_DIV_CON_MASK = 0x7ff,
/* CRU_CLK_GATE10_CON */
CLK_I2S1_OUT_MCLK_PAD_MASK = 0x1 << 9,
CLK_I2S1_OUT_MCLK_PAD_ENABLE = 0x1 << 9,
CLK_I2S1_OUT_MCLK_PAD_DISABLE = 0x0 << 9,
/* CRU_PMU_MODE */
GPLL_MODE_SHIFT = 0,
GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
/* CRU_PMU_CLK_SEL0_CON */
CLK_PMU_PCLK_DIV_SHIFT = 0,
CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
};
#endif

144
arch/arm/include/asm/arch-rockchip/grf_px30.h Normal file
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@ -0,0 +1,144 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*/
#ifndef _ASM_ARCH_GRF_px30_H
#define _ASM_ARCH_GRF_px30_H
#include <common.h>
struct px30_grf {
unsigned int gpio1al_iomux;
unsigned int gpio1ah_iomux;
unsigned int gpio1bl_iomux;
unsigned int gpio1bh_iomux;
unsigned int gpio1cl_iomux;
unsigned int gpio1ch_iomux;
unsigned int gpio1dl_iomux;
unsigned int gpio1dh_iomux;
unsigned int gpio2al_iomux;
unsigned int gpio2ah_iomux;
unsigned int gpio2bl_iomux;
unsigned int gpio2bh_iomux;
unsigned int gpio2cl_iomux;
unsigned int gpio2ch_iomux;
unsigned int gpio2dl_iomux;
unsigned int gpio2dh_iomux;
unsigned int gpio3al_iomux;
unsigned int gpio3ah_iomux;
unsigned int gpio3bl_iomux;
unsigned int gpio3bh_iomux;
unsigned int gpio3cl_iomux;
unsigned int gpio3ch_iomux;
unsigned int gpio3dl_iomux;
unsigned int gpio3dh_iomux;
unsigned int gpio1a_p;
unsigned int gpio1b_p;
unsigned int gpio1c_p;
unsigned int gpio1d_p;
unsigned int gpio2a_p;
unsigned int gpio2b_p;
unsigned int gpio2c_p;
unsigned int gpio2d_p;
unsigned int gpio3a_p;
unsigned int gpio3b_p;
unsigned int gpio3c_p;
unsigned int gpio3d_p;
unsigned int gpio1a_sr;
unsigned int gpio1b_sr;
unsigned int gpio1c_sr;
unsigned int gpio1d_sr;
unsigned int gpio2a_sr;
unsigned int gpio2b_sr;
unsigned int gpio2c_sr;
unsigned int gpio2d_sr;
unsigned int gpio3a_sr;
unsigned int gpio3b_sr;
unsigned int gpio3c_sr;
unsigned int gpio3d_sr;
unsigned int gpio1a_smt;
unsigned int gpio1b_smt;
unsigned int gpio1c_smt;
unsigned int gpio1d_smt;
unsigned int gpio2a_smt;
unsigned int gpio2b_smt;
unsigned int gpio2c_smt;
unsigned int gpio2d_smt;
unsigned int gpio3a_smt;
unsigned int gpio3b_smt;
unsigned int gpio3c_smt;
unsigned int gpio3d_smt;
unsigned int gpio1a_e;
unsigned int gpio1b_e;
unsigned int gpio1c_e;
unsigned int gpio1d_e;
unsigned int gpio2a_e;
unsigned int gpio2b_e;
unsigned int gpio2c_e;
unsigned int gpio2d_e;
unsigned int gpio3a_e;
unsigned int gpio3b_e;
unsigned int gpio3c_e;
unsigned int gpio3d_e;
unsigned int reserved0[(0x180 - 0x11C) / 4 - 1];
unsigned int io_vsel;
unsigned int iofunc_con0;
unsigned int reserved1[(0x400 - 0x184) / 4 - 1];
unsigned int soc_con[6];
unsigned int reserved2[(0x480 - 0x414) / 4 - 1];
unsigned int soc_status0;
unsigned int reserved3[(0x500 - 0x480) / 4 - 1];
unsigned int cpu_con[3];
unsigned int reserved4[5];
unsigned int cpu_status[2];
unsigned int reserved5[2];
unsigned int soc_noc_con[2];
unsigned int reserved6[6];
unsigned int ddr_bankhash[4];
unsigned int reserved7[(0x700 - 0x55c) / 4 - 1];
unsigned int host0_con[2];
unsigned int reserved8[(0x880 - 0x704) / 4 - 1];
unsigned int otg_con3;
unsigned int reserved9[3];
unsigned int host0_status4;
unsigned int reserved10[(0x904 - 0x890) / 4 - 1];
unsigned int mac_con1;
};
check_member(px30_grf, mac_con1, 0x904);
struct px30_pmugrf {
unsigned int gpio0a_e;
unsigned int gpio0b_e;
unsigned int gpio0c_e;
unsigned int gpio0d_e;
unsigned int gpio0a_p;
unsigned int gpio0b_p;
unsigned int gpio0c_p;
unsigned int gpio0d_p;
unsigned int gpio0al_iomux;
unsigned int gpio0bl_iomux;
unsigned int gpio0cl_iomux;
unsigned int gpio0dl_iomux;
unsigned int gpio0l_sr;
unsigned int gpio0h_sr;
unsigned int gpio0l_smt;
unsigned int gpio0h_smt;
unsigned int reserved1[(0x100 - 0x3c) / 4 - 1];
unsigned int soc_con[4];
unsigned int reserved2[(0x180 - 0x10c) / 4 - 1];
unsigned int pvtm_con[2];
unsigned int reserved3[2];
unsigned int pvtm_status[2];
unsigned int reserved4[(0x200 - 0x194) / 4 - 1];
unsigned int os_reg[12];
unsigned int reset_function_status;
};
check_member(px30_pmugrf, reset_function_status, 0x230);
#endif

168
arch/arm/include/asm/arch-rockchip/sdram.h
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@ -1,102 +1,86 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2015 Google, Inc
*
* Copyright 2014 Rockchip Inc.
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
*/
#ifndef _ASM_ARCH_RK3288_SDRAM_H__
#define _ASM_ARCH_RK3288_SDRAM_H__
#ifndef _ASM_ARCH_SDRAM_H
#define _ASM_ARCH_SDRAM_H
struct rk3288_sdram_channel {
/*
* bit width in address, eg:
* 8 banks using 3 bit to address,
* 2 cs using 1 bit to address.
*/
u8 rank;
u8 col;
u8 bk;
u8 bw;
u8 dbw;
u8 row_3_4;
u8 cs0_row;
u8 cs1_row;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/*
* For of-platdata, which would otherwise convert this into two
* byte-swapped integers. With a size of 9 bytes, this struct will
* appear in of-platdata as a byte array.
*
* If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
*/
u8 dummy;
#endif
enum {
DDR4 = 0,
DDR3 = 0x3,
LPDDR2 = 0x5,
LPDDR3 = 0x6,
LPDDR4 = 0x7,
UNUSED = 0xFF
};
struct rk3288_sdram_pctl_timing {
u32 togcnt1u;
u32 tinit;
u32 trsth;
u32 togcnt100n;
u32 trefi;
u32 tmrd;
u32 trfc;
u32 trp;
u32 trtw;
u32 tal;
u32 tcl;
u32 tcwl;
u32 tras;
u32 trc;
u32 trcd;
u32 trrd;
u32 trtp;
u32 twr;
u32 twtr;
u32 texsr;
u32 txp;
u32 txpdll;
u32 tzqcs;
u32 tzqcsi;
u32 tdqs;
u32 tcksre;
u32 tcksrx;
u32 tcke;
u32 tmod;
u32 trstl;
u32 tzqcl;
u32 tmrr;
u32 tckesr;
u32 tdpd;
};
check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
/*
* sys_reg2 bitfield struct
* [31] row_3_4_ch1
* [30] row_3_4_ch0
* [29:28] chinfo
* [27] rank_ch1
* [26:25] col_ch1
* [24] bk_ch1
* [23:22] low bits of cs0_row_ch1
* [21:20] low bits of cs1_row_ch1
* [19:18] bw_ch1
* [17:16] dbw_ch1;
* [15:13] ddrtype
* [12] channelnum
* [11] rank_ch0
* [10:9] col_ch0,
* [8] bk_ch0
* [7:6] low bits of cs0_row_ch0
* [5:4] low bits of cs1_row_ch0
* [3:2] bw_ch0
* [1:0] dbw_ch0
*/
#define SYS_REG_DDRTYPE_SHIFT 13
#define SYS_REG_DDRTYPE_MASK 7
#define SYS_REG_NUM_CH_SHIFT 12
#define SYS_REG_NUM_CH_MASK 1
#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
#define SYS_REG_ROW_3_4_MASK 1
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
#define SYS_REG_COL_MASK 3
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
#define SYS_REG_BK_MASK 1
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
#define SYS_REG_DBW_MASK 3
struct rk3288_sdram_phy_timing {
u32 dtpr0;
u32 dtpr1;
u32 dtpr2;
u32 mr[4];
};
/*
* sys_reg3 bitfield struct
* [7] high bit of cs0_row_ch1
* [6] high bit of cs1_row_ch1
* [5] high bit of cs0_row_ch0
* [4] high bit of cs1_row_ch0
* [3:2] cs1_col_ch1
* [1:0] cs1_col_ch0
*/
#define SYS_REG_VERSION_SHIFT 28
#define SYS_REG_VERSION_MASK 0xf
#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2)
#define SYS_REG_EXTEND_CS0_ROW_MASK 1
#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2)
#define SYS_REG_EXTEND_CS1_ROW_MASK 1
#define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2)
#define SYS_REG_CS1_COL_MASK 3
struct rk3288_base_params {
u32 noc_timing;
u32 noc_activate;
u32 ddrconfig;
u32 ddr_freq;
u32 dramtype;
/*
* DDR Stride is address mapping for DRAM space
* Stride Ch 0 range Ch1 range Total
* 0x00 0-256MB 256MB-512MB 512MB
* 0x05 0-1GB 0-1GB 1GB
* 0x09 0-2GB 0-2GB 2GB
* 0x0d 0-4GB 0-4GB 4GB
* 0x17 N/A 0-4GB 4GB
* 0x1a 0-4GB 4GB-8GB 8GB
*/
u32 stride;
u32 odt;
};
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
/* Called by U-Boot board_init_r for Rockchip SoCs */
int dram_init(void);
#endif

116
arch/arm/include/asm/arch-rockchip/sdram_common.h
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@ -1,19 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
* Copyright (C) 2018 Rockchip Electronics Co., Ltd
*/
#ifndef _ASM_ARCH_SDRAM_COMMON_H
#define _ASM_ARCH_SDRAM_COMMON_H
enum {
DDR4 = 0,
DDR3 = 0x3,
LPDDR2 = 0x5,
LPDDR3 = 0x6,
LPDDR4 = 0x7,
UNUSED = 0xFF
};
#ifndef MHZ
#define MHZ (1000 * 1000)
#endif
#define PATTERN (0x5aa5f00f)
#define MIN(a, b) (((a) > (b)) ? (b) : (a))
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
struct sdram_cap_info {
unsigned int rank;
@ -32,6 +32,8 @@ struct sdram_cap_info {
unsigned int row_3_4;
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int cs0_high16bit_row;
unsigned int cs1_high16bit_row;
unsigned int ddrconfig;
};
@ -43,8 +45,9 @@ struct sdram_base_params {
unsigned int odt;
};
#define DDR_SYS_REG_VERSION (0x2)
/*
* sys_reg bitfield struct
* sys_reg2 bitfield struct
* [31] row_3_4_ch1
* [30] row_3_4_ch0
* [29:28] chinfo
@ -64,49 +67,38 @@ struct sdram_base_params {
* [5:4] cs1_row_ch0
* [3:2] bw_ch0
* [1:0] dbw_ch0
*/
#define SYS_REG_DDRTYPE_SHIFT 13
#define DDR_SYS_REG_VERSION 2
#define SYS_REG_DDRTYPE_MASK 7
#define SYS_REG_NUM_CH_SHIFT 12
#define SYS_REG_NUM_CH_MASK 1
#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
#define SYS_REG_ROW_3_4_MASK 1
*/
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT)
#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \
SYS_REG_NUM_CH_SHIFT)
#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
#define SYS_REG_RANK_MASK 1
#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
SYS_REG_RANK_SHIFT(ch))
#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
#define SYS_REG_COL_MASK 3
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
#define SYS_REG_BK_MASK 1
#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16)))
#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1))
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16)))
#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3))
#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
SYS_REG_BK_SHIFT(ch))
#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
#define SYS_REG_CS0_ROW_MASK 3
#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
#define SYS_REG_CS1_ROW_MASK 3
#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
#define SYS_REG_BW_MASK 3
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
(8 + ((ch) * 16)))
#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1))
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16)))
#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3))
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16)))
#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3))
/* sys reg 3 */
#define SYS_REG_ENC_VERSION(n) ((n) << 28)
#define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf)
#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
(5 + 2 * (ch)); \
} while (0)
#define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \
((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \
((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12)
#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
(os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
(os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
@ -115,14 +107,12 @@ struct sdram_base_params {
(4 + 2 * (ch)); \
} while (0)
#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch))
#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
#define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \
((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \
((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12)
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
/* Called by U-Boot board_init_r for Rockchip SoCs */
int dram_init(void);
#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch)))
#define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3))
#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
inline void sdram_print_dram_type(unsigned char dramtype)
@ -144,4 +134,26 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
void sdram_print_stride(unsigned int stride);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
void sdram_org_config(struct sdram_cap_info *cap_info,
struct sdram_base_params *base,
u32 *p_os_reg2, u32 *p_os_reg3, u32 channel);
int sdram_detect_bw(struct sdram_cap_info *cap_info);
int sdram_detect_cs(struct sdram_cap_info *cap_info);
int sdram_detect_col(struct sdram_cap_info *cap_info,
u32 coltmp);
int sdram_detect_bank(struct sdram_cap_info *cap_info,
u32 coltmp, u32 bktmp);
int sdram_detect_bg(struct sdram_cap_info *cap_info,
u32 coltmp);
int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type);
int sdram_detect_row(struct sdram_cap_info *cap_info,
u32 coltmp, u32 bktmp, u32 rowtmp);
int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
u32 coltmp, u32 bktmp);
int sdram_detect_high_row(struct sdram_cap_info *cap_info);
int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type);
u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type);
void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n);
#endif

85
arch/arm/include/asm/arch-rockchip/sdram_msch.h Normal file
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@ -0,0 +1,85 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
#ifndef _ASM_ARCH_SDRAM_MSCH_H
#define _ASM_ARCH_SDRAM_MSCH_H
union noc_ddrtiminga0 {
u32 d32;
struct {
unsigned acttoact : 6;
unsigned reserved0 : 2;
unsigned rdtomiss : 6;
unsigned reserved1 : 2;
unsigned wrtomiss : 6;
unsigned reserved2 : 2;
unsigned readlatency : 8;
} b;
};
union noc_ddrtimingb0 {
u32 d32;
struct {
unsigned rdtowr : 5;
unsigned reserved0 : 3;
unsigned wrtord : 5;
unsigned reserved1 : 3;
unsigned rrd : 4;
unsigned reserved2 : 4;
unsigned faw : 6;
unsigned reserved3 : 2;
} b;
};
union noc_ddrtimingc0 {
u32 d32;
struct {
unsigned burstpenalty : 4;
unsigned reserved0 : 4;
unsigned wrtomwr : 6;
unsigned reserved1 : 18;
} b;
};
union noc_devtodev0 {
u32 d32;
struct {
unsigned busrdtord : 3;
unsigned reserved0 : 1;
unsigned busrdtowr : 3;
unsigned reserved1 : 1;
unsigned buswrtord : 3;
unsigned reserved2 : 1;
unsigned buswrtowr : 3;
unsigned reserved3 : 17;
} b;
};
union noc_ddrmode {
u32 d32;
struct {
unsigned autoprecharge : 1;
unsigned bypassfiltering : 1;
unsigned fawbank : 1;
unsigned burstsize : 2;
unsigned mwrsize : 2;
unsigned reserved2 : 1;
unsigned forceorder : 8;
unsigned forceorderstate : 8;
unsigned reserved3 : 8;
} b;
};
union noc_ddr4timing {
u32 d32;
struct {
unsigned ccdl : 3;
unsigned wrtordl : 5;
unsigned rrdl : 4;
unsigned reserved1 : 20;
} b;
};
#endif

139
arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h Normal file
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@ -0,0 +1,139 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd
*/
#ifndef _ASM_ARCH_SDRAM_PCTL_PX30_H
#define _ASM_ARCH_SDRAM_PCTL_PX30_H
#include <asm/arch-rockchip/sdram_common.h>
struct ddr_pctl_regs {
u32 pctl[30][2];
};
/* ddr pctl registers define */
#define DDR_PCTL2_MSTR 0x0
#define DDR_PCTL2_STAT 0x4
#define DDR_PCTL2_MSTR1 0x8
#define DDR_PCTL2_MRCTRL0 0x10
#define DDR_PCTL2_MRCTRL1 0x14
#define DDR_PCTL2_MRSTAT 0x18
#define DDR_PCTL2_MRCTRL2 0x1c
#define DDR_PCTL2_DERATEEN 0x20
#define DDR_PCTL2_DERATEINT 0x24
#define DDR_PCTL2_PWRCTL 0x30
#define DDR_PCTL2_PWRTMG 0x34
#define DDR_PCTL2_HWLPCTL 0x38
#define DDR_PCTL2_RFSHCTL0 0x50
#define DDR_PCTL2_RFSHCTL1 0x54
#define DDR_PCTL2_RFSHCTL2 0x58
#define DDR_PCTL2_RFSHCTL4 0x5c
#define DDR_PCTL2_RFSHCTL3 0x60
#define DDR_PCTL2_RFSHTMG 0x64
#define DDR_PCTL2_RFSHTMG1 0x68
#define DDR_PCTL2_RFSHCTL5 0x6c
#define DDR_PCTL2_INIT0 0xd0
#define DDR_PCTL2_INIT1 0xd4
#define DDR_PCTL2_INIT2 0xd8
#define DDR_PCTL2_INIT3 0xdc
#define DDR_PCTL2_INIT4 0xe0
#define DDR_PCTL2_INIT5 0xe4
#define DDR_PCTL2_INIT6 0xe8
#define DDR_PCTL2_INIT7 0xec
#define DDR_PCTL2_DIMMCTL 0xf0
#define DDR_PCTL2_RANKCTL 0xf4
#define DDR_PCTL2_CHCTL 0xfc
#define DDR_PCTL2_DRAMTMG0 0x100
#define DDR_PCTL2_DRAMTMG1 0x104
#define DDR_PCTL2_DRAMTMG2 0x108
#define DDR_PCTL2_DRAMTMG3 0x10c
#define DDR_PCTL2_DRAMTMG4 0x110
#define DDR_PCTL2_DRAMTMG5 0x114
#define DDR_PCTL2_DRAMTMG6 0x118
#define DDR_PCTL2_DRAMTMG7 0x11c
#define DDR_PCTL2_DRAMTMG8 0x120
#define DDR_PCTL2_DRAMTMG9 0x124
#define DDR_PCTL2_DRAMTMG10 0x128
#define DDR_PCTL2_DRAMTMG11 0x12c
#define DDR_PCTL2_DRAMTMG12 0x130
#define DDR_PCTL2_DRAMTMG13 0x134
#define DDR_PCTL2_DRAMTMG14 0x138
#define DDR_PCTL2_DRAMTMG15 0x13c
#define DDR_PCTL2_DRAMTMG16 0x140
#define DDR_PCTL2_ZQCTL0 0x180
#define DDR_PCTL2_ZQCTL1 0x184
#define DDR_PCTL2_ZQCTL2 0x188
#define DDR_PCTL2_ZQSTAT 0x18c
#define DDR_PCTL2_DFITMG0 0x190
#define DDR_PCTL2_DFITMG1 0x194
#define DDR_PCTL2_DFILPCFG0 0x198
#define DDR_PCTL2_DFILPCFG1 0x19c
#define DDR_PCTL2_DFIUPD0 0x1a0
#define DDR_PCTL2_DFIUPD1 0x1a4
#define DDR_PCTL2_DFIUPD2 0x1a8
#define DDR_PCTL2_DFIMISC 0x1b0
#define DDR_PCTL2_DFITMG2 0x1b4
#define DDR_PCTL2_DFITMG3 0x1b8
#define DDR_PCTL2_DFISTAT 0x1bc
#define DDR_PCTL2_DBICTL 0x1c0
#define DDR_PCTL2_ADDRMAP0 0x200
#define DDR_PCTL2_ADDRMAP1 0x204
#define DDR_PCTL2_ADDRMAP2 0x208
#define DDR_PCTL2_ADDRMAP3 0x20c
#define DDR_PCTL2_ADDRMAP4 0x210
#define DDR_PCTL2_ADDRMAP5 0x214
#define DDR_PCTL2_ADDRMAP6 0x218
#define DDR_PCTL2_ADDRMAP7 0x21c
#define DDR_PCTL2_ADDRMAP8 0x220
#define DDR_PCTL2_ADDRMAP9 0x224
#define DDR_PCTL2_ADDRMAP10 0x228
#define DDR_PCTL2_ADDRMAP11 0x22c
#define DDR_PCTL2_ODTCFG 0x240
#define DDR_PCTL2_ODTMAP 0x244
#define DDR_PCTL2_SCHED 0x250
#define DDR_PCTL2_SCHED1 0x254
#define DDR_PCTL2_PERFHPR1 0x25c
#define DDR_PCTL2_PERFLPR1 0x264
#define DDR_PCTL2_PERFWR1 0x26c
#define DDR_PCTL2_DQMAP0 0x280
#define DDR_PCTL2_DQMAP1 0x284
#define DDR_PCTL2_DQMAP2 0x288
#define DDR_PCTL2_DQMAP3 0x28c
#define DDR_PCTL2_DQMAP4 0x290
#define DDR_PCTL2_DQMAP5 0x294
#define DDR_PCTL2_DBG0 0x300
#define DDR_PCTL2_DBG1 0x304
#define DDR_PCTL2_DBGCAM 0x308
#define DDR_PCTL2_DBGCMD 0x30c
#define DDR_PCTL2_DBGSTAT 0x310
#define DDR_PCTL2_SWCTL 0x320
#define DDR_PCTL2_SWSTAT 0x324
#define DDR_PCTL2_POISONCFG 0x36c
#define DDR_PCTL2_POISONSTAT 0x370
#define DDR_PCTL2_ADVECCINDEX 0x374
#define DDR_PCTL2_ADVECCSTAT 0x378
#define DDR_PCTL2_PSTAT 0x3fc
#define DDR_PCTL2_PCCFG 0x400
#define DDR_PCTL2_PCFGR_n 0x404
#define DDR_PCTL2_PCFGW_n 0x408
#define DDR_PCTL2_PCTRL_n 0x490
/* PCTL2_MRSTAT */
#define MR_WR_BUSY BIT(0)
void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
u32 dramtype);
int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
u32 dramtype);
u32 pctl_dis_zqcs_aref(void __iomem *pctl_base);
void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq);
u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs,
struct sdram_cap_info *cap_info,
u32 dram_type);
int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
u32 sr_idle, u32 pd_idle);
#endif

62
arch/arm/include/asm/arch-rockchip/sdram_phy_px30.h Normal file
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@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd
*/
#ifndef _ASM_ARCH_SDRAM_PHY_PX30_H
#define _ASM_ARCH_SDRAM_PHY_PX30_H
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
struct ddr_phy_regs {
u32 phy[5][2];
};
#define PHY_REG(base, n) ((base) + 4 * (n))
/* PHY_REG0 */
#define DIGITAL_DERESET BIT(3)
#define ANALOG_DERESET BIT(2)
#define DIGITAL_RESET (0 << 3)
#define ANALOG_RESET (0 << 2)
/* PHY_REG1 */
#define PHY_DDR2 (0)
#define PHY_LPDDR2 (1)
#define PHY_DDR3 (2)
#define PHY_LPDDR3 (3)
#define PHY_DDR4 (4)
#define PHY_BL_4 (0 << 2)
#define PHY_BL_8 BIT(2)
/* PHY_REG2 */
#define PHY_DTT_EN BIT(0)
#define PHY_DTT_DISB (0 << 0)
#define PHY_WRITE_LEVELING_EN BIT(2)
#define PHY_WRITE_LEVELING_DISB (0 << 2)
#define PHY_SELECT_CS0 (2)
#define PHY_SELECT_CS1 (1)
#define PHY_SELECT_CS0_1 (0)
#define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6)
#define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4)
struct ddr_phy_skew {
u32 a0_a1_skew[15];
u32 cs0_dm0_skew[11];
u32 cs0_dm1_skew[11];
u32 cs0_dm2_skew[11];
u32 cs0_dm3_skew[11];
u32 cs1_dm0_skew[11];
u32 cs1_dm1_skew[11];
u32 cs1_dm2_skew[11];
u32 cs1_dm3_skew[11];
};
void phy_soft_reset(void __iomem *phy_base);
void phy_dram_set_bw(void __iomem *phy_base, u32 bw);
void phy_cfg(void __iomem *phy_base,
struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew,
struct sdram_base_params *base, u32 bw);
int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);
#endif

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arch/arm/include/asm/arch-rockchip/sdram_phy_ron_rtt_px30.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd
*/
#ifndef _ASM_ARCH_SDRAM_PHY_RON_RTT_PX30_H
#define _ASM_ARCH_SDRAM_PHY_RON_RTT_PX30_H
#define PHY_DDR3_RON_RTT_DISABLE (0)
#define PHY_DDR3_RON_RTT_451ohm (1)
#define PHY_DDR3_RON_RTT_225ohm (2)
#define PHY_DDR3_RON_RTT_150ohm (3)
#define PHY_DDR3_RON_RTT_112ohm (4)
#define PHY_DDR3_RON_RTT_90ohm (5)
#define PHY_DDR3_RON_RTT_75ohm (6)
#define PHY_DDR3_RON_RTT_64ohm (7)
#define PHY_DDR3_RON_RTT_56ohm (16)
#define PHY_DDR3_RON_RTT_50ohm (17)
#define PHY_DDR3_RON_RTT_45ohm (18)
#define PHY_DDR3_RON_RTT_41ohm (19)
#define PHY_DDR3_RON_RTT_37ohm (20)
#define PHY_DDR3_RON_RTT_34ohm (21)
#define PHY_DDR3_RON_RTT_33ohm (22)
#define PHY_DDR3_RON_RTT_30ohm (23)
#define PHY_DDR3_RON_RTT_28ohm (24)
#define PHY_DDR3_RON_RTT_26ohm (25)
#define PHY_DDR3_RON_RTT_25ohm (26)
#define PHY_DDR3_RON_RTT_23ohm (27)
#define PHY_DDR3_RON_RTT_22ohm (28)
#define PHY_DDR3_RON_RTT_21ohm (29)
#define PHY_DDR3_RON_RTT_20ohm (30)
#define PHY_DDR3_RON_RTT_19ohm (31)
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
#endif

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arch/arm/include/asm/arch-rockchip/sdram_px30.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd
*/
#ifndef _ASM_ARCH_SDRAM_PX30_H
#define _ASM_ARCH_SDRAM_PX30_H
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sdram_msch.h>
#include <asm/arch-rockchip/sdram_pctl_px30.h>
#include <asm/arch-rockchip/sdram_phy_px30.h>
#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
#define SR_IDLE 93
#define PD_IDLE 13
/* PMUGRF */
#define PMUGRF_OS_REG0 (0x200)
#define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4)
/* DDR GRF */
#define DDR_GRF_CON(n) (0 + (n) * 4)
#define DDR_GRF_STATUS_BASE (0X100)
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
#define DDR_GRF_LP_CON (0x20)
#define SPLIT_MODE_32_L16_VALID (0)
#define SPLIT_MODE_32_H16_VALID (1)
#define SPLIT_MODE_16_L8_VALID (2)
#define SPLIT_MODE_16_H8_VALID (3)
#define DDR_GRF_SPLIT_CON (0x8)
#define SPLIT_MODE_MASK (0x3)
#define SPLIT_MODE_OFFSET (9)
#define SPLIT_BYPASS_MASK (1)
#define SPLIT_BYPASS_OFFSET (8)
#define SPLIT_SIZE_MASK (0xff)
#define SPLIT_SIZE_OFFSET (0)
/* CRU define */
/* CRU_PLL_CON0 */
#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15))
#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12))
#define FBDIV(n) ((0xFFF << 16) | (n))
/* CRU_PLL_CON1 */
#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15))
#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14))
#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13))
#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12))
#define LOCK(n) (((n) >> 10) & 0x1)
#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
#define REFDIV(n) ((0x3F << 16) | (n))
/* CRU_MODE */
#define CLOCK_FROM_XIN_OSC (0)
#define CLOCK_FROM_PLL (1)
#define CLOCK_FROM_RTC_32K (2)
#define DPLL_MODE(n) ((0x3 << (4 + 16)) | ((n) << 4))
/* CRU_SOFTRESET_CON1 */
#define upctl2_psrstn_req(n) (((0x1 << 6) << 16) | ((n) << 6))
#define upctl2_asrstn_req(n) (((0x1 << 5) << 16) | ((n) << 5))
#define upctl2_srstn_req(n) (((0x1 << 4) << 16) | ((n) << 4))
/* CRU_SOFTRESET_CON2 */
#define ddrphy_psrstn_req(n) (((0x1 << 2) << 16) | ((n) << 2))
#define ddrphy_srstn_req(n) (((0x1 << 0) << 16) | ((n) << 0))
/* CRU register */
#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
#define CRU_MODE (0xa0)
#define CRU_GLB_CNT_TH (0xb0)
#define CRU_CLKSEL_CON_BASE 0x100
#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4))
#define CRU_CLKGATE_CON_BASE 0x200
#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4))
#define CRU_CLKSFTRST_CON_BASE 0x300
#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4))
struct px30_ddr_grf_regs {
u32 ddr_grf_con[4];
u32 reserved1[(0x20 - 0x10) / 4];
u32 ddr_grf_lp_con;
u32 reserved2[(0x100 - 0x24) / 4];
u32 ddr_grf_status[11];
};
struct msch_regs {
u32 coreid;
u32 revisionid;
u32 deviceconf;
u32 devicesize;
u32 ddrtiminga0;
u32 ddrtimingb0;
u32 ddrtimingc0;
u32 devtodev0;
u32 reserved1[(0x110 - 0x20) / 4];
u32 ddrmode;
u32 ddr4timing;
u32 reserved2[(0x1000 - 0x118) / 4];
u32 agingx0;
u32 reserved3[(0x1040 - 0x1004) / 4];
u32 aging0;
u32 aging1;
u32 aging2;
u32 aging3;
};
struct sdram_msch_timings {
union noc_ddrtiminga0 ddrtiminga0;
union noc_ddrtimingb0 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
union noc_devtodev0 devtodev0;
union noc_ddrmode ddrmode;
union noc_ddr4timing ddr4timing;
u32 agingx0;
};
struct px30_sdram_channel {
struct sdram_cap_info cap_info;
struct sdram_msch_timings noc_timings;
};
struct px30_sdram_params {
struct px30_sdram_channel ch;
struct sdram_base_params base;
struct ddr_pctl_regs pctl_regs;
struct ddr_phy_regs phy_regs;
struct ddr_phy_skew *skew;
};
int sdram_init(void);
#endif

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arch/arm/include/asm/arch-rockchip/sdram_rk3288.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 Google, Inc
*
* Copyright 2014 Rockchip Inc.
*/
#ifndef _ASM_ARCH_RK3288_SDRAM_H__
#define _ASM_ARCH_RK3288_SDRAM_H__
struct rk3288_sdram_channel {
/*
* bit width in address, eg:
* 8 banks using 3 bit to address,
* 2 cs using 1 bit to address.
*/
u8 rank;
u8 col;
u8 bk;
u8 bw;
u8 dbw;
u8 row_3_4;
u8 cs0_row;
u8 cs1_row;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/*
* For of-platdata, which would otherwise convert this into two
* byte-swapped integers. With a size of 9 bytes, this struct will
* appear in of-platdata as a byte array.
*
* If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
*/
u8 dummy;
#endif
};
struct rk3288_sdram_pctl_timing {
u32 togcnt1u;
u32 tinit;
u32 trsth;
u32 togcnt100n;
u32 trefi;
u32 tmrd;
u32 trfc;
u32 trp;
u32 trtw;
u32 tal;
u32 tcl;
u32 tcwl;
u32 tras;
u32 trc;
u32 trcd;
u32 trrd;
u32 trtp;
u32 twr;
u32 twtr;
u32 texsr;
u32 txp;
u32 txpdll;
u32 tzqcs;
u32 tzqcsi;
u32 tdqs;
u32 tcksre;
u32 tcksrx;
u32 tcke;
u32 tmod;
u32 trstl;
u32 tzqcl;
u32 tmrr;
u32 tckesr;
u32 tdpd;
};
check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
struct rk3288_sdram_phy_timing {
u32 dtpr0;
u32 dtpr1;
u32 dtpr2;
u32 mr[4];
};
struct rk3288_base_params {
u32 noc_timing;
u32 noc_activate;
u32 ddrconfig;
u32 ddr_freq;
u32 dramtype;
/*
* DDR Stride is address mapping for DRAM space
* Stride Ch 0 range Ch1 range Total
* 0x00 0-256MB 256MB-512MB 512MB
* 0x05 0-1GB 0-1GB 1GB
* 0x09 0-2GB 0-2GB 2GB
* 0x0d 0-4GB 0-4GB 4GB
* 0x17 N/A 0-4GB 4GB
* 0x1a 0-4GB 4GB-8GB 8GB
*/
u32 stride;
u32 odt;
};
#endif

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arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
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#ifndef _ASM_ARCH_SDRAM_RK3328_H
#define _ASM_ARCH_SDRAM_RK3328_H
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sdram_pctl_px30.h>
#include <asm/arch-rockchip/sdram_phy_px30.h>
#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
#define SR_IDLE 93
#define PD_IDLE 13
#define SDRAM_ADDR 0x00000000
#define PATTERN (0x5aa5f00f)
/* ddr pctl registers define */
#define DDR_PCTL2_MSTR 0x0
#define DDR_PCTL2_STAT 0x4
#define DDR_PCTL2_MSTR1 0x8
#define DDR_PCTL2_MRCTRL0 0x10
#define DDR_PCTL2_MRCTRL1 0x14
#define DDR_PCTL2_MRSTAT 0x18
#define DDR_PCTL2_MRCTRL2 0x1c
#define DDR_PCTL2_DERATEEN 0x20
#define DDR_PCTL2_DERATEINT 0x24
#define DDR_PCTL2_PWRCTL 0x30
#define DDR_PCTL2_PWRTMG 0x34
#define DDR_PCTL2_HWLPCTL 0x38
#define DDR_PCTL2_RFSHCTL0 0x50
#define DDR_PCTL2_RFSHCTL1 0x54
#define DDR_PCTL2_RFSHCTL2 0x58
#define DDR_PCTL2_RFSHCTL4 0x5c
#define DDR_PCTL2_RFSHCTL3 0x60
#define DDR_PCTL2_RFSHTMG 0x64
#define DDR_PCTL2_RFSHTMG1 0x68
#define DDR_PCTL2_RFSHCTL5 0x6c
#define DDR_PCTL2_INIT0 0xd0
#define DDR_PCTL2_INIT1 0xd4
#define DDR_PCTL2_INIT2 0xd8
#define DDR_PCTL2_INIT3 0xdc
#define DDR_PCTL2_INIT4 0xe0
#define DDR_PCTL2_INIT5 0xe4
#define DDR_PCTL2_INIT6 0xe8
#define DDR_PCTL2_INIT7 0xec
#define DDR_PCTL2_DIMMCTL 0xf0
#define DDR_PCTL2_RANKCTL 0xf4
#define DDR_PCTL2_CHCTL 0xfc
#define DDR_PCTL2_DRAMTMG0 0x100
#define DDR_PCTL2_DRAMTMG1 0x104
#define DDR_PCTL2_DRAMTMG2 0x108
#define DDR_PCTL2_DRAMTMG3 0x10c
#define DDR_PCTL2_DRAMTMG4 0x110
#define DDR_PCTL2_DRAMTMG5 0x114
#define DDR_PCTL2_DRAMTMG6 0x118
#define DDR_PCTL2_DRAMTMG7 0x11c
#define DDR_PCTL2_DRAMTMG8 0x120
#define DDR_PCTL2_DRAMTMG9 0x124
#define DDR_PCTL2_DRAMTMG10 0x128
#define DDR_PCTL2_DRAMTMG11 0x12c
#define DDR_PCTL2_DRAMTMG12 0x130
#define DDR_PCTL2_DRAMTMG13 0x134
#define DDR_PCTL2_DRAMTMG14 0x138
#define DDR_PCTL2_DRAMTMG15 0x13c
#define DDR_PCTL2_DRAMTMG16 0x140
#define DDR_PCTL2_ZQCTL0 0x180
#define DDR_PCTL2_ZQCTL1 0x184
#define DDR_PCTL2_ZQCTL2 0x188
#define DDR_PCTL2_ZQSTAT 0x18c
#define DDR_PCTL2_DFITMG0 0x190
#define DDR_PCTL2_DFITMG1 0x194
#define DDR_PCTL2_DFILPCFG0 0x198
#define DDR_PCTL2_DFILPCFG1 0x19c
#define DDR_PCTL2_DFIUPD0 0x1a0
#define DDR_PCTL2_DFIUPD1 0x1a4
#define DDR_PCTL2_DFIUPD2 0x1a8
#define DDR_PCTL2_DFIMISC 0x1b0
#define DDR_PCTL2_DFITMG2 0x1b4
#define DDR_PCTL2_DFITMG3 0x1b8
#define DDR_PCTL2_DFISTAT 0x1bc
#define DDR_PCTL2_DBICTL 0x1c0
#define DDR_PCTL2_ADDRMAP0 0x200
#define DDR_PCTL2_ADDRMAP1 0x204
#define DDR_PCTL2_ADDRMAP2 0x208
#define DDR_PCTL2_ADDRMAP3 0x20c
#define DDR_PCTL2_ADDRMAP4 0x210
#define DDR_PCTL2_ADDRMAP5 0x214
#define DDR_PCTL2_ADDRMAP6 0x218
#define DDR_PCTL2_ADDRMAP7 0x21c
#define DDR_PCTL2_ADDRMAP8 0x220
#define DDR_PCTL2_ADDRMAP9 0x224
#define DDR_PCTL2_ADDRMAP10 0x228
#define DDR_PCTL2_ADDRMAP11 0x22c
#define DDR_PCTL2_ODTCFG 0x240
#define DDR_PCTL2_ODTMAP 0x244
#define DDR_PCTL2_SCHED 0x250
#define DDR_PCTL2_SCHED1 0x254
#define DDR_PCTL2_PERFHPR1 0x25c
#define DDR_PCTL2_PERFLPR1 0x264
#define DDR_PCTL2_PERFWR1 0x26c
#define DDR_PCTL2_DQMAP0 0x280
#define DDR_PCTL2_DQMAP1 0x284
#define DDR_PCTL2_DQMAP2 0x288
#define DDR_PCTL2_DQMAP3 0x28c
#define DDR_PCTL2_DQMAP4 0x290
#define DDR_PCTL2_DQMAP5 0x294
#define DDR_PCTL2_DBG0 0x300
#define DDR_PCTL2_DBG1 0x304
#define DDR_PCTL2_DBGCAM 0x308
#define DDR_PCTL2_DBGCMD 0x30c
#define DDR_PCTL2_DBGSTAT 0x310
#define DDR_PCTL2_SWCTL 0x320
#define DDR_PCTL2_SWSTAT 0x324
#define DDR_PCTL2_POISONCFG 0x36c
#define DDR_PCTL2_POISONSTAT 0x370
#define DDR_PCTL2_ADVECCINDEX 0x374
#define DDR_PCTL2_ADVECCSTAT 0x378
#define DDR_PCTL2_PSTAT 0x3fc
#define DDR_PCTL2_PCCFG 0x400
#define DDR_PCTL2_PCFGR_n 0x404
#define DDR_PCTL2_PCFGW_n 0x408
#define DDR_PCTL2_PCTRL_n 0x490
/* PCTL2_MRSTAT */
#define MR_WR_BUSY BIT(0)
/* PHY_REG0 */
#define DIGITAL_DERESET BIT(3)
#define ANALOG_DERESET BIT(2)
#define DIGITAL_RESET (0 << 3)
#define ANALOG_RESET (0 << 2)
/* PHY_REG1 */
#define PHY_DDR2 (0)
#define PHY_LPDDR2 (1)
#define PHY_DDR3 (2)
#define PHY_LPDDR3 (3)
#define PHY_DDR4 (4)
#define PHY_BL_4 (0 << 2)
#define PHY_BL_8 BIT(2)
/* PHY_REG2 */
#define PHY_DTT_EN BIT(0)
#define PHY_DTT_DISB (0 << 0)
#define PHY_WRITE_LEVELING_EN BIT(2)
#define PHY_WRITE_LEVELING_DISB (0 << 2)
#define PHY_SELECT_CS0 (2)
#define PHY_SELECT_CS1 (1)
#define PHY_SELECT_CS0_1 (0)
#define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6)
#define PHY_DATA_TRAINING_SELECTCS(n) (n << 4)
#define PHY_DDR3_RON_RTT_DISABLE (0)
#define PHY_DDR3_RON_RTT_451ohm (1)
#define PHY_DDR3_RON_RTT_225ohm (2)
#define PHY_DDR3_RON_RTT_150ohm (3)
#define PHY_DDR3_RON_RTT_112ohm (4)
#define PHY_DDR3_RON_RTT_90ohm (5)
#define PHY_DDR3_RON_RTT_75ohm (6)
#define PHY_DDR3_RON_RTT_64ohm (7)
#define PHY_DDR3_RON_RTT_56ohm (16)
#define PHY_DDR3_RON_RTT_50ohm (17)
#define PHY_DDR3_RON_RTT_45ohm (18)
#define PHY_DDR3_RON_RTT_41ohm (19)
#define PHY_DDR3_RON_RTT_37ohm (20)
#define PHY_DDR3_RON_RTT_34ohm (21)
#define PHY_DDR3_RON_RTT_33ohm (22)
#define PHY_DDR3_RON_RTT_30ohm (23)
#define PHY_DDR3_RON_RTT_28ohm (24)
#define PHY_DDR3_RON_RTT_26ohm (25)
#define PHY_DDR3_RON_RTT_25ohm (26)
#define PHY_DDR3_RON_RTT_23ohm (27)
#define PHY_DDR3_RON_RTT_22ohm (28)
#define PHY_DDR3_RON_RTT_21ohm (29)
#define PHY_DDR3_RON_RTT_20ohm (30)
#define PHY_DDR3_RON_RTT_19ohm (31)
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
/* noc registers define */
#define DDRCONF 0x8
@ -219,16 +36,16 @@
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
/* CRU_SOFTRESET_CON5 */
#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15))
#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14))
#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13))
#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12))
#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11))
#define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9))
#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8))
#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7))
#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | ((n) << 15))
#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | ((n) << 14))
#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | ((n) << 13))
#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | ((n) << 12))
#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | ((n) << 11))
#define msch_srstn_req(n) (((0x1 << 9) << 16) | ((n) << 9))
#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | ((n) << 8))
#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | ((n) << 7))
/* CRU_SOFTRESET_CON9 */
#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9))
#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | ((n) << 9))
/* CRU register */
#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
@ -255,56 +72,46 @@
#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
#define REFDIV(n) ((0x3F << 16) | (n))
union noc_ddrtiming {
u32 d32;
struct {
unsigned acttoact:6;
unsigned rdtomiss:6;
unsigned wrtomiss:6;
unsigned burstlen:3;
unsigned rdtowr:5;
unsigned wrtord:5;
unsigned bwratio:1;
} b;
} NOC_TIMING_T;
union noc_activate {
u32 d32;
struct {
unsigned rrd:4;
unsigned faw:6;
unsigned fawbank:1;
unsigned reserved1:21;
} b;
u16 ddr_cfg_2_rbc[] = {
/*
* [5:4] row(13+n)
* [3] cs(0:0 cs, 1:2 cs)
* [2] bank(0:0bank,1:8bank)
* [1:0] col(11+n)
*/
/* row, cs, bank, col */
((3 << 4) | (0 << 3) | (1 << 2) | 0),
((3 << 4) | (0 << 3) | (1 << 2) | 1),
((2 << 4) | (0 << 3) | (1 << 2) | 2),
((3 << 4) | (0 << 3) | (1 << 2) | 2),
((2 << 4) | (0 << 3) | (1 << 2) | 3),
((3 << 4) | (1 << 3) | (1 << 2) | 0),
((3 << 4) | (1 << 3) | (1 << 2) | 1),
((2 << 4) | (1 << 3) | (1 << 2) | 2),
((3 << 4) | (0 << 3) | (0 << 2) | 1),
((2 << 4) | (0 << 3) | (1 << 2) | 1),
};
union noc_devtodev {
u32 d32;
struct {
unsigned busrdtord:2;
unsigned busrdtowr:2;
unsigned buswrtord:2;
unsigned reserved2:26;
} b;
};
union noc_ddr4timing {
u32 d32;
struct {
unsigned ccdl:3;
unsigned wrtordl:5;
unsigned rrdl:4;
unsigned reserved2:20;
} b;
};
union noc_ddrmode {
u32 d32;
struct {
unsigned autoprecharge:1;
unsigned bwratioextended:1;
unsigned reserved3:30;
} b;
u16 ddr4_cfg_2_rbc[] = {
/***************************
* [6] cs 0:0cs 1:2 cs
* [5:3] row(13+n)
* [2] cs(0:0 cs, 1:2 cs)
* [1] bw 0: 16bit 1:32bit
* [0] diebw 0:8bit 1:16bit
***************************/
/* cs, row, cs, bw, diebw */
((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
};
u32 addrmap[21][9] = {
@ -355,17 +162,65 @@ u32 addrmap[21][9] = {
0x07070707, 0x00000f07, 0x3f00}
};
struct rk3328_msch_timings {
union noc_ddrtiming ddrtiming;
union noc_ddrmode ddrmode;
u32 readlatency;
union noc_activate activate;
union noc_devtodev devtodev;
union noc_ddr4timing ddr4timing;
u32 agingx0;
struct rk3328_ddr_grf_regs {
u32 ddr_grf_con[4];
u32 reserved[(0x100 - 0x10) / 4];
u32 ddr_grf_status[11];
};
struct rk3328_msch_regs {
union noc_ddrtiming {
u32 d32;
struct {
unsigned acttoact:6;
unsigned rdtomiss:6;
unsigned wrtomiss:6;
unsigned burstlen:3;
unsigned rdtowr:5;
unsigned wrtord:5;
unsigned bwratio:1;
} b;
};
union noc_activate {
u32 d32;
struct {
unsigned rrd:4;
unsigned faw:6;
unsigned fawbank:1;
unsigned reserved1:21;
} b;
};
union noc_devtodev {
u32 d32;
struct {
unsigned busrdtord:2;
unsigned busrdtowr:2;
unsigned buswrtord:2;
unsigned reserved2:26;
} b;
};
union noc_ddr4timing {
u32 d32;
struct {
unsigned ccdl:3;
unsigned wrtordl:5;
unsigned rrdl:4;
unsigned reserved2:20;
} b;
};
union noc_ddrmode {
u32 d32;
struct {
unsigned autoprecharge:1;
unsigned bwratioextended:1;
unsigned reserved3:30;
} b;
};
struct msch_regs {
u32 coreid;
u32 revisionid;
u32 ddrconf;
@ -384,58 +239,27 @@ struct rk3328_msch_regs {
u32 ddr4_timing;
};
struct rk3328_ddr_grf_regs {
u32 ddr_grf_con[4];
u32 reserved[(0x100 - 0x10) / 4];
u32 ddr_grf_status[11];
};
struct rk3328_ddr_pctl_regs {
u32 pctl[30][2];
};
struct rk3328_ddr_phy_regs {
u32 phy[5][2];
};
struct rk3328_ddr_skew {
u32 a0_a1_skew[15];
u32 cs0_dm0_skew[11];
u32 cs0_dm1_skew[11];
u32 cs0_dm2_skew[11];
u32 cs0_dm3_skew[11];
u32 cs1_dm0_skew[11];
u32 cs1_dm1_skew[11];
u32 cs1_dm2_skew[11];
u32 cs1_dm3_skew[11];
struct sdram_msch_timings {
union noc_ddrtiming ddrtiming;
union noc_ddrmode ddrmode;
u32 readlatency;
union noc_activate activate;
union noc_devtodev devtodev;
union noc_ddr4timing ddr4timing;
u32 agingx0;
};
struct rk3328_sdram_channel {
unsigned int rank;
unsigned int col;
/* 3:8bank, 2:4bank */
unsigned int bk;
/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned int bw;
/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned int dbw;
unsigned int row_3_4;
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int ddrconfig;
struct rk3328_msch_timings noc_timings;
struct sdram_cap_info cap_info;
struct sdram_msch_timings noc_timings;
};
struct rk3328_sdram_params {
struct rk3328_sdram_channel ch;
unsigned int ddr_freq;
unsigned int dramtype;
unsigned int odt;
struct rk3328_ddr_pctl_regs pctl_regs;
struct rk3328_ddr_phy_regs phy_regs;
struct rk3328_ddr_skew skew;
struct sdram_base_params base;
struct ddr_pctl_regs pctl_regs;
struct ddr_phy_regs phy_regs;
struct ddr_phy_skew skew;
};
#define PHY_REG(base, n) (base + 4 * (n))
#endif

98
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
View File

@ -5,6 +5,8 @@
#ifndef _ASM_ARCH_SDRAM_RK3399_H
#define _ASM_ARCH_SDRAM_RK3399_H
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sdram_msch.h>
struct rk3399_ddr_pctl_regs {
u32 denali_ctl[332];
@ -18,55 +20,6 @@ struct rk3399_ddr_pi_regs {
u32 denali_pi[200];
};
union noc_ddrtimingc0 {
u32 d32;
struct {
unsigned burstpenalty : 4;
unsigned reserved0 : 4;
unsigned wrtomwr : 6;
unsigned reserved1 : 18;
} b;
};
union noc_ddrmode {
u32 d32;
struct {
unsigned autoprecharge : 1;
unsigned bypassfiltering : 1;
unsigned fawbank : 1;
unsigned burstsize : 2;
unsigned mwrsize : 2;
unsigned reserved2 : 1;
unsigned forceorder : 8;
unsigned forceorderstate : 8;
unsigned reserved3 : 8;
} b;
};
struct rk3399_msch_regs {
u32 coreid;
u32 revisionid;
u32 ddrconf;
u32 ddrsize;
u32 ddrtiminga0;
u32 ddrtimingb0;
u32 ddrtimingc0;
u32 devtodev0;
u32 reserved0[(0x110 - 0x20) / 4];
u32 ddrmode;
u32 reserved1[(0x1000 - 0x114) / 4];
u32 agingx0;
};
struct rk3399_msch_timings {
u32 ddrtiminga0;
u32 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
u32 devtodev0;
union noc_ddrmode ddrmode;
u32 agingx0;
};
struct rk3399_ddr_cic_regs {
u32 cic_ctrl0;
u32 cic_ctrl1;
@ -83,14 +36,38 @@ struct rk3399_ddr_cic_regs {
#define START 1
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
#define PWRUP_SREFRESH_EXIT BIT(16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
struct msch_regs {
u32 coreid;
u32 revisionid;
u32 ddrconf;
u32 ddrsize;
union noc_ddrtiminga0 ddrtiminga0;
union noc_ddrtimingb0 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
union noc_devtodev0 devtodev0;
u32 reserved0[(0x110 - 0x20) / 4];
union noc_ddrmode ddrmode;
u32 reserved1[(0x1000 - 0x114) / 4];
u32 agingx0;
};
struct sdram_msch_timings {
union noc_ddrtiminga0 ddrtiminga0;
union noc_ddrtimingb0 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
union noc_devtodev0 devtodev0;
union noc_ddrmode ddrmode;
u32 agingx0;
};
struct rk3399_sdram_channel {
struct sdram_cap_info cap_info;
struct rk3399_msch_timings noc_timings;
struct sdram_msch_timings noc_timings;
};
struct rk3399_sdram_params {
@ -101,11 +78,20 @@ struct rk3399_sdram_params {
struct rk3399_ddr_publ_regs phy_regs;
};
#define PI_CA_TRAINING (1 << 0)
#define PI_WRITE_LEVELING (1 << 1)
#define PI_READ_GATE_TRAINING (1 << 2)
#define PI_READ_LEVELING (1 << 3)
#define PI_WDQ_LEVELING (1 << 4)
#define PI_CA_TRAINING BIT(0)
#define PI_WRITE_LEVELING BIT(1)
#define PI_READ_GATE_TRAINING BIT(2)
#define PI_READ_LEVELING BIT(3)
#define PI_WDQ_LEVELING BIT(4)
#define PI_FULL_TRAINING 0xff
enum {
STRIDE_128B = 0,
STRIDE_256B = 1,
STRIDE_512B = 2,
STRIDE_4KB = 3,
UN_STRIDE = 4,
PART_STRIDE = 5,
};
#endif

2
arch/arm/lib/Makefile
View File

@ -35,7 +35,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o
obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
else
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
endif

2
arch/arm/lib/crt0.S
View File

@ -149,7 +149,7 @@ here:
bl c_runtime_cpu_setup /* we still call old routine here */
#endif
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK)
#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
#if !defined(CONFIG_SPL_EARLY_BSS)
SPL_CLEAR_BSS

2
arch/arm/lib/crt0_64.S
View File

@ -120,6 +120,7 @@ relocation_return:
*/
bl c_runtime_cpu_setup /* still call old routine */
#endif /* !CONFIG_SPL_BUILD */
#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
#if defined(CONFIG_SPL_BUILD)
bl spl_relocate_stack_gd /* may return NULL */
/* set up gd here, outside any C code, if new stack is returned */
@ -152,5 +153,6 @@ clear_loop:
b board_init_r /* PC relative jump */
/* NOTREACHED - board_init_r() does not return */
#endif
ENDPROC(_main)

49
arch/arm/mach-rockchip/Kconfig
View File

@ -1,5 +1,27 @@
if ARCH_ROCKCHIP
config ROCKCHIP_PX30
bool "Support Rockchip PX30"
select ARM64
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
select TPL
select TPL_TINY_FRAMEWORK if TPL
select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply SPL_SEPARATE_BSS
select SPL_SERIAL_SUPPORT
select TPL_SERIAL_SUPPORT
select DEBUG_UART_BOARD_INIT
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
help
The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
including NEON and GPU, Mali-400 graphics, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
config ROCKCHIP_RK3036
bool "Support Rockchip RK3036"
select CPU_V7A
@ -105,6 +127,29 @@ config ROCKCHIP_RK3288
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
config ROCKCHIP_RK3308
bool "Support Rockchip RK3308"
select ARM64
select DEBUG_UART_BOARD_INIT
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
select SPL_ATF
select SPL_ATF_NO_PLATFORM_PARAM
select SPL_LOAD_FIT
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_CLK
imply SPL_REGMAP
imply SPL_SYSCON
imply SPL_RAM
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
imply SPL_SEPARATE_BSS
help
The Rockchip RK3308 is a ARM-based Soc which embedded with quad
Cortex-A35 and highly integrated audio interfaces.
config ROCKCHIP_RK3328
bool "Support Rockchip RK3328"
select ARM64
@ -115,6 +160,7 @@ config ROCKCHIP_RK3328
select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
@ -183,6 +229,7 @@ config ROCKCHIP_RK3399
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL_SUPPORT
imply TPL_LIBCOMMON_SUPPORT
@ -315,11 +362,13 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
config SPL_MMC_SUPPORT
default y if !SPL_ROCKCHIP_BACK_TO_BROM
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3128/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk322x/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3308/Kconfig"
source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"

5
arch/arm/mach-rockchip/Makefile
View File

@ -11,6 +11,7 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
@ -25,13 +26,15 @@ obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
obj-$(CONFIG_ROCKCHIP_PX30) += px30/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/

42
arch/arm/mach-rockchip/board.c
View File

@ -61,29 +61,55 @@ static struct dwc2_plat_otg_data otg_data = {
int board_usb_init(int index, enum usb_init_type init)
{
int node;
ofnode node;
const char *mode;
bool matched = false;
const void *blob = gd->fdt_blob;
/* find the usb_otg node */
node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
while (node > 0) {
mode = fdt_getprop(blob, node, "dr_mode", NULL);
node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
while (ofnode_valid(node)) {
mode = ofnode_read_string(node, "dr_mode");
if (mode && strcmp(mode, "otg") == 0) {
matched = true;
break;
}
node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2");
node = ofnode_by_compatible(node, "snps,dwc2");
}
if (!matched) {
debug("Not found usb_otg device\n");
return -ENODEV;
}
otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
otg_data.regs_otg = ofnode_get_addr(node);
#ifdef CONFIG_ROCKCHIP_RK3288
int ret;
u32 phandle, offset;
ofnode phy_node;
ret = ofnode_read_u32(node, "phys", &phandle);
if (ret)
return ret;
node = ofnode_get_by_phandle(phandle);
if (!ofnode_valid(node)) {
debug("Not found usb phy device\n");
return -ENODEV;
}
phy_node = ofnode_get_parent(node);
if (!ofnode_valid(node)) {
debug("Not found usb phy device\n");
return -ENODEV;
}
otg_data.phy_of_node = phy_node;
ret = ofnode_read_u32(node, "reg", &offset);
if (ret)
return ret;
otg_data.regs_phy = offset +
(u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
#endif
return dwc2_udc_probe(&otg_data);
}

7
arch/arm/mach-rockchip/misc.c
View File

@ -57,13 +57,18 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
const u32 cpuid_length,
u8 *cpuid)
{
#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) || CONFIG_IS_ENABLED(ROCKCHIP_OTP)
struct udevice *dev;
int ret;
/* retrieve the device */
#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(rockchip_efuse), &dev);
#elif CONFIG_IS_ENABLED(ROCKCHIP_OTP)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(rockchip_otp), &dev);
#endif
if (ret) {
debug("%s: could not find efuse device\n", __func__);
return -1;

59
arch/arm/mach-rockchip/px30-board-tpl.c Normal file
View File

@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/sdram_px30.h>
#define TIMER_LOAD_COUNT0 0x00
#define TIMER_LOAD_COUNT1 0x04
#define TIMER_CUR_VALUE0 0x08
#define TIMER_CUR_VALUE1 0x0c
#define TIMER_CONTROL_REG 0x10
#define TIMER_EN 0x1
#define TIMER_FMODE (0 << 1)
#define TIMER_RMODE (1 << 1)
void secure_timer_init(void)
{
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT0);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT1);
writel(TIMER_EN | TIMER_FMODE,
CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
}
void board_init_f(ulong dummy)
{
int ret;
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
printascii("U-Boot TPL board init\n");
#endif
secure_timer_init();
ret = sdram_init();
if (ret)
printascii("sdram_init failed\n");
/* return to maskrom */
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}

41
arch/arm/mach-rockchip/px30/Kconfig Normal file
View File

@ -0,0 +1,41 @@
if ROCKCHIP_PX30
config TARGET_EVB_PX30
bool "EVB_PX30"
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
config SYS_SOC
default "px30"
config SYS_MALLOC_F_LEN
default 0x400
config SPL_SERIAL_SUPPORT
default y
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_TEXT_BASE
default 0xff0e1000
config TPL_MAX_SIZE
default 10240
config TPL_STACK
default 0xff0e4fff
config DEBUG_UART2_CHANNEL
int "Mux channel to use for debug UART2"
depends on DEBUG_UART_BOARD_INIT
default 0
help
UART2 can use two different set of pins to route the output.
For using the UART for early debugging the route to use needs
to be declared (0 or 1).
source "board/rockchip/evb_px30/Kconfig"
endif

13
arch/arm/mach-rockchip/px30/Makefile Normal file
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@ -0,0 +1,13 @@
#
# (C) Copyright 2017 Rockchip Electronics Co., Ltd.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clk_px30.o
ifndef CONFIG_TPL_BUILD
obj-y += syscon_px30.o
endif
obj-y += px30.o

31
arch/arm/mach-rockchip/px30/clk_px30.c Normal file
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@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_px30.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_px30_cru), devp);
}
void *rockchip_get_cru(void)
{
struct px30_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}

248
arch/arm/mach-rockchip/px30/px30.c Normal file
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@ -0,0 +1,248 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-rockchip/grf_px30.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/uart.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_px30.h>
#include <dt-bindings/clock/px30-cru.h>
static struct mm_region px30_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xff000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xff000000UL,
.phys = 0xff000000UL,
.size = 0x01000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = px30_mem_map;
#define PMU_PWRDN_CON 0xff000018
#define GRF_BASE 0xff140000
#define CRU_BASE 0xff2b0000
#define VIDEO_PHY_BASE 0xff2e0000
#define SERVICE_CORE_ADDR 0xff508000
#define DDR_FW_BASE 0xff534000
#define FW_DDR_CON 0x40
#define QOS_PRIORITY 0x08
#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
/* GRF_GPIO1CL_IOMUX */
enum {
GPIO1C1_SHIFT = 4,
GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT,
GPIO1C1_GPIO = 0,
GPIO1C1_UART1_TX,
GPIO1C0_SHIFT = 0,
GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT,
GPIO1C0_GPIO = 0,
GPIO1C0_UART1_RX,
};
/* GRF_GPIO1DL_IOMUX */
enum {
GPIO1D3_SHIFT = 12,
GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT,
GPIO1D3_GPIO = 0,
GPIO1D3_SDMMC_D1,
GPIO1D3_UART2_RXM0,
GPIO1D2_SHIFT = 8,
GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT,
GPIO1D2_GPIO = 0,
GPIO1D2_SDMMC_D0,
GPIO1D2_UART2_TXM0,
};
/* GRF_GPIO1DH_IOMUX */
enum {
GPIO1D7_SHIFT = 12,
GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT,
GPIO1D7_GPIO = 0,
GPIO1D7_SDMMC_CMD,
GPIO1D6_SHIFT = 8,
GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT,
GPIO1D6_GPIO = 0,
GPIO1D6_SDMMC_CLK,
GPIO1D5_SHIFT = 4,
GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT,
GPIO1D5_GPIO = 0,
GPIO1D5_SDMMC_D3,
GPIO1D4_SHIFT = 0,
GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT,
GPIO1D4_GPIO = 0,
GPIO1D4_SDMMC_D2,
};
/* GRF_GPIO2BH_IOMUX */
enum {
GPIO2B6_SHIFT = 8,
GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT,
GPIO2B6_GPIO = 0,
GPIO2B6_CIF_D1M0,
GPIO2B6_UART2_RXM1,
GPIO2B4_SHIFT = 0,
GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT,
GPIO2B4_GPIO = 0,
GPIO2B4_CIF_D0M0,
GPIO2B4_UART2_TXM1,
};
/* GRF_GPIO3AL_IOMUX */
enum {
GPIO3A2_SHIFT = 8,
GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT,
GPIO3A2_GPIO = 0,
GPIO3A2_UART5_TX = 4,
GPIO3A1_SHIFT = 4,
GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT,
GPIO3A1_GPIO = 0,
GPIO3A1_UART5_RX = 4,
};
int arch_cpu_init(void)
{
static struct px30_grf * const grf = (void *)GRF_BASE;
u32 __maybe_unused val;
#ifdef CONFIG_SPL_BUILD
/* We do some SoC one time setting here. */
/* Disable the ddr secure region setting to make it non-secure */
writel(0x0, DDR_FW_BASE + FW_DDR_CON);
/* Set cpu qos priority */
writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY);
#if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \
(CONFIG_DEBUG_UART_BASE != 0xff160000) || \
(CONFIG_DEBUG_UART_CHANNEL != 0)
/* fix sdmmc pinmux if not using uart2-channel0 as debug uart */
rk_clrsetreg(&grf->gpio1dl_iomux,
GPIO1D3_MASK | GPIO1D2_MASK,
GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT |
GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT);
rk_clrsetreg(&grf->gpio1dh_iomux,
GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK,
GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT |
GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT |
GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT |
GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
#endif
#endif
/* Enable PD_VO (default disable at reset) */
rk_clrreg(PMU_PWRDN_CON, 1 << 13);
/* Disable video phy bandgap by default */
writel(0x82, VIDEO_PHY_BASE + 0x0000);
writel(0x05, VIDEO_PHY_BASE + 0x03ac);
/* Clear the force_jtag */
rk_clrreg(&grf->cpu_con[1], 1 << 7);
return 0;
}
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
static struct px30_grf * const grf = (void *)GRF_BASE;
static struct px30_cru * const cru = (void *)CRU_BASE;
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
/* uart_sel_clk default select 24MHz */
rk_clrsetreg(&cru->clksel_con[34],
UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK,
UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);
rk_clrsetreg(&cru->clksel_con[35],
UART1_CLK_SEL_MASK,
UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT);
rk_clrsetreg(&grf->gpio1cl_iomux,
GPIO1C1_MASK | GPIO1C0_MASK,
GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
/* uart_sel_clk default select 24MHz */
rk_clrsetreg(&cru->clksel_con[46],
UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK,
UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);
rk_clrsetreg(&cru->clksel_con[47],
UART5_CLK_SEL_MASK,
UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT);
rk_clrsetreg(&grf->gpio3al_iomux,
GPIO3A2_MASK | GPIO3A1_MASK,
GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
#else
/* GRF_IOFUNC_CON0 */
enum {
CON_IOMUX_UART2SEL_SHIFT = 10,
CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
CON_IOMUX_UART2SEL_M0 = 0,
CON_IOMUX_UART2SEL_M1,
CON_IOMUX_UART2SEL_USBPHY,
};
/* uart_sel_clk default select 24MHz */
rk_clrsetreg(&cru->clksel_con[37],
UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
rk_clrsetreg(&cru->clksel_con[38],
UART2_CLK_SEL_MASK,
UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
#if (CONFIG_DEBUG_UART2_CHANNEL == 1)
/* Enable early UART2 */
rk_clrsetreg(&grf->iofunc_con0,
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);
rk_clrsetreg(&grf->gpio2bh_iomux,
GPIO2B6_MASK | GPIO2B4_MASK,
GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT |
GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
#else
rk_clrsetreg(&grf->iofunc_con0,
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
rk_clrsetreg(&grf->gpio1dl_iomux,
GPIO1D3_MASK | GPIO1D2_MASK,
GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
#endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */
#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
}
#endif /* CONFIG_DEBUG_UART_BOARD_INIT */

53
arch/arm/mach-rockchip/px30/syscon_px30.c Normal file
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@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
static const struct udevice_id px30_syscon_ids[] = {
{ .compatible = "rockchip,px30-pmu", .data = ROCKCHIP_SYSCON_PMU },
{ .compatible = "rockchip,px30-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,px30-grf", .data = ROCKCHIP_SYSCON_GRF },
{ }
};
U_BOOT_DRIVER(syscon_px30) = {
.id = UCLASS_SYSCON,
.name = "px30_syscon",
.of_match = px30_syscon_ids,
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int px30_syscon_bind_of_platdata(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
return 0;
}
U_BOOT_DRIVER(rockchip_px30_pmu) = {
.name = "rockchip_px30_pmu",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids,
.bind = px30_syscon_bind_of_platdata,
};
U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
.name = "rockchip_px30_pmugrf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 1,
.bind = px30_syscon_bind_of_platdata,
};
U_BOOT_DRIVER(rockchip_px30_grf) = {
.name = "rockchip_px30_grf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 2,
.bind = px30_syscon_bind_of_platdata,
};
#endif

2
arch/arm/mach-rockchip/rk3036/rk3036.c
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@ -43,7 +43,7 @@ void board_debug_uart_init(void)
#if !CONFIG_IS_ENABLED(RAM)
/*
* When CONFIG_RAM is enabled, the dram_init() function is implemented
* in sdram_common.c.
* in sdram.c.
*/
int dram_init(void)
{

2
arch/arm/mach-rockchip/rk3288/rk3288.c
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@ -15,7 +15,7 @@
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
#include <asm/arch-rockchip/qos_rk3288.h>
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sdram.h>
DECLARE_GLOBAL_DATA_PTR;

27
arch/arm/mach-rockchip/rk3308/Kconfig Normal file
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@ -0,0 +1,27 @@
if ROCKCHIP_RK3308
config TARGET_EVB_RK3308
bool "EVB_RK3308"
select BOARD_LATE_INIT
config TARGET_ROC_RK3308_CC
bool "Firefly roc-rk3308-cc"
select BOARD_LATE_INIT
config SYS_SOC
default "rk3308"
config SYS_MALLOC_F_LEN
default 0x400
config SPL_SERIAL_SUPPORT
default y
config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
source "board/rockchip/evb_rk3308/Kconfig"
source "board/firefly/firefly-rk3308/Kconfig"
endif

9
arch/arm/mach-rockchip/rk3308/Makefile Normal file
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@ -0,0 +1,9 @@
#
# (C) Copyright 2018 Rockchip Electronics Co., Ltd.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += syscon_rk3308.o
obj-y += rk3308.o
obj-y += clk_rk3308.o

31
arch/arm/mach-rockchip/rk3308/clk_rk3308.c Normal file
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@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch/cru_rk3308.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3308_cru), devp);
}
void *rockchip_get_cru(void)
{
struct rk3308_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}

175
arch/arm/mach-rockchip/rk3308/rk3308.c Normal file
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@ -0,0 +1,175 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*Copyright (c) 2018 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3308.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/gpio.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/armv8/mmu.h>
static struct mm_region rk3308_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xff000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xff000000UL,
.phys = 0xff000000UL,
.size = 0x01000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = rk3308_mem_map;
#define GRF_BASE 0xff000000
#define SGRF_BASE 0xff2b0000
enum {
GPIO1C7_SHIFT = 8,
GPIO1C7_MASK = GENMASK(11, 8),
GPIO1C7_GPIO = 0,
GPIO1C7_UART1_RTSN,
GPIO1C7_UART2_TX_M0,
GPIO1C7_SPI2_MOSI,
GPIO1C7_JTAG_TMS,
GPIO1C6_SHIFT = 4,
GPIO1C6_MASK = GENMASK(7, 4),
GPIO1C6_GPIO = 0,
GPIO1C6_UART1_CTSN,
GPIO1C6_UART2_RX_M0,
GPIO1C6_SPI2_MISO,
GPIO1C6_JTAG_TCLK,
GPIO4D3_SHIFT = 6,
GPIO4D3_MASK = GENMASK(7, 6),
GPIO4D3_GPIO = 0,
GPIO4D3_SDMMC_D3,
GPIO4D3_UART2_TX_M1,
GPIO4D2_SHIFT = 4,
GPIO4D2_MASK = GENMASK(5, 4),
GPIO4D2_GPIO = 0,
GPIO4D2_SDMMC_D2,
GPIO4D2_UART2_RX_M1,
UART2_IO_SEL_SHIFT = 2,
UART2_IO_SEL_MASK = GENMASK(3, 2),
UART2_IO_SEL_M0 = 0,
UART2_IO_SEL_M1,
UART2_IO_SEL_USB,
GPIO3B3_SEL_SRC_CTRL_SHIFT = 7,
GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7),
GPIO3B3_SEL_SRC_CTRL_IOMUX = 0,
GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
GPIO3B3_SEL_PLUS_SHIFT = 4,
GPIO3B3_SEL_PLUS_MASK = GENMASK(6, 4),
GPIO3B3_SEL_PLUS_GPIO3_B3 = 0,
GPIO3B3_SEL_PLUS_FLASH_ALE,
GPIO3B3_SEL_PLUS_EMMC_PWREN,
GPIO3B3_SEL_PLUS_SPI1_CLK,
GPIO3B3_SEL_PLUS_LCDC_D23_M1,
GPIO3B2_SEL_SRC_CTRL_SHIFT = 3,
GPIO3B2_SEL_SRC_CTRL_MASK = BIT(3),
GPIO3B2_SEL_SRC_CTRL_IOMUX = 0,
GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
GPIO3B2_SEL_PLUS_SHIFT = 0,
GPIO3B2_SEL_PLUS_MASK = GENMASK(2, 0),
GPIO3B2_SEL_PLUS_GPIO3_B2 = 0,
GPIO3B2_SEL_PLUS_FLASH_RDN,
GPIO3B2_SEL_PLUS_EMMC_RSTN,
GPIO3B2_SEL_PLUS_SPI1_MISO,
GPIO3B2_SEL_PLUS_LCDC_D22_M1,
};
enum {
IOVSEL3_CTRL_SHIFT = 8,
IOVSEL3_CTRL_MASK = BIT(8),
VCCIO3_SEL_BY_GPIO = 0,
VCCIO3_SEL_BY_IOVSEL3,
IOVSEL3_SHIFT = 3,
IOVSEL3_MASK = BIT(3),
VCCIO3_3V3 = 0,
VCCIO3_1V8,
};
/*
* The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
* interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
* use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
* then we can switch to io_vsel3 after system power on, and release GPIO0_A4
* for other usage.
*/
#define GPIO0_A4 4
int rk_board_init(void)
{
static struct rk3308_grf * const grf = (void *)GRF_BASE;
u32 val;
int ret;
ret = gpio_request(GPIO0_A4, "gpio0_a4");
if (ret < 0) {
printf("request for gpio0_a4 failed:%d\n", ret);
return 0;
}
gpio_direction_input(GPIO0_A4);
if (gpio_get_value(GPIO0_A4))
val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
VCCIO3_1V8 << IOVSEL3_SHIFT;
else
val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
VCCIO3_3V3 << IOVSEL3_SHIFT;
rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
gpio_free(GPIO0_A4);
return 0;
}
#if defined(CONFIG_DEBUG_UART)
__weak void board_debug_uart_init(void)
{
static struct rk3308_grf * const grf = (void *)GRF_BASE;
/* Enable early UART2 channel m1 on the rk3308 */
rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
rk_clrsetreg(&grf->gpio4d_iomux,
GPIO4D3_MASK | GPIO4D2_MASK,
GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
}
#endif
#if defined(CONFIG_SPL_BUILD)
int arch_cpu_init(void)
{
static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
/* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
rk_clrreg(&sgrf->con_secure0, 0x2b83);
return 0;
}
#endif

20
arch/arm/mach-rockchip/rk3308/syscon_rk3308.c Normal file
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@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3308_syscon_ids[] = {
{ .compatible = "rockchip,rk3308-grf", .data = ROCKCHIP_SYSCON_GRF },
{ }
};
U_BOOT_DRIVER(syscon_rk3308) = {
.name = "rk3308_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3308_syscon_ids,
};

20
arch/arm/mach-rockchip/rk3399/Kconfig
View File

@ -62,6 +62,25 @@ config TARGET_CHROMEBOOK_BOB
display. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
config TARGET_ROCKPRO64_RK3399
bool "Pine64 Rockpro64 board"
help
Rockro64 is SBC produced by Pine64. Key features:
* Rockchip RK3399
* 2/4GB Dual-Channel LPDDR3
* SD card slot
* eMMC socket
* 128Mb SPI Flash
* Gigabit ethernet
* PCIe 4X slot
* WiFI/BT module socket
* HDMI In/Out, DP, MIPI DSI/CSI, eDP
* USB 3.0, 2.0
* USB Type C power and data
* GPIO expansion ports
* DC 12V/2A
endchoice
config ROCKCHIP_BOOT_MODE_REG
@ -98,5 +117,6 @@ source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
source "board/vamrs/rock960_rk3399/Kconfig"
source "board/google/gru/Kconfig"
source "board/pine64/rockpro64_rk3399/Kconfig"
endif

85
arch/arm/mach-rockchip/sdram_common.c → arch/arm/mach-rockchip/sdram.c
View File

@ -7,7 +7,7 @@
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/arch-rockchip/sdram.h>
#include <dm/uclass-internal.h>
DECLARE_GLOBAL_DATA_PTR;
@ -76,39 +76,88 @@ int dram_init_banksize(void)
size_t rockchip_sdram_size(phys_addr_t reg)
{
u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
size_t chipsize_mb = 0;
size_t size_mb = 0;
u32 ch;
u32 sys_reg = readl(reg);
u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
u32 cs1_col = 0;
u32 bg = 0;
u32 dbw, dram_type;
u32 sys_reg2 = readl(reg);
u32 sys_reg3 = readl(reg + 4);
u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
& SYS_REG_NUM_CH_MASK);
debug("%s %x %x\n", __func__, (u32)reg, sys_reg);
dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
for (ch = 0; ch < ch_num; ch++) {
rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
SYS_REG_RANK_MASK);
col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
SYS_REG_COL_MASK);
cs1_col = cs0_col;
bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
SYS_REG_VERSION_MASK) == 0x2) {
cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
SYS_REG_CS1_COL_MASK);
if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
SYS_REG_CS0_ROW_SHIFT(ch) &
SYS_REG_CS0_ROW_MASK) == 7)
cs0_row = 12;
else
cs0_row = 13 + (sys_reg2 >>
SYS_REG_CS0_ROW_SHIFT(ch) &
SYS_REG_CS0_ROW_MASK) +
((sys_reg3 >>
SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
SYS_REG_CS1_ROW_SHIFT(ch) &
SYS_REG_CS1_ROW_MASK) == 7)
cs1_row = 12;
else
cs1_row = 13 + (sys_reg2 >>
SYS_REG_CS1_ROW_SHIFT(ch) &
SYS_REG_CS1_ROW_MASK) +
((sys_reg3 >>
SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
} else {
cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
SYS_REG_CS0_ROW_MASK);
cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
SYS_REG_CS1_ROW_MASK);
bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
}
bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
SYS_REG_BW_MASK));
row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
SYS_REG_ROW_3_4_MASK;
chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
if (dram_type == DDR4) {
dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
SYS_REG_DBW_MASK;
bg = (dbw == 2) ? 2 : 1;
}
chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
if (rank > 1)
chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
(cs0_col - cs1_col));
if (row_3_4)
chipsize_mb = chipsize_mb * 3 / 4;
size_mb += chipsize_mb;
debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
rank, col, bk, cs0_row, bw, row_3_4);
if (rank > 1)
debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
cs1_row %d bw %d row_3_4 %d\n",
rank, cs0_col, cs1_col, bk, cs0_row,
cs1_row, bw, row_3_4);
else
debug("rank %d cs0_col %d bk %d cs0_row %d\
bw %d row_3_4 %d\n",
rank, cs0_col, bk, cs0_row,
bw, row_3_4);
}
/*

19
arch/arm/mach-rockchip/spl.c
View File

@ -9,7 +9,6 @@
#include <ram.h>
#include <spl.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/sdram.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -103,7 +102,7 @@ __weak int arch_cpu_init(void)
void board_init_f(ulong dummy)
{
int ret;
#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT)
#if !defined(CONFIG_TPL) || defined(CONFIG_SPL_OS_BOOT)
struct udevice *dev;
#endif
@ -128,20 +127,20 @@ void board_init_f(ulong dummy)
hang();
}
arch_cpu_init();
#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT)
debug("\nspl:init dram\n");
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return;
}
#endif
#if !defined(CONFIG_ROCKCHIP_RK3188)
rockchip_stimer_init();
#endif
#ifdef CONFIG_SYS_ARCH_TIMER
/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
timer_init();
#endif
#if !defined(CONFIG_TPL) || defined(CONFIG_SPL_OS_BOOT)
debug("\nspl:init dram\n");
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return;
}
#endif
preloader_console_init();
}

2
arch/powerpc/lib/Makefile
View File

@ -41,5 +41,5 @@ obj-y += time.o
endif # not minimal
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
obj-$(CONFIG_$(SPL_TPL)_FRAMEWORK) += spl.o
endif

15
board/firefly/firefly-rk3308/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_ROC_RK3308_CC
config SYS_BOARD
default "firefly-rk3308"
config SYS_VENDOR
default "firefly"
config SYS_CONFIG_NAME
default "firefly_rk3308"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

5
board/firefly/firefly-rk3308/MAINTAINERS Normal file
View File

@ -0,0 +1,5 @@
ROC-RK3308-CC
M: Andy Yan <andy.yan@rock-chips.com>
S: Maintained
F: board/firefly/firefly-rk3308/roc_cc_rk3308.c
F: configs/roc-cc-rk3308_defconfig

7
board/firefly/firefly-rk3308/Makefile Normal file
View File

@ -0,0 +1,7 @@
#
# (C) Copyright 2018 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += roc_cc_rk3308.o

81
board/firefly/firefly-rk3308/roc_cc_rk3308.c Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <adc.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3308.h>
#include <asm/arch-rockchip/hardware.h>
#if defined(CONFIG_DEBUG_UART)
#define GRF_BASE 0xff000000
enum {
GPIO1C7_SHIFT = 8,
GPIO1C7_MASK = GENMASK(11, 8),
GPIO1C7_GPIO = 0,
GPIO1C7_UART1_RTSN,
GPIO1C7_UART2_TX_M0,
GPIO1C7_SPI2_MOSI,
GPIO1C7_JTAG_TMS,
GPIO1C6_SHIFT = 4,
GPIO1C6_MASK = GENMASK(7, 4),
GPIO1C6_GPIO = 0,
GPIO1C6_UART1_CTSN,
GPIO1C6_UART2_RX_M0,
GPIO1C6_SPI2_MISO,
GPIO1C6_JTAG_TCLK,
GPIO4D3_SHIFT = 6,
GPIO4D3_MASK = GENMASK(7, 6),
GPIO4D3_GPIO = 0,
GPIO4D3_SDMMC_D3,
GPIO4D3_UART2_TX_M1,
GPIO4D2_SHIFT = 4,
GPIO4D2_MASK = GENMASK(5, 4),
GPIO4D2_GPIO = 0,
GPIO4D2_SDMMC_D2,
GPIO4D2_UART2_RX_M1,
UART2_IO_SEL_SHIFT = 2,
UART2_IO_SEL_MASK = GENMASK(3, 2),
UART2_IO_SEL_M0 = 0,
UART2_IO_SEL_M1,
UART2_IO_SEL_USB,
};
void board_debug_uart_init(void)
{
static struct rk3308_grf * const grf = (void *)GRF_BASE;
/* Enable early UART2 channel m0 on the rk3308 */
rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
rk_clrsetreg(&grf->gpio1ch_iomux,
GPIO1C6_MASK | GPIO1C7_MASK,
GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
}
#endif
#define KEY_DOWN_MIN_VAL 0
#define KEY_DOWN_MAX_VAL 30
int rockchip_dnl_key_pressed(void)
{
unsigned int val;
if (adc_channel_single_shot("saradc", 1, &val)) {
printf("%s read adc key val failed\n", __func__);
return false;
}
if (val >= KEY_DOWN_MIN_VAL && val <= KEY_DOWN_MAX_VAL)
return true;
else
return false;
}

15
board/pine64/rockpro64_rk3399/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_ROCKPRO64_RK3399
config SYS_BOARD
default "rockpro64_rk3399"
config SYS_VENDOR
default "pine64"
config SYS_CONFIG_NAME
default "rockpro64_rk3399"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

8
board/pine64/rockpro64_rk3399/MAINTAINERS Normal file
View File

@ -0,0 +1,8 @@
ROCKPRO64
M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/pine64/rockpro64_rk3399
F: include/configs/rockpro64_rk3399.h
F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
F: configs/rockpro64-rk3399_defconfig

7
board/pine64/rockpro64_rk3399/Makefile Normal file
View File

@ -0,0 +1,7 @@
#
# (C) Copyright 2019 Vasily Khoruzhick
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += rockpro64-rk3399.o

55
board/pine64/rockpro64_rk3399/rockpro64-rk3399.c Normal file
View File

@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/misc.h>
#define GRF_IO_VSEL_BT565_SHIFT 0
#define PMUGRF_CON0_VSEL_SHIFT 8
#ifdef CONFIG_MISC_INIT_R
static void setup_iodomain(void)
{
struct rk3399_grf_regs *grf =
syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
struct rk3399_pmugrf_regs *pmugrf =
syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
/* BT565 is in 1.8v domain */
rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
int misc_init_r(void)
{
const u32 cpuid_offset = 0x7;
const u32 cpuid_length = 0x10;
u8 cpuid[cpuid_length];
int ret;
setup_iodomain();
ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
if (ret)
return ret;
ret = rockchip_cpuid_set(cpuid, cpuid_length);
if (ret)
return ret;
ret = rockchip_setup_macaddr();
return ret;
}
#endif

15
board/rockchip/evb_px30/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_EVB_PX30
config SYS_BOARD
default "evb_px30"
config SYS_VENDOR
default "rockchip"
config SYS_CONFIG_NAME
default "evb_px30"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/rockchip/evb_px30/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
EVB-PX30
M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
F: board/rockchip/evb_px30
F: include/configs/evb_px30.h
F: configs/evb-px30_defconfig

7
board/rockchip/evb_px30/Makefile Normal file
View File

@ -0,0 +1,7 @@
#
# (C) Copyright 2017 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += evb_px30.o

4
board/rockchip/evb_px30/evb_px30.c Normal file
View File

@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/

15
board/rockchip/evb_rk3308/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_EVB_RK3308
config SYS_BOARD
default "evb_rk3308"
config SYS_VENDOR
default "rockchip"
config SYS_CONFIG_NAME
default "evb_rk3308"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/rockchip/evb_rk3308/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
EVB-RK3308
M: Andy Yan <andy.yan@rock-chips.com>
S: Maintained
F: board/rockchip/evb_rk3308
F: include/configs/evb_rk3308.h
F: configs/evb-rk3308_defconfig

7
board/rockchip/evb_rk3308/Makefile Normal file
View File

@ -0,0 +1,7 @@
#
# (C) Copyright 2018 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += evb_rk3308.o

44
board/rockchip/evb_rk3308/evb_rk3308.c Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <adc.h>
DECLARE_GLOBAL_DATA_PTR;
#define KEY_DOWN_MIN_VAL 0
#define KEY_DOWN_MAX_VAL 30
/*
* Two board variants whith adc channel 3 is for board id
* v10: 1024, v11: 512
* v10: adc channel 0 for dnl key
* v11: adc channel 1 for dnl key
*/
int rockchip_dnl_key_pressed(void)
{
unsigned int key_val, id_val;
int key_ch;
if (adc_channel_single_shot("saradc", 3, &id_val)) {
printf("%s read board id failed\n", __func__);
return false;
}
if (abs(id_val - 1024) <= 30)
key_ch = 0;
else
key_ch = 1;
if (adc_channel_single_shot("saradc", key_ch, &key_val)) {
printf("%s read adc key val failed\n", __func__);
return false;
}
if (key_val >= KEY_DOWN_MIN_VAL && key_val <= KEY_DOWN_MAX_VAL)
return true;
else
return false;
}

9
board/rockchip/evb_rk3399/MAINTAINERS
View File

@ -58,7 +58,7 @@ F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
ROC-RK3399-PC
M: Levin Du <djw@t-chip.com.cn>
S: Maintained
F: configs/roc-rk3399-pc_defconfig
F: configs/roc-pc-rk3399_defconfig
F: arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
ROCK-PI-4
@ -67,10 +67,3 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/rock-pi-4-rk3399_defconfig
F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
ROCKPRO64
M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/rockpro64-rk3399_defconfig
F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi

7
board/rockchip/tinker_rk3288/MAINTAINERS
View File

@ -4,3 +4,10 @@ S: Maintained
F: board/rockchip/tinker_rk3288
F: include/configs/tinker_rk3288.h
F: configs/tinker-rk3288_defconfig
TINKER-S-RK3288
M: Michael Trimarchi <michael@amarulasolutions.com>
S: Maintained
F: board/rockchip/tinker_rk3288
F: include/configs/tinker_rk3288.h
F: configs/tinker-s-rk3288_defconfig

12
board/rockchip/tinker_rk3288/tinker-rk3288.c
View File

@ -8,6 +8,8 @@
#include <env.h>
#include <i2c_eeprom.h>
#include <netdev.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/io.h>
static int get_ethaddr_from_eeprom(u8 *addr)
{
@ -33,3 +35,13 @@ int rk3288_board_late_init(void)
return 0;
}
int mmc_get_env_dev(void)
{
u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
if (bootdevice_brom_id == BROM_BOOTSOURCE_EMMC)
return 0;
return 1;
}

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