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i.MX7ULP: Correct the clock index

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On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Bai Ping 2019-07-22 01:24:45 +00:00 committed by Stefano Babic
parent 7777406a8a
commit 3ed6734e69
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-imx/mx7ulp/scg.c
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@ -440,7 +440,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk)
case SCG_SCS_SLOW_IRC:
case SCG_SCS_FAST_IRC:
case SCG_SCS_RTC_OSC:
rate = scg_src_get_rate(scg_scs_array[val]);
rate = scg_src_get_rate(scg_scs_array[val - 1]);
break;
case 5:
rate = scg_apll_get_rate();