mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs. MT8512/MT8110 SoCs puts the tune register at top layer, so need add new code to support it. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
This commit is contained in:
mingming lee
Tom Rini
parent
51fcd56c0d
commit
3b0397d48b
@ -12,6 +12,7 @@
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#include <mmc.h>
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#include <errno.h>
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#include <malloc.h>
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#include <mapmem.h>
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#include <stdbool.h>
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#include <watchdog.h>
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#include <asm/gpio.h>
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@ -135,6 +136,25 @@
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#define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
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#define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
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/* EMMC_TOP_CONTROL mask */
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#define PAD_RXDLY_SEL BIT(0)
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#define DELAY_EN BIT(1)
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#define PAD_DAT_RD_RXDLY2 (0x1f << 2)
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#define PAD_DAT_RD_RXDLY (0x1f << 7)
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#define PAD_DAT_RD_RXDLY_S 7
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#define PAD_DAT_RD_RXDLY2_SEL BIT(12)
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#define PAD_DAT_RD_RXDLY_SEL BIT(13)
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#define DATA_K_VALUE_SEL BIT(14)
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#define SDC_RX_ENH_EN BIT(15)
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/* EMMC_TOP_CMD mask */
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#define PAD_CMD_RXDLY2 (0x1f << 0)
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#define PAD_CMD_RXDLY (0x1f << 5)
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#define PAD_CMD_RXDLY_S 5
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#define PAD_CMD_RD_RXDLY2_SEL BIT(10)
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#define PAD_CMD_RD_RXDLY_SEL BIT(11)
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#define PAD_CMD_TX_DLY (0x1f << 12)
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/* SDC_CFG_BUSWIDTH */
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#define MSDC_BUS_1BITS 0x0
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#define MSDC_BUS_4BITS 0x1
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@ -219,6 +239,21 @@ struct mtk_sd_regs {
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u32 sdc_fifo_cfg;
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};
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struct msdc_top_regs {
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u32 emmc_top_control;
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u32 emmc_top_cmd;
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u32 emmc50_pad_ctl0;
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u32 emmc50_pad_ds_tune;
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u32 emmc50_pad_dat0_tune;
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u32 emmc50_pad_dat1_tune;
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u32 emmc50_pad_dat2_tune;
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u32 emmc50_pad_dat3_tune;
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u32 emmc50_pad_dat4_tune;
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u32 emmc50_pad_dat5_tune;
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u32 emmc50_pad_dat6_tune;
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u32 emmc50_pad_dat7_tune;
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};
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struct msdc_compatible {
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u8 clk_div_bits;
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u8 sclk_cycle_shift;
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@ -249,6 +284,7 @@ struct msdc_tune_para {
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struct msdc_host {
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struct mtk_sd_regs *base;
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struct msdc_top_regs *top_base;
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struct mmc *mmc;
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struct msdc_compatible *dev_comp;
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@ -964,6 +1000,36 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
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return delay_phase;
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}
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static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
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{
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void __iomem *tune_reg = &host->base->pad_tune;
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if (host->dev_comp->pad_tune0)
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tune_reg = &host->base->pad_tune0;
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if (host->top_base)
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clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
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value << PAD_CMD_RXDLY_S);
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else
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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value << MSDC_PAD_TUNE_CMDRDLY_S);
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}
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static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
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{
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void __iomem *tune_reg = &host->base->pad_tune;
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if (host->dev_comp->pad_tune0)
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tune_reg = &host->base->pad_tune0;
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if (host->top_base)
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clrsetbits_le32(&host->top_base->emmc_top_control,
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PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
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else
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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value << MSDC_PAD_TUNE_DATRRDLY_S);
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}
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static int hs400_tune_response(struct udevice *dev, u32 opcode)
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{
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struct msdc_plat *plat = dev_get_platdata(dev);
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@ -1010,7 +1076,7 @@ static int hs400_tune_response(struct udevice *dev, u32 opcode)
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PAD_CMD_TUNE_RX_DLY3_S);
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final_delay = final_cmd_delay.final_phase;
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dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
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dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
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return final_delay == 0xff ? -EIO : 0;
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}
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@ -1217,21 +1283,14 @@ static int msdc_tune_together(struct udevice *dev, u32 opcode)
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u32 rise_delay = 0, fall_delay = 0;
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struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
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u8 final_delay, final_maxlen;
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void __iomem *tune_reg = &host->base->pad_tune;
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int i, ret;
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if (host->dev_comp->pad_tune0)
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tune_reg = &host->base->pad_tune0;
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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i << MSDC_PAD_TUNE_CMDRDLY_S);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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i << MSDC_PAD_TUNE_DATRRDLY_S);
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msdc_set_cmd_delay(host, i);
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msdc_set_data_delay(host, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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rise_delay |= (1 << i);
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@ -1246,11 +1305,8 @@ static int msdc_tune_together(struct udevice *dev, u32 opcode)
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setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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i << MSDC_PAD_TUNE_CMDRDLY_S);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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i << MSDC_PAD_TUNE_DATRRDLY_S);
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msdc_set_cmd_delay(host, i);
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msdc_set_data_delay(host, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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fall_delay |= (1 << i);
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@ -1263,27 +1319,17 @@ skip_fall:
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if (final_maxlen == final_rise_delay.maxlen) {
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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final_rise_delay.final_phase <<
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MSDC_PAD_TUNE_CMDRDLY_S);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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final_rise_delay.final_phase <<
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MSDC_PAD_TUNE_DATRRDLY_S);
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final_delay = final_rise_delay.final_phase;
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} else {
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setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
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setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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final_fall_delay.final_phase <<
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MSDC_PAD_TUNE_CMDRDLY_S);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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final_fall_delay.final_phase <<
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MSDC_PAD_TUNE_DATRRDLY_S);
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final_delay = final_fall_delay.final_phase;
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}
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dev_err(dev, "Final pad delay: %x\n", final_delay);
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msdc_set_cmd_delay(host, final_delay);
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msdc_set_data_delay(host, final_delay);
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dev_info(dev, "Final pad delay: %x\n", final_delay);
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return final_delay == 0xff ? -EIO : 0;
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}
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@ -1400,8 +1446,12 @@ static void msdc_init_hw(struct msdc_host *host)
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3 << MSDC_PB2_RESPWAIT_S);
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if (host->dev_comp->enhance_rx) {
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setbits_le32(&host->base->sdc_adv_cfg0,
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SDC_RX_ENHANCE_EN);
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if (host->top_base)
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setbits_le32(&host->top_base->emmc_top_control,
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SDC_RX_ENH_EN);
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else
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setbits_le32(&host->base->sdc_adv_cfg0,
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SDC_RX_ENHANCE_EN);
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} else {
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clrsetbits_le32(&host->base->patch_bit2,
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MSDC_PB2_RESPSTSENSEL_M,
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@ -1476,7 +1526,6 @@ static int msdc_drv_probe(struct udevice *dev)
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cfg->f_min = host->src_clk_freq / (4 * 255);
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else
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cfg->f_min = host->src_clk_freq / (4 * 4095);
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cfg->f_max = host->src_clk_freq / 2;
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cfg->b_max = 1024;
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cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
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@ -1502,11 +1551,19 @@ static int msdc_ofdata_to_platdata(struct udevice *dev)
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struct msdc_plat *plat = dev_get_platdata(dev);
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struct msdc_host *host = dev_get_priv(dev);
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struct mmc_config *cfg = &plat->cfg;
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fdt_addr_t base, top_base;
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int ret;
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host->base = (void *)dev_read_addr(dev);
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if (!host->base)
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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host->base = map_sysmem(base, 0);
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top_base = dev_read_addr_index(dev, 1);
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if (top_base == FDT_ADDR_T_NONE)
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host->top_base = NULL;
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else
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host->top_base = map_sysmem(top_base, 0);
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ret = mmc_of_parse(dev, cfg);
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if (ret)
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@ -1579,6 +1636,16 @@ static const struct msdc_compatible mt7623_compat = {
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.enhance_rx = false
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};
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static const struct msdc_compatible mt8512_compat = {
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.clk_div_bits = 12,
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.sclk_cycle_shift = 20,
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.pad_tune0 = true,
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.async_fifo = true,
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.data_tune = true,
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.busy_check = true,
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.stop_clk_fix = true,
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};
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static const struct msdc_compatible mt8516_compat = {
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.clk_div_bits = 12,
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.sclk_cycle_shift = 20,
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@ -1602,6 +1669,7 @@ static const struct msdc_compatible mt8183_compat = {
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static const struct udevice_id msdc_ids[] = {
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{ .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
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{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
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{ .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
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{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
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{ .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
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{}
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