board/BuR/brppt2: initial commit
This commit adds support for the brppt2 board. The board is based on the i.mx6 dual-lite SoC. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
This commit is contained in:
Hannes Schmelzer
Stefano Babic
parent
910b2fca97
commit
c04ac5bd40
@ -565,6 +565,7 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
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ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
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dtb-y += \
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imx6dl-brppt2.dtb \
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imx6dl-dhcom-pdk2.dtb \
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imx6dl-icore.dtb \
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imx6dl-icore-mipi.dtb \
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278
arch/arm/dts/imx6dl-brppt2.dts
Normal file
278
arch/arm/dts/imx6dl-brppt2.dts
Normal file
@ -0,0 +1,278 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 B&R Industrial Automation GmbH
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx6dl.dtsi"
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#include "imx6qdl-u-boot.dtsi"
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#include <dt-bindings/pwm/pwm.h>
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#include <include/dt-bindings/gpio/gpio.h>
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/ {
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model = "PPT50";
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compatible = "fsl,imx6dl";
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config {
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u-boot,spl-payload-offset = <0x100000>;
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};
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fset: factory-settings {
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bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
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order-no = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
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hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
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serial-no = <0>;
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device-id = <0x0>;
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parent-id = <0x0>;
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hw-variant = <0x0>;
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};
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aliases {
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ds1timing0 = &timing0;
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ds1timing1 = &timing1;
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ds1bkl = &backlight;
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fset = &fset;
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mxcfb0 = &mxcfb0;
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touch0 = &touch0;
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touch1 = &touch1;
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touch2 = &touch2;
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display_regulator = &display_regulator;
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ldb = &ldb;
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mmc0 = &usdhc4;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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mxcfb0: fb@0 {
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compatible = "fsl,mxc_sdc_fb";
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disp_dev = "ldb";
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interface_pix_fmt = "RGB24";
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default_bpp = <32>;
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int_clk = <0>;
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late_init = <0>;
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rotation = <0>;
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status = "okay";
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};
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lcd@0 {
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compatible = "fsl,lcd";
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vlcd-supply = <&display_regulator>;
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ipu_id = <0>;
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disp_id = <0>;
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default_ifmt = "RGB24";
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status = "disabled";
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display-timings {
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native-mode = <&timing1>;
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timing1: lcd {
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};
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};
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm4 0 5000000>;
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brightness-levels = <0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100>;
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default-brightness-level = <0>;
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status = "okay";
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enable-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
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};
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beeper: pwm-beep {
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compatible = "pwm-beeper";
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pwms = <&pwm3 0 0 0>;
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};
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vbus1_regulator: regulator@1 {
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u-boot,dm-preloc;
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compatible = "regulator-fixed";
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regulator-name = "vbus1_regulator";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vbus2_regulator: regulator@2 {
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compatible = "regulator-fixed";
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regulator-name = "vbus2_regulator";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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usbhub_regulator: gpio-regulator@3 {
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compatible = "regulator-gpio";
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regulator-name = "ushbub_regulator";
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enable-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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enable-at-boot;
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states = <0 0 1 1>;
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};
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display_regulator: regulator@4 {
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compatible = "regulator-fixed";
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regulator-name = "display_regulator";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <1000>;
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};
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};
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&fec {
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phy-mode = "rgmii-id";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&uart1 {
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u-boot,dm-spl;
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u-boot,dm-preloc;
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status = "okay";
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};
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&pwm3 {
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status = "okay";
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};
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&pwm4 {
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status = "okay";
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};
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&ldb {
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status = "disabled";
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vldb-supply = <&display_regulator>;
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lvds-channel@0 {
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fsl,data-mapping = "spwg";
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fsl,data-width = <24>;
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primary;
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status = "okay";
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crtc = "ipu1-di0";
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display-timings {
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native-mode = <&timing0>;
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timing0: lcd {
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};
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};
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};
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};
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&usdhc4 {
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&usbotg {
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vbus-supply = <&vbus1_regulator>;
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dr_mode = "host";
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status = "okay";
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};
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&usbh1 {
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vbus-supply = <&vbus2_regulator>;
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dr_mode = "host";
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <400000>;
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status = "okay";
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touch0: egalax_i2c@2a {
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compatible = "eeti,egalax_i2c";
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reg = <0x2a>;
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interrupt-parent = <&gpio4>;
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interrupts = <9 2>;
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int-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
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};
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touch1: gt911@5d {
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compatible = "goodix,gt911";
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reg = <0x5d>;
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interrupt-parent = <&gpio4>;
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interrupts = <9 2>;
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irq-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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touch2: i2c-hid-dev@2c {
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compatible = "hid-over-i2c";
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reg = <0x2c>;
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hid-descr-addr = <0x0001>;
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interrupt-parent = <&gpio4>;
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interrupts = <9 2>;
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status = "disabled";
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};
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};
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&gpio1 {
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u-boot,dm-spl;
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status = "okay";
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};
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&gpio2 {
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u-boot,dm-spl;
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status = "okay";
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};
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&gpio3 {
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u-boot,dm-spl;
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status = "okay";
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};
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&gpio4 {
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u-boot,dm-spl;
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status = "okay";
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};
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&usdhc4 {
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status = "okay";
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};
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&ecspi1 {
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u-boot,dm-spl;
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cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
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status = "okay";
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spi-max-frequency = <25000000>;
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m25p32@1 {
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u-boot,dm-spl;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p", "jedec,spi-nor";
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spi-max-frequency = <25000000>;
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reg = <1>;
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};
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};
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@ -596,6 +596,24 @@ config TARGET_ZC5601
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_BRPPT2
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bool "brppt2"
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select BOARD_LATE_INIT
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select MX6QDL
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select OF_CONTROL
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select SPL_OF_LIBFDT
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_I2C
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select DM_MMC
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select SUPPORT_SPL
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select SPL_DM if SPL
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select SPL_OF_CONTROL if SPL
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help
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Support
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B&R BRPPT2 platform
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based on Freescale's iMX6 SoC
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endchoice
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config SYS_SOC
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@ -653,5 +671,6 @@ source "board/udoo/Kconfig"
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source "board/udoo/neo/Kconfig"
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source "board/wandboard/Kconfig"
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source "board/warp/Kconfig"
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source "board/BuR/brppt2/Kconfig"
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endif
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18
board/BuR/brppt2/Kconfig
Normal file
18
board/BuR/brppt2/Kconfig
Normal file
@ -0,0 +1,18 @@
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if TARGET_BRPPT2
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config SYS_BOARD
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default "brppt2"
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config SYS_VENDOR
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default "BuR"
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config SYS_SOC
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default "mx6"
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config SYS_CONFIG_NAME
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default "brppt2"
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config SPL_DM_SPI
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def_bool y
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endif
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6
board/BuR/brppt2/MAINTAINERS
Normal file
6
board/BuR/brppt2/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
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BUR_PPT2 BOARD
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M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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S: Maintained
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F: board/BuR/brppt2/
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F: include/configs/brppt2.h
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F: configs/brppt2_defconfig
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8
board/BuR/brppt2/Makefile
Normal file
8
board/BuR/brppt2/Makefile
Normal file
@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0+
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# Copyright (C) 2019
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# B&R Industrial Automation GmbH - http://www.br-automation.com
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#
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obj-y := ../common/common.o
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obj-y += board.o
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542
board/BuR/brppt2/board.c
Normal file
542
board/BuR/brppt2/board.c
Normal file
@ -0,0 +1,542 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board functions for BuR BRPPT2 board
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*
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* Copyright (C) 2019
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* B&R Industrial Automation GmbH - http://www.br-automation.com/
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*
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*/
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#include <common.h>
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#include <spl.h>
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#include <dm.h>
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#include <miiphy.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#ifdef CONFIG_SPL_BUILD
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# include <asm/arch/mx6-ddr.h>
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#endif
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#define USBHUB_RSTN IMX_GPIO_NR(1, 16)
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#define BKLT_EN IMX_GPIO_NR(1, 15)
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#define CAPT_INT IMX_GPIO_NR(4, 9)
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#define CAPT_RESETN IMX_GPIO_NR(4, 11)
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#define SW_INTN IMX_GPIO_NR(3, 26)
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#define VCCDISP_EN IMX_GPIO_NR(5, 18)
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#define EMMC_RSTN IMX_GPIO_NR(6, 8)
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#define PMIC_IRQN IMX_GPIO_NR(5, 22)
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#define TASTER IMX_GPIO_NR(5, 23)
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#define ETH0_LINK IMX_GPIO_NR(1, 27)
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#define ETH1_LINK IMX_GPIO_NR(1, 28)
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#define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
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PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
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PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
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PAD_CTL_SRE_FAST)
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#define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
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PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
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#if !defined(CONFIG_SPL_BUILD)
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static iomux_v3_cfg_t const eth_pads[] = {
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/*
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* Gigabit Ethernet
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*/
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/* CLKs */
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MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK),
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MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK),
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/* MDIO */
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MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU),
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MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU),
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/* RGMII */
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MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1),
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MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
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MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
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MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
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MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
|
||||
MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
|
||||
MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU),
|
||||
/* ETH0_LINK */
|
||||
MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD),
|
||||
/* ETH1_LINK */
|
||||
MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const board_pads[] = {
|
||||
/*
|
||||
* I2C #3, #4
|
||||
*/
|
||||
MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL),
|
||||
MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
|
||||
|
||||
/*
|
||||
* UART#4 PADS
|
||||
* UART_Tasten
|
||||
*/
|
||||
MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL),
|
||||
MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL),
|
||||
MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL),
|
||||
MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL),
|
||||
/*
|
||||
* ESCPI#1
|
||||
* M25P32 NOR-Flash
|
||||
*/
|
||||
MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
|
||||
/*
|
||||
* ESCPI#2
|
||||
* resTouch SPI ADC
|
||||
*/
|
||||
MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL),
|
||||
/*
|
||||
* USDHC#4
|
||||
*/
|
||||
MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
|
||||
/*
|
||||
* USB OTG power & ID
|
||||
*/
|
||||
/* USB_OTG_5V_EN */
|
||||
MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD),
|
||||
MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD),
|
||||
/* USB_OTG_JUMPER */
|
||||
MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD),
|
||||
/*
|
||||
* PWM-Pins
|
||||
*/
|
||||
/* BKLT_CTL */
|
||||
MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD),
|
||||
/* SPEAKER */
|
||||
MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD),
|
||||
/*
|
||||
* GPIOs
|
||||
*/
|
||||
/* USB_HUB_nRESET */
|
||||
MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD),
|
||||
/* BKLT_EN */
|
||||
MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD),
|
||||
/* capTouch_INT */
|
||||
MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD),
|
||||
/* capTouch_nRESET */
|
||||
MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD),
|
||||
/* SW_nINT */
|
||||
MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU),
|
||||
/* VCC_DISP_EN */
|
||||
MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD),
|
||||
/* eMMC_nRESET */
|
||||
MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD),
|
||||
/* HWID*/
|
||||
MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
|
||||
/* PMIC_nIRQ */
|
||||
MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU),
|
||||
/* nTASTER */
|
||||
MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU),
|
||||
/* RGB LCD Display */
|
||||
MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL),
|
||||
MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
gpio_direction_output(USBHUB_RSTN, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
ulong b_mode = 4;
|
||||
|
||||
if (gpio_get_value(TASTER) == 0)
|
||||
b_mode = 12;
|
||||
|
||||
env_set_ulong("b_mode", b_mode);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
if (gpio_request(BKLT_EN, "BKLT_EN"))
|
||||
printf("Warning: BKLT_EN setup failed\n");
|
||||
gpio_direction_output(BKLT_EN, 0);
|
||||
|
||||
if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
|
||||
printf("Warning: USBHUB_nRST setup failed\n");
|
||||
gpio_direction_output(USBHUB_RSTN, 0);
|
||||
|
||||
if (gpio_request(TASTER, "TASTER"))
|
||||
printf("Warning: TASTER setup failed\n");
|
||||
gpio_direction_input(TASTER);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
|
||||
SETUP_IOMUX_PADS(board_pads);
|
||||
SETUP_IOMUX_PADS(eth_pads);
|
||||
|
||||
/* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
|
||||
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
|
||||
enable_fec_anatop_clock(0, ENET_25MHZ);
|
||||
enable_enet_clk(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = imx_ddr_size();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
|
||||
static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
|
||||
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
|
||||
.dram_sdclk_0 = 0x00020030,
|
||||
.dram_sdclk_1 = 0x00020030,
|
||||
.dram_cas = 0x00020030,
|
||||
.dram_ras = 0x00020030,
|
||||
.dram_reset = 0x00020030,
|
||||
/* SDCKE[0:1]: 100k pull-up */
|
||||
.dram_sdcke0 = 0x00003000,
|
||||
.dram_sdcke1 = 0x00003000,
|
||||
/* SDBA2: pull-up disabled */
|
||||
.dram_sdba2 = 0x00000000,
|
||||
/* SDODT[0:1]: 100k pull-up, 40 ohm */
|
||||
.dram_sdodt0 = 0x00003030,
|
||||
.dram_sdodt1 = 0x00003030,
|
||||
/* SDQS[0:7]: Differential input, 40 ohm */
|
||||
.dram_sdqs0 = 0x00000030,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_sdqs2 = 0x00000030,
|
||||
.dram_sdqs3 = 0x00000030,
|
||||
.dram_sdqs4 = 0x00000030,
|
||||
.dram_sdqs5 = 0x00000030,
|
||||
.dram_sdqs6 = 0x00000030,
|
||||
.dram_sdqs7 = 0x00000030,
|
||||
/* DQM[0:7]: Differential input, 40 ohm */
|
||||
.dram_dqm0 = 0x00020030,
|
||||
.dram_dqm1 = 0x00020030,
|
||||
.dram_dqm2 = 0x00020030,
|
||||
.dram_dqm3 = 0x00020030,
|
||||
.dram_dqm4 = 0x00020030,
|
||||
.dram_dqm5 = 0x00020030,
|
||||
.dram_dqm6 = 0x00020030,
|
||||
.dram_dqm7 = 0x00020030,
|
||||
};
|
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
|
||||
static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
|
||||
/* DDR3 */
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
/* disable DDR pullups */
|
||||
.grp_ddrpke = 0x00000000,
|
||||
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
|
||||
.grp_addds = 0x00000030,
|
||||
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
|
||||
.grp_ctlds = 0x00000030,
|
||||
/* DATA[00:63]: Differential input, 40 ohm */
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_b2ds = 0x00000030,
|
||||
.grp_b3ds = 0x00000030,
|
||||
.grp_b4ds = 0x00000030,
|
||||
.grp_b5ds = 0x00000030,
|
||||
.grp_b6ds = 0x00000030,
|
||||
.grp_b7ds = 0x00000030,
|
||||
};
|
||||
|
||||
/*
|
||||
* DDR3 desriptions - these are the memory chips we support
|
||||
*/
|
||||
|
||||
/* NT5CC128M16FP-DII */
|
||||
static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
|
||||
.mem_speed = 1600,
|
||||
.density = 2,
|
||||
.width = 16,
|
||||
.banks = 8,
|
||||
.rowaddr = 14,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1375,
|
||||
.trcmin = 4875,
|
||||
.trasmin = 3500,
|
||||
};
|
||||
|
||||
/* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
|
||||
static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
|
||||
/* write leveling calibration determine, MR1-value = 0x0002 */
|
||||
.p0_mpwldectrl0 = 0x003F003E,
|
||||
.p0_mpwldectrl1 = 0x003A003A,
|
||||
.p1_mpwldectrl0 = 0x001B001C,
|
||||
.p1_mpwldectrl1 = 0x00190031,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x02640264,
|
||||
.p0_mpdgctrl1 = 0x02440250,
|
||||
.p1_mpdgctrl0 = 0x02400250,
|
||||
.p1_mpdgctrl1 = 0x0238023C,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x40464644,
|
||||
.p1_mprddlctl = 0x464A4842,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x38343034,
|
||||
.p1_mpwrdlctl = 0x36323830,
|
||||
};
|
||||
|
||||
/* measured on board TSERIES_ARM/1 V_LVDS_S32 */
|
||||
static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
|
||||
/* write leveling calibration determine, MR1-value = 0x0002 */
|
||||
.p0_mpwldectrl0 = 0x00410043,
|
||||
.p0_mpwldectrl1 = 0x003A003C,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x023C0244,
|
||||
.p0_mpdgctrl1 = 0x02240230,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x484C4A48,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x3C363434,
|
||||
};
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
|
||||
u32 val, dram_strap = 0;
|
||||
struct mx6_ddr3_cfg *mem = NULL;
|
||||
struct mx6_mmdc_calibration *calib = NULL;
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
/* width of data bus:0=16,1=32,2=64 */
|
||||
.dsize = -1, /* CPU type specific (overwritten) */
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32, /* 32Gb per CS */
|
||||
.ncs = 1, /* single chip select */
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
|
||||
.rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
.ddr_type = 0, /* DDR3 */
|
||||
};
|
||||
|
||||
/*
|
||||
* MMDC Calibration requires the following data:
|
||||
* mx6_mmdc_calibration - board-specific calibration (routing delays)
|
||||
* these calibration values depend on board routing, SoC, and DDR
|
||||
* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
|
||||
* mx6_ddr_cfg - chip specific timing/layout details
|
||||
*/
|
||||
|
||||
/* setup HWID3-2 to input */
|
||||
val = readl(&gpio->gpio_dir);
|
||||
val &= ~(0x1 << 0 | 0x1 << 1);
|
||||
writel(val, &gpio->gpio_dir);
|
||||
|
||||
/* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
|
||||
dram_strap = readl(&gpio->gpio_psr) & 0x3;
|
||||
|
||||
switch (dram_strap) {
|
||||
/* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
|
||||
case 0:
|
||||
puts("DRAM strap 00\n");
|
||||
mem = &cfg_nt5cc128m16fp_dii;
|
||||
sysinfo.dsize = 2;
|
||||
calib = &cal_nt5cc128m16fp_dii_128x64_s;
|
||||
break;
|
||||
/* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
|
||||
case 1:
|
||||
puts("DRAM strap 01\n");
|
||||
mem = &cfg_nt5cc128m16fp_dii;
|
||||
sysinfo.dsize = 1;
|
||||
calib = &cal_nt5cc128m16fp_dii_128x32_s;
|
||||
break;
|
||||
default:
|
||||
printf("DRAM strap 0x%x (invalid)\n", dram_strap);
|
||||
break;
|
||||
}
|
||||
|
||||
if (!mem) {
|
||||
puts("Error: Invalid Memory Configuration\n");
|
||||
hang();
|
||||
}
|
||||
if (!calib) {
|
||||
puts("Error: Invalid Board Calibration Configuration\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
mx6sdl_dram_iocfg(16 << sysinfo.dsize,
|
||||
&ddr_iomux_s,
|
||||
&grp_iomux_s);
|
||||
|
||||
mx6_dram_cfg(&sysinfo, calib, mem);
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const board_pads_spl[] = {
|
||||
/* UART#1 PADS */
|
||||
MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL),
|
||||
MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL),
|
||||
/* ESCPI#1 PADS */
|
||||
MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
|
||||
MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
|
||||
/* USDHC#4 PADS */
|
||||
MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
|
||||
MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
|
||||
/* HWID*/
|
||||
MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
|
||||
MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
|
||||
};
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
preloader_console_init();
|
||||
}
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/*
|
||||
* We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
|
||||
* initializes DMA very early (before all board code), so the only
|
||||
* opportunity we have to initialize APBHDMA clocks is in SPL.
|
||||
* setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
||||
*/
|
||||
|
||||
writel(0x00C03F3F, &ccm->CCGR0);
|
||||
writel(0x00F0FC03, &ccm->CCGR1);
|
||||
writel(0x0FFFF000, &ccm->CCGR2);
|
||||
writel(0x3FF00000, &ccm->CCGR3);
|
||||
writel(0x00FFF300, &ccm->CCGR4);
|
||||
writel(0x0F0030C3, &ccm->CCGR5);
|
||||
writel(0x000003F0, &ccm->CCGR6);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
ccgr_init();
|
||||
arch_cpu_init();
|
||||
timer_init();
|
||||
gpr_init();
|
||||
|
||||
SETUP_IOMUX_PADS(board_pads_spl);
|
||||
spl_dram_init();
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
36
board/BuR/brppt2/config.mk
Normal file
36
board/BuR/brppt2/config.mk
Normal file
@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
|
||||
# B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
#
|
||||
|
||||
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/imx6dl-//')
|
||||
|
||||
payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
|
||||
|
||||
quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
|
||||
cmd_prodbin = \
|
||||
dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
|
||||
dd conv=notrunc bs=1 if=SPL of=$@ seek=1024 2>/dev/null && \
|
||||
dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
|
||||
|
||||
quiet_cmd_prodzip = SAPZIP $@
|
||||
cmd_prodzip = \
|
||||
test -d misc && rm -r misc; \
|
||||
mkdir misc && \
|
||||
cp SPL misc/ && \
|
||||
cp u-boot-dtb.img misc/ && \
|
||||
zip -9 -r $@ misc/* >/dev/null $<
|
||||
|
||||
ifeq ($(hw-platform-y),brppt2)
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
ALL-y += $(hw-platform-y)_prog.bin
|
||||
ALL-y += $(hw-platform-y)_prod.zip
|
||||
endif
|
||||
endif
|
||||
|
||||
$(hw-platform-y)_prog.bin: u-boot-dtb.img spl SPL
|
||||
$(call if_changed,prodbin)
|
||||
|
||||
$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
|
||||
$(call if_changed,prodzip)
|
||||
93
configs/brppt2_defconfig
Normal file
93
configs/brppt2_defconfig
Normal file
@ -0,0 +1,93 @@
|
||||
CONFIG_ARM=y
|
||||
# CONFIG_SPL_SYS_THUMB_BUILD is not set
|
||||
CONFIG_SYS_L2CACHE_OFF=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
|
||||
CONFIG_SYS_TEXT_BASE=0x17800000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_TARGET_BRPPT2=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
# CONFIG_CMD_BMODE is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-brppt2"
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
|
||||
# CONFIG_EXPERT is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
|
||||
CONFIG_SPI_BOOT=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run b_default"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts dmas dma-names"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
# CONFIG_DM_DEVICE_REMOVE is not set
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
# CONFIG_OF_TRANSLATE is not set
|
||||
# CONFIG_SPL_BLK is not set
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
|
||||
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_MMC_BROKEN_CD=y
|
||||
# CONFIG_SPL_DM_MMC is not set
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
120
include/configs/brppt2.h
Normal file
120
include/configs/brppt2.h
Normal file
@ -0,0 +1,120 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Config file for BuR BRPP2_IMX6 board
|
||||
*
|
||||
* Copyright (C) 2018
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com/
|
||||
*/
|
||||
#ifndef __CONFIG_BRPP2_IMX6_H
|
||||
#define __CONFIG_BRPP2_IMX6_H
|
||||
|
||||
#include <configs/bur_cfg_common.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* -- i.mx6 specifica -- */
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF
|
||||
#define CONFIG_SYS_L2_PL310
|
||||
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
|
||||
#endif /* !CONFIG_SYS_L2CACHE_OFF */
|
||||
|
||||
#define CONFIG_BOARD_POSTCLK_INIT
|
||||
#define CONFIG_MXC_GPT_HCLK
|
||||
|
||||
#define CONFIG_LOADADDR 0x10700000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* MMC */
|
||||
#define CONFIG_FSL_USDHC
|
||||
|
||||
/* Boot */
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_MACH_TYPE 0xFFFFFFFF
|
||||
|
||||
/* misc */
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
#define CONFIG_ENV_OFFSET 0x20000
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
BUR_COMMON_ENV \
|
||||
"autoload=0\0" \
|
||||
"cfgaddr=0x106F0000\0" \
|
||||
"scraddr=0x10700000\0" \
|
||||
"loadaddr=0x10800000\0" \
|
||||
"dtbaddr=0x12000000\0" \
|
||||
"ramaddr=0x12100000\0" \
|
||||
"cfgscr=mw ${loadaddr} 0 128\0" \
|
||||
"cfgscrl=fdt addr ${dtbaddr} &&"\
|
||||
" sf probe; sf read ${cfgaddr} 0x40000 0x10000 && source ${cfgaddr}\0" \
|
||||
"console=ttymxc0,115200n8 consoleblank=0 quiet\0" \
|
||||
"t50args#0=setenv bootargs b_mode=${b_mode} console=${console} " \
|
||||
" root=/dev/mmcblk0p2 rootfstype=ext4 rootwait panic=2 \0" \
|
||||
"b_t50lgcy#0=" \
|
||||
"load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
|
||||
"load ${loaddev}:2 ${dtbaddr} /boot/imx6dl-brppt50.dtb; " \
|
||||
"run t50args#0; run cfgscrl; bootz ${loadaddr} - ${dtbaddr}\0" \
|
||||
"t50args#1=setenv bootargs console=${console} b_mode=${b_mode}" \
|
||||
" rootwait panic=2\0" \
|
||||
"b_t50lgcy#1=" \
|
||||
"load ${loaddev}:1 ${loadaddr} zImage && " \
|
||||
"load ${loaddev}:1 ${dtbaddr} imx6dl-brppt50.dtb && " \
|
||||
"load ${loaddev}:1 ${ramaddr} rootfsPPT50.uboot && " \
|
||||
"run t50args#1; run cfgscrl; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0"\
|
||||
"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
|
||||
"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
|
||||
"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
|
||||
"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
|
||||
"b_tgts_std=mmc0 mmc1 t50lgcy#0 t50lgcy#1 usb0 net\0" \
|
||||
"b_tgts_rcy=t50lgcy#1 usb0 net\0" \
|
||||
"b_tgts_pme=net usb0 mmc0 mmc1\0" \
|
||||
"b_mode=4\0" \
|
||||
"b_break=0\0" \
|
||||
"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
|
||||
" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
|
||||
" else setenv b_tgts ${b_tgts_std}; fi\0" \
|
||||
"b_default=run b_deftgts; for target in ${b_tgts};"\
|
||||
" do echo \"### booting ${target} ###\"; run b_${target};" \
|
||||
" if test ${b_break} = 1; then; exit; fi; done\0" \
|
||||
"loaddev=mmc 0\0" \
|
||||
"altbootcmd=setenv b_mode 0; run b_default;\0" \
|
||||
"bootlimit=1\0" \
|
||||
"net2nor=sf probe && dhcp &&" \
|
||||
" tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \
|
||||
" sf write ${loadaddr} 400 ${filesize} &&" \
|
||||
" tftp ${loadaddr} u-boot-dtb.img && sf erase 0x100000 +${filesize} &&" \
|
||||
" sf write ${loadaddr} 0x100000 ${filesize}\0"
|
||||
|
||||
/* RAM */
|
||||
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_FEC_FIXED_SPEED _1000BASET
|
||||
#define CONFIG_ARP_TIMEOUT 1500UL
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL
|
||||
#include "imx6_spl.h"
|
||||
|
||||
#endif /* CONFIG_SPL */
|
||||
#endif /* __CONFIG_BRPP2_IMX6_H */
|
||||
Loading…
Reference in New Issue
Block a user