net: phy: mv88e61xx: rework to enable detection of 88E6071 devices
Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Anatolij Gustschin
Joe Hershberger
parent
b2f2643b39
commit
f41a722baa
@ -39,15 +39,11 @@
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#define PHY_AUTONEGOTIATE_TIMEOUT 5000
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#define PORT_COUNT 11
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#define PORT_MASK ((1 << PORT_COUNT) - 1)
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#define PORT_MASK(port_count) ((1 << (port_count)) - 1)
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/* Device addresses */
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#define DEVADDR_PHY(p) (p)
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#define DEVADDR_PORT(p) (0x10 + (p))
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#define DEVADDR_SERDES 0x0F
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#define DEVADDR_GLOBAL_1 0x1B
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#define DEVADDR_GLOBAL_2 0x1C
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/* SMI indirection registers for multichip addressing mode */
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#define SMI_CMD_REG 0x00
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@ -182,17 +178,26 @@
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#endif
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/* ID register values for different switch models */
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#define PORT_SWITCH_ID_6020 0x0200
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#define PORT_SWITCH_ID_6070 0x0700
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#define PORT_SWITCH_ID_6071 0x0710
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#define PORT_SWITCH_ID_6096 0x0980
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#define PORT_SWITCH_ID_6097 0x0990
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#define PORT_SWITCH_ID_6172 0x1720
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#define PORT_SWITCH_ID_6176 0x1760
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#define PORT_SWITCH_ID_6220 0x2200
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#define PORT_SWITCH_ID_6240 0x2400
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#define PORT_SWITCH_ID_6250 0x2500
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#define PORT_SWITCH_ID_6352 0x3520
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struct mv88e61xx_phy_priv {
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struct mii_dev *mdio_bus;
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int smi_addr;
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int id;
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int port_count; /* Number of switch ports */
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int port_reg_base; /* Base of the switch port registers */
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u8 global1; /* Offset of Switch Global 1 registers */
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u8 global2; /* Offset of Switch Global 2 registers */
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};
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static inline int smi_cmd(int cmd, int addr, int reg)
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@ -329,11 +334,12 @@ static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
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static int mv88e61xx_phy_wait(struct phy_device *phydev)
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{
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struct mv88e61xx_phy_priv *priv = phydev->priv;
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int val;
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u32 timeout = 100;
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do {
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val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
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val = mv88e61xx_reg_read(phydev, priv->global2,
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GLOBAL2_REG_PHY_CMD);
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if (val >= 0 && (val & SMI_BUSY) == 0)
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return 0;
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@ -347,13 +353,15 @@ static int mv88e61xx_phy_wait(struct phy_device *phydev)
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static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
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int devad, int reg)
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{
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struct mv88e61xx_phy_priv *priv;
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struct phy_device *phydev;
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int res;
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phydev = (struct phy_device *)smi_wrapper->priv;
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priv = phydev->priv;
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/* Issue command to read */
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res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
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res = mv88e61xx_reg_write(phydev, priv->global2,
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GLOBAL2_REG_PHY_CMD,
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smi_cmd_read(dev, reg));
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@ -363,25 +371,27 @@ static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
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return res;
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/* Read retrieved data */
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return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
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return mv88e61xx_reg_read(phydev, priv->global2,
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GLOBAL2_REG_PHY_DATA);
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}
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static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
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int devad, int reg, u16 data)
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{
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struct mv88e61xx_phy_priv *priv;
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struct phy_device *phydev;
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int res;
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phydev = (struct phy_device *)smi_wrapper->priv;
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priv = phydev->priv;
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/* Set the data to write */
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res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
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res = mv88e61xx_reg_write(phydev, priv->global2,
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GLOBAL2_REG_PHY_DATA, data);
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if (res < 0)
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return res;
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/* Issue the write command */
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res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
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res = mv88e61xx_reg_write(phydev, priv->global2,
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GLOBAL2_REG_PHY_CMD,
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smi_cmd_write(dev, reg));
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if (res < 0)
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@ -408,13 +418,18 @@ static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
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static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
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{
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return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
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struct mv88e61xx_phy_priv *priv = phydev->priv;
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return mv88e61xx_reg_read(phydev, priv->port_reg_base + port, reg);
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}
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static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
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u16 val)
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{
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return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
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struct mv88e61xx_phy_priv *priv = phydev->priv;
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return mv88e61xx_reg_write(phydev, priv->port_reg_base + port,
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reg, val);
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}
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static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
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@ -515,12 +530,13 @@ static int mv88e61xx_parse_status(struct phy_device *phydev)
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static int mv88e61xx_switch_reset(struct phy_device *phydev)
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{
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struct mv88e61xx_phy_priv *priv = phydev->priv;
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int time;
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int val;
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u8 port;
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/* Disable all ports */
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for (port = 0; port < PORT_COUNT; port++) {
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for (port = 0; port < priv->port_count; port++) {
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val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
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if (val < 0)
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return val;
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@ -536,19 +552,19 @@ static int mv88e61xx_switch_reset(struct phy_device *phydev)
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udelay(2000);
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/* Reset switch */
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val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
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val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_CTRL);
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if (val < 0)
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return val;
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val |= GLOBAL1_CTRL_SWRESET;
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val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
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GLOBAL1_CTRL, val);
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val = mv88e61xx_reg_write(phydev, priv->global1,
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GLOBAL1_CTRL, val);
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if (val < 0)
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return val;
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/* Wait up to 1 second for switch reset complete */
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for (time = 1000; time; time--) {
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val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
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GLOBAL1_CTRL);
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val = mv88e61xx_reg_read(phydev, priv->global1,
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GLOBAL1_CTRL);
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if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
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break;
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udelay(1000);
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@ -732,22 +748,23 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
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static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
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{
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struct mv88e61xx_phy_priv *priv = phydev->priv;
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int val;
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/* Set CPUDest */
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val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
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val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_MON_CTRL);
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if (val < 0)
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return val;
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val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
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GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
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CONFIG_MV88E61XX_CPU_PORT);
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val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
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GLOBAL1_MON_CTRL, val);
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val = mv88e61xx_reg_write(phydev, priv->global1,
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GLOBAL1_MON_CTRL, val);
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if (val < 0)
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return val;
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/* Allow CPU to route to any port */
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val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
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val = PORT_MASK(priv->port_count) & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
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val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
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if (val < 0)
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return val;
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@ -856,6 +873,48 @@ static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
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return 0;
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}
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/*
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* This function is used to pre-configure the required register
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* offsets, so that the indirect register access to the PHY registers
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* is possible. This is necessary to be able to read the PHY ID
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* while driver probing or in get_phy_id(). The globalN register
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* offsets must be initialized correctly for a detected switch,
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* otherwise detection of the PHY ID won't work!
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*/
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static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev)
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{
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struct mv88e61xx_phy_priv *priv = phydev->priv;
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/*
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* Initial 'port_reg_base' value must be an offset of existing
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* port register, then reading the ID should succeed. First, try
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* to read via port registers with device address 0x10 (88E6096
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* and compatible switches).
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*/
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priv->port_reg_base = 0x10;
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priv->id = mv88e61xx_get_switch_id(phydev);
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if (priv->id != 0xfff0) {
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priv->global1 = 0x1B;
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priv->global2 = 0x1C;
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return 0;
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}
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/*
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* Now try via port registers with device address 0x08
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* (88E6020 and compatible switches).
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*/
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priv->port_reg_base = 0x08;
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priv->id = mv88e61xx_get_switch_id(phydev);
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if (priv->id != 0xfff0) {
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priv->global1 = 0x0F;
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priv->global2 = 0x07;
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return 0;
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}
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debug("%s Unknown ID 0x%x\n", __func__, priv->id);
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return -ENODEV;
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}
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static int mv88e61xx_probe(struct phy_device *phydev)
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{
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struct mii_dev *smi_wrapper;
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@ -910,13 +969,43 @@ static int mv88e61xx_probe(struct phy_device *phydev)
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phydev->priv = priv;
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priv->id = mv88e61xx_get_switch_id(phydev);
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res = mv88e61xx_priv_reg_offs_pre_init(phydev);
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if (res < 0)
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return res;
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debug("%s ID 0x%x\n", __func__, priv->id);
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switch (priv->id) {
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case PORT_SWITCH_ID_6096:
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case PORT_SWITCH_ID_6097:
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case PORT_SWITCH_ID_6172:
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case PORT_SWITCH_ID_6176:
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case PORT_SWITCH_ID_6240:
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case PORT_SWITCH_ID_6352:
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priv->port_count = 11;
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break;
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case PORT_SWITCH_ID_6020:
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case PORT_SWITCH_ID_6070:
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case PORT_SWITCH_ID_6071:
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case PORT_SWITCH_ID_6220:
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case PORT_SWITCH_ID_6250:
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priv->port_count = 7;
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break;
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default:
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free(priv);
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return -ENODEV;
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}
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res = mdio_register(smi_wrapper);
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if (res)
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printf("Failed to register SMI bus\n");
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return 0;
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}
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static int mv88e61xx_phy_config(struct phy_device *phydev)
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{
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struct mv88e61xx_phy_priv *priv = phydev->priv;
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int res;
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int i;
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int ret = -1;
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@ -925,7 +1014,7 @@ static int mv88e61xx_phy_config(struct phy_device *phydev)
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if (res < 0)
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return res;
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for (i = 0; i < PORT_COUNT; i++) {
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for (i = 0; i < priv->port_count; i++) {
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if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
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phydev->addr = i;
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@ -988,13 +1077,14 @@ static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
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static int mv88e61xx_phy_startup(struct phy_device *phydev)
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{
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struct mv88e61xx_phy_priv *priv = phydev->priv;
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int i;
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int link = 0;
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int res;
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int speed = phydev->speed;
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int duplex = phydev->duplex;
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for (i = 0; i < PORT_COUNT; i++) {
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for (i = 0; i < priv->port_count; i++) {
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if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
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phydev->addr = i;
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if (!mv88e61xx_phy_is_connected(phydev))
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@ -1068,6 +1158,16 @@ int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
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temp_phy.priv = &temp_priv;
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temp_mii.priv = &temp_phy;
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/*
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* get_phy_id() can be called by framework before mv88e61xx driver
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* probing, in this case the global register offsets are not
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* initialized yet. Do this initialization here before indirect
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* PHY register access.
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*/
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val = mv88e61xx_priv_reg_offs_pre_init(&temp_phy);
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if (val < 0)
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return val;
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val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
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if (val < 0)
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return -EIO;
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