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arm64: zynqmp: Use ethernet-phy as node name for ethernet phys

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Ethernet phys based on devicetree specification should be using
ethernet-phy@ node name instead of pure phy@.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2019-08-08 12:44:22 +02:00
parent 50d9283347
commit 2975a42b42
13 changed files with 13 additions and 13 deletions
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2
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
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@ -58,7 +58,7 @@
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
phy0: phy@0 { /* marwell m88e1512 */
phy0: ethernet-phy@0 { /* marwell m88e1512 */
reg = <0>;
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */

2
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
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@ -89,7 +89,7 @@
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
phy0: phy@0 { /* marwell m88e1512 - SGMII */
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
reg = <0>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};

2
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
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@ -76,7 +76,7 @@
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: phy@0 {
phy0: ethernet-phy@0 {
reg = <0>;
};
};

2
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@ -75,7 +75,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
phy0: ethernet-phy@0 {
reg = <0>;
};
};

2
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View File

@ -85,7 +85,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@5 {
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;

2
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
View File

@ -76,7 +76,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 { /* VSC8211 */
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
};
};

2
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
View File

@ -73,7 +73,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
phy0: ethernet-phy@0 {
reg = <0>;
};
};

2
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -110,7 +110,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@21 {
phy0: ethernet-phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;

2
arch/arm/dts/zynqmp-zcu102-revB.dts
View File

@ -16,7 +16,7 @@
&gem3 {
phy-handle = <&phyc>;
phyc: phy@c {
phyc: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;

2
arch/arm/dts/zynqmp-zcu104-revA.dts
View File

@ -54,7 +54,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@c {
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;

2
arch/arm/dts/zynqmp-zcu104-revC.dts
View File

@ -55,7 +55,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@c {
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;

2
arch/arm/dts/zynqmp-zcu106-revA.dts
View File

@ -110,7 +110,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@c {
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;

2
arch/arm/dts/zynqmp-zcu111-revA.dts
View File

@ -106,7 +106,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@c {
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;