colibri-imx6ull: migrate pinctrl and regulators to dtb/dm
Migrate pinctrl and regulators to device tree resp. driver model: Ethernet, NAND and UART. Drop BOARD_EARLY_INIT_F as it is anyway no longer used. Enable CMD_DM, CMD_MTD, CMD_REGULATOR and DM_REGULATOR_FIXED. While at it also update copyright period. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
This commit is contained in:
Marcel Ziswiler
Stefano Babic
parent
82c99b3e12
commit
cd69e8ef9b
@ -1,8 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Toradex AG
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* Copyright (C) 2018-2019 Toradex AG
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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@ -14,7 +15,6 @@
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/serial_mxc.h>
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#include <fdt_support.h>
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@ -28,25 +28,16 @@
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#include <netdev.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#include "../common/tdx-common.h"
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#include "../common/tdx-cfg-block.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_DSE_48ohm)
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@ -65,13 +56,6 @@ int dram_init(void)
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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#ifdef CONFIG_FSL_ESDHC
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -90,31 +74,12 @@ static iomux_v3_cfg_t const usb_cdet_pads[] = {
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};
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#ifdef CONFIG_NAND_MXS
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static iomux_v3_cfg_t const gpmi_pads[] = {
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MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
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};
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static void setup_gpmi_nand(void)
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{
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imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
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setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
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(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
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}
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#endif
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#endif /* CONFIG_NAND_MXS */
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#ifdef CONFIG_VIDEO_MXS
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static iomux_v3_cfg_t const lcd_pads[] = {
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@ -170,31 +135,6 @@ static int setup_lcd(void)
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}
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#endif
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#ifdef CONFIG_FEC_MXC
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static iomux_v3_cfg_t const fec2_pads[] = {
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MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
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MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
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}
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
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@ -247,20 +187,17 @@ int board_mmc_init(bd_t *bis)
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#endif
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#ifdef CONFIG_FEC_MXC
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static int setup_fec(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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setup_iomux_fec();
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/* provide the PHY clock from the i.MX 6 */
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ret = enable_fec_anatop_clock(1, ENET_50MHZ);
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if (ret)
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return ret;
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/* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */
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/* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
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clrsetbits_le32(&iomuxc_regs->gpr[1],
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IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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@ -277,14 +214,7 @@ int board_phy_config(struct phy_device *phydev)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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#endif /* CONFIG_FEC_MXC */
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int board_init(void)
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{
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@ -15,7 +15,6 @@ CONFIG_VERSION_VARIABLE=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_IMI is not set
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@ -24,9 +23,11 @@ CONFIG_CMD_ASKENV=y
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CONFIG_CRC32_VERIFY=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_DM=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_NAND_TRIMFFS=y
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CONFIG_CMD_NAND_TORTURE=y
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CONFIG_CMD_USB=y
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@ -34,6 +35,7 @@ CONFIG_CMD_USB_SDP=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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CONFIG_CMD_BMP=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx6ull-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
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@ -63,6 +65,7 @@ CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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# CONFIG_SPL_SERIAL_PRESENT is not set
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CONFIG_DM_SERIAL=y
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CONFIG_MXC_UART=y
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