ARM: imx6q_logic: Remove legacy pinmuxing code from board file.
With the OCRAM expanded to 256KB and the SPL_PINCTRL enabled with -u-boot.dtsi entries to include the pinmuxing in SPL, the manual code setting up the pinmux can go away. This patch removes the legacy pinmuxing code from the board file. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
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@ -42,32 +42,6 @@ int dram_init(void)
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart3_pads[] = {
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MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
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}
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static iomux_v3_cfg_t const nand_pads[] = {
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MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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@ -135,7 +109,6 @@ int overwrite_console(void)
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_nand_pins();
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return 0;
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}
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@ -177,36 +150,6 @@ int spl_start_uboot(void)
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}
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#endif
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/* SD interface */
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#define USDHC_PAD_CTRL \
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(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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#ifdef CONFIG_FSL_ESDHC_IMX
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struct fsl_esdhc_cfg usdhc_cfg[] = {
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{USDHC1_BASE_ADDR}, /* SOM */
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{USDHC2_BASE_ADDR} /* Baseboard */
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};
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void board_boot_order(u32 *spl_boot_list)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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@ -236,34 +179,6 @@ void board_boot_order(u32 *spl_boot_list)
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spl_boot_list[2] = BOOT_DEVICE_BOARD;
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}
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int board_mmc_init(bd_t *bis)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned int reg = readl(&psrc->sbmr1) >> 11;
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/*
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* Upon reading BOOT_CFG register the following map is done:
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* Bit 11 and 12 of BOOT_CFG register can determine the current
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* mmc port
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* 0x1 SD1-SOM
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* 0x2 SD2-Baseboard
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*/
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reg &= 0x3; /* Only care about bottom 2 bits */
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switch (reg) {
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case 0:
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SETUP_IOMUX_PADS(usdhc1_pads);
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break;
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case 1:
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SETUP_IOMUX_PADS(usdhc2_pads);
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break;
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}
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return 0;
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}
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#endif
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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