Add basic Xilinx ZynqMP arm64 support.
Serial and SD is supported.
It supports emulation platfrom ep108 and QEMU.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This code was introduced to support the multiple .config
configuration in U-Boot. We do not need it any more.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
With a389531 we now call readl() from this file so add <asm/io.h> so
that we have a prototype for the function.
Signed-off-by: Tom Rini <trini@konsulko.com>
After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.
Such patch formalizes current development status.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Integrate latest validated register settings from Toradex WinCE BSP
4.2 working accross all module versions from early V1.x, V1.2D, V2.2B
to V2.4A.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Specify a CONFIG_BOARD_SIZE_LIMIT of 256 KB in order to avoid
overwriting the factory configuration block located at offset 0x40000
in NOR flash.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
To save more than 20 KB of precious space in NOR flash get rid of the
following configuration options:
CONFIG_CMD_LOADB
CONFIG_CMD_LOADS
CONFIG_SYS_LONGHELP
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Migrate Toradex Colibri PXA270 to use CONFIG_SYS_GENERIC_BOARD.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
I couldn't quite figure out whether or not CONFIG_SYS_ENV_IS_NOWHERE
actually ever worked but nowadays this is called CONFIG_ENV_IS_NOWHERE.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Basically finish what the following commit started a long time ago:
488f5d8790
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
For mx35pdk/woodburn:
Acked-by: Stefano Babic <sbabic@denx.de>
Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs. The line
size is still 128 byte. Thus, the way size is 32KB/64KB for old/new
SoCs.
To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB. It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.
The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The 3CS support card (CONFIG_DCC_MICRO_SUPPORT_CARD) used to be used
very often before, but it is recently getting a minority. Swith to
the 1CS support card (CONFIG_PFC_MICRO_SUPPORT_CARD).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Two support card variants are used with UniPhier reference boards:
- 1 chip select support card (original CPLD)
- 3 chip selects support card (ARIMA-compatible CPLD)
Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously. Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Support xHCI host driver used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Each USB port corresponds to the following IP core:
port0: xHCI (0x65a00000) SS+HS
port1: xHCI (0x65c00000) HS (SS PHY is not implemented)
port2: EHCI (0x5a800100) HS
port3: EHCI (0x5a810100) HS
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
EHCI host controllers have a common register interface.
We may wish to implement a generic EHCI driver someday.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers. We still keep UART platform devices because they might
be useful for SPL.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Deassert the reset signal and provide the clock for STDMAC core.
This is necessary for the USB 2.0 host controllers.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For all the UniPhier SoCs so far, the reset signal of the NAND core
is automatically deasserted after the PLL gets stabled.
(The bit 2 of SC_RSTCTRL is default to one.)
This causes a fatal problem on the NAND controller of PH1-LD4.
For that SoC, the NAND I/O pins are not set up yet at the power-on
reset except the NAND boot mode. As a result, the NAND controller
begins automatic device scanning with wrong I/O pins and finally
hangs up.
Actually, U-Boot dies after printing "NAND:" on the console unless
the boot mode latch detected the NAND boot mode.
To work around this problem, reset the NAND core in SPL for non-NAND
boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is
deasserted again in U-Boot proper. At this time, I/O pins have been
correctly set up, the device scanning should succeed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Split the current clkrst_init() into two functions:
- early_clkrst_init(): called from SPL
Deassert the reset signals of the memory controller and some other
basic cores.
- clkrst_init(): called from main U-boot
Deassert the reset signals that are necessary for the access to
peripherals etc.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
We do not have to set the LCR register every time we change the
baud-rate. We just need to set it up once in the probe function.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11)
is not working correctly. As a side effect, it also modifies MCR
register (offset = 0x10) and results in unexpected behavior.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since commit 0e7368c6c4 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).
This also provides a big cleanup of the L2 cache init code avoiding
some duplication. The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
time) and left resident in iRAM for the kernel to use when bringing
up additional CPUs. It used configure_l2_ctlr() and
configure_l2_actlr() when it detected it was on an A15. This was
needed (despite the L2 cache registers being shared among all A15s)
because we might have been the first man in after the whole A15
cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
time. Strangely this called configure_l2_ctlr() but not
configure_l2_actlr() which was almost certainly wrong. Given that
we'll call both (see next bullet) later in the boot process it
didn't matter for normal boot, but I guess this is how L2 cache
settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
This should happen at boot time (normally in the SPL except for USB
boot where it happens in main U-Boot).
Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time. For resume time we'd get it
anyway when the 2nd A15 core came up.
Let's make this a whole lot simpler. Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.
Intended net effects of this change (other than cleanup):
* Timings go from before:
data: 0 cycle setup, 3 cycles (0x2) latency
tag: 0 cycle setup, 3 cycles (0x2) latency
after:
data: 1 cycle setup, 4 cycles (0x3) latency
tag: 1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.
One note is that we're still relying on luck to keep low_power_start()
working. The compiler is being nice and not storing anything on the
stack.
Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL. The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
(after it has turned the L2 cache off). This is why the functions
are in a header file instead of lowlevel_init.c.
* Have the kernel save the L2 cache settings of the boot CPU and apply
them to all other CPUs. We get a little lucky here because the old
code was using "|=" to modify the registers and all of the bits that
it's setting are also present in the new settings (!). That means
that when the 2nd CPU in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do jump to 0x0 but consider following instructions as a Thumb
instructions which in turn makes them loop inside the iROM code instead of
jumping to power_down_core.
This issue is fixed by replacing the "mov pc" instruction with a "bx"
instruction which switches state along with the jump to make the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switching.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.
Logic of the workaround:
Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value."
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 & 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
it puts pointer to function power_down_core into 0x02020004
and provides DSB and SEV for all cores so that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds "iRAM, CPU state and low power" configs
which are the addresses acting as flag registers.
iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal
to CONFIG_LOWPOWER_EN then it jumps to the address (0x02020000+CPUID*4).
This is a part of iROM logic. Rest other flags are being used at
various places during kernel switching and reset.
They are nowhere documented because they are part programming.
These configs are serving as flags for us because they are
representing the addresses in iRAM which we are using for
storing and extracting CPU Status and GIC status.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.
Such patch formalizes current development status.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
This patch does the following:
1. The function names for encapsulation and decapsulation
were inconsitent in freescale's implementation and cmd_blob file.
This patch corrects the issues.
2. The function protopye is also modified to change the length parameter
from u8 to u32 to allow encapsulation and decapsulation of larger images.
3. Modified the description of km paramter in the command usage for better
readability.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Configure the serial number using the serial# environment variable
during the fastboot bind.
This enables "fastboot devices" to return the serial number for
the attached devices.
Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Acked-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
If the string is copied without NULL termination using strncpy(),
then strncat() on the next line, may concatenate the string after
some stale (or random) data, if the response string was not
zero-initialized.
Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
OUT transactions must be aligned to wMaxPacketSize for each transfer,
or else transfer will not complete successfully. This patch modifies
rx_bytes_expected to return a transfer length that is aligned to
wMaxPacketSize.
Note that the value of wMaxPacketSize and ep->maxpacket may not be
the same value, and it is the value of wMaxPacketSize that should be
used for alignment. wMaxPacketSize is passed depending on the speed of
connection.
Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Add a check for USB cable attached and only enter fastboot when a cable
is attached.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Adds the fastboot erase functionality, to erase a partition
specified by name. The erase is performed based on erase group size,
to avoid erasing other partitions. The start address and the size
is aligned to the erase group size for this.
Currently only supports erasing from eMMC.
Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
This common call can be used for setting proper entities based
on dfu command arguments.
The config: CONFIG_SET_DFU_ALT_INFO, was used only for few configs,
and now it is common.
The board file should implement:
- set_dfu_alt_info() function
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[Test HW: Odroid U3 (Exynos 4412)]
Add "oem format" command to write partition table. This relies on the
env variable partitions to contain the list of partitions as required by
the gpt command.
Note that this does not erase any data other than the partition table.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Steve Rae <srae@broadcom.com>
Add code stub to handle "fastboot oem __" command. As unlock is a common
fastboot command, distinguish that it is not implemented.
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Steve Rae <srae@broadcom.com>
Porter is an entry level development board based on R-Car M2 SoC (R8A7791)
This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, SD, USB Host
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Now this feature works. Let's turn it on by default so we do not
depend on specific tool-chains.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
SuperH is supposed to support the Private Library feature, but it is
actually not working.
If CONFIG_USE_PRIVATE_LIBGCC is enabled, the build fails for the
undefined references to '__sdivsi3_i4i' and '__udivsi3_i4i'.
To fix this error, import missing libraries from Linux 3.19
and adjust them for U-Boot:
- Remove "#include <linux/module.h>" and "EXPORT_SYMBOL(...)"
- Use SPDX-License-Identifier
- Remove white space
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Rename two files to the corresponding file names in Linux.
This helps us find missing libraries in the next commit.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows:
BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1,
the prescaler is 0 due to SCSMR settings, hence n=0
Also SCSCR must be set to use internal or external clock source.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Lager board has two SDHI port as SDHI0 and SDHI2.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Gose board has three SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Koelsch board has three SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Alt board has two SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds drivers model support of serial port to Silk board,
and migrate serial port to drivers model.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds drivers model support of serial port to Alt board,
and migrate serial port to drivers model.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds drivers model support of serial port to Lager board,
and migrate serial port to drivers model.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds drivers model support of serial port to Gose board,
and migrate serial port to drivers model.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds drivers model support of serial port to Koelsch board,
and migrate serial port to drivers model.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal
from the project.
Cc: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal
from the project.
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal
from the project.
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Now CONFIG_SPL_BUILD is not defined in Kconfig, so
"!depends on SPL_BUILD" and "if !SPL_BUILD" are redundant.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL). There were
actually two options, "single .config" and "multiple .config".
After some discussions and thought experiments, I chose the latter,
i.e. to create ".config", "spl/.config", "tpl/.config" for Normal,
SPL, TPL, respectively.
It is true that the "multiple .config" strategy provided us the
maximum flexibility and helped to avoid duplicating CONFIGs among
Normal, SPL, TPL, but I have noticed some fatal problems:
[1] It is impossible to share CONFIG options across the images.
If you change the configuration of Main image, you often have to
adjust some SPL configurations correspondingly. Currently, we
cannot handle the dependencies between them. It means one of the
biggest advantages of Kconfig is lost.
[2] It is too painful to change both ".config" and "spl/.config".
Sunxi guys started to work around this problem by creating a new
configuration target. Commit cbdd9a9737 (sunxi: kconfig: Add
%_felconfig rule to enable FEL build of sunxi platforms.) added
"make *_felconfig" to enable CONFIG_SPL_FEL on both images.
Changing the configuration of multiple images in one command is a
generic demand. The current implementation cannot propose any
good solution about this.
[3] Kconfig files are getting ugly and difficult to understand.
Commit b724bd7d63 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to
Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files.
[4] The build system got more complicated than it should be.
To adjust Linux-originated Kconfig to U-Boot, the helper script
"scripts/multiconfig.sh" was introduced. Writing a complicated
text processor is a shell script sometimes caused problems.
Now I believe the "single .config" will serve us better. With it,
all the problems above would go away. Instead, we will have to add
some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM,
but we will not have much. Anyway, this is what we do now in
scripts/Makefile.spl.
I admit my mistake with my apology and this commit switches to the
single .config configuration.
It is not so difficult to do that:
- Remove unnecessary processings from scripts/multiconfig.sh
This file will remain for a while to support the current defconfig
format. It will be removed after more cleanups are done.
- Adjust some makefiles and Kconfigs
- Add some entries to include/config_uncmd_spl.h and the new file
scripts/Makefile.uncmd_spl. Some CONFIG options that are not
supported on SPL must be disabled because one .config is shared
between SPL and U-Boot proper going forward. I know this is not
a beautiful solution and I think we can do better, but let's see
how much we will have to describe them.
- update doc/README.kconfig
More cleaning up patches will follow this.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present defaults in arch-specific Kconfig files are ignored if the
top-level item comes ahead of it in include order. This means that it is
not possible to have a U-Boot default that architectures and boards can
override. This does not seem very useful.
Move the include earlier to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
It is true that malloc is necessary for Driver Model before
relocation, but there is no good reason to reserve the malloc
space more than enough. The default value 0x400 works well.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit referenced in subject breaks IGEP0032 build with the following
error:
drivers/misc/status_led.c:30:7: error: 'RED_LED_GPIO' undeclared here (not in a function)
scripts/Makefile.build:275: recipe for target 'drivers/misc/status_led.o' failed
make[2]: *** [drivers/misc/status_led.o] Error 1
scripts/Makefile.build:420: recipe for target 'drivers/misc' failed
make[1]: *** [drivers/misc] Error 2
Makefile:1093: recipe for target 'drivers' failed
make: *** [drivers] Error 2
Fix this by skipping the status led on IGEP0032 machine as is not available
and throw an error for future machines if the status led is not configured
to avoid build breakage.
Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
The RCPM FSM may not be reset after power-on, for example,
in the cases of cold boot and wakeup from deep sleep.
It causes cache coherency problem and may block deep sleep.
Therefore, reset them if they are not be reset.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The patch adds Freescale Layerscape PCIe driver and provides
up to 4 controllers support.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins
0x48_00000000. In order to access PCIe device, we must create
TLB to map the 40bit physical address to 32bit virtual address.
This patch will enable MMU after DDR is available and creates MMU
table in DRAM to map all 4G space; then, re-use the reserved space
to map PCIe region. The following the mapping layout.
VA mapping:
------- <---- 0GB
| |
| |
|-------| <---- 0x24000000
|///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
|-------| <---- 0x300000000
| |
|-------| <---- 0x34000000
|///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
|-------| <---- 0x40000000
| |
|-------| <---- 0x80000000 DDR0 space start
|\\\\\\\|
|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
|\\\\\\\|
------- <---- 4GB DDR0 space end
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch is to define default values for some CCSR macros
to make header files cleaner.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from "fsl,dprcr" to "fsl-mc". Print MC version info when
appropriate.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers
stay in sync. DP-DDR has only one controller so it does no harm.
Signed-off-by: York Sun <yorksun@freescale.com>
This patch enusres that right banners are printed for LS2085A
emulator and simulator platforms.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Move the load address of the kernel image to get it away from the
region of the uncompressed kernel.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Since Linux v3.16-rc1 earlyprintk has been removed for arm64.
Switch to using earlycon.
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.
Signed-off-by: York Sun <yorksun@freescale.com>
LS NADK memory manager by default works on HugeTLB. Hence bootargs
must include parameters default_hugepagesz (default hugepagesize,
hugepagesz (hugepage size) and hugepages (number of hugepages to be
reserved in kernel for the given size).
Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.
Signed-off-by: York Sun <yorksun@freescale.com>
On ZeBu emulator, CAS to preamble overrides need to be set to
satisfy the timing. This only impact platforms with CONFIG_EMU.
These should be set before MEM_EN is set.
Signed-off-by: York Sun <yorksun@freescale.com>
This patch adds the fdt-fixup logic for the clock frequency of the
NS16550A related device tree nodes.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS2085A and its variants can have up to four clusters. It is safe
to enable timebase for all even some may be disabled.
Signed-off-by: York Sun <yorksun@freescale.com>
Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flushing is
completed. Timeout is needed for simualtor on which CCN-504 is not
implemented. Return value can be checked for timeout situation.
Change bootm.c to disable dcache instead of simply flushing, required
by flushing L3.
Signed-off-by: York Sun <yorksun@freescale.com>
U-Boot should only add "enable-method" and "cpu-release-address"
properties to the "cpu" node of the online cores.
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
According to hardware implementation, a single outer shareable global
coherence group is defined. Inner shareable has not bee enabled.
Signed-off-by: York Sun <yorksun@freescale.com>
This patch ensures that the TZPC (BP147) and TZASC-400 programming
happens for LS2085A SoC only when the desired config flags are
enabled and ensures that the TZPC programming is done to allow Non-secure
(NS) + secure (S) transactions only for DCGF registers.
The TZASC component is not present on LS2085A-Rev1, so the TZASC-400
config flag is turned OFF for now.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
When booting from USB peripheral boot, the bootrom will not properly deinit the
MUSB controller, which doesn't clearly indicate an USB disconnection to the host
and leaves U-Boot to deal with the state of the previous USB session.
On some host controller drivers (e.g. xhci_hcd), this ends up in a failure
during set address, caused by the lack of proper disconnection notification.
Resetting the controller early in U-Boot notifies the host of the disconnection
and doesn't hurt other use cases.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@ti.com>
The dwc3_set_mode function is used only in
drivers/usb/host/xhci-exynos5.c so make it to static.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Fix bus width switching from 8-bit mode down to 4-bit or 1-bit modes on
Samsung SoCs using SDHCI_QUIRK_USE_WIDE8. These SoCs report controller
version 2.0 yet they support 8-bit bus widths. If 8-bit mode was
previously enabled and then an operation like "mmc dev" caused a switch
back down to 4-bit or 1-bit mode, WIDE8 was left set, causing failures.
This problem was manifested by "mmc dev" timing out.
Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
Depending on the boot priority, the eMMC/SD cards,
can be initialized with the same numbers for each boot.
To be sure which mmc device is SD and which is eMMC,
this info is printed by 'mmc list' command, when
the init is done.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibility to boot from more then one device,
the CONFIG_SYS_MMC_ENV_DEV should always point to right mmc device.
This can be achieved by init boot device as first, so it will be
always registered as mmc 0. Thanks to this, the 'saveenv' command
will work fine for all mmc boot devices.
Exynos based boards usually uses mmc host channels configuration:
- 0, or 0+1 for 8 bit - as a default boot device (usually eMMC)
- 2 for 4bit - as an optional boot device (usually SD card slot)
And usually the boot order is defined by OM pin configuration,
which can be changed in a few ways, eg.
- Odroid U3 - eMMC card insertion -> first boot from eMMC
- Odroid X2/XU3 - boot priority jumper
By this commit, Exynos dwmmc driver will check the OM pin configuration,
and then try to init the boot device and register it as mmc 0.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Akshay Saraswat <akshay.s@samsung.com>
High Capacity (e)MMC cards work fine on sun4i / sun5i, and not having this
capability set causes u-boot to not recognize the eMMC on an Utoo P66 A13
tablet, so always set it thereby fixing this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Clksel value is exynos specific value.
It removed "clksel_val" into dwmci_host and created the
"dwmci_exynos_priv_data" structure for exynos specific data.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
"clksel_val" is assigned to property of mmc or defined value.
But it doesn't write at initial sequence.
There is a reason that get the wrong source-clock value.
This patch fixed it.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
The SD/MMC version scheme was buggy when dealing with standard
major.minor.change cases. Fix it by using something similar to
the linux's kernel versioning method.
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Reported-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Right now U-Boot supports the CONFIG_OLD_SUNXI_KERNEL_COMPAT option,
which makes it go out of its way in limiting the selection of PLL clock
frequencies and PMIC voltages in order not to upset outdated buggy
sunxi-3.4 kernel releases. And if the CONFIG_OLD_SUNXI_KERNEL_COMPAT
option is not set, then booting such old kernels exhibits various
failures at runtime. This is very user unfriendly, and there were
already several incidents when people wasted their time being hit
by these runtime failures and trying to debug them.
The right solution is not to add hacks and workarounds to the mainline
U-Boot, but to fix these bugs in the sunxi-3.4 kernel. And in fact,
the updated sunxi-3.4 kernels already exist. Still we need to follow
the 'Principle of Least Surprise' and U-Boot needs to ensure that
the old buggy kernels are not getting happily booted when the
CONFIG_OLD_SUNXI_KERNEL_COMPAT option is not set. And this patch
addresses this particular issue.
This patch makes U-Boot store the 'compatibility revision' number in
the top 4 bits of the machine id and pass it to the kernel. The old
buggy kernels will fail to load with a very much googlable error
message on the serial console (the "r1 = 0x100010bb" part of it):
"Error: unrecognized/unsupported machine ID (r1 = 0x100010bb)"
This error message can be documented in the linux-sunxi wiki with
proper explanations about how to resolve this situation and where
to get the necessary bugfixes for the sunxi-3.4 kernel.
The fixed sunxi-3.4 kernels implement a revision compatibility check
and clear the top 4 bits of the machine id if everything is alright.
By accepting the machine id with the bits 31:28 set to 1, the sunxi-3.4
kernel effectively certifies that it has the PLL5 clock speed and
AXP209 DCDC3 voltage fixes applied.
It is still possible to set the CONFIG_OLD_SUNXI_KERNEL_COMPAT option
in U-Boot if the user desires to use an outdated unpatched sunxi-3.4
kernel.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
While discussing with some people how to get the Linux kernel to do the
right thing wrt sending output to both the serial console and the
hdmi out / lcd screen when booting on ARM devices, Grant Likely pointed out
that there already is a solution for this.
All we need to do is set the /chosen/stdout-path fdt property, and if no
console= arguments were specified on the kernel commandline the kernel
will honor this and add this device as a console (next to the primary
video output on hdmi).
And u-boot already has support for setting this, all we need to do is
define OF_STDOUT_PATH and then everything will just work ootb, without
people needing to meddle with adding console= arguments in extlinux.conf .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Tom Rini <trini@ti.com>
Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
halving the mbus frequency, so set it to 300 MHz ourselves and base the
mbus divider on that.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Sending out 5V when there is a charger connected to the otg port is not a
good idea, so check for this and error out.
Note this commit currently breaks otg support on the q8h tablets, as we need
to do some magic with the pmic there to get vbus info, this is deliberate
(better safe then sorry), fixing this is on my TODO list.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The UTOO P66 is a 6" A13 tablet / lcd ereader. It features a 6" 480x800 ips
lcd screen, 512MB RAM & 4GB emmc.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
High Capacity (e)MMC cards work fine on sun4i / sun5i, and not having this
capability set causes u-boot to not recognize the eMMC on an Utoo P66 A13
tablet, so always set it thereby fixing this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
USB doesn't seem to work yet; the controller detects the on-board Hub/
Ethernet device but can't read the descriptors from it. I haven't
investigated yet.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The bcm2835 and bcm2836 are essentially identical, except:
- The CPU is an ARM1176 v.s. a quad-core Cortex-A7.
- The physical address of many IO controllers has moved.
Rather than introducing a whole new bcm2836 value for $(SOC) or $(ARCH),
update the existing bcm2835 code to handle the minor differences, and
plumb it into the ARMv7 CPU architecture.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
This commit adds $(srctree)/arch/arm/$(machdirs)/include/mach to
the headers search path.
It allows us to replace "#include <asm/arch/foo.h>" with
"#include <mach/foo.h>". As "#include <asm/arch/foo.h>" is still
supported, we can modify each file one by one.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
In U-Boot, SoC-specific headers are placed in
arch/$(ARCH)/include/asm/arch-$(SOC) and a symbolic link to that
directory is created at the early stage of the build process.
Creating and removing a symbolic link during the build is not
preferred. In fact, Linux Kernel did away with include/asm-$(ARCH)
directories a long time time ago.
As for ARM, now it is possible to collect SoC sources into
arch/arm/mach-$(SOC). It is also reasonable to move SoC headers
into arch/arm/mach-$(SOC)/include/mach.
This commit prepares for that.
If the directory arch/$(ARCH)/mach-$(SOC)/include/mach exists,
a symbolic to that directory is created. Otherwise, a symbolic link
to arch/$(ARCH)/include/asm/arch-$(SOC) or arch-$(CPU) is created.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Move
arch/arm/cpu/arm926ejs/kirkwood/* -> arch/arm/mach-kirkwood/*
Note:
Perhaps, can we merge arch/arm/mach-kirkwood and
arch/arm/mvebu-common into arch/arm/mach-mvebu, like Linux?
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
In U-boot, the directory structure, arch/$(ARCH)/cpu/$(CPU)/$(SOC)/
has been adopted except that $(CPU) is missing from some
architectures and $(SOC) is missing from some CPUs.
This structure did not fit very well in some cases.
[1] AT91
AT91 SoC family have been developed across some ARM processor
generations. Generally speaking, some IPs are often re-used in the
same SoC family (same SoC vendor) even when the main processor is
updated. As a result, a SoC-common directory is needed in the upper
level. Currently, AT91 source files are placed as follows:
arch/arm/cpu/arm920t/at91/*
arch/arm/cpu/arm926ejs/at91/*
arch/arm/cpu/armv7/at91/*
arch/arm/cpu/at91-common/*
Once directories are split, the motivation for refactorings across
CPU directories is lost. Some files in arm920t/at91/ and
arm926ejs/at91/ are so similar that they could be merged.
[2] Tegra
Tegra is a little bit special case where different CPUs are used for
SPL and the main U-boot. To obey the arch/$(ARCH)/cpu/$(CPU)/$(SOC)
structure, the source files must be placed across the CPUs,
again SoC-common directory is necessary in the upper level.
Moreover, there are several families in Tegra: Tegra20, Tegra30,
Tegra114, Tegra124. Here again, the tegra-common directory is needed
to contain commonly-used files.
Tegra directories have been sprinkled in the directory structure.
arch/arm/cpu/arm720t/tegra20
arch/arm/cpu/arm720t/tegra30
arch/arm/cpu/arm720t/tegra114
arch/arm/cpu/arm720t/tegra124
arch/arm/cpu/arm720t/tegra-common
arch/arm/cpu/armv7/tegra20
arch/arm/cpu/armv7/tegra30
arch/arm/cpu/armv7/tegra114
arch/arm/cpu/armv7/tegra124
arch/arm/cpu/armv7/tegra-common
arch/arm/cpu/tegra20-common
arch/arm/cpu/tegra30-common
arch/arm/cpu/tegra114-common
arch/arm/cpu/tegra124-common
arch/arm/cpu/tegra-common
As you see, splitting SoC code by the CPU is not going well,
especially for ARM.
Why don't we collect SoC-specific files into a single place?
A good example we can follow is Linux's arch/arm/mach-* structure.
This item was discussed in the following thread:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/188548/
Looks like I got some positive responses and we are almost ready to
start this movement.
This commit prepares arch/arm/Makefile for describing machdirs in it.
After this commit, we can move SoC directory to arch/arm/mach-$(SOC)
in simple steps although some cases such as AT91 and Tegra need more
fixes.
What we generally have to do is:
[1] Move files arch/arm/cpu/$(CPU)/$(SOC)/* to arch/arm/mach-$(SOC)/*
[2] Add machine entry into arch/arm/Makefile
[3] Remove "obj-y += $(SOC)" from arch/arm/cpu/$(CPU)/Makefile
[4] Fix the Kconfig file path in arch/arm/Kconfig
[5] Modify MAINTAINERS if necessary
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The board select menu in arch/arm/Kconfig is still big.
To slim down it, this commit moves AT91 boards to
arch/arm/mach-at91/Kconfig.
Also, consolidate "config SYS_SOC" in each board Kconfig.
The Kconfig files under board/ directory were modified with the
following command:
find board -name Kconfig | xargs sed -i -e '
/config SYS_SOC/ {
N
/default "at91"/ {
N
d
}
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.co>
Add support for the 6" 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and
Aigo M60/M608/M606 tablets.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commits adds support for configuring a a bitbang i2c controller, which
is used on some boards to configure the LCD panel (via i2c).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On some boards there is a gpio to reset the LCD panel, add support for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Since device_unbind() is also defined in device-remove.c,
which is compiled in only in case CONFIG_DM_DEVICE_REMOVE
is defined, protect the device_unbind() prototype with the
same CONFIG_DM_DEVICE_REMOVE check.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add debug UART functions to permit ns16550 to provide an early debug UART.
Try to avoid using the stack so that this can be called from assembler before
a stack is set up (at least on ARM and PowerPC).
Signed-off-by: Simon Glass <sjg@chromium.org>
For the debug UART we need to be able to provide any parameters before
driver model is set up. Add parameters to the low-level access functions
to make this possible.
Signed-off-by: Simon Glass <sjg@chromium.org>
This came up in a discussion on the mailing list here:
https://patchwork.ozlabs.org/patch/384613/
My concerns at the time were:
- it doesn't need to be written in assembler
- it doesn't need to be ARM-specific
This patch provides a possible alternative. It works by allowing any serial
driver to export one init function and provide a putc() function. These
can be used to output debug data before the real serial driver is available.
This implementation does not depend on driver model, and it is possible for
it to operate without a stack on some architectures (e.g. PowerPC, ARM). It
provides the same features as the ARM-specific debug.S but with more UART
and architecture support.
Signed-off-by: Simon Glass <sjg@chromium.org>
Make this option available in Kconfig and clean up the board that uses it.
Note there is also an entry in exynos5-common.h but this affects multiple
boards and should be dropped as part of the Samsung I2C migration to
driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since both I2C and SPI are converted to Kconfig, we can convert cros_ec
to Kconfig for these buses.
LPC will need to wait until driver mode PCI is available.
Signed-off-by: Simon Glass <sjg@chromium.org>
I2C chips do exist that require a write of some multi-byte data to occur in
a single bus transaction (aka atomic transfer), otherwise either the write
does not come into effect at all, or normal operation of internal circuitry
cannot be guaranteed. The current implementation of the 'i2c write' command
(transfer of multiple bytes from a memory buffer) in fact performs a separate
transaction for each byte to be written and thus cannot support such types of
I2C slave devices.
This patch provides an alternative by allowing 'i2c write' to execute the
write transfer of the given number of bytes in a single bus transaction if
the '-s' option is specified as a final command argument. Else the current
re-addressing method is used.
Signed-off-by: Lubomir Popov <l-popov@ti.com>
hs: adapt to CONFIG_DM_I2C
If the i2c driver returns an error status, error out immediately.
Continuing the loop just results in printing error messages
again and again.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
If you want to inspect the control device tree using the fdt command,
the "fdt address -c" command previously unhelpfully printed the phys
memory address of the device tree. That address could not then be used
to set the fdt address for inspection. Changed the resulting print to
one that can be copied directly to the 'fdt address <addr>' command.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Commit 90bac29a76 claims to fix this bug
that was introduced in commit a92fd6577e
but doesn't actually make the change that the commit message describes.
Actually fix the bug this time.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduce arch_reserve_stacks() to tailor gd->start_addr_sp and gd->irq_sp to
the architecture needs.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Before avr32 had an extra storage for stack end to have a nice stack printout
on exception. Remove this extra storage and use generic gd->start_addr_sp
instead.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Prefix mmu.h PAGE_xxx definitions with MMU_ in order to prevent a naming
conflict with other definitions.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
cpu_mmc_init() is required by the init sequence to have a working MMC interface
on avr32. This will not be included in the binary if we omit the avr32 board.c
when building the generic board.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
For example on a raspberry pi the u-boot environment can be
saved in a file on the first VFAT partition.
This example illustrates how to use it with fw_printenv/fw_setenv.
Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
The only LPC3250 board works fine with enabled generic board support,
add CONFIG_SYS_GENERIC_BOARD right into the arch config header.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
This is not used anymore since the procedure was split into a simple
read function and a later alaysis.
The ivm_read_eeprom name is now used for the previous
ivm_simple_read_eeprom function.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This allows to define the ethaddr env variable according to the the IVM
content by reading the IVM in misc_init_r.
Later, when HUSH is available the content read earlier is analyzed to
populate some non env variables.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This allows to define the ethaddr env variable according to the the IVM
content by reading the IVM in misc_init_r.
Later, when HUSH is available the content read earlier is analyzed to
populate some non env variables.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This allows to define the ethaddr env variable according to the the IVM
content by reading the IVM in misc_init_r.
Later, when HUSH is available the content read earlier is analyzed to
populate some non env variables.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This allows to define the ethaddr env variable according to the the IVM
content by reading the IVM in misc_init_r.
Later, when HUSH is available the content read earlier is analyzed to
populate some non env variables.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This allows to first read the IVM content (earlier in the boot sequence)
and define the ethaddr env variable thanks to the ivm_read_eepromi().
Later, the IVM content can be parsed and used to define some hush
variables, when the hush subsystem is available thanks to
ivm_analyze_eeprom().
To avoid the HW read to happen twice, the buffer passed to
ivm_read_eeprom() has to be reused by ivm_analyze_eeprom (and thus
allocated before calling ivm_read_eeprom()).
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
executing "tools/buildman/buildman mpc5xx" drops this warning:
common/spl/spl_nor.c: In function 'spl_nor_load_image':
common/spl/spl_nor.c:26:10: warning: assignment discards 'const' qualifier from pointer target type [enabled by default]
fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
PCI specification allow prefetchable memory to be 32-bit or 64-bit.
PCI express specification states that all memmory bars for prefetchable
memory must be implemented as 64-bit. They all require that 64 bit
prefetchble memory are suported especially when u-boot is ported to
more and more 64bit processors.
Signed-off-by: David Feng <fenghua@phytium.com.cn>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
So that the CONFIG_SPL_FEL option is not needed anymore. And the regular
SPL binary, generated by the default u-boot build, is now also bootable
over USB in the FEL mode. The SPL still can boot from the SD card too.
A bunch of system registers need to be saved/restored in order to ensure
that the IRQ handler still works in the BROM FEL code after getting
control back from the SPL. This is done in the sunxi code instead of
abusing ifdefs in 'start.S'.
The decision whether to load the main u-boot binary from the SD card or
return to the FEL code in the BROM is done at runtime.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[hdegoede@redhat.com: Since we now restore various regs before returning to
the FEL BROM code we can drop the sunxi specific #ifdefs in start.S]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of
creating its own. There are some #ifdefs required in start.S. Future work
will hopefully remove these.
This series is available at u-boot-dm, branch sunxi-working.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Some boards have a special way of loading U-Boot that does not fit with
the existing SPL code. For example sunxi uses an 'FEL' mode where U-Boot
is loaded over USB. Add a CONFIG option and boot mode for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The link register value can be required on some boards (e.g. FEL mode on
sunxi) so use a branch instruction to jump to save_boot_params() instead
of a branch link.
This requires a branch back to save_boot_params_ret so adjust the users
to deal with this. For exynos just drop the function since it doesn't
do anything.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Peripheral mode needs us to signal vusb high to the phy for it to work,
just like the host mode does.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move the dram helper functions to a separate C file, rather then having them
as inline helpers in dram.h. This saves 144 bytes in the .text segment for
sun6i builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Only use CONFIG_SUNXI_MAX_FB_SIZE to reserve memory at the top when relocating
u-boot, and calculate the actual amount of memory necessary when setting up
the video-mode and use only that, freeing up some additional memory for use
by the kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Do not use CONFIG_SYS_MEM_TOP_HIDE for the framebuffer, instead override
board_get_usable_ram_top to make sure that u-boot is not relocated into the
area where we want to use the framebuffer, and patch the devicetree from
sunxi_simplefb_setup() to tell the kernel to not touch the framebuffer.
This makes u-boot properly see the framebuffer as dram, and initalize the
level 2 cache for it, fixing the very slow cfb scrolling problem.
As an added bonus this stops us from reserving the framebuffer when simplefb
is not used because an older kernel is booted, or hdp is used and no hdmi
cable was plugged in, freeing up the memory for kernel use in these cases.
Reported-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The recent changes to config_distro_bootcmd.h require CONFIG_CMD_PART to be
defined, as the default bootcmd now uses the "part" command.
This fixes sunxi boards not booting with v2015.04-rc1.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Commit a93648d197 introduced linker generated
lists for imagetool which is the base for some host tools (mkimage, dumpimage,
et al.). Unfortunately some host tool chains do not support the used type of
linker scripts. Therefore this commit broke these host-tools for them, namely
FreeBSD and Darwin (OS/X).
This commit tries to fix this. In order to have a clean distinction between host
and embedded code space we need to introduce our own linker generated list
instead of re-using the available linker_lists.h provided functionality. So we
copy the implementation used in linux kernel script/mod/file2alias.c which has
the very same problem (cause it is a host tool). This code also comes with an
abstraction for Mach-O binary format used in Darwin systems.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
On Keystone2 devices serdes must be initialized before accessing MDIO bus.
This commit moves the keystone2_net_serdes_setup() from keystone2_eth_open
to keystone2_emac_initialize to meet that requirement.
This also eliminates unnecessary serdes initializatin every time when the
keystone2_eth_open is being called.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Nishanth Menon <nm@ti.com>
KS2 ddr3 initialization uses ddr3_size global variable before u-boot
relocation. Even if the variable is not being used after relocation,
writing to it corrupts relocation table.
This patch removes the global ddr3_size variable and uses local one
instead.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
When EMAC is in the boot order, the boot ROM sets OPP50 and the
MAC clock is set to /2. SPL needs to change it to /5 for Ethernet
to generate the correct txclk. This patch sets it correctly.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This fixes the random crashes seen on DRA72-evm.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The patch c316f577b4 breaks
siemens boards because prefetch mode is not enabled.
I assume it breaks other boards as well that don't use
prefetch.
This patch sets read_buf to nand_read_buf if
NAND_OMAP_GPMC_PREFETCH is not defined.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
CC: Daniel Mack <zonque@gmail.com>
CC: Guido Martínez <guido@vanguardiasur.com.ar>
CC: Tom Rini <trini@ti.com>
CC: Heiko Schocher <hs@denx.de>
The README describes the recovery method which can be used if the NAS box
is not reachable anymore. Addionally, it describes the different boot
scripts.
Signed-off-by: Michael Walle <michael@walle.cc>
An option is provided to avoid using SDL in U-Boot sandbox (and drop
support for the LCD). However the check in the Makefile is too late
and warnings are printed even if NO_SDL=y is given.
Adjust the order to avoid this warning.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
When a command is passed into sandbox using the '-c' argument the
command is run directly. This is most helpful when running tests (such
as test-dm.sh). Previously the exit code was an unused enum. Change it
to be the actual return code from the command so that the script calling
sandbox can know if the command succeeded (tests passed). Also remove
the now completely unused "exit_state" in sandbox.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
When buildman scans a toolchain path, it stops at the
first toolchain found. However, a single path can contains
several toolchains, each with its own prefix.
This patch lets buildman scan all toolchains in the path.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Simon Glass <sjg@chromium.org>
We should read this file to obtain a set of aliases. This reduces the need
to create them in the ~/.patman file.
This feature did exist in some version of patman, and is mentioned in the
help but it did not find its way upstream.
Reported-by: Graeme Russ <gruss@tss-engineering.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This causes an error when trying to build a local branch which has a local
branch as its upstream.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since we have src, div and pre-div mask bits defined corresponding
to peripherals, calculation of clock specific to I2C appears
redundant and confusing. Using clk_bit_info struct we can write
calculations generic to all peripherals which makes code easy to
understand and free from peripheral specific exceptions.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Also, removing dead code of peripheral and SoC specific function
implementations which was used earlier for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Exynos5420 has different registers with other exynos5 SoCs to control
usb device phy, so need separated function to enable exynos5420 usb
device phy.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This needs for special handling of nRESET_OUT line(GPD1-0 gpio) for eMMC
memory to perform complete reboot on Odroid XU3 board.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This needs for special handling of nRESET_OUT line(GPK1-2 gpio) for eMMC
memory to perform complete reboot on Odroid X2/U3 boards.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Some exynos boards require special handling of nRESET_OUT line for eMMC
memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards.
This will support eMMC reset using DT from reset_misc of samsung common
board file.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The most exynos used the "Ratio + 1" as div value.
And value at register is "Ratio".
So if want to set exact value, it needs to subtract one.
Value at register ("Ratio") = div - 1
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
incompatible with ISAv1 (AKA ARCompact).
Significant difference between ISAv2 and v1 is implementation of
interrupt vector table.
In v1 it is implemented in the same way as on many other architectures -
as a special location where user may put whether code executed in place
(if machine word of space is enough) or jump to a full-scale interrupt
handler.
In v2 interrupt table is just an array of adresses of real interrupt
handlers. That requires a separate section for IVT that is not encoded
as code by assembler.
This change adds support for following cores:
* ARC EM6 (simple 32-bit microcontroller without MMU)
* ARC HS36 (advanced 32-bit microcontroller without MMU)
* ARC HS38 (advanced 32-bit microcontroller with MMU)
As a part of ARC HS38 new version of MMU (v4) was introduced.
Also this change adds AXS131 board which is the same DW ARC SDP base board but
with ARC HS38 CPU tile.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we
need to enable SMP bit of Auxiliary Control Register.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
SILK is an entry level development board based on R-Car E2 SoC (R8A7794)
This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, MMC, USB Host
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA
relocation (mostly only GOT) where functions aray are not
updated. This patch is fixing function pointers for DM core
and serial-uclass to ensure that relocated functions are called.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch add DT support for mxc gpio driver.
There are one place using CONFIG_OF_CONTROL macro.
1. The U_BOOT_DEVICES and mxc_plat array are complied out. To DT,
platdata is alloced using calloc, so there is no need to use mxc_plat.
The following situations are tested, and all work fine:
1. with DM, without DT
2. with DM and DT
3. without DM
Since device tree has not been upstreamed, if want to test this patch.
The followings need to be done.
+ pieces of code does not gpio_request when using gpio_direction_xxx and
etc, need to request gpio.
+ move the gpio settings from board_early_init_f to board_init
+ define CONFIG_DM ,CONFIG_DM_GPIO and CONFIG_OF_CONTROL
+ Add device tree file and do related configuration in
`make ARCH=arm menuconfig`
These will be done in future patches by step.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Simon Glass <sjg@chromium.org>
Add a new entry in platdata structure and intialize
bank_index in mxc_plat array.
This new entry can avoid using `plat - mxc_plat` by using
`plat->bank_index`.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Simon Glass <sjg@chromium.org>
With driver model the number of PIO ports is defined by platform data, so
remove it from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
This adds driver model support with this driver. This was tested by Koelsch
board and Gose board.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Acked-by: Simon Glass <sjg@chromium.org>
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Make the driver model I2C API available always, even if driver model
is not enabled. This allows for a 'soft' switch-over, where drivers can
use the new structures in code which is compiled but not yet used. This
makes migration easier in some cases.
Fix up the existing drivers which define their own 'struct i2c_msg'.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
As with i2c_read() and i2c_write(), add a dm_ prefix to the driver model
versions of these functions to avoid conflicts.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Drop the old checksum functions in favour of the new ones.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This also displays the "Board:" line in the bootup text with the
generic board support code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
These additional nodes need to be provided to get U-Boot to boot correctly
on the Canyonlands / Glacier board:
- chosen path to the console-uart
- reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This is necessary, as ppc4xx has the reset vector located at the end
of the U-Boot image. This needs to be flashed to the end of the NOR
flash. Adding the dtb to the main U-Boot image will break booting
on ppc4xx. This patch now embeds the dtb in the U-Boot image instead.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This uses the ns16550 driver but sets up the clock at run-time. It does
not seem to be available in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Define an _end symbol indicating the end of u-boot.bin. Also add some dummy
words into the link script to ensure that u-boot.bin will always extend
that far. There may be a better way of doing this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is required at present for device tree control. The ppc4xx does support
GPIOs but does not seem to have a proper driver. So this file is empty.
Signed-off-by: Simon Glass <sjg@chromium.org>
The canyonlands.h config file works with canyonlands, glacier and arches
boards. Bring in the device tree files for these from Linux 3.17.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new ramboot config for glacier so that it is possible to test U-Boot
loaded over Ethernet instead of using JTAG.
Signed-off-by: Simon Glass <sjg@chromium.org>
Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in
the various board config files. Also simplify the CONFIG_440 check in
config.mk
Signed-off-by: Simon Glass <sjg@chromium.org>
At present on some architectures we set up the following before calling
board_init_f():
- global_data
- stack
- early malloc memory
Adding the code to support early malloc and global data setup to every
arch's assembler start-up is a pain. Also this code is not actually
architecture-specific. We can use common code for all architectures and
with a bit of care we can write this code in C.
Add a new function to deal with this. It should be called after memory
is available, with a pointer to the top of the area that should be used
before relocation. The function will set things up and return the lowest
memory address that it allocated/used. That can then be set as the top
of the stack.
Note that on some archs this function will use the stack, so the stack
pointer should be set to same value as is pased to board_init_f_mem().
A margin of 128 bytes will be left for this stack, so that it is not
overwritten. This means that 64 bytes is wasted by this early call.
This is not strictly necessary on several more modern archs, so we could
remove this at the cost of some arch-dependent code.
With this function there is no-longer any need for the assembler code to
zero global_data or set up the early malloc pointers.
Signed-off-by: Simon Glass <sjg@chromium.org>
All callers of malloc should already do error checking, and may even be able
to continue without the alloc succeeding.
Moreover, common/malloc_simple.c is the only user of .rodata.str1.1 in
common/built-in.o when building the SPL, triggering this gcc bug:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54303
Causing .rodata to grow with e.g. 0xc21 bytes, nullifying all benefits of
using malloc_simple in the first place.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
If no device is connected to I2C bus, the i2c probe command
can take a lot of time for probe each address. This commit
reduces the busy timeout to 10ms for standard and high speed
modes. This doesn't break the transmission an also allow for
properly probe the devices.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Changes v3:
- new commit, after split the next one
Tested-by: Simon Glass <sjg@chromium.org>
Use dev_get_priv() rather than dev_get_platdata() to get correct address of
private data.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Segfaults can occur when a mandatory argument is not provided to
"demo hello" and "demo status". Eg:
=> demo hello
Segmentation fault (core dumped)
Add a check to ensure all required arguments are provided.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use the bootz command to load zImages in case of any new boot scripts. Only
the legacy one will still use bootm. Apart form the fact, that this will
simplify the image generation process, it saves one copy of the kernel
image: Common practice is to generate an uImage with a loading address of
0x8000. This uImage contains a compressed zImage, which will unpack the
kernel image to the beginning of the RAM. But because there is already the
compressed image the uncompressor first relocates the compressed image to a
higher location. The load address is encoded into the uImage which is
generated by the distributions and thus cannot be easily changed. By using
the bootz command we can load the compressed image to a higher memory
address and the decompressor doesn't have to reloacte the image.
Signed-off-by: Michael Walle <michael@walle.cc>
The dtb was loaded at a memory address after the initial ramdisk. Thus a
large ramdisk would overwrite the dtb. Move it to "ramdisk_start - 64k".
64k should be enough for the device tree blob. Also the kernel
documentation arm/Booting suggests to put the dtb before the initial
ramdisk.
Signed-off-by: Michael Walle <michael@walle.cc>
The load addresses for the bootcmd_legacy script were taken from the
original bootloader from Buffalo. But newer kernels are too big and the
uncompressing will overwrite parts of the initial ramdisk. Therefore,
we switch to the load addresses which are also used by the other boot
script.
Signed-off-by: Michael Walle <michael@walle.cc>
The recent changes to config_distro_bootcmd.h require CONFIG_CMD_PART to be
defined, as the default bootcmd not uses the "part" command.
This fixes sunxi boards not booting with v2015.04-rc1.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add linux/compiler-gcc5/h from the kernel sources at:
commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
Author: Steven Noonan <steven@uplinklabs.net>
Date: Sat Oct 25 15:09:42 2014 -0700
compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
lcd_logo() currently performs tasks well beyond just displaying the logo.
It has code which displays splash image, it has logic which determines
when the different display features are displayed, and it is coupled with
the lcd console because it holds the responsibility of returning the
lcd console base address.
Make lcd_logo() just about the logo by:
* Moving splash image display code into a dedicated function
* Moving the logic regarding when various features are displayed to
lcd_clear() (which is arguably not the correct name for housing such
code either, but it is currently the most fitting location code wise)
* Move the responsibility of setting the console base address to
lcd_clear() too.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
The name "bitmap_plot" is misleading because it implies that this is a generic
function capable of dealing with any bitmap, but its implementation only works
with the logo data.
Rename the function to better reflect this.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Reduce the lcd_display_bitmap #ifdef complexity by extracting Atmel-specific
code for setting cmap for bitmap images into a new function lcd_set_cmap().
A default version is implemented with the remainder of the code.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Reduce the bitmap_plot #ifdef complexity by extracting MPC823-specific code for
setting cmap into its own implementation of lcd_logo_set_cmap(), implemented in
mpc8xx_lcd.c. In the MPC823 implementation, ARRAY_SIZE(bmp_logo_palette) is
switched for BMP_LOGO_COLORS to avoid having to include bmp_logo_data.h, which
would cause a compilation error because the logo data and palette arrays would
be defined twice.
This is a step towards cleaning bitmap_plot() of platform-specific code.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Reduce the bitmap_plot #ifdef complexity by extracting Atmel-specific code for
setting cmap into a new function lcd_logo_set_cmap(), which is implemented in
atmel_lcdfb driver and defined as part of common/lcd.c api with a weak dummy
version. In the Atmel implementation, ARRAY_SIZE(bmp_logo_palette) is
switched for BMP_LOGO_COLORS to avoid having to include bmp_logo_data.h, which
would cause a compilation error because the logo data and palette arrays would
be defined twice.
This is a step towards cleaning bitmap_plot() of platform-specific code.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Reduce the amount of platform-specific code in common/lcd.c by moving MPC823
implementation of fb_put_byte() to mpc8xx_lcd.c. Since we must also have a
default implementation for everybody else, make the remainder of the code
into a weak function.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Reduce the amount of platform-specific code in common/lcd.c by moving Atmel
implementation of fb_put_word() to atmel_lcdfb.c. Since we must also have a
default implementation for everybody else, make the remainder of the code
into a weak function.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
configuration_get_cmap() is multiple platform-specific functions stuffed into
one function. Split it into multiple versions, and move each version to the
appropriate driver to reduce the #ifdef complexity.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
common/lcd code is full of platform-specific code and definitions, which
ideally should reside with the respective driver code. Take a step towards that
goal by moving platform-specific structs from lcd.h to their own header files.
The structs for the generic case (the #else for all the platform-specific
cases) is retained in lcd.h as the default case.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Currently by running the following test:
=> setenv bootcmd reset
=> save
=> reset
, we observe a hang after approximately 20-30 minutes of stress reboot test.
Investigation of this issue revealed that when a single DDR chip select is used,
the hang does not happen. It only happens when the two chip selects are active.
MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence":
"The controller must keep the memory lines quiet (except for CK) for the ZQ
calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256
for other ZQCL and 64 for ZQCS)."
According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL:
"Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines.
Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)"
So make sure to activate one chip select at time (CS0 first and then CS1 later),
so that the required JEDEC delay is respected for each chip select.
With this change applied the board has gone through three days of reboot stress
test without any hang.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)
Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a pseudo break-point when booting in JTAG mode
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery.
This patch changes the behaviour of the dropout control of the DC-DC
converter (refer to section 11.12.9 of the mx28 Application Processor
Reference Manual - Document Number: MCIMX28RM, Rev 2, 08/2013) to the
following:
- Always use 4P2 Linear Regulator if CONFIG_SYS_MXS_VDD5V_ONLY is defined
- Switch between 4P2 Linear Regulator and Battery, using whichever has
the highest voltage if CONFIG_SYS_MXS_VDD5V_ONLY isnot set (this is
the same as the pre-patch behaviour)
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Signed-off-by: Damien Gotfroi <dgotfroi@greenwatch.be>
It is difficult to track down fail to boot issues in the mxs SPL.
Implement the following to make it easier:
- Add debug outputs to allow tracing of SPL progress in order to track
where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must
be defined to enable debug output in SPL
- Add TODO comments where it is not clear if the code is doing what it
is meant to be doing, even tough the board boots properly (these comments
refer to existing code, not to any code added by this patch)
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Should use AIPS3 configuration address 0x0227C000 to set AIPS3,
not the AIPS3 base address.
Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with
AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem.
Signed-off-by: Ye.Li <B37916@freescale.com>
Add QuadSPI boot support to imximage tool.
Note: The QuadSPI configuration parameters at offset 0x400 are not
included in this patch. Need other tools to generate the parameters
part.
Signed-off-by: Ye.Li <B37916@freescale.com>
Since a clock function setup_gpmi_io_clk is implemented for GPMI
IO clock settings, change to use this common function in GPMI setup.
Signed-off-by: Ye.Li <B37916@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
"#define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250)"
This macro is for configuring SW1A/B/C Output Voltage easily.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This patch has some parts connected together:
- Use _gd in bss section which is automatically cleared
Location at SPL_MALLOC_END wasn't cleared at all
- Use MALLOC_F_LEN(early alloc) instead of FULL MALLOC
(mem_malloc_init is not called at all)
- Simplify malloc and stack init.
At the end of SPL addr is malloc area and below is stack
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Because it is not compatible with DM where
malloc_base has to be available early and init
has to be done in ASM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Microblaze target supports both OF and !OF cases
and from log is not clear which version is running.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Compile code with -fPIC to get GOT. Do not build SPL
with fPIC because it increasing SPL size for nothing.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Setup gd from ASM to be availalbe for board_init_r.
Setting it up in spl_board_init is too late when
MALLOC is used.
Space for gd is located behind MALLOC area at the end of BRAM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Do not use specific macros for debugging.
Also remove compilation warning:
w+../arch/microblaze/cpu/interrupts.c: In function 'interrupt_handler':
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 2 has type 'void
(*)(void *)' [-Wformat]
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 4 has type 'void
*' [-Wformat]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Do not save registers below r1 stack pointer because
it is not checked by stack undeflow is not able to detect
it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This way we may have very limited set of functions implemented so we
save some space.
Also it allows us to build U-Boot for any ARC core with the same one
toolchain because we don't rely on pre-built libgcc.
For example:
* we may use little-endian toolchain but build U-Boot for ether
endianess
* we may use non-multilibbed uClibc toolchain but build U-Boot for
whatever ARC CPU flavour that current GCC supports
Private libgcc built from generic C implementation contributes only 144
bytes to .text section so we don't see significant degradation of size:
--->8---
$ arc-linux-size u-boot.libgcc-prebuilt
text data bss dec hex filename
222217 24912 214820 461949 70c7d u-boot.libgcc-prebuilt
$ arc-linux-size u-boot.libgcc-private
text data bss dec hex filename
222361 24912 214820 462093 70d0d u-boot.libgcc-private
--->8---
Also I don't notice visible performance degradation compared to
pre-built libgcc (where at least "*div*" functions are had-written in
assembly) on typical operations of downloading 10Mb uImage over TFTP and
bootm.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
As a preparation to ARCv2 port submission we're moving CPU slection
flags to a common location.
Also it will allow us to have more flexible CPU specification, not only
ISA version but CPU family as well checking CONFIG_ARC_CPU_xxx.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Following SPARK ARC now has SYS_MONITOR_BASE setup via Kconfig.
This makes "include/configs/*.h" cleaner and more flexible.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards
so there's no sense in separate per-board definitions.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Currently there's nothing related to really low-level init on ARC so
CONFIG_SKIP_LOWLEVEL_INIT definition makes no sense.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
There're no other options for ARC except "generic board" so ther's no
point to define CONFIG_SYS_GENERIC_BOARD per board.
We now have it set fo all ARC boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.
It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.
It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Now we may select a particular version of ARC700:
* ARC750D or
* ARC770D
It allows more flexible (or more fine tuned) configuration of U-Boot.
Before that change we relied on minimal configuration but now we may
use specific features of each CPU.
Moreover allows us to escape manual selection of options that
exist in both CPUs but may have say different version like MMUv2 in
ARC750D vs MMUv3 in ARC770D.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
With switch to Kconfig we only need very board-specific descriptions in
include/configs.
CPU selection is performed with either defconfig or manually via
menuconfig.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
It's prohibited to put branch instruction in the very end of zero-delay
loop. On execution this causes "Illegal instruction" exception.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
call hw_watchdog_init() also if CONFIG_AT91SAM9_WATCHDOG
is used.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch will save U-Boot environment as a file: uboot.env, in FAT partition
instead of saving it in raw sector of MMC card.
This make us easier to manage the environment file.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
This patch will save U-Boot environment as a file: uboot.env, in FAT partition
instead of in raw sector of MMC card.
This make us easier to manage the environment file.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
This patch will save U-Boot environment as a file: uboot.env, in FAT partition
instead of saving it in raw sector of MMC card.
This make us easier to manage the environment file.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Current the MMC support will enable MCI port A, Which is only exist
for 2mmc board.
So by default we need to disable MMC (port A) support. And only enable
it for 2mmc board. Otherwise, dataflash won't work in at91sam9260ek board
as MMC has confliction with Dataflash in the CLK pin.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Some SoC need to redirect the saic to aic to make the interrupt to
work, here add a weak function to be replaced by real function.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
The SFR (special function registers) can be shared bwteen
sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adoptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This matrix header file can be shared between sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adaptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
We can't use config.h directly as some platforms include headers that
aren't safe to use in normal Linux userland.
Signed-off-by: Tom Rini <trini@ti.com>
Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig
so it looks misaligned. Replace the space with tab to indent.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are two typos in the comment block in bootstage.h, fix them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add some instructions about building U-Boot for Intel Galileo board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Galileo board has a microSD slot which is routed from Quark SoC
SDIO controller. Enable SD/MMC support so that we can use an SD card.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
which is just the same one found in other x86 chipset. Since we
programmed the GPIO register block base address, we should be
able to enable the GPIO support on Intel Galileo board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we have added Quark MRC codes, call MRC in dram_init() so
that DRAM can be initialized on a Quark based board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add standard dt-bindings macros to be used by Intel Quark MRC node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can
decode Intel Quark MRC node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
For some unknown reason, the TSC calibration via PIT does not work on
Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ
to 400 per Quark datasheet in the Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should allow the value of TSC_FREQ_IN_MHZ to be overridden by
the one in arch/cpu/<xxx>/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make the Intel quark/galileo support avaiable in Kconfig and Makefile.
With this patch, we can generate u-boot.rom for Intel galileo board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Add minimum codes to support Intel Quark SoC. DRAM initialization
is not ready yet so a hardcoded gd->ram_size is assigned.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM (CAR) before system memory is available.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to
arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these
macros can be used for pci configuration space access.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
to this network are accomplished by populating the message control
register (MCR), Message Control Register eXtension (MCRX) and the
message data register (MDR).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
device.h for integrated pci devices' bdf on Quark SoC and quark.h for
various memory-mapped and i/o-mapped base addresses within SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.
This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).
Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some information has been gleaned on tools and procedures for porting
U-Boot to different x86 platforms. Add a few notes to start things off.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On some hardware this time can be significant. Add bootstage support for
measuring this. The result can be obtained using 'bootstage report' or
passed on to the Linux via the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The base address is found in a different way and the protection bit is also
in a different place. Otherwise it is very similar.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
While queensbay is the first chip with these settings, others will want to
use them too. Make them common.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This patch fixes the following compilation warning for maxbcm:
Building maxbcm board...
text data bss dec hex filename
160075 6596 38240 204911 3206f ./u-boot
board/maxbcm/maxbcm.c: In function 'reset_phy':
board/maxbcm/maxbcm.c:68:6: warning: unused variable 'reg' [-Wunused-variable]
u16 reg;
^
board/maxbcm/maxbcm.c:66:6: warning: unused variable 'devadr' [-Wunused-variable]
u16 devadr = CONFIG_PHY_BASE_ADDR;
^
Additionally support Spansion SPI NOR flash is added. With larger SPI device
support via the CONFIG_SPI_FLASH_BAR define.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the following serdes/PHY setup code, the Armada-XP support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion. Hopefully other MVEBU SoC's will follow here.
Support for some SoC's has been removed in this version. This is:
MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused.
And its partial and not sufficient for this device in this stage.
So lets remove it to make the code clearer and increase the readability.
MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the
Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.
Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
is B0 and this is the only one that is actively supported in this code
version.
Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
on a custom fixed DDR configuration board (maxbcm).
Note:
This code has undergone many hours of coding-style cleanup and refactoring.
It still is not checkpatch clean though, I'm afraid. As the factoring of the
code has so many levels of indentation that many lines are longer than 80
chars. This might be some task to tackly later on.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This is used on the AXP boards, to pad u-boot.img to the desired offset in
SPI flash (only this boot target supported right now). This offset is
used by the SPL then to load u-boot.img into SDRAM and execute it there.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This build target now includes the SPL binary as the bin_hdr into the
kwb image. Its used on the AXP port with the mainlined DDR training code.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the db-mv784mp-gp eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
With this patchset the Marvell bin_hdr (DDR training) code is intergrated
into mainline U-Boot. We can remove the placeholder file again, which was
only introduced to make U-Boot compile and link again.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Checking if the pointer is NULL would be easier to know the tail
of the boot_device_table[] array.
For clarification, add the /* sentinel */ comment.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The return value of get_boot_mode_sel() is used as the index of
the boot_device_table[] array. Its type should be "int" rather
than "u32".
Use only the iterator "i" for the loop in do_pinmon().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0)
and bit 11 (SCL1/SDA1) of IECTRL register must be set.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
It is true that unused functions are removed from the ELF image
by the compiler's garbage collection but relying on it too much
does not look nice.
Currently, the build is taking more than it should.
Refactor the makefiles to compile only files that are really needed.
CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the
optimization.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since commit 0365ffcc0b (generic-board: show model name in
board_init_f() too), checkboard() is invoked only when
show_board_info() fails to get the model name from Device Tree.
It never happens because UniPhier SoCs now only work with
CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees
have the "model" property.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since commit 0365ffcc0b (generic-board: show model name in
board_init_f() too), the support card information has not been
displayed because check_support_card() is invoked only when
show_board_info() fails to get the model name from Device Tree.
This commit adds misc_init_f() function to call check_support_card()
from there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Now init functions called from board_postclk_init() and dram_init()
are only necessary for SPL.
Move them to spl_board_init() for clean-up.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Currently, I/O pin settings are not necessary for SPL.
The board_early_init_f() seems a suitable place to call pin_init().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The EEPROM chips on UniPhier reference daughter boards expect 2-byte
offset address.
Since 7132b9fd68 (dm: i2c: dts: Support an offset-len device tree
property), I2C sub-nodes can have "u-boot,i2c-offset-len" property.
It is convenient to set the default I2C offset address length in
Device Tree, so that we do not have to set it on the command line.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This EEPROM chip is installed on the expansion board commonly used
on UniPhier platform. To avoid duplicated description, move the
EEPROM node to a separate file and include it from other device tree
sources.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
To boot UniPhier boards with the NAND boot mode, two images
(u-boot-spl.bin and u-boot-dtb.img) must be written at the correct
offset addresses.
TFTP downloading is useful to update such images in the NAND device.
We generally do:
=> nand erase 0 0x100000
=> tftpboot u-boot-spl.bin
=> nand write $loadaddr 0 0x10000
=> tftpboot u-boot-dtb.img
=> nand write $loadaddr 0x10000 0xf0000
It is a tedious and error-prone operation.
This commit provides the shorthand:
=> run nandupdate
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This dummy header was introduced by commit 630bf80ebb (ARM:
UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL).
Thanks to commit a08d643dbd (dm: Drop gpio.h header from
fdtdec.c), such an ugly workaround is no longer needed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For now this code seems to be the same for all FSP platforms. Make it
common until we see what differences are required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
to two API functions which use that convention. UPD_TERMINATOR is common
so move it into a common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Since we must run a PCI BIOS ROM, and this can take a calamitous amount of
time, measure it using bootstage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If the BIOS emulator is not available, allow use of native execution if
available, and vice versa. This can be controlled by the caller.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Rather than requiring the Makefile to be modified, provide a build option to
enable the ROM to be built.
We cannot do this by default since it requires binary blobs. Without these
the build will fail.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver which locates the available XHCI controllers on the PCI bus
and makes them available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There is an existing function prototype in the header file but it is not
implemented. Implement something similar.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sometimes microcode is delivered as a header file. Allow the tool to
support this as well as collecting multiple microcode blocks into a
single update.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This results in a much more readable callgraph, because now they
can't be confused with the function having exactly the same name
in the generic mmc code.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In addition to the current Android magic settings, allow to optionally use
DDR3 timing parameters, which are tailored for different clock frequencies
and JEDEC speed bins. This should improve reliability and performance.
Adding '+S:CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H=y' to the board defconfig
allows to use timings, which are calculated for the DDR3-1066F speed bin.
A lot of DDR3 chips, which are used in real Allwinner based devices,
support DDR3-1066F speed bin timings.
And adding '+S:CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y' should work
with any DDR3 chips, because this targets the slowest JEDEC speed bins.
The vendor magic values are still used by default for DRAM, but board
maintainers now have more flexibility in DRAM timings selection.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an
unstable image when active low v or hsync is used.
The problem seems to be specific to the OLinuxIno A13 (normal & micro)
boards. I've just looked up the schematics and they use an opendrain driver
for the vga sync lines, and with sync pulses it is the logical high->low
edge of the pulse which counts for the timing, which with an active low
sync is being driven by the pull-up, and that simply seems to not drive
it hard enough to get a stable image.
So force v and hsync active high on these boards. independent of what the
modeline says. This fixes the unstable image.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers;
it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro
USB socket for OTG and another for power in, HDMI, SATA, 5V power for
SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a
MIPI camera connector.
Like the BananaPi, this board needs GMAC_TX_DELAY set to 3 in order for
GMAC to work reliably at gigabit speeds.
For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano
Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
It turns out that the device_mode_data is rsb specific, rather then slave
specific, so integrate the rsb_set_device_mode() call into rsb_init().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
CONFIG_TARGET_FOO was only used in board/sunxi/Makefile to select the
dram config for sun5i and sun7i boards and in board/sunxi/gmac.c for some
special handling of the bananapi/bananapro (both sun7i), all sun5i and sun7i
boards have been moved over to using a single dram_sun5i_autoconfig file,
and the tx clk delay handling for the Banana boards now has its own Kconfig.
IOW nothing is using CONFIG_TARGET_FOO anymore, so remove it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
And use this to set the GMAC Transmit Clock Delay Chain value on Banana
boards, rather then keying of CONFIG_TARGET_FOO.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Currently we've separate detailed dram settings for all sun5i boards, this
moves them over to using auto dram configuration so that we can get rid of
all the per board dram_foo.c files.
This has been tested on a A10s-Olinuxino, A13-Olinuxino, A13-OlinuxinoM,
mk802-a10s and r7-tv-dongle board.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We do not need i2c support in the SPL when there is no PMIC (some sun4i
boards), or when the PMIC is not using i2c such as on sun6i and sun8i.
This reduces the SPL size from (e.g.) 21812 to 19260 bytes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add an explanation for how to set up git so that patman can find the alias
file. Fix up the get_maintainers message too.
Reported-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
True commit lines start at column zero. Anything that is indented
is part of the commit message instead. I noticed this by trying to
run buildman with commit e3a4facdfc
as master, which contained a reference to a Linux commit inside
the commit message. ProcessLine saw that as a genuite commit
line, and thus buildman tried to build it, and died with an
exception because that SHA is not present in the U-Boot tree.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
When run with the --dry-run argument patman prints out information
showing what it would do. This information currently doesn't line up
with what patman/git send-email really do. Some basic examples:
- If an email address is addressed via "Series-cc" and "Patch-cc" patman
shows that email address would be CC-ed two times.
- If an email address is addressed via "Series-to" and "Patch-cc" patman
shows that email address would be sent TO and CC-ed.
- If an email address is addressed from a combination of tag aliases,
get_maintainer.pl output, "Series-cc", "Patch-cc", etc patman shows
that the email address would be CC-ed multiple times.
Patman currently does try to send duplicate emails like the --dry-run
output shows, but "git send-email" intelligently removes duplicate
addresses so this patch shouldn't change the non-dry-run functionality.
Change patman's output and email addressing to line up with the
"git send-email" logic. This trims down patman's dry-run output and
prevents confusion about what patman will do when emails are actually
sent.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
It is painful to specify the full path to the device tree with the -d
option. It is normally kept in the same directory as U-Boot, so provide
an option to use this by default.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch adds a phy driver for the Micrel KSZ8895 switch. As the SoC MAC
is directly connected to the switch MAC the link to the switch is always up.
But the KSZ8895 switch can be hardwired in three configuration modes :
- not configurable with eventually an eeprom-stored configuration
- configurable by the mdio/mdc connection (SMI protocol)
- configurable by a SPI connection.
In not configurable mode, the switch starts automatically, but in the
other modes, it must be started programmatically, by writing 1 in
configuration register 1.
We only support the not configurable and mdio/mdc (aka SMI) modes here.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
If the PHY is not recognized don't access phydev (NULL)
and return 0 to signal failure.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
The Juno Development Platform is a physical Versatile Express
device with some differences from the emulated semihosting
models. The main difference is that the system is split in
a SoC and an FPGA where the SoC hosts the serial ports at
totally different adresses.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Versatile Express ARMv8 semihosted FVP platform is still
using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure
some compile-time flags. Get rid of this and create a Kconfig
entry for the FVP model, and a selectable bool for the
semihosting library.
The FVP subboard is now modeled as a target choice so we can
eventually choose between different ARMv8 versatile express
boards (FVP, base model, Juno...) this way. All dependent
symbols are updated to reflect this.
The 64bit Versatile Express board symbols are renamed
VEXPRESS64 so we have some chance to see what is actually
going on. Tested on the FVP fast model.
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add documentation on how to setup a system to use the generic distro
configs and boot commands. This spells out what is needed to make a
system conformant, but does not limit the board to only the defaults.
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
[swarren, added concept, user config, BOOT_TARGET_DEVICES sections.
edited the rest]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Fix this:
drivers/pci/pci_rom.c:95:15: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]
rom_header = (struct pci_rom_header *)rom_address;
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
only tested tested under QEMU with vexpress_ca9x4 ("-M vexpress-a9") and
vexpress_ca15_tc2 ("-M vexpress-a15"). Makes the ugly warning go away.
Signed-off-by: Chris Kuethe <chris.kuethe+github@gmail.com>
Modify $bootcmd_dhcp to read the downloaded script filename from an
environment variable rather than hard-coding it. This allows the user
(or another script) to select a different script name if they want,
without editing the whole value of $bootcmd_dhcp.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/.
The CPU specific config.mk files need to remain until
CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move all au1x00 code out of arch/mips/cpu/mips32 to allow
unification of CPU code in a later patch. The reorganization
of the SoC specific header files will be done in a later patch
series.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle setting the KX bit of the cop0 Status register when the
mips32 start.S is built for mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle mips64 relocations in the mips32 start.S when built for
mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Where the mips32 & mips64 implementations of start.S differ in terms of
access sizes & offsets, use the appropriate macros from asm.h to
abstract those differences away. This is in preparation for sharing a
single copy of start.S between mips32 & mips64.
The exception to this is loads of immediates to be written to the cop0
Config register, which is a 32bit register on mips64 and therefore
constants written to it can be loaded as such.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
These functions are useful in case the board calls them. Also fix a missing
parameter caused by applying the wrong patch (actually I failed to send v2
and applied v1 by mistake).
Signed-off-by: Simon Glass <sjg@chromium.org>
Since U-Boot can support different offset lengths (0-4 bytes), add a device
tree property to specify this. This avoids hard-coding it in the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch enables CONFIG_DM_I2C and also CONFIG_DM_I2C_COMPAT.
The last one should be removed when all the i2c peripheral
drivers will use dm i2c framework.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
This patch enables CONFIG_DM_I2C and also CONFIG_DM_I2C_COMPAT.
The last one should be removed when the dm pmic framework will
be finished.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
This commit adjusts the s3c24x0 driver to new i2c api
based on driver-model. The driver supports standard
and high-speed i2c as previous.
Tested on Trats2, Odroid U3, Arndale, Odroid XU3
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch modify i2c nodes in exynos4.dtsi with:
- adding proper interrupts arrays for each i2c node,
which allows to decode periph id
- add reg address for each i2c node for i2c driver internal use
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
There is no MAX77686 pmic on this board,
so the driver support should be removed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
This patch fixes build error for CONFIG_DM_I2C_COMPAT.
In i2c_get_chip_for_busnum() call, one of argument was missed,
which was offset_len. Now it is set to 'alen' as previous.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently the hash functions used in RSA are called directly from the sha1
and sha256 libraries. Change the RSA checksum library to use the progressive
hash API's registered with struct hash_algo. This will allow the checksum
library to use the hardware accelerated progressive hash API's once available.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Fixed build error in am335x_boneblack_vboot due to duplicate CONFIG_DM)
Change-Id: Ic44279432f88d4e8594c6e94feb1cfcae2443a54
The hash_algo structure has some implementations in which progressive hash
API's are not defined. These are basically the hardware based implementations
of SHA. An API is added to find the algo which has progressive hash API's
defined. This can then be integrated with RSA checksum library which uses
Progressive Hash API's.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Kconfig option added for devices which support RSA Verification.
1. RSA_SOFTWARE_EXP
Enables driver for supporting RSA Modular Exponentiation in Software
2. RSA_FREESCALE_EXP
Enables driver for supporting RSA Modular Exponentiation using Freescale specific
driver
The above drivers use RSA uclass
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Removed duplicate line in Kconfig comment)
Change-Id: I7663c4d5350e2bfc3dfa2696f70ef777d6ccc6f6
Modify rsa_verify to use the rsa driver of DM library .The tools
will continue to use the same RSA sw library.
CONFIG_RSA is now dependent on CONFIG_DM. All configurations which
enable FIT based signatures have been modified to enable CONFIG_DM
by default.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
For the platforms which use,CONFIG_FIT_SIGNATURE, the required configs are
moved to the platform's defconfig file. Selecting CONFIG_FIT_SIGNATURE using
defconfig automatically resolves the dependencies for signature verification.
The RSA library gets automatically selected and user does not have to define
CONFIG_RSA manually.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Add a new rsa uclass for performing modular exponentiation and implement
the software driver basing on this uclass.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
For FIT signature based approach to work, RSA library needs to be selected.
The FIT_SIGNATURE option in Kconfig is modified to automatically select RSA.
Selecting RSA compiles the RSA library required for image verification.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Public exponentiation which is required in rsa verify functionality is
tightly integrated with verification code in rsa_verify.c. The patch
splits the file into twp separating the modular exponentiation.
1. rsa-verify.c
- The file parses device tree keys node to fill a keyprop structure.
The keyprop structure can then be converted to implementation specific
format.
(struct rsa_pub_key for sw implementation)
- The parsed device tree node is then passed to a generic rsa_mod_exp
function.
2. rsa-mod-exp.c
Move the software specific functions related to modular exponentiation
from rsa-verify.c to this file.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
this is an atempt to make the export of functions typesafe.
I replaced the jumptable void ** by a struct (jt_funcs) with function pointers.
The EXPORT_FUNC macro now has 3 fixed parameters and one
variadic parameter
The first is the name of the exported function,
the rest of the parameters are used to format a functionpointer
in the jumptable,
the EXPORT_FUNC macros are expanded three times,
1. to declare the members of the struct
2. to initialize the structmember pointers
3. to call the functions in stubs.c
Signed-off-by: Martin Dorwig <dorwig@tetronik.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(resending to the list since my tweaks are not quite trivial)
I2C is now deprecated on ARM platforms and there are no devices that use it
with the v3 protocol. We can't require v3 support if we want to support I2C.
Adjust the error handling to suit.
Signed-off-by: Simon Glass <sjg@chromium.org>
This has moved to driver model so we don't need the fdtdec support.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
At present we go through various contortions to store the I2C's chip
address in its private data. This only exists when the chip is active so
must be set up when it is probed. Until the device is probed we don't
actually record what address it will appear on.
However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the address when the child is bound,
and avoid the messy contortions.
Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually know what chip select it will appear on.
However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the chip select when the child is bound,
and avoid the messy contortions.
Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we use struct spi_slave as our device pointer in a lot of places
to avoid changing the old SPI API. At some point this will go away.
But for now, it is better if the SPI uclass sets up this pointer, rather
than relying on passing it into the device when it is probed. We can use the
new uclass child_pre_probe() method to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some buses need to set up their devices before they can be used. This setup
may well be common to all buses in a particular uclass. Support a common
pre-probe method for the uclass, called before any bus devices are probed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For buses, after a child is bound, allow the uclass to perform some
processing. This can be used to figure out the address of the child (e.g.
the chip select for SPI slaves) so that it is ready to be probed.
This avoids bus drivers having to repeat the same process, which really
should be done by the uclass, since it is common.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This is common to all SPI drivers and specifies a structure used by the
uclass. It makes more sense to define it in the uclass.
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
In many cases the per-child private data for a device's children is defined
by the uclass rather than the individual driver. For example, a SPI bus
needs to store information about each of its children, but all SPI drivers
store the same information. It makes sense to allow the uclass to define
this data.
If the driver provides a size value for its per-child private data, then use
it. Failng that, fall back to that provided by the uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
At present we try to use the 'reg' property and device tree aliases to give
devices a sequence number. The 'reg' property is often actually a memory
address, so the sequence numbers thus-obtained are not useful. It would be
better if the devices were just sequentially numbered in that case. In fact
neither I2C nor SPI use this feature, so drop it.
Some devices need us to look up an alias to number them within the uclass.
Add a flag to control this, so it is not done unless it is needed.
Adjust the tests to test this new behaviour.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Allow parent drivers to be called when a new child is bound to them. This
allows a bus to set up information it needs for that child.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
In many cases the child platform data for a device's children is defined by
the uclass rather than the individual devices. For example, a SPI bus needs
to know the chip select and speed for each of its children. It makes sense
to allow this information to be defined the SPI uclass rather than each
individual driver.
If the device provides a size value for its child platdata, then use it.
Failng that, fall back to that provided by the uclass.
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
For buses it is common for parents to need to know the address of the child
on the bus, the bus speed to use for that child, and other information. This
can be provided in platform data attached to each child.
Add driver model support for this, including auto-allocation which can be
requested using a new property to specify the size of the data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
When using allocated platform data, allocate it when we bind the device.
This makes it possible to fill in this information before the device is
probed.
This fits with the platform data model (when not using device tree),
since platform data exists at bind-time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Make the error handling more standard to make it easier to build on top of
it. Also correct a bug in the error path where there is no parent.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The root device corresponds to the root device tree node, so set this up.
Also add a few notes to the documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than assuming that the chip offset length is 1, allow it to be
provided. This allows chips that don't use the default offset length to
be used (at present they are only supported by the command line 'i2c'
command which sets the offset length explicitly).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
For boards which use multiple I2C devices, or for SOCs which support
multiple boards, we might want to convert these to driver model at different
times. At present this is difficult because we need to either use
CONFIG_DM_I2C for a board or not.
Add a compatibility layer which implements the old API, thus allowing a
board to move to driver model for I2C without requiring that everything it
uses is moved in the same commit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a dm_ prefix to driver model I2C functions so that we can keep the old
ones around.
This is a little unfortunate, but on reflection it is too difficult to
change the API. We can undo this rename when most boards and drivers are
converted to use driver model for I2C.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that we support device tree GPIO bindings directly in the driver model
GPIO uclass we can remove these functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
U-Boot now supports using GPIOs using bank phandles instead of global
numbers. Update the exynos device tree files to use this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
This deals with the polarity bit. It also changes the GPIO devices so that
the correct device tree node is linked to each one. This allows us to use
the new uclass phandle functionality to implement a proper GPIO binding.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new 'demo light' command which uses GPIOs to control imaginary lights.
Each light is assigned a bit number in the overall value. This provides an
example driver for using the new GPIO API.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a deprecation notice to each function so that it is more obvious that we
are moving GPIOs to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present U-Boot sort-of supports the standard way of reading GPIOs from
device tree nodes, but the support is incomplete, a bit clunky and only
works for GPIO bindings where #gpio-cells is 2.
Add new functions to request GPIOs, taking full account of the device
tree binding. These permit requesting a GPIO with a simple call like:
gpio_request_by_name(dev, "cd-gpios", 0, &desc, GPIOD_IS_IN);
This will request the GPIO, looking at the device's node which might be
this, for example:
cd-gpios = <&gpio TEGRA_GPIO(B, 3) GPIO_ACTIVE_LOW>;
The GPIO will be set to input mode in this case and polarity will be
honoured by the GPIO calls.
It is also possible to request and free a list of GPIOs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Only the GPIO driver knows about the full GPIO device tree binding used by
a device. Add a method to allow the driver to provide this information to the
uclass, including the GPIO offset within the device and flags such as the
polarity.
Signed-off-by: Simon Glass <sjg@chromium.org>
So far driver model's GPIO uclass just implements the existing GPIO API.
This has some limitations:
- it requires manual device tree munging to support GPIOs in device tree
(fdtdec_get_gpio() and friends)
- it does not understand polarity
- it is somewhat slower since we must scan for the GPIO device each time
- Global GPIO numbering can change if other GPIO drivers are probed
- it requires extra steps to set the GPIO direction and value
The new functions have a dm_ prefix where necessary to avoid name conflicts
but we can remove that when it is no-longer needed. The new struct gpio_desc
holds all required information about the GPIO. For now this is intended to
be stored by the client requesting the GPIO, but in future it might be
brought into the uclass in some way.
With these changes the old GPIO API still works, and uses the driver model
API underneath.
Signed-off-by: Simon Glass <sjg@chromium.org>
For GPIOs and other functions we want to look up a phandle and then decode
a list of arguments for that phandle. Each phandle can have a different
number of arguments, specified by a property in the target node. This is
the "#gpio-cells" property for GPIOs.
Add a function to provide this feature, taken modified from Linux 3.18.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the tegra GPIO driver does not fully support the existing device
tree binding, but add the binding file to cover the existing partial support.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the exynos GPIO driver does not fully support the existing device
tree binding, but add the binding file to cover the existing partial support.
Signed-off-by: Simon Glass <sjg@chromium.org>
The common/board_r.c has show_model_r() to display the model name
if the DTB has a "model" property. It sounds useful to have a similar
function in common/board_f.c too because most of the boards show
their board name before relocation.
Instead of implementing the same function in both common/board_f.c
and common/board_r.c, let's split it up into common/show_board_info.c.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds on-chip I2C driver used on newer SoCs of Panasonic
UniPhier platform.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Fake option is enabled only when CONFIG_TRACE is
enabled in common/bootm.c:do_boot_states().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
default_image.c and socfpgaimage.c are the only image modules that print error
messages during header verification. The verify_header() is used to query if a
given image file is processed by the image format. Thus, if the image format
can't handle the file, it must simply return an error. Otherwise we pollute the
screen with errors messages until we find the image format that handle a given
image file.
Signed-off-by: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
The dumpimage is able to extract components contained in a FIT image:
$ ./dumpimage -T flat_dt -i CONTAINER.ITB -p INDEX FILE
The CONTAINER.ITB is a regular FIT container file. The INDEX is the poisition
of the sub-image to be retrieved, and FILE is the file (path+name) to save the
extracted sub-image.
For example, given the following kernel.its to build a kernel.itb:
/dts-v1/;
/ {
...
images {
kernel@1 {
description = "Kernel 2.6.32-34";
data = /incbin/("/boot/vmlinuz-2.6.32-34-generic");
type = "kernel";
arch = "ppc";
os = "linux";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
hash@1 {
algo = "md5";
};
};
...
};
...
};
The dumpimage can extract the 'kernel@1' node through the following command:
$ ./dumpimage -T flat_dt -i kernel.itb -p 0 kernel
Extracted:
Image 0 (kernel@1)
Description: Kernel 2.6.32-34
Created: Wed Oct 22 15:50:26 2014
Type: Kernel Image
Compression: gzip compressed
Data Size: 4040128 Bytes = 3945.44 kB = 3.85 MB
Architecture: PowerPC
OS: Linux
Load Address: 0x00000000
Entry Point: 0x00000000
Hash algo: md5
Hash value: 22352ad39bdc03e2e50f9cc28c1c3652
Which results in the file 'kernel' being exactly the same as '/boot/vmlinuz-2.6.32-34-generic'.
Signed-off-by: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
Some image types, like "KeyStone GP", do not have magic numbers to
distinguish them from other image types. Thus, the automatic image
type discovery does not work correctly.
This patch also fix some integer type mismatches.
Signed-off-by: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
The registration was introduced in commit f86ed6a8d5
This commit also removes all registration functions, and the member "next"
from image_type_params struct
Signed-off-by: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
Move the image_save_datafile() function from an U-Multi specific file
(default_image.c) to a file common to all image types (image.c). And rename it
to genimg_save_datafile(), to make clear it is useful for any image type.
Signed-off-by: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
The get_type() and verify_print_header() functions have the
same code on both dumpimage.c and mkimage.c modules.
Signed-off-by: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
According to fit_image_print(), the "os" property from "image" node is required
also when "type=ramdisk".
Signed-off-by: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
Move the bootcmd commands into a seperate distro_bootcmd environment
variable. Allowing a user to easily launch the distro boot sequence if
the default bootcmd did not default to distro boot commands.
Also set CONFIG_BOOTCOMMAND to "run distro_bootcmd" if it hasn't been
configured yet rather then putting it directly in the environment. This
allows boards to make the distro boot commands available without
necessarily default to them or to use them as a fallback after running
some board specific commands instead.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Not all devices use the convention that the boot scripts are on the
first partition. For example on chromebooks it seems common for the
first two partitions to be ChromeOS kernel partitions.
So instead of just the first partition scan all partitions on a device
with a filesystem u-boot can recognize.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Add an optional third argument to the "part list" command which puts a
space seperated list of valid partitions into the given environment
variable. This is useful for allowing boot scripts to iterate of all
partitions of a device.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
New command to determine the filesystem type of a given partition.
Optionally stores the filesystem type in a environment variable.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
- use linux display timing settings
- change backlight duty cycle 500ns
- some defaultenvironment changes
- change fit_addr_r to 0x14000000 as needed if
MAX_LOCKDEP_SUBCLASSES in linux gets increased.
- Environment now at 0xd0000 in nand flash
Signed-off-by: Heiko Schocher <hs@denx.de>
Use the STATUS_LED APIs for indicating a boot progress instead of
show_boot_progress.
This patch also fixes a problem introduced with commit b3f4ca1135 (dm: omap3:
Move to driver model for GPIO and serial). After that commit the board doesn't
boot. Looks like the problem is the gpio_request call inside the function
show_boot_progress.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
In f0c3a6c we stopped setting gd in board_init_f, but later had to
revert to due problems on certain platforms. As davinci does not look
to have these problems, we can drop the setting here and rely upon
crt0.S to do it.
Cc: Peter Howard <pjh@northern-ridge.com.au>
Signed-off-by: Tom Rini <trini@ti.com>
Generic board with #define CONFIG_SYS_GENERIC_BOARD is working fine.
There is no visible difference between legacy and generic board code.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by a number of
corresponding PMIC OTP versions.
This patch implements correct operation of the core voltages
scaling routine by ensuring that each SMPS that is supplying
more than one domain shall be written only once, and with the
highest voltage of those fused in the SoC (or of those defined
in the corresponding header if fuse read is disabled or fails)
for the power rails belonging to the group.
The patch also replaces some PMIC-related magic numbers with
the appropriate definitions. The default OPP_NOM voltages for
the DRA7xx SoCs are updated as well, per the latest DMs.
Signed-off-by: Lubomir Popov <l-popov@ti.com>
Move board/compulab/common/splash.c code to
common/splash_source.c to make it available for everybody. This move
renames cl_splash_screen_prepare() to splash_source_load(), and
the compilation of this code is conditional on CONFIG_SPLASH_SOURCE.
splash_source features:
* Provide a standardized way for declaring board specific splash screen
locations
* Provide existing routines for auto loading the splash image from the
locations as declared by the board
* Introduce the "splashsource" environment variable, which makes it
possible to select the splash image source.
cm-t35 and cm-fx6 are updated to use the modified version.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Add support for splash screen.
The splash screen is loaded from the SPI flash and is displayed on the
HDMI display.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
[grinberg@compulab.co.il: minor code and commit message updates]
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Add support for loading splash from sf.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
[grinberg@compulab.co.il: staticize the sf global variable]
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Define a generic way for boards to define splash image locations:
- introduce struct splash_location
- introduce enum splash_storage
- update cl_splash_screen_prepare() to take an array of above struct
and select the appropriate one based on the splashsource environment
variable (if it is not defined- use the first splash location as default).
cm-t35 is updated to work with the new interface.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Move storage device specific code into its own function instead of
calling it directly from an otherwise storage device independent
function (cl_splash_screen_prepare).
This is a preparation for supporting multiple splash locations.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
When passing eth address to Linux via dtb, the "local-mac-address"
property should be set for "/soc/aips-bus@02100000/ethernet@02188000",
not "/fec".
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Expand boot sequence to the following order:
1) mmc boot: mmc boot script, then mmc bootm, then mmc bootz.
2) usb boot: usb boot script.
3) sata boot: sata boot script, sata bootm, sata bootz.
4) nand boot: nand bootm, then nand bootz.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
The ability to load ELF files is sometimes useful on Malta boards,
particularly for use with small embedded applications. Enable the
loadelf command in the malta config.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The malta board is used for development and thus the shell is interacted
with often. Enable HUSH to make the experience a little more pleasant.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reset isn't instant, so delay to give it a chance. Otherwise we go on
to print a failure message before resetting anyway.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch adds IDE support to the MIPS Malta board. The IDE controller
is enabled after probing the PCI bus and otherwise just makes use of
U-boot generic IDE support.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The mips_init_[id]cache functions are small & only called once from a
single callsite. Inlining them allows mips_cache_reset to avoid having
to bother moving arguments around & leaves it a leaf function which is
thus able to simply keep the return address live in the ra register
throughout, simplifying the code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reduce duplication between reading the configuration of the L1 dcache &
icache by performing both using a macro which calculates the appropriate
line & cache sizes from the coprocessor 0 Config1 register.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The mips32 & mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in
order to reduce duplication. The temporary registers used are shuffled
slightly in order to work for both mips32 & mips64 builds. The RA
register is defined differently to suit mips32 & mips64, but will be
removed by a later commit in the series after further cleanup.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move the more developed mips32 version of the cache maintenance
functions to a common arch/mips/lib/cache.c, in order to reduce
duplication between mips32 & mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
As a step towards unifying the cache maintenance code for mips32 &
mips64 CPUs, stop using ".set <ISA>" directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When not present, simply don't
bother with the .set directives since U-boot always builds with
-march=mips32 or higher anyway.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Enable ubifs_replay_journal during mount_ubifs, which was
disabled before.
This commit fix an issue with unrecoverable ubifs volumes
after power cut.
Therefor the gc.c is imported now from 1860e37 Linux 3.15
hs: added SPDX-License-Identifier for fs/ubifs/gc.c
Signed-off-by: Anton Habegger <anton.habegger@gmail.com>
This commit 904672e (lcd: refactor lcd console stuff into its
own file), which cause lcd console address is not initialized.
This patch initialize the lcd console use the default value,
will be update when splash screen is enabled.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
When build for Atmel related boards which support SPL,
it will generate boot.bin, also clean when it when do
"make clean" operation.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Microblaze currently doesn't use printf in SPL. So this one line was the only
reference to it and resulted in the printf functionality to be pulled in.
Exceeding the 4k size limit. Lets change the printf back to puts so that
Microblaze is fixed again. The only drawback is that the detected boot-device
number will not be printed. But this message alone should be helpful enough
to get an idea where the boot process is broken.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
This commit is a preperation for a subsequent UBIFS commit
which needs atomic_long operations.
Therefor "include/asm-generic/atomic-long.h" is imported
from 1860e37 Linux 3.15
Signed-off-by: Anton Habegger <anton.habegger@gmail.com>
updated the zynq config to support the lthor
download protocol.
This lthor functionality helps us to load linux
images on to DDR/MMC and can boot linux using bootm.
In order to load images the user should run lthor
command run "thor_ram" from u-boot prompt and
then send the images from host using lthor utility.
Define g_dnl_bind_fixup for zynq so that correct vendor
and product ids assigned incase of DFU and lthor.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable DFU functionality in zynq.
This DFU functionality helps us to load linux
images on to DDR and can boot linux using bootm.
In order to load images the user should run dfu
command "dfu 0 ram 0" from u-boot prompt and then
send the images from host.
The malloc size has been increased to match the DFU
buffer requirements.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Dont send always emio value as zero for zynq_gem_initialize
send it based on config.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Based on:
"am335x_evm: Enable CMD_EXT4 and CMD_FS_GENERIC, add bootpart to env"
(sha1: 73a27a84e5)
Fix filesystem specific commands for loading.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Setup half of memory from ram_size for ECC case.
All the time the same board can be configured
with or without ECC. Based on ECC case detection
use half of memory with the same configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added the lowlevel_init to enable the Neon instructions.
Initially the u-boot was causing undefined instruction
exception if loaded through tcl, and working fine if loaded
through FSBL. The exception was causing in convertion formula
of given time to ticks. It was because, the Neon instructions
were disabled and hence causing the undefined exception. In
FSBL case, the FSBL was enabling the Neon instructions. Hence,
added the lowlevel_init to enable the Neon instructions.
Also enable neon instructions for non-xilinx toolchain.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Each board with defines it's own set of values. If we do not define
CONFIG_MVGBE_PORTS we will hit following error:
mvgbe.c: In function 'mvgbe_initialize':
mvgbe.c:700:34: error: 'CONFIG_MVGBE_PORTS' undeclared (first use in this function)
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
This patch fixes above described problem.
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
When diffing through the changes only the relevant changes
should be displayed.
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>
Add deep sleep support on Freescale LS1021QDS platform.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <yorksun@freescale.com>
The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.
Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.
Signed-off-by: Simon Glass <sjg@chromium.org>
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass <sjg@chromium.org>
As a temporary measure before the ICH driver moves over to driver model,
add device tree support to the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
On x86 we use CMOS RAM to read and write some settings. Add basic support
for this, including access to registers 128-255.
Signed-off-by: Simon Glass <sjg@chromium.org>
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move the checksum code out into its own file so it can be used elsewhere.
Also use a new version which supports a length which is not a multiple of
2 and add a new function to add two checksums.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add this to the enum so that we can use the various fdtdec functions. A
later commit will move this driver to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch adds LPUART support for LS1021ATWR board.
For ls1021atwr_nor_lpuart_defconfig, LPUART is used as the console.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds LPUART support for LS1021AQDS board.
For ls1021aqds_nor_lpuart_defconfig, LPUART is used as the console.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
S0 will cause CAAM self test failure. This patch is to enable snooping
for S0 slave interface. These CCI-400 operations are moved to
board_early_init_f() to be initialized earlier. For S4 slave interface,
issuing of snoop requests and DVM message requests are enabled.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Defining variable gic_dist_addr as a globe one prevents some
functions, which use it, from being used before relocation
which is the case in the deep sleep resume process on Freescale
SoC platforms.
Besides, we can always get the GIC base address by calling
get_gicd_base_address() without referring gic_dist_addr.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <yorksun@freescale.com>
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>. As a result, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they
do not support GPIO.
The right fix would be to split the lib/fdtdec.c to remove
dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h>
to support OF_CONTROL for LS102x platform. This dummy header
will be removed after FDT-GPIO stuff is fixed correctly.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
Signed-off-by: York Sun <yorksun@freescale.com>
commit a62e84d7b1 incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
"reg" property should be parsed from the dtb (as was previously the
case).
With this patch i can successfully network boot my jetson tk1
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Various minor code format issues are fixed in start16.S:
- U-boot -> U-Boot
- 32bit -> 32-bit
- Use TAB instead of SPACE to indent
- Move the indention location of the GDT comment block
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Scrolling a line at a time is very slow for reasons that I don't understand.
It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope
with this, scroll 5 lines each time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some machines are very slow to scroll their displays. To cope with this,
support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows
the display to operate at an acceptable speed by scrolling 5 lines at
a time.
This same option is available for LCDs so when these systems are unified
this code can be unified also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Each time U-Boot boots on Intel Crown Bay board, the displayed hard
drive information is wrong. It could be either wrong capacity or just
a 'Capacity: not available' message. After enabling the debug switch,
we can see the scsi inquiry command did not execute successfully.
However, doing a 'scsi scan' in the U-Boot shell does not expose
this issue.
SCSI: Target spinup took 0 ms.
SATA link 1 timeout.
AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
ahci_device_data_io: 0 byte transferred. <--- scsi inquiry fails
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
Device 0: (0:0) Vendor: ATA Prod.: Rev: ?8
Type: Hard Disk
Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512)
Found 1 device(s).
So uninitialized contents on the stack were passed to dev_print() to
display those wrong information.
The symptom were observed on two hard drives (one is Seagate, the
other one is Western Digital). The fix is to make sure the AHCI
interface is not busy by checking the error and status information
from task file register after enabling the port in ahci_port_start()
before proceeding other operations like scsi_scan().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that we have a full VESA driver we may as well use that. We need to
support the VESA layer being set up by early start-up code or by
running a VGA ROM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a driver intended to cope with any VESA-compatible x86 graphics
adapter. It will not support ROMs which use OpenFirmware (Forth) since
there is no support for that in U-Boot. This means that MAC OS cards
will not work.
Signed-off-by: Simon Glass <sjg@chromium.org>
These are quite common and we may as well press on and not be so picky.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We shouldn't assume that the VGA ROM can always be loaded at c0000. This
is only true on x86 machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code is too x86-dependent at present. Correct it so that it can run on
big-endian machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
The CPU info is already logged during boot e.g.
CPU: Allwinner A20 (SUN7I)
so the prompt is just one more thing to change for each new SoC, just makes it
"sunxi#" instead.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
It turns out that there are some panels where the pwm input is not active low,
so make it configurable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
HDMI, SATA, USB and Ethernet appear functional, I've not done extensive tests
of all peripherals though.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently we've separate detailed dram settings for all sun7i boards, this
moves them over to using auto dram configuration so that we can get rid of
all the per board dram_foo.c files.
This has been tested on a A20-Olinuxino-Lime, A20-Olinuxino_MICRO, Bananapi,
Bananapro, Cubieboard2, Cubietruck, Mele_M3 and a Linksprite_pcDuino3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The qt840a is one of the many tv-boxes using the "i12" A20 pcb, but it
populates only one of the 2 places for a 16 bit dram ic, thus reducing
the buswidth to 16 bits, and the amount of ram to 512M, which is why we
had a separate config for it.
This commit switches the generic i12-tvbox_defconfig over to DRAM
autoconfiguration, so that it will work with the qt840a too, and drops the
qt840a specific config, like we've done with other memory-amount specific
configs before.
Tested on a generic i12-tvbox with 32 bit bus-width / 1G RAM, and on a
qt840a with 16 bit bus-width / 512M RAM.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Chuwi V7 is an A10 (sun4i) based tablet with 1G of RAM, 16G of nand flash,
microsd slot, 7" 1024x768 lvds ips panel, mini hdmi out, headphones out,
stereo speakers, front & back camera and usb wifi.
It is clearly marked "CHUWI", "V7" and "Model: CW0825" on the back of the
tablet.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
lcd controller which needs to be initialized over SPI, once that is
done they work like a regular LVDS panel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
lcd controller which needs to be initialized over SPI, once that is
done they work like a regular LVDS panel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined
by <linux/sizes.h> for readability.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only
available bit in this register. There is no effect of the write
access to the other bits.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The assembly directive ".rept ... .endr" allows us to write the
init_page_table much shorter. To make things further simpler,
set the text and stack area as Normal Memory, and the other sections
as Device attribute.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The DDR PHY training function, ddrphy_prepare_training() would not
work if compiled with GCC 4.9.
The struct ddrphy (arch/arm/include/asm/arch-uniphier/ddrphy-regs.h)
is specified with __packed because it represents a hardware register
mapping, but it turned out to cause a problem on GCC 4.9.
If -mno-unaligned-access is specified (yes, it is in
arch/arm/cpu/armv7/config.mk), GCC 4.9 is aware of the
__attribute__((packed)) and generates extra instructions to perform
the memory access in a way that does not cause unaligned access.
(Actually it is not need here because the register base, the first
argument of the ddrphy_prepare_training(), is always given with a
4-byte aligned address.)
Anyway, as a result, readl() / writel() is divided into byte-wise
accesses. The problem is that this hardware only accepts 4-byte
register access. Byte-wise accesses lead to unexpected behavior.
There are some options to avoid this problem.
[1] Remove -mno-unaligned-access
[2] Add __aligned(4) along with __packed to struct ddrphy
[3] Remove __packed from struct ddrphy
[1] solves the problem for ARMv7, but it does not for pre-ARMv6 and
ARMv6-M architectures where -mno-unaligned-access is default.
So, [1] does not seem reasonable in terms of code portability.
Both [2] and [3] work well, but [2] seems too much. All the members
of struct ddrphy have the u32 type. No padding would be inserted
even if __packed is dropped.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Hookup OTG USB controller support and enable the otg controller + USB-keyb
on various tablets.
This allows tablet owners to interact with u-boot without needing to solder
a serial console onto their tablet PCB.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Gemei G9 is an A10 based tablet, with 1G RAM, 16G NAND, 1024x768
IPS LCD display, stereo speakers, 1.3MP front camera and 5 MP
rear camera, 8000mAh battery, GT901 2+1 touchscreen, Bosch BMA250
accelerometer and RTL8188CUS USB wifi. It also has MicroSD slot,
miniHDMI, 1 x MicroUSB OTG port and 1 x MicroUSB host port and
3.5mm headphone jack.
More details are available at: http://linux-sunxi.org/Gemei_G9
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Testing has shown that on sun4i the display backend engine does not have
deep enough fifo-s causing flickering / tearing in full-hd mode due to
fifo underruns. On sun4i use the display frontend engine to do the dma from
memory, as the frontend does have deep enough fifo-s.
As added advantage of this is that it results in much better memory bandwidth
as it reduces the amount of dram bank switches, for more details see:
http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html
Note that this changes the pipeline searched for in the simplefb node, we can
get away with doing this now, since no kernel has yet shipped with simplefb
dtb nodes, and I will make sure to get a simplefb node with the new pipeline
into 3.19 before it ships.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This patch add support for Marsboard A10 board.
The Marsboard A10 is a A10 based development board with 1G RAM, 1G NAND,
micro SD card slot, SATA 2.0 socket, 10/100 ethernet, mini HDMI port,
1 USB OTG port and 2 USB 2.0 ports. Board does not use the AXP209 pmic,
it does not have a pmic at all.
Board also have 2 expansion 70 pin headers.
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Instead of using the internal 'tx_clk' clock source, it is also
possible to use the pixel clock signal from the parallel LCD
interface ('pclk') as the reference clock for PLL.
The 'tx_clk' clock speed may be different on different boards/devices
(the allowed range is 8MHz - 30MHz). Which is not very convenient,
especially considering the need to know the exact 'tx_clk' clock
speed. This clock speed may be difficult to identify without having
device schematics and/or accurate documentation/sources every time.
Using 'pclk' is free from all these problems.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The MSI Primo81 tablet has B079XAN01/LP079X01 7.85" 768x1024 IPS
MIPI display, connected to the parallel LCD interface via SSD2828
bridge chip. The panel has 18-bit color depth and needs dithering,
in spite of having RGB data delivered from A31s to SSD2828 using
24-bit arrangement.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Convert GPIO names from Kconfig strings into pin numbers for
the 'ssd2828_config' struct. Add SSD2828 initialization between
enabling the parallel LCD interface and turning on the backlight.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
SSD2828 can take pixel data coming from a parallel LCD interface
and translate it on the fly into MIPI DSI interface for driving
a MIPI compatible TFT display. SSD2828 is configured over SPI
interface, which may or may not have MISO pin wired up on some
hardware. So a write-only SPI mode also has to be supported.
The SSD2828 support code is implemented as a utility function
and needs to be called from real display drivers, which are
responsible for driving parallel LCD hardware in front of the
video pipeline. The usage instructions are provided as comments
in the header file.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The file, originally named "include/video/mipi_display.h", is taken from
linux 3.18 (commit b2776bf7149bddd1f4161f14f79520f17fc1d71d).
It provides MIPI DSI constants for DCS commands, which are needed to
implement support for SSD2828 in u-boot.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
And also add Kconfig option for selecting ELDO3 voltage. The reason
for having this option is that the Android kernel sets ELDO3 to
1.2V when powering up LCD in the case if 'lcd_if' configuration
variable is set to 6 (LCD_IF_EXT_DSI) in the FEX file. Most likely
to supply power for a SSD2828 chip.
However on the MSI Primo81 tablet, which is using this particular
'lcd_if = 6' setup for LCD, setting the ELDO3 voltage appears to
be unnecessary and it works regardless. Having no schematics of
this tablet, I can only guess that 1.2V is supplied to SSD2828
in some other way.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The mk802_a10s re-uses is the "classic" mk802 case and functionality, but has
an A10s SoC inside rather then the A10, it features 512M or 1G RAM, 4G nand,
a mini-hdmi female connector, USB-A receptacle, mini-usb receptacle (OTG)
and a sdio realtek wifi chip. Unlike the original mk802 it does have a pmic,
the axp152.
For more details see: http://linux-sunxi.org/Semitime_g2
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The mk802ii is a revised version of the mk802 A10 based hdmi tv-stick, it
features 1G RAM, 4G nand, a hdmi male connector, USB-A receptacle, 2 micro
usb receptacles (OTG & power) and USB-wifi, and does come with an axp209 pmic.
For more details see: http://linux-sunxi.org/Rikomagic_mk802ii
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The mk802 is the "classic" Allwinner A10 based hdmi tv-stick, it features
512M or 1G RAM, 4G nand, a mini-hdmi female connector, USB-A receptacle,
mini-usb receptacle (OTG) and USB-wifi. Somewhat unique the mk802 does not
use the AXP209 pmic, it does not have a pmic at all.
For more details see: http://linux-sunxi.org/Rikomagic_mk802
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
CONFIG_TARGET_FOO is only used in board/sunxi/Makefile to select the
dram config for sun5i and sun7i boards and in board/sunxi/gmac.c for some
special handling of the bananapi/bananapro (both sun7i), iow it is not used
at all on any sun4i, sun6i and sun8i boards so lets get rid of it there.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Currently we've separate detailed dram settings for all sun4i boards, this
moves them over to using auto dram configuration so that we can get rid of
all the per board dram_foo.c files.
Tested-by: Hans de Goede <hdegoede@redhat.com> on a A10-OLinuXino-Lime,
Chuwi_V7_CW0825 and ba10_tv_box
Tested-by: Zoltan HERPAI <wigyori@uid0.hu> on a pcduino
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
While working on adding more boards I noticed that we lack a config for
the 512M cubieboard, and that some of the new boards which I want to add also
have 512M and 1G variants, rather then adding 2 defconfig's for all of these,
lets switch the exising boards which have both a 512M and 1024M variant over
to the sun4i dram autoconfig code.
This also drops the foo_RAMSIZE_defconfig variants of boards where we currently
have 2 separate configs already.
Note:
1) The newly introduced CONFIG_DRAM_EMR1 kconfig value is not used with
a value other then its default for now, but we need this to be configurable
to support some new boards with auto dram config.
2) We always set all CONFIG_DRAM_foo values in defconfigs, even if they match
the defaults, this is done to make it more clear what values are used for a
certain board.
This has been tested on a Mele A1000, Mini-X and a Cubieboard, all 1G
variants, the dram autoconfig code has also been tested on a 512M mk802
(a defconfig for the mk802 is added in a later patch).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We do not use the axp209 interrupt, and at least in my mini-x (which does not
have a power button) the pwr-button pin and the irq pin are soldered together,
so if the axp209 keeps it irq asserted too long it will see a 10s pwr-button
press and hard power off the board, disabling the irqs fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The clocks on the A80 are hooked up slightly different, add support for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Wait 1 second for the sdcard to respond, rather then waiting for
0xfffff milliseconds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
going.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a headerfile with all the base addresses from the sun9i blocks.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite
different, so add a wrapper cpu.h which includes the right mach specific
cpu_sun#i.h based on mach, like we already do with clock.h and dram.h .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Which pll-s are available depends on the machine type, move the
clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files
so that we only declare what is actually available. e.g. clock_get_pll5p()
is not available on sun6i / sun8i, and with sun9i we get a completely
different set of plls.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
As the comment says now that we have SPL support this is no longer necessary,
as PLL6 is already setup with the exact same parameters by the SPL.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
To support different ddr3 memory sizes we should start using
imx_ddr_size(..) instead of the define PHYS_SDRAM_SIZE.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
To align with other mx6 boards, change ENV offset from 384KB to
512KB position to fit a larger u-boot image.
Signed-off-by: Ye.Li <B37916@freescale.com>
Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs.
Add a new function mx6sx_dram_iocfg to configure dram io.
Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1
to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1
effects as "mmdc1->entry=value".
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2 recent sunxi changes have removed the usage of lowlevel_init by moving some
code around and then setting CONFIG_SKIP_LOWLEVEL_INIT.
This is problematic for 2 reasons:
1) It does not just stop s_init from being called, it also stops
cpu_init_cp15 from getting called, which is undesirable.
2) We want u-boot.bin to be usable standalone, without SPL, some people e.g.
use an upstream u-boot.bin together with Allwinner's boot0 loader. So
u-boot.bin must (re)initialize the gpios, timer, etc.
This commit restores the lowlevel_init / s_init usage, while keeping the
changes to no longer use the global-data (gd) struct in the SPL.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch configures and initializes the L2 switch on T1040rdb board.
The external L2 switch ports may be connected to PHYs only over
QSGMII, for T1040rdb.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
This patch configures and initializes the L2 switch on T1040QDS board.
The L2 switch ports must be initialized according to the SerDes
protocols.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Freescale's T1040qds board may be configured to have up to
5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports,
2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2),
connected to other two ports from an intergrated
VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link
ports have no PHYs attatched, so they don't have a
corresponding MDIO.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale's T1040qds board may be configured to have up to
5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports,
2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2),
connected to other two ports from an intergrated
VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link
ports have no PHYs attatched, so they don't have a
corresponding MDIO.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch initializes VSC9953 L2 Switch for boards that have
CONFIG_VSC9953 defined in their config file.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Implement MIPS specific setup of the gd_t structure to support
pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified,
a memory area will be reserved after the initial stack area and
the gd->malloc_base pointer will be initialized.
After this patch the new driver model can be used on MIPS.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Support the existing config option CONFIG_SYS_INIT_SP_ADDR on
MIPS. This allows to move the initial stack to other places
than the beginning of RAM.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Conditionally set head-y and lib-y with boolean Kconfig symbols
for selected CPU. This deprecates the usage of the $(CPU) variable.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The common code just needs the C0_COUNT as free running counter,
without the need of writing and checking C0_COMPARE.
The function get_tbclk() is still implemented here instead of changing
all places of CONFIG_SYS_MIPS_TIMER_FREQ to CONFIG_SYS_TIMER_RATE.
The change was tested on a MIPS32 system, but as the MIPS64 code
was/is the same, this should be no problem.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Add the initial code to prepare a flattened device tree for
the kernel like relocating the FDT blob and fixing up the
/chosen and /memory nodes.
The final hand over to the kernel is not yet implemented. After
the community agreed on the MIPS boot interface for device trees,
the corresponding code will be added.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
If the user wants to boot a kernel without legacy environment,
information like memory size, initrd address and size should be
handed over to the kernel in the command line.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move preparation of Linux kernel environment in a separate
function and mark it as legacy. Add a Kconfig option to make
that legacy mode configurable.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move preparation of Linux kernel command line in a separate
function and mark it as legacy. Add a Kconfig option to make
that legacy mode configurable.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch fix the compilation warning
w+../drivers/net/xilinx_ll_temac.c: In function 'll_temac_init':
w+../drivers/net/xilinx_ll_temac.c:235:3: warning: format '%X' expects
argument of type 'unsigned int', but argument 4 has type 'phys_addr_t'
[-Wformat]
introduced by
"net: Declare physical address as phys_addr_t unsigned type"
(sha1: 16ae782722).
Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Show fpga_op->info even if desc->iface_fns is not defined.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This problem is reported by checkpatch.pl
Warnings:
CHECK: extern prototypes should be avoided in .h files
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
For case where CMD_FPGA_LOADMK is enabled and GZIP disable.
Warning log:
common/built-in.o: In function `do_fpga':
/mnt/disk/u-boot/common/cmd_fpga.c:218: undefined reference to `gunzip'
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.
Signed-off-by: Simon Glass <sjg@chromium.org>
The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefano Babic <sbabic@denx.de>
The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.
Signed-off-by: Simon Glass <sjg@chromium.org>
Wider bus widths (larger than default 1 bit) appeared in MMC standard
version 4.0. So, for MMC cards of any earlier version trying to change
the bus width (including ext_csd comparison) does not make any sense.
It may work incorrectly and at least cause unnecessary timeouts.
So, just skip the entire bus width related activity for earlier versions.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Tested-by: Alexey Brodkin <abrodkin@synopsys.com>
If all the commands switching an MMC card to 4- or 8-bit bus width fail,
and the bus width for the controller and the driver is still set
to default 1 bit, there is no need to send one more command to switch
the card to 1-bit bus width. Also, if the card or host controller do not
support wider bus widths, there is no need to send a switch command at all.
However, if one of switch commands succeeds, but the subsequent ext_csd
fields comparison fails, the card should be switched to some other bus width
(next in the list for the loop), or to default 1-bit bus width as a last
resort. That's why it would be incorrect to just remove the 1-bit bus width
case from the list, it should still be processed in some cases.
panto: Minor cosmetic edit removing superfluous parentheses.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Tested-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
This extends the mmcinfo hardware partition info output to show
partitions with write reliability enabled with the "WRREL" string.
If the partition does not have write reliability enabled the "WRREL"
string is omitted; this is analogous to the ehhanced attribute.
Example output:
Device: OMAP SD/MMC
Manufacturer ID: fe
OEM: 14e
Name: MMC16
Tran Speed: 52000000
Rd Block Len: 512
MMC version 4.41
High Capacity: Yes
Capacity: 13.8 GiB
Bus Width: 4-bit
Erase Group Size: 8 MiB
HC WP Group Size: 16 MiB
User Capacity: 13.8 GiB ENH WRREL
User Enhanced Start: 0 Bytes
User Enhanced Size: 512 MiB
Boot Capacity: 16 MiB ENH
RPMB Capacity: 128 KiB ENH
GP1 Capacity: 64 MiB ENH WRREL
GP2 Capacity: 64 MiB ENH WRREL
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
This change extends the mmc hwpartition sub-command to change the
per-partition write reliability settings. It also changes the
syntax used for the enhanced user data area slightly to better
accomodate the write reliability option.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
The eMMC partition write reliability settings are to be set while
partitioning a device, as per the eMMC spec, so changes to these
attributes needs to be done in the hardware partitioning API.
This commit adds such support.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
Adds the mmc hwpartition sub-command to perform eMMC hardware
partitioning on an mmc device. The number of arguments can be
large for a complex partitioning, but as the partitioning has
to be done in one go it is difficult to make it simpler.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
This adds an API to do hardware partitioning on eMMC devices. The
new mmc_hwpart_config() function does the partitioning in one go.
As the different attributes and partitioning options on eMMC may
be interdependent validation has to be done based on the complete
partitioning configuration. The function accepts three modes:
- MMC_HWPART_CONF_CHECK: just validates that the configuration
is valid.
- MMC_HWPART_CONF_SET: validates and sets all the fields in
EXT_CSD but without setting the "partitioning completed" bit,
and thus is reversible.
- MMC_HWPART_CONF_COMPLETE: does everything and is thus not
reversible.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
The mmc_startup() function uses the ext_csd data even if reading it
from the mmc device failed. This bug was introduced in commit
bc897b1d4d. We now bail out if
reading it fails, this should not be a problem as ext_csd was
introduced in MMC 4.0 and this code is conditional on MMC >= 4.0.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
The eMMC spec says that partitioning is only effective after the
PARTITION_SETTING_COMPLETED is set in EXT_CSD (and a power cycle was done,
but that we cannot know). Thus the partition sizes and attributes should
be ignored when that bit is not set, otherwise the various capacities
are not coherent (e.g., the user data capacity will be that of the
unpartitioned device while partition sizes would be non-zero).
Prescence of non-zero partitioning data is nevertheless still used to
activate the high-capacity size definitions (EXT_CSD_ERASE_GROUP_DEF)
as it is necessary to set that to write any of the partitioning fields
in EXT_CSD, so having partitioning data means someone previously
activated that and we should keep it activated.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
This adds the erase group size and high-capacity WP group size to
mmcinfo's output. The erase group size is necessary to properly align
erase requests on eMMC. The high-capacity WP group size is necessary
to properly align partitions on eMMC.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
Read the eMMC high capacity write protect group size at mmc device
initialization. This is useful to correctly partition an eMMC device,
as partitions need to be aligned to this size.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
The erase_grp_size in struct mmc is to be a size in 512-byte sectors
but the code used to compute it for eMMC when EXT_CSD_ERASE_GROUP_DEF is
enabled computed it as bytes, leading to erase sizes and alignment
much larger than what is actually required by the mmc device.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
This adds output to show the eMMC enhanced user data area size and offset
along with the partition sizes in mmcinfo's output.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
This modification reads the size of the eMMC enhanced user data area
upon initialization of an mmc device, it will be used later by
mmcinfo.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
The eMMC spec mandates that the high-capacity group size definitions
should be enabled when the device is partitioned (by setting
ERASE_GROUP_DEF in EXT_CSD). The current test to determine when this is
required misses a few cases. In particular a device may have been
partitioned without setting the enhanced attribute on any partition
or partitioning may be completed without creating any extra partitions.
This change moves the code to set ERASE_GROUP_DEF to after reading
all partition information. It is also enabled when
PARTITIONING_SETTING_COMPLETED is set as it is necessary to enable
ERASE_GROUP_DEF before setting that bit, so it means that the user
previously switched to the high capacity definitions.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
eMMC partitions are defined as of eMMC 4.41, but mmcinfo process
partition info for eMMC >= 4.0, change it to do it for >= 4.41
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
The eMMC spec numbers general purpose partitions starting at 1, but
the mmcinfo output follows the internal numbering which starts at 0.
Make the mmcinfo command output number partitions as in the eMMC
spec to avoid confusion.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
This extends the mmcinfo command's output to show which eMMC partitions
have the enhanced attribute set. Note that the eMMC spec says that
if the enhanced attribute is supported then the boot and RPMB
partitions are of the enhanced type.
The output of mmcinfo becomes:
Device: OMAP SD/MMC
Manufacturer ID: fe
OEM: 14e
Name: MMC16
Tran Speed: 52000000
Rd Block Len: 512
MMC version 4.41
High Capacity: Yes
Capacity: 13.8 GiB
Bus Width: 4-bit
User Capacity: 13.8 GiB ENH
Boot Capacity: 16 MiB ENH
RPMB Capacity: 128 KiB ENH
GP1 Capacity: 64 MiB ENH
GP2 Capacity: 64 MiB ENH
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
There is currently no command that will provide an overview of the hardware
partitions present on an eMMC device, one has to switch to every partition
via "mmc dev" and run mmcinfo for each to get the partition's capacity.
This commit adds a few lines of output to mmcinfo with the sizes of the
present partitions, like this:
Device: OMAP SD/MMC
Manufacturer ID: fe
OEM: 14e
Name: MMC16
Tran Speed: 52000000
Rd Block Len: 512
MMC version 4.41
High Capacity: Yes
Capacity: 13.8 GiB
Bus Width: 4-bit
User Capacity: 13.8 GiB
Boot Capacity: 16 MiB
RPMB Capacity: 128 KiB
GP1 Capacity: 64 MiB
GP2 Capacity: 64 MiB
panto: Minor edit removing superfluous parentheses.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
As sama5d3 xplained support the PMECC. So add the PMECC header for spl
binary. That make ROM loader can use PMECC to avoid error flips in spl
code in nandflash.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
- corvus board fix problems with toshiba nand chips
on the corvus board problems with toshiba chips
Manufacturer ID: 0x98 Chip ID: 0xdc encounterd.
Solve this in the following way:
- set other nand timings
- enable CONFIG_SYS_NAND_READY_PIN
- correct the MACH_TYPE setting
Signed-off-by: Heiko Schocher <hs@denx.de>
if in SPL mode recovery button is pressed, erase also spi flash
from offset 0 to CONFIG_SYS_NAND_U_BOOT_SIZE on the taurus board.
Signed-off-by: Heiko Schocher <hs@denx.de>
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:
{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'
so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.
Signed-off-by: Heiko Schocher <hs@denx.de>
Add support for the NAND Flash chip with page size of 4096+224-bytes OOB area length
For example Micron MT29F4G08 NAND flash device defines a OOB area which is
224 bytes long (oobsize).
Signed-off-by: Alexandre Coffignal <acoffignal@geral.com>
This patch adds the new Barco platinum platform. It currently
includes those two boards:
platinum-titanium
-----------------
This is the same board as the titanium that is already supported in
mainline U-Boot. But its now moved to this new platform to support
multiple "flavors" of imx6 boards in one directory. Its also moved
to support SPL booting. And with this we use the run-time DDR
configuration of this SPL support. The board is equipped with the
Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR
related registers tuples from the imximage.cfg file. As all this
is done in the SPL at run-time.
platinum-picon
--------------
This board is new and based on the MX6DL with 1GiB DDR using the
Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND
chips (each 512MiB).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pieter Ronsijn <pieter.ronsijn@barco.com>
Since commit 1f98e31bc0 ("imx: mx6sxsabresd: Use the pfuze common init
function") board_late_init() became empty, so we can safely remove this unneeded
function.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The Fusion LCD needs the 32bit color depth to properly work; the
default is different on the 3.10.17 kernels and it is better to ensure
it work out of box using proper default color setting.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This patch enables U-Boot to modify the MAC address of the AX88179.
Tested on RECS5250 (similar to Arndale5250)
Signed-off-by: Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
Make construct_urb take an urb and hep parameter, rather then having it always
operate on the file global urb and hep structs. This is a preperation patch
for adding interrupt queue support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
If a transfer / urb times-out, properly remove it from the schedule, rather
then letting it sit on the ep head. This stops the musb code from getting
confused and refusing to queue further transfers after a timeout.
Tested by unplugging a usb-keyboard, replugging it and doing a usb-reset,
before this commit the keyboard would not work after the usb-reset.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit fixes a number of issues with the reset sequence of musb-new
in host mode:
1) Our usb device probe relies on a second device reset being done after the
first descriptors read. Factor the musb reset code into a usb_reset_root_port
function (and add this as an empty define for other controllers), and call
this when a device has no parent.
2) Just like with normal usb controllers there needs to be a delay after
reset, for normal usb controllers, this is handled in hub_port_reset, add a
delay to usb_reset_root_port.
3) Sync the musb reset sequence with the upstream kernel, clear all bits of
power except bits 4-7, and increase the time reset is asserted to 50 ms.
With these fixes an usb keyboard I have now always enumerates properly, where
as earlier it would only enumerare properly once every 5 tries.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
For bulk and ctrl transfers common/usb.c sets udev->status = USB_ST_NOT_PROC,
but it does not do so for interrupt transfers.
musb_uboot.c: submit_urb() however was waiting for USB_ST_NOT_PROC to become 0,
and thus without anyone setting USB_ST_NOT_PROC would exit immediately for
interrupt urbs, returning the urb status of EINPROGRESS as error.
This commit fixes this, thereby also making usb_kbd.c work together with
musb_new and CONFIG_SYS_USB_EVENT_POLL.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
CPU cycle based timeouts are no good, because how long they use depends on
CPU speed. Instead use time based timeouts, and wait one second for a
device connection to show up (per the USB spec), and wait USB_TIMEOUT_MS
for various urbs to complete.
This fixes "usb start" taking for ever when no device is plugged into the
otg port.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This is based on Jussi Kivilinna's work for the linux-sunxi-3.4 kernel to use
the kernels musb driver instead of Allwinners own custom driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Before this commit u-boot would print the following on boot with musb and
no usb device plugged in:
starting USB...
USB0: Port not available.
USB error: all controllers failed lowlevel init
This commit changes this to:
starting USB...
USB0: Port not available.
Which is the correct thing to do since the low-level init went fine.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
When iomuxing is used we must not only deregister the device with stdio.c,
but also remove the reference to the device in the console_devices array
used by console-muxing. Add a call to iomux_doenv to usb_kbd_deregister to
update console_devices, which will drop the reference.
This fixes the console filling with "Failed to enqueue URB to controller"
messages after a "usb stop force", or when the USB keyboard is gone after a
"usb reset".
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently create_int_queue is only implemented by the ehci code, and that
does not honor interrupt intervals, but other drivers which might also want
to implement create_int_queue may honor intervals, so add an interval param.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that "usb start" will only start usb if not already started, we can simply
call "usb start" whenever we (may) need access to usb devices, and it will only
actually scan the bus at the first call.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently we've this magic in include/config_distro_bootcmd.h to avoid
scanning the usb bus multiple times.
And it does not work when also using an usb keyboard because then the
preboot command has already scanned the bus, so we're still scanning it
twice.
This commit makes "usb start" only start usb if it is no already started,
allowing us to remove all the magic for it from include/config_distro_bootcmd.h
and just call it unconditionally.
This also causes "usb start" and "usb reset" to actually do what their
different names suggest, rather then both of them doing exactly the same.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Fix use-before-initialized bug in pxa25x_udc driver.
Function usb_gadget_register_driver calls udc_disable,
and udc_disable calls pullup_off that uses dev->mach->udc_command.
But dev->mach is initialized in usb_gadget_register_driver after
calling udc_disable. This patch fixes the order of initialization.
Signed-off-by: Alex Sadovsky <Nable.MainInbox@googlemail.com>
Without this function the USB compliance test (USB 2.0 Command Verifier) will
fail in the "Interface Descriptor Test" with this error message:
FAIL
(1.2.51) A successful GetInterface request must return the alternate setting
set by a prior call to SetInterface.
Lets add this function to read back the value so that the DFU device fully
passes the USB compliance test.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Enrico Leto <enrico.leto@siemens.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
On the DXR2 board (AM335x using MUSB) the USB compliance test suite
(USB 2.0 Command Verifier) will cause the board to crash and reset
upon the "BOS Descriptor Test - Addressed state". Here the output
from the DRX2 while running this test:
GADGET DRIVER: usb_dnl_dfu
musb-hdrc: peripheral reset irq lost!
composite_setup (776)
data abort
pc : [<87f693ac>] lr : [<87f6911c>]
sp : 86f33a58 ip : 00000000 fp : 86f3bbac
r10: 00000f00 r9 : 86f33ef4 r8 : 86f37da8
r7 : 00000005 r6 : 86f33a90 r5 : 00000000 r4 : 86f37e30
r3 : 00000000 r2 : 00000000 r1 : 87f9c888 r0 : 00000016
Flags: Nzcv IRQs off FIQs on Mode SVC_32
Resetting CPU ...
resetting ...
By adding the case statement for USB_DT_BOS and therefore not running
into the default case (jump to unkown label) this crash is fixed.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Enrico Leto <enrico.leto@siemens.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
This does nothing now, so drop it. We have SPL anyway to do our low-level
init.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The current sunxi implementation uses gdata, which is going away. It also
sets up DRAM before board_init_f() in SPL.
There is really no reason to do much in s_init() since board_init_f() is
called immediately afterwards. The only change is that we need our own
implementation of board_init_f() which sets up DRAM before the BSS (which
is in DRAM) is cleared.
The s_init() code runs once for SPL and again for U-Boot proper. We
shouldn't need to init the clock/timer/gpio/i2c init twice, so just have it
in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
We need to get rid of this SPL-specific setting of the global_data pointer.
It is already set up in start.S immediately before board_init_f() is called,
and there may be information there that is needed (e.g. pre-reloc malloc
info).
Signed-off-by: Simon Glass <sjg@chromium.org>
Prior to this change we set the gd pointer early so that we can store
data in it. This becomes problematic for DM changes as well as being
odd in general. Re-work the code paths so that we don't need to set the
gd pointer so early and instead can rely upon the normal setting of it.
In order to do this we do need to move certain calls from s_init into
spl_board_init(), mainly preloader_console_init and
save_omap_boot_params.
Tested on: Beaglebone Black, AM43xx GP EVM, Beagleboard, Beagleboard xM,
OMAP5 uEVM, DRA7xx EVM
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP
is integrated in Freescale T1040 and T1020 SoCs.
The L2 switch has 10 Ethernet ports: 2 internal fixed-links
(ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps.
The external ports may be connected to PHYs over QSGMII and SGMII.
Commands have also been added to enable/disable a port and to
check a port's link speed, duplexity and status. The commands are:
ethsw port <port_nr> enable|disable - enable/disable an l2 switch port
ethsw port <port_nr> show - show an l2 switch port's configuration
port_nr=0..9; use "all" for all ports
For more detailse please see doc/README.t1040-l2switch
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
If SerDes is configured to connect L2 Switch ports from T1040
over SGMII or QSGMII, the two FMAN fixed ports (FM1@DTSEC1 and FM2@DTSEC2)
that are connected to two L2 swtch ports must be enabled. These
ports don't have PHYs and must be treated accordingly.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Some Freescale SoCs like T1020 and T1040 have an integrated
L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs
over SGMII and QSGMII.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The number of supported serdes protocols on Freescale SoCs
has increased over time. Until now, an u64 variable have been
initialized on boot with the configured protocols. However,
since this number has increased (enum srds_prtcl has more
than 64 values), 64 bits are no longer sufficient to hold track
of all the configured protocols.
This patch replaces the u64 map values with static arrays.
To keep track of the number of serdes protocols, the
SERDES_PRCTL_COUNT vale has been added at the end of
enum srds_prtcl. This value must always be the last one.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
U-boot assumes that all FMAN ports have a PHY. Some SoCs (like T1040)
have fixed links. This means that the ports are connected MAC to MAc
and there is no Ethernet PHY attatched. This patch initializes a
FMAN MAC even if it doesn't have a PHY attached.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
All the boards that support deep sleep feature are converted
to deep sleep generic board interface. The old interface which
support non-generic board is not used anymore. So clean it up.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY.
rcw_0x095 is used for 10G XFI + 3x PCIex1
rcw_0x135 is used for 2.5G SGMII + 2x PCIex1
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Besides, added SPI/SD/NAND boot deep sleep support.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
CONFIG_BOOTDELAY is missing from board header file. Add this macro
to enable counting down of auto boot.
Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
SerDes 2 protocol 56 is not valid any longer due to
the new RCW; protocol 55 is used instead, so add
SerDes 2 protocol 55 to align with RCW.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>. As a result, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h>.
The right fix would be to split the lib/fdtdec.c to remove
dependency on GPIO.
This commit adds a dummy <asm/arch/gpio.h> to support OF_CONTROL
for mpc85xx platform. A file mpc85xx_gpio.h exists in
arch/powerpc/include/asm. The defintions in that file conflict
with the ones in asm-generic/gpio.h. Hence a dummy header file
has been added. This will be removed after FDT-GPIO stuff is
fixed correctly.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Now TQM8xx is the only remaining board family of mpc8xx.
It uses its own linker script, board/tqc/tqm8xx/u-boot.lds.
arch/powerpc/cpu/mpc8xx/u-boot.lds is not used by any boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
As a preparation to ARCv2 port submission we rename "arc700" folder to
"arcv1" which stands for ARCv1 ISA also known as ARCompact.
This will allow us to add more flavours of binary-compatible ARCv1 CPUs
like ARC600 if needed later on and all required ARCv2 CPUs (which are
binary incompatible with ARCv1) in "arcv2" folder in subsequent commits.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Both ARCangel4 and AXS10x are FPGA-based boards so they may have
different CPUs. For now we have only 1 option (ARC700) and we define
this as default in arch Kconfig.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
"reset.c" and "cpu.c" have no architecture-specific code at all.
Others are applicable to either ARC CPU.
This change is a preparation to submission of ARCv2 architecture port.
Even though ARCv1 and ARCv2 ISAs are not binary compatible most of
built-in modules still have the same programming model - AUX registers
are mapped in the same addresses and hold the same data (new featues
extend existing ones).
So only low-level assembly code (start-up, interrupt handlers) is left
as CPU(actually ISA)-specific. This significantyl simplifies maintenance
of multiple CPUs/ISAs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
* use better symbols for relocatable region boundaries
("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE")
* remove useless debug messages because they will only show up in case
of both problem (when normal "if" branch won't be taken) and DEBUG take
place which is pretty rare situation.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Even though existing implementation works fine in preparation to
submission of ARCv2 architecture we need this change.
In case of ARCv2 interrupt vector table consists of just addresses
of corresponding handlers. And if those addresses will be in .text
section then assembler will encode them as everything in .text section
as middle-endian and then on real execution CPU will read swapped
addresses and will jump into the wild.
Once introduced new section is situated so .text section remains the
first which allows us to use common linker option for linking everything
to a specified CONFIG_SYS_TEXT_BASE.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Depending on MMU presence in CPU there're differences in HW behavior.
For example address of instruction that caused exception is put in
ECR register if MMU exists and in ERET register otherwise.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
To disable interrupts we need to reset corresponding flags in STATUS32
register. For this we need to OR flags for interrupts level1 and level2
and then AND with current value in STATUS32.
Before that implementation was incorrect.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Exception cause register (ECR) contains value that describes a reason
for exception that has happened. This helps a lot to figure-out what
went wrong.
Now we print this register contents when dumping registers.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Some cache operations ({i|d}cache_{enable|disable|status} or
flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF
is set.
This is required for force disable of caches on early boot.
What if something was executed before U-boot and enabled caches
(low-level bootloaders, previously run kernel etc.)?
But if CPU doesn't really have caches any attempt to access
cache-related AUX registers triggers instruction error exception.
So for convenience we'll try to avoid exceptions by checking if CPU
actually has caches (we check separately data and instruction cache
existence) at all.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
Normally buildman runs with 'make -s' meaning that only errors and warnings
appear in the log file. Add a -V option to run make in verbose mode, and
with V=1, causing a full build log to be created.
Signed-off-by: Simon Glass <sjg@chromium.org>
The site at https://www.kernel.org/pub/tools/crosstool/ is a convenient
repository of toolchains which can be used for U-Boot. Add a feature to
download and install a toolchain for a selected architecture automatically.
It isn't clear how long this site will stay in the current place and
format, but we should be able to rely on bug reports if it changes.
Suggested-by: Marek Vašut <marex@denx.de>
Suggested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
We should create a test setting file when running testes, not use whatever
happens to be on the local machine.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since we need a few modules which might not be available in a bare-bones
distribution, add a note about that to the README.
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Wolfgang Denk <wd@denx.de>
In some cases there may be multiple toolchains with the same name in the
path. Provide an option to use the full path in the CROSS_COMPILE
environment variable.
Note: Wolfgang mentioned that this is dangerous since in some cases there
may be other tools on the path that are needed. So this is set up as an
option, not the default. I will need test confirmation (i.e. that this
commit fixes a real problem) before merging it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Steve Rae <srae@broadcom.com>
If:
1. Toolchains A and B have the same filename
2. Toolchain A is in the PATH
3. Toolchain B is given in ~/.buildman and buildman uses it to build
then buildman will add toolchain B to the end of its path but will not
necessarily use it since U-Boot will find toolchain A first in the PATH.
Try to fix this by putting the toolchain first in the path instead of
last.
Signed-off-by: Simon Glass <sjg@chromium.org>
The assumption that the compiler name will always end in gcc is incorrect
for clang and apparently on BSD.
Signed-off-by: Simon Glass <sjg@chromium.org>
When running tests the output directory is often wiped. This is only safe if
a branch is being built. The output directory may contain other things
besides the buildman test output.
Signed-off-by: Simon Glass <sjg@chromium.org>
When building current source for a single board, buildman puts the output
in <output_dir>/current/current/<board>. Add an option to make it use
<output_dir>/<board> instead. This removes the unnecessary directories
in that case, controlled by the --no-subdirs/-N option.
Suggested-by: Tom Rini <trini@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Buildman normally obtains the upstream commit by asking git. Provided that
the branch was created with 'git checkout -b <branch> <some_upstream>' then
this normally works.
When there is no upstream, we can try to guess one, by looking up through
the commits until we find a branch. Add a function to try this and print
a warning if buildman ends up relying on it.
Also update the documentation to match.
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Wolfgang Denk <wd@denx.de>
This is not needed since we always do a full (non-incremental) build. Also
it might be dangerous since it will try to delete everything below the
base directory.
Fix this potentially nasty bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Buildman currently puts current-source builds in a current/current
subdirectory, but there is no need for the extra depth.
Suggested-by: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
It makes sense to specify CONFIG_SYS_CLK_FREQ in "configs/xx_defconfig"
instead of "include/configs/xxx.h" because then header will be reusable
across boards with different CPU clocks.
Also this nice to have an ability for end user to tune this value
himself via "menuconfig".
For now I'm only applying this change to all ARC configs because
otherwise scope of change will be huge.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Hans de Goede <hdegoede@redhat.com>
cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
If CONFIG_SPL_NOR_SUPPORT is defined, spl_nor_load_image() requires
spl_start_uboot(), CONFIG_SYS_OS_BASE, CONFIG_SYS_SPL_ARGS_ADDR,
CONFIG_SYS_FDT_BASE to be defined even if users just want to run
U-Boot, not Linux. This is inconvenient.
This patch is following the codying style of common/spl/spl_nand.c.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Some MTD defines are repeated twice; once with UBI and then with MTD.
Remove the duplicate MTD defines from the UBI grouping.
Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Adjust the code so that the error reporting can all be done at the end,
and is the same for each decompression method. Try to detect when
decompression fails due to lack of space. Keep the behaviour of
resetting on failure even though there should be no memory corruption
now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Refactor to allow this function to be used to announce the image being
loaded regardless of compression type and even when there is no
decompression.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use each compression method (including uncompressed). Test for normal
operation, insufficient space and corrupted data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Export this function for testing. Also add a parameter so that values other
than CONFIG_SYS_BOOTM_LEN can be used for the maximum uncompressed size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Prior to commit d455d87 there was an inconsistency between the position of
the 'address' parameter in 'sb load' and 'sb save'. This was corrected but
it broke some tests. Fix the tests and also the help for 'sb save'.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code is repeated in several places, and does not detect a common
fault where the image is too large. Move it into its own function and
provide a more helpful messages in this case, for compression schemes
which support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit 4d3b8a0d fixed a problem with lzma decompress where it would
run out of bytes to decompress. The algorithm needs to know how many
uncompressed bytes it is expected to produce.
However, the fix introduced a potential buffer overrun, and causes
the compression test to fail (test_compression command in sandbox).
The correct fix seems to be to use the minimum of the expected number
of uncompressed bytes and the amount of output space available. That
way things work normally when there is enough space, and return an
error (without overrunning available space) when there is not.
Signed-off-by: Antonios Vamporakis <ant@area128.com>
CC: Kees Cook <keescook@chromium.org>
CC: Simon Glass <sjg@chromium.org>
CC: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
CC: Luka Perkov <luka@openwrt.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This commit was generated by the following command:
scripts/fill_scrapyard.py
The commit-ID of CPCIISER4 removal has been fixed by hand because
the board was removed by commit 3705726010 (ppc4xx: remove CPCIISER4
board), but it was added to README.scrapyard by commit 9a4018e09a
(ppc4xx: remove DP405 board).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
We are removing bunch of non-generic boards these days.
Updating doc/README.scrapyard is a really tedious task, but it can
be automated. I hope this tool will make our life easier.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The axp221 / axp223's N_VBUSEN pin can be configured as an output rather
then an input, and this is used on some boards to control usb-vbus0, add
support for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Most of the usb-controller init code found in ehci-sunxi.c also is necessary
to init the otg usb controller, so move it to a common place.
While at it also update various #ifdefs / defines for sun8i support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The axp221 / axp223's N_VBUSEN pin can be configured as an output rather
then an input, add axp_drivebus_enable() and _disable() functions to set
the pin in output mode and control it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The voltage setting code knows it needs to call axp221_init before calling
the various voltage setting functions.
But users of axp utility functions like axp221_get_sid() do not know this,
so the utility functions always call axp221_init() to ensure that the
p2wi / rsb setup magic has been done.
Since doing this repeatedly is quite expensive, add a check to axp221_init
so that it only does the initialization once.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
ALDO2 is used to power LPDDR2 SDRAM on both the reference design and the
Hummingbird A31, when this type of RAM is present.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Hummingbird A31 uses an external DAC connected to the LCD0 outputs
for the on board VGA output. The DAC has a power control that's toggled
by GPIO.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The external DAC for VGA output might have either a power or reset
control pin that needs to be pulled up, as is the case on the
Hummingbird A31.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Using an external DAC for VGA output was available on sun5i. Since
some other SoCs don't have a builtin TV encoder, but might have
use for a VGA output, enable the option for the platforms that
don't have TV encoders.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently the pre-console buffer can accumulate early log messages
and flush them to the serial console as soon as it becomes available.
This patch just adds one more pre-console buffer flushing point and
does all the same for the other consoles too. This is particularly
useful for the vga/hdmi/lcd console, where we can see all the older
messages now (except for the log messages from SPL).
Naturally, we don't want to get an extra copy of the log messages
on the serial console again at the second flushing point, so the
serial console has to be explicitly filtered out.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
"adr rX, text_end" only works if the label is close. Adding further code
to the other functions will prevent this. So move the containing
function close to label. No functional change.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Based on the original version by Marc Zyngier. It adds a psci_cpu_off
implementation for the A20 SoC. The mechanism works by first preparing
the calling CPU to go offline (disable and flush cache, disable SMP),
then requesting CPU 0 to pull the plug. The request is sent as FIQ on
SGI15.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for a sun4i board built by Linksprite. This addition covers
both v1 and v2 versions. As the board has been working with 408MHz memory
setting in the u-boot-sunxi branch, and has been proven to be running stable
during my tests as well, a respective new DRAM config file is added as well.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In some extreme cases it may be necessary to wait 1.5 seconds or more for a hpd
signal to show up (and be able to read edid info), but we do not want to
penalize all headless boots with an extra second boot delay, so add a hpd_delay
parameter which can be set through the video-mode env. variable.
While at it raise the default from 300ms to 500ms as 300 may very well be too
low in many cases.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for VGA directly from the sunxi SoC / display engine.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
If a board has no LCD, but does have VGA fallback to VGA when no HDMI cable
is connected (unless hpd=0).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for using PORTD hsync/vsync pins with tcon1, this is a preparation
patch for adding native VGA support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Use sunxi_lcdc_get_clk_delay to calculate tcon1 delay instead of hardcoding
it to 30. We will still end up using 30 for most modes, but for e.g. 800x600
this makes a (small) difference.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Having both a sunxi_display.enabled variable and
sunxi_display.monitor == sunxi_monitor_none duplicates state, use
sunxi_display.monitor = sunxi_monitor_none when ever we do not have a display.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Enable VGA output on the A13-OLinuXino and A13-OLinuXinoM now that we've
support for it.
Also add LCD timing and gpio info for the Olimex 7" LCD module. We can safely
put this in the default config on this boards, since by default we will always
use VGA, and the LCD timing info will only get used if the user explicitly
sets monitor=lcd in the video-mode env. variable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Before video output support can be enabled on the A13-OLinuXinoM, bootm_size
must first be reduced to take into account that the framebuffer is shaved of
the top of the DRAM. For other boards this is not an issue since bootm was set
to 256M and all boards have at least 512M except for the A13-OLinuXinoM.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for external DACs connected to the parallel LCD interface driving
a VGA connector, such as found on the Olimex A13 boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A23 (sun8i) only has lcd output support, so allow building the video code
without HDMI support for use with the A23.
Also the A23 has the same reset bits (and necessity to enable the DRC block)
as the sun6i, so enable those bits for sun8i too.
Note building without HDMI support is useful for the A13 (sun5i variant) too,
as that one does not have HDMI either.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add lcd output support, see the new Kconfig entries and doc/README.video for
how to enable / configure this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move sunxi_drc_init to directly above sunxi_engines_init, to avoid
unnecessary #ifdef-ery in later patches.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1, this is a
preparation patch for adding lcd support.
While at it also swap the divider search order, searching from low to
high, as the comment above the code says we should do. In cases where there
are multiple solutions this will result in picking a lower pll clock and
divider, which is more stable and saves power.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Refactor sunxi_mode_set into a bunch of helpers, and make it do a switch
case on sunxi_display.monitor to decide what to do.
Also rename sunxi_lcdc_mode_set to sunxi_lcdc_tcon1_mode_set, as it sets the
timings for tcon1, and for lcd support we need a similar function operating
on tcon0.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a sunxi_monitor enum and parse the monitor option string into this enum
once, rather then doing strcmp-s on it in various places. This also adds
checking for it being a valid value.
This also adds new "none" and "lcd" values in preparation for lcd support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Some boards use GPIO-s on the pmic, one example of this is the A13-OLinuXino
board, which uses gpio0 of the axp209 for the lcd-power signal.
This commit adds support for gpio pins on the AXP209 pmic, the sunxi_gpio.c
changes are universal, adding gpio support for the other AXP pmics (when
necessary) should be a matter of adding the necessary axp_gpio_foo functions
to their resp. drivers, and add "#define AXP_GPIO" to their header file.
Note this commit only adds support for the non device-model version of the
gpio code, patches for adding support to the device-model version are very
welcome.
The string representation for these gpio-s is AXP0-#, the 0 in the AXP0 prefix
is there in case we need to support gpio-s on more then 1 pmic in the future.
At least A80 boards have 2 pmics, and we may end up needing to support gpio-s
on both.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move a few mux defines around so that all the mux defines are properly sorted
by port number.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a write to the "unknown" (*) register to enable auto input sync, when
initially adding sunxi hdmi output support this magic write from the android
kernel code was missed, causing lcdc -> hdmi encoder sync problems.
With this write added, we can drop the modesetting retries and the extra
delays added to work around these sync problems.
With the retries dropped there also is no need to 0 all the enable flags at
the beginning of the modeset, as they are initialized to 0 already by
engines_init.
*) "unknown" is the actual name of this register in the android kernel sources
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
When using a hdmi powered hdmi to vga dongle, and cold booting a sunxi
device, the hpd detect code would not see the dongle (until a warm reboot),
because the dongle needs some time to boot.
Testing has shown that this dongle needs 213ms to respond on a cold boot,
so wait up to 300ms for a hpd signal to show up before giving up.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
When using edid use CEA681 edid extension blocks to select between dvi and
hdmi output formats, so that u-boot will automatically do the right thing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add a sunxi_hdmi_edid_get_block helper function, this is a preparation patch
for adding support for parsing EDID extension blocks.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
So far we've been programming the hdmi-encoder to send out dvi data over the
hdmi connector. This works well for most devices, including hdmi devices, but
not all devices accept dvi data on a hdmi input.
Add support for sending proper hdmi data over the hdmi output found on most
sunxi boards. This can be turned on by adding monitor=hdmi as option to the
video-mode env. variable.
A follow up patch will determine whether to send dvi or hdmi automatically when
EDID is used.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add DDC & EDID support and use it to automatically select the native mode of
the attached monitor. This can be disabled by adding edid=0 as option
to the video-mode env. variable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Allow the user to specify hpd=0 as option in the video-mode env. variable,
if hpd is set to 0 then the hdmi output will be brought up even if no cable
is connected.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add support for the standard video-mode environment variable using the
videomodes.c video_get_ctfb_res_modes() helper function.
This will allow users to specify the resolution e.g. :
setenv video-mode sunxi:video-mode=1280x1024-24@60
saveenv
Also make the reserved fb mem slightly larger to allow 1920x1200 to work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Switch from fb_videomode to ctfb_res_modes and use the predefined videotimings
from videomodes.c, rather then defining our own.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add a struct describing the (fixed) bits of cea681 edid extension blocks,
and defines for accessing various bitfields.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add a helper function to check the checksum of an EDID data block.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add a video_edid_dtd_to_ctfb_res_modes helper function to convert an EDID
detailed timing to a struct ctfb_res_modes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add 2 helper functions to get strings, respectively integers from the options
value returned by video_get_video_mode() / video_get_ctfb_res_modes().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add a video_get_ctfb_res_modes() helper function, which uses
video_get_video_mode() to parse the 'video-mode' environment variable and then
looks up the matching mode in res_mode_init and returns the matching mode.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
The timings for the modes defined in videomodes.c differ (significantly)
from vesa standard timings for these modes.
This commit adds a version with the proper std timings for these modes,
since I do not want to cause regressions, boards which want to use the standard
timings need to define CONFIG_VIDEO_STD_TIMINGS to get the new correct timings.
Since there is no std timing for 960x720 this commit uses the timing used
by the nvidia video drivers for 960x720, which uses a standard pixelclock
of 74.25 MHz rather then the weird 76.335... clock used by the old modes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add pixelclock_khz and refresh fields to ctfb_res_modes:
1) pixelclocks are usually referred to in hz, not picoseconds, and e.g
pll-s are also typically programmed in hz, not ps. Converting between the
2 leads to rounding differences, add a pixelclock_khz field to directly
store the *exact* pixelclock for a mode, so that drivers do not need to
resort to rounding tricks to try and guess the exact pixelclock;
2) The video-mode environment variable, as parsed by video_get_video_mode
also contains the vertical refresh rate, add a refresh field, so that
the refresh-rate can be matched when parsing the video-mode environment
variable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add support for the new Bananapro A20 development board from lemaker.org.
This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for
OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver,
3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
After reboot, reset or even short power off, DRAM typically retains
the old stale data for some period of time (for this type of memory,
the bits of data are stored in slowly discharging capacitors).
The current sun6i/sun8i DRAM size detection logic, which is
inherited from the Allwinner code, relies on using a large magic
signature with the hope that it is unique enough and unlikely to
ever accidentally match this leftover garbage data in RAM. But
this approach is inherently unsafe, as can be demonstrated using
the following test program:
/***** A testcase for reproducing the problem ******/
void main(int argc, char *argv[])
{
size_t size, i;
uint32_t *buf;
/* Allocate the buffer */
if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) ||
!(buf = malloc(size))) {
printf("Need buffer size in MiB as a cmdline argument\n");
exit(1);
}
/* Fill it with the Allwinner DRAM "magic" values */
for (i = 0; i < size / 4; i++)
buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64;
/* Try to reboot */
system("reboot");
/* And wait */
for (;;) {}
}
/***************************************************/
If this test program is run on the device (giving it a large
chunk of memory), then the DRAM size detection logic in u-boot
gets confused after reboot and fails to initialize DRAM properly.
A better approach is not to rely on luck and abstain from making
any assumptions about the properties of the leftover garbage
data in RAM. Instead just use a more reliable code for testing
whether two different addresses refer to the same memory location.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch uses the same DRAM settings as in the pre-installed
Android firmware. The LCD display is supported too.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The CONFIG_UART0_PORT_F option has been supported since
http://git.denx.de/?p=u-boot.git;a=commit;h=ff2b47f6a9cc1025
This option is primarily useful only for low level u-boot debugging
on tablets, where normal UART0 is difficult to access and requires
device disassembly and/or soldering.
This patch now allows it to be selected from menuconfig. A dependency on
SPL_FEL is added because u-boot does not support booting from NAND yet
and also booting from SD card is impossible when a MicroSD breakout board
is plugged into the SD slot.
Additionally a compilation problem is fixed:
common/spl/built-in.o: In function `spl_mmc_load_image':
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:94: undefined reference to `mmc_initialize'
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:96: undefined reference to `find_mmc_device'
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:104: undefined reference to `mmc_init'
scripts/Makefile.spl:206: recipe for target 'spl/u-boot-spl' failed
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We need separate defconfigs for the v5 and v1.2 versions of this board, as
they use different DRAM parameters.
Note they also use different dtb files, as the wifi is different too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Now that we've sun8i dram-init support we can enable the SPL for sun8i boards.
While at it also replace CONFIG_DEFAULT_DEVICE_TREE with CONFIG_FDTFILE,
the former is for u-boot's own fdt usage, which we do not use (yet), the later
specifies the fdt to pass to the kernel, which is the one we want.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sun8i boot0 code fills the DRAM with a "random" pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not do it, instead relying on the memory contents being random enough
to begin with for the memcmp to properly detect the wrap-around address, iow
it is working purely by chance. Since our sun6i dram code was modelled after
the boot0 code it contained the same issue.
This commit fixes this by filling the memory with a unique, distinct pattern.
The new mctl_mem_fill function this introduces is added as an inline helper
in dram.h, so that it can be shared with the sun8i dram code.
While at it move mctl_mem_matches to dram.h for re-use in sun8i too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h, rather then adding yet another copy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Our old hardcoded k and m values are based on PLL5 being configured in steps
of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the
DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i)
the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps.
This commit adjusts clock_set_pll5 to automatically select the best k and m
depending on the requested clk rate.
Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sun8i dram code sometimes wants to enable sigma delta mode,
add a parameter to allow this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
dcdc4 is not used on sun8i, disable it.
While at it also add comments to the other fixed voltages to document what
they are used for.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Explicitly turn off unused voltages, rather then leaving them as is. Likewise
explictly enabled the dcdc convertors, rather then assuming they are already
enabled at boot.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The dcdc1 voltage is typically used as generic 3.3V IO voltage for things like
GPIO-s, sdcard interfaces, etc. On most boards this is undervolted to 3.0V to
safe battery, but not on all, make it configurable so that we can use the
same settings as the original firmware on all boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Some of the ldo-s of the axp221 are used in the same way on most boards, add
comments to the Kconfig help text to reflect this, and give them defaults
matching their typical usage.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The axp223 appears to be the same as the axp221, except that it uses the
rsb to communicate rather then the p2wi. At least all the registers we use
are 100% the same.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.
This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
It does not make sense to make gpio_direction_input() return the gpio input
status. The return value of gpio_direction_input() is inconsistent if
CONFIG_DM_GPIO is defined.
And we don't need to call gpio_direction_input() int sunxi_mmc_getcd().
Just init the gpio once in mmc_resource_init() is enough.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
On sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a helper function to abstract this away.
This makes our MAC address generation code also work on sun6i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
For sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a function to retreive the sid.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.
The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).
For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.
This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Colombus defconfig settings are missing a number of settings for recently
added features, because we did not know exactly how things were hooked up.
Maxime Ripard has run various tests to get us the necessary details, this
commit updates the defconfig with this info.
This commit also updates the dram clk and zq values with values verified
by Maxime to be the ones used by the original firmware for this board.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between
the A31s and the A31.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.
Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Add netargs and netboot option.
* This enables tftp and nfs booting
* This puts omap5 devices inline with other devices such as am335x and am437x
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
AM43xx Industrial Development Kit is a new board
based on AM437x line of SoCs. Targetted at Industrial
Automation applications, it comes with EtherCAT, motor
control and other goodies.
Thanks to James Doublesin for all the help.
Cc: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This regulator is used with AM437x IDK to feed
VDD_MPU, without means to scale VDD_MPU we can't
support higher frequencies.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Make sure that all OPPs are checked on
scale_vcores(). While at that also fix 600MHz
VDD_MPU voltage according to AM437x Data Manual
available at [1].
Table 5-3 on that document, lists all valid
voltages per frequency.
[1] http://www.ti.com/lit/ds/symlink/am4379.pdf
Signed-off-by: Felipe Balbi <balbi@ti.com>
DCDC1 is used as VDD_MPU in all known boards,
let's define all other valid voltages for that
rail so it can be used by our boards.
Signed-off-by: Felipe Balbi <balbi@ti.com>
The frequencies for 25MHz in dpll_per were out of spec for 25MHz,
correct.
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Switch to using hardware leveling for certain parameters on the EMIF
rather than using precalculated values. Doing this also means we have a
common place now between am437x and am335x for setting
emif_sdram_ref_ctrl with a value for the correct delay length.
Tested-by: Felipe Balbi <balbi@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Need to provide PLL values for all possible input frequencies (19.2, 24,
25, 26MHz). Values provide are also optimized for jitter (needed
especially for PER PLL and DDR PLL).
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Enable GPMC's prefetch feature for NAND access. This speeds up NAND read
access a lot by pre-fetching contents in the background and reading them
through the FIFO address.
The current implementation has two limitations:
a) it only works in 8-bit mode
b) it only supports read access
Both is easily fixable by someone who has hardware to implement it.
Note that U-Boot code uses non word-aligned buffers to read data into, and
request read lengths that are not multiples of 4, so both partial buffers
(head and tail) have to be addressed.
Tested on AM335x hardware.
Tested-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Guido Martínez <guido@vanguardiasur.com.ar>
Signed-off-by: Daniel Mack <zonque@gmail.com>
[trini: Make apply again, use 'cs' fix pointed out by Guido]
Signed-off-by: Tom Rini <trini@ti.com>
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want to make these two options configurable
so that we can easily change them during 'make menuconfig' so that
the generated U-Boot image for coreboot is board configuration aware.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
Normally the bypass should be turned on in a simulation environment
like qemu.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
These two are not worth having separate inline functions as they are
really simple, so drop them.
Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.
Update the documentation to list some of the available commands.
This does not support fixed MTRRs as yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.
For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.
Signed-off-by: Simon Glass <sjg@chromium.org>
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.
Signed-off-by: Simon Glass <sjg@chromium.org>
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.
Signed-off-by: Simon Glass <sjg@chromium.org>
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.
We set RAM as cacheable (with write-back) and registers as non-cacheable.
Signed-off-by: Simon Glass <sjg@chromium.org>
For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.
Signed-off-by: Simon Glass <sjg@chromium.org>
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded
code.
These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).
Signed-off-by: Simon Glass <sjg@chromium.org>
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
The hex value is more commonly understood, so use that instead of decimal.
Add a 0x prefix to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.
Signed-off-by: Simon Glass <sjg@chromium.org>
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.
We could add a command to run the video BIOS later when needed, but this is
not considered at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This can be very slow - typically 80ms even on a fast machine since it uses
the SPI flash to read the data. Add an option to display the time taken.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If the video has not been set up, we should not return a success code. This
can be detected by seeing if any of the variables are non-zero.
Signed-off-by: Simon Glass <sjg@chromium.org>
This currently assumes that U-Boot resides at the start of ROM. Update
it to remove this assumption.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
We don't need this in U-Boot since we calculate it based on available memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.
Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.
Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commits cleans up the board dts files.
- Correct the serial port register size to 8
- Remove the misleading status = "disabled" statement in the
serial.dtsi
- Move the inclusion of skeleton.dtsi from serial.dtsi to board
dts files
- Let the board dts file define stdout-path in the chosen node
- Remove device nodes in board dts files thar are duplicated to
skeleton.dtsi
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The name of coreboot.dtsi is misleading, as it actually describes
the legacy serial port device node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
common/lcd.c is a mix of code portions that do different but related
things. To improve modularity, the various code portions should be split
into their own modules. Separate lcd console code into its own file.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Introduce lcd_getbgcolor() and lcd_getfgcolor(), and use them where
applicable.
This is a preparatory step for extracting lcd console code into its own
file.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
COLOR_MASK macro doesn't do anything; Remove it to reduce visual
complexity.
This is a preparatory step for extracting lcd console code into its own
file.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Introduce set_console_row(), set_console_col(), and lcd_init_console().
Use these functions in lcd functions: lcd_init(), lcd_clear(), lcd_logo().
This is a preparatory step for extracting lcd console code into its own
file.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Replace CONSOLE_(ROWS|COLS) macros with variables, and assign the
original macro values.
This is a preparatory step for extracting lcd console code into its own
file.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Rename console_(row|col) to console_curr_(row|col) to better distinguish
it from console_(rows|cols).
This is a preparatory step for extracting lcd console code into its own file.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
When using summary mode (-s) we don't always want to display errors.
Allow this option to be omitted.
Series-to: u-boot
Series-cc: albert
Change-Id: I6b37754d55eb920ecae114fceba55834b43ea3b9
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
Ensure that we don't print duplicate board names when -l is used.
Change-Id: I56adb138fc18f772ba61eba0fa194cdd7bc7efc6
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
2014-11-03 14:10:52 -07:00
2472 changed files with 84481 additions and 156336 deletions
# install toolchains based on INSTALL_TOOLCHAIN} variable
- if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
- if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
- if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/mips/eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh ; fi
- if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then sh eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh -y ; fi
script:
# the execution sequence for each test
- echo ${TEST_CONFIG_CMD}
- ${TEST_CONFIG_CMD}
- echo ${TEST_CMD}
- ${TEST_CMD}
matrix:
include:
# we need to build by vendor due to 50min time limit for builds
mcr p15, 0, r0, c7, c14, 1/*@ clean & invalidate D line */
dsb /*@data sync barrier */
ldmfd sp!, {r1-r12}
bx lr
Some files were not shown because too many files have changed in this diff
Show More
Reference in New Issue
Block a user
Blocking a user prevents them from interacting with repositories, such as opening or commenting on pull requests or issues. Learn more about blocking a user.
