leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

x86: quark: Add Memory Reference Code (MRC) main routines

Browse Source 
Add the main routines for Quark Memory Reference Code (MRC).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2015-02-05 23:42:22 +08:00 committed by Simon Glass
parent ea94532461
commit 0a391b1c79
2 changed files with 391 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

204
arch/x86/cpu/quark/mrc.c Normal file
View File

@ -0,0 +1,204 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* Ported from Intel released Quark UEFI BIOS
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
*
* SPDX-License-Identifier: Intel
*/
/*
* This is the main Quark Memory Reference Code (MRC)
*
* These functions are generic and should work for any Quark-based board.
*
* MRC requires two data structures to be passed in which are initialized by
* mrc_adjust_params().
*
* The basic flow is as follows:
* 01) Check for supported DDR speed configuration
* 02) Set up Memory Manager buffer as pass-through (POR)
* 03) Set Channel Interleaving Mode and Channel Stride to the most aggressive
* setting possible
* 04) Set up the Memory Controller logic
* 05) Set up the DDR_PHY logic
* 06) Initialise the DRAMs (JEDEC)
* 07) Perform the Receive Enable Calibration algorithm
* 08) Perform the Write Leveling algorithm
* 09) Perform the Read Training algorithm (includes internal Vref)
* 10) Perform the Write Training algorithm
* 11) Set Channel Interleaving Mode and Channel Stride to the desired settings
*
* DRAM unit configuration based on Valleyview MRC.
*/
#include <common.h>
#include <asm/arch/mrc.h>
#include <asm/arch/msg_port.h>
#include "mrc_util.h"
#include "smc.h"
static const struct mem_init init[] = {
{ 0x0101, BM_COLD | BM_FAST | BM_WARM | BM_S3, clear_self_refresh },
{ 0x0200, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_timing_control },
{ 0x0103, BM_COLD | BM_FAST , prog_decode_before_jedec },
{ 0x0104, BM_COLD | BM_FAST , perform_ddr_reset },
{ 0x0300, BM_COLD | BM_FAST | BM_S3, ddrphy_init },
{ 0x0400, BM_COLD | BM_FAST , perform_jedec_init },
{ 0x0105, BM_COLD | BM_FAST , set_ddr_init_complete },
{ 0x0106, BM_FAST | BM_WARM | BM_S3, restore_timings },
{ 0x0106, BM_COLD , default_timings },
{ 0x0500, BM_COLD , rcvn_cal },
{ 0x0600, BM_COLD , wr_level },
{ 0x0120, BM_COLD , prog_page_ctrl },
{ 0x0700, BM_COLD , rd_train },
{ 0x0800, BM_COLD , wr_train },
{ 0x010b, BM_COLD , store_timings },
{ 0x010c, BM_COLD | BM_FAST | BM_WARM | BM_S3, enable_scrambling },
{ 0x010d, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_control },
{ 0x010e, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_dra_drb },
{ 0x010f, BM_WARM | BM_S3, perform_wake },
{ 0x0110, BM_COLD | BM_FAST | BM_WARM | BM_S3, change_refresh_period },
{ 0x0111, BM_COLD | BM_FAST | BM_WARM | BM_S3, set_auto_refresh },
{ 0x0112, BM_COLD | BM_FAST | BM_WARM | BM_S3, ecc_enable },
{ 0x0113, BM_COLD | BM_FAST , memory_test },
{ 0x0114, BM_COLD | BM_FAST | BM_WARM | BM_S3, lock_registers }
};
/* Adjust configuration parameters before initialization sequence */
static void mrc_adjust_params(struct mrc_params *mrc_params)
{
const struct dram_params *dram_params;
uint8_t dram_width;
uint32_t rank_enables;
uint32_t channel_width;
ENTERFN();
/* initially expect success */
mrc_params->status = MRC_SUCCESS;
dram_width = mrc_params->dram_width;
rank_enables = mrc_params->rank_enables;
channel_width = mrc_params->channel_width;
/*
* Setup board layout (must be reviewed as is selecting static timings)
* 0 == R0 (DDR3 x16), 1 == R1 (DDR3 x16),
* 2 == DV (DDR3 x8), 3 == SV (DDR3 x8).
*/
if (dram_width == X8)
mrc_params->board_id = 2; /* select x8 layout */
else
mrc_params->board_id = 0; /* select x16 layout */
/* initially no memory */
mrc_params->mem_size = 0;
/* begin of channel settings */
dram_params = &mrc_params->params;
/*
* Determine column bits:
*
* Column: 11 for 8Gbx8, else 10
*/
mrc_params->column_bits[0] =
((dram_params[0].density == 4) &&
(dram_width == X8)) ? (11) : (10);
/*
* Determine row bits:
*
* 512Mbx16=12 512Mbx8=13
* 1Gbx16=13 1Gbx8=14
* 2Gbx16=14 2Gbx8=15
* 4Gbx16=15 4Gbx8=16
* 8Gbx16=16 8Gbx8=16
*/
mrc_params->row_bits[0] = 12 + (dram_params[0].density) +
(((dram_params[0].density < 4) &&
(dram_width == X8)) ? (1) : (0));
/*
* Determine per-channel memory size:
*
* (For 2 RANKs, multiply by 2)
* (For 16 bit data bus, divide by 2)
*
* DENSITY WIDTH MEM_AVAILABLE
* 512Mb x16 0x008000000 ( 128MB)
* 512Mb x8 0x010000000 ( 256MB)
* 1Gb x16 0x010000000 ( 256MB)
* 1Gb x8 0x020000000 ( 512MB)
* 2Gb x16 0x020000000 ( 512MB)
* 2Gb x8 0x040000000 (1024MB)
* 4Gb x16 0x040000000 (1024MB)
* 4Gb x8 0x080000000 (2048MB)
*/
mrc_params->channel_size[0] = (1 << dram_params[0].density);
mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1;
mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1;
mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2;
/* Determine memory size (convert number of 64MB/512Mb units) */
mrc_params->mem_size += mrc_params->channel_size[0] << 26;
LEAVEFN();
}
static void mrc_mem_init(struct mrc_params *mrc_params)
{
int i;
ENTERFN();
/* MRC started */
mrc_post_code(0x01, 0x00);
if (mrc_params->boot_mode != BM_COLD) {
if (mrc_params->ddr_speed != mrc_params->timings.ddr_speed) {
/* full training required as frequency changed */
mrc_params->boot_mode = BM_COLD;
}
}
for (i = 0; i < ARRAY_SIZE(init); i++) {
uint64_t my_tsc;
if (mrc_params->boot_mode & init[i].boot_path) {
uint8_t major = init[i].post_code >> 8 & 0xff;
uint8_t minor = init[i].post_code >> 0 & 0xff;
mrc_post_code(major, minor);
my_tsc = rdtsc();
init[i].init_fn(mrc_params);
DPF(D_TIME, "Execution time %llx", rdtsc() - my_tsc);
}
}
/* display the timings */
print_timings(mrc_params);
/* MRC complete */
mrc_post_code(0x01, 0xff);
LEAVEFN();
}
void mrc_init(struct mrc_params *mrc_params)
{
ENTERFN();
DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION,
__DATE__, __TIME__);
/* Set up the data structures used by mrc_mem_init() */
mrc_adjust_params(mrc_params);
/* Initialize system memory */
mrc_mem_init(mrc_params);
LEAVEFN();
}

187
arch/x86/include/asm/arch-quark/mrc.h Normal file
View File

@ -0,0 +1,187 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* Ported from Intel released Quark UEFI BIOS
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
*
* SPDX-License-Identifier: Intel
*/
#ifndef _MRC_H_
#define _MRC_H_
#define MRC_VERSION 0x0111
/* architectural definitions */
#define NUM_CHANNELS 1 /* number of channels */
#define NUM_RANKS 2 /* number of ranks per channel */
#define NUM_BYTE_LANES 4 /* number of byte lanes per channel */
/* software limitations */
#define MAX_CHANNELS 1
#define MAX_RANKS 2
#define MAX_BYTE_LANES 4
#define MAX_SOCKETS 1
#define MAX_SIDES 1
#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
/* Specify DRAM and channel width */
enum {
X8, /* DRAM width */
X16, /* DRAM width & Channel Width */
X32 /* Channel Width */
};
/* Specify DRAM speed */
enum {
DDRFREQ_800,
DDRFREQ_1066
};
/* Specify DRAM type */
enum {
DDR3,
DDR3L
};
/*
* density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
* cl: DRAM CAS Latency in clocks
* ras: ACT to PRE command period
* wtr: Delay from start of internal write transaction to internal read command
* rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K)
* faw: Four activate window (JESD79 specific to page size 1K/2K)
*
* ras/wtr/rrd/faw timings are in picoseconds
*
* Refer to JEDEC spec (or DRAM datasheet) when changing these values.
*/
struct dram_params {
uint8_t density;
uint8_t cl;
uint32_t ras;
uint32_t wtr;
uint32_t rrd;
uint32_t faw;
};
/*
* Delay configuration for individual signals
* Vref setting
* Scrambler seed
*/
struct mrc_timings {
uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
uint32_t wcmd[NUM_CHANNELS];
uint32_t scrambler_seed;
/* need to save for the case of frequency change */
uint8_t ddr_speed;
};
/* Boot mode defined as bit mask (1<<n) */
enum {
BM_UNKNOWN,
BM_COLD = 1, /* full training */
BM_FAST = 2, /* restore timing parameters */
BM_S3 = 4, /* resume from S3 */
BM_WARM = 8
};
/* MRC execution status */
#define MRC_SUCCESS 0 /* initialization ok */
#define MRC_E_MEMTEST 1 /* memtest failed */
/*
* Memory Reference Code parameters
*
* It includes 3 parts:
* - input parameters like boot mode and DRAM parameters
* - context parameters for MRC internal state
* - output parameters like initialization result and memory size
*/
struct mrc_params {
/* Input parameters */
uint32_t boot_mode; /* BM_COLD, BM_FAST, BM_WARM, BM_S3 */
/* DRAM parameters */
uint8_t dram_width; /* x8, x16 */
uint8_t ddr_speed; /* DDRFREQ_800, DDRFREQ_1066 */
uint8_t ddr_type; /* DDR3, DDR3L */
uint8_t ecc_enables; /* 0, 1 (memory size reduced to 7/8) */
uint8_t scrambling_enables; /* 0, 1 */
/* 1, 3 (1'st rank has to be populated if 2'nd rank present) */
uint32_t rank_enables;
uint32_t channel_enables; /* 1 only */
uint32_t channel_width; /* x16 only */
/* 0, 1, 2 (mode 2 forced if ecc enabled) */
uint32_t address_mode;
/* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */
uint8_t refresh_rate;
/* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */
uint8_t sr_temp_range;
/*
* RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED
* (select MRS1.DIC driver impedance control)
*/
uint8_t ron_value;
/* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
uint8_t rtt_nom_value;
/* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
uint8_t rd_odt_value;
struct dram_params params;
/* Internally used context parameters */
uint32_t board_id; /* board layout (use x8 or x16 memory) */
uint32_t hte_setup; /* when set hte reconfiguration requested */
uint32_t menu_after_mrc;
uint32_t power_down_disable;
uint32_t tune_rcvn;
uint32_t channel_size[NUM_CHANNELS];
uint32_t column_bits[NUM_CHANNELS];
uint32_t row_bits[NUM_CHANNELS];
uint32_t mrs1; /* register content saved during training */
uint8_t first_run;
/* Output parameters */
/* initialization result (non zero specifies error code) */
uint32_t status;
/* total memory size in bytes (excludes ECC banks) */
uint32_t mem_size;
/* training results (also used on input) */
struct mrc_timings timings;
};
/*
* MRC memory initialization structure
*
* post_code: a 16-bit post code of a specific initialization routine
* boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3
* init_fn: real memory initialization routine
*/
struct mem_init {
uint16_t post_code;
uint16_t boot_path;
void (*init_fn)(struct mrc_params *mrc_params);
};
/* MRC platform data flags */
#define MRC_FLAG_ECC_EN 0x00000001
#define MRC_FLAG_SCRAMBLE_EN 0x00000002
#define MRC_FLAG_MEMTEST_EN 0x00000004
/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
#define MRC_FLAG_TOP_TREE_EN 0x00000008
/* If set ODR signal is asserted to DRAM devices on writes */
#define MRC_FLAG_WR_ODT_EN 0x00000010
/**
* mrc_init - Memory Reference Code initialization entry routine
*
* @mrc_params: parameters for MRC
*/
void mrc_init(struct mrc_params *mrc_params);
#endif /* _MRC_H_ */