arm: rmobile: lager: Migrate serial driver to drivers model
This adds drivers model support of serial port to Lager board, and migrate serial port to drivers model. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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@ -11,6 +11,8 @@
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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@ -189,3 +191,15 @@ void reset_cpu(ulong addr)
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val |= 0x02;
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i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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}
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static const struct sh_serial_platdata serial_platdata = {
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.base = SCIF0_BASE,
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.type = PORT_SCIF,
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.clk = 14745600,
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.clk_mode = EXT_CLK,
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};
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U_BOOT_DEVICE(lager_serials) = {
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.name = "serial_sh",
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.platdata = &serial_platdata,
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};
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@ -1,3 +1,5 @@
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CONFIG_ARM=y
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CONFIG_RMOBILE=y
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CONFIG_TARGET_LAGER=y
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CONFIG_DM=y
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CONFIG_DM_SERIAL=y
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@ -39,8 +39,6 @@
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE
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#define CONFIG_CONS_SCIF0
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#define CONFIG_SCIF_USE_EXT_CLK
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/* SPI */
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#define CONFIG_SPI
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@ -83,7 +81,6 @@
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#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
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#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
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#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
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#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */
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#define CONFIG_SYS_TMU_CLK_DIV 4
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