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Exynos542x: Add workaround for ARM errata 798870

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This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Akshay Saraswat 2015-02-20 13:27:13 +05:30 committed by Minkyu Kang
parent ac0d98cd55
commit 0c08baf053
1 changed files with 16 additions and 0 deletions
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16
arch/arm/include/asm/armv7.h
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@ -69,6 +69,22 @@
#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
/*
* Workaround for ARM errata # 798870
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
* stalled for 1024 cycles to verify that its hazard condition still exists.
*/
static inline void v7_enable_l2_hazard_detect(void)
{
uint32_t val;
/* L2ACTLR[7]: Enable hazard detect timeout */
asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
val |= (1 << 7);
asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
}
void v7_en_l2_hazard_detect(void);
void v7_outer_cache_enable(void);
void v7_outer_cache_disable(void);
void v7_outer_cache_flush_all(void);