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ARM: remove a320evb board support

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This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Po-Yu Chuang <ratbert@faraday-tech.com>
Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Masahiro Yamada 2015-02-24 11:45:08 +09:00 committed by Tom Rini
parent a2f39e830e
commit 29fc6f2492
14 changed files with 1 additions and 573 deletions
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5
arch/arm/Kconfig
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@ -73,10 +73,6 @@ config TARGET_INTEGRATORCP_CM920T
bool "Support integratorcp_cm920t"
select CPU_ARM920T
config TARGET_A320EVB
bool "Support a320evb"
select CPU_ARM920T
config ARCH_AT91
bool "Atmel AT91"
@ -770,7 +766,6 @@ source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/faraday/a320evb/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"

1
arch/arm/cpu/arm920t/Makefile
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@ -10,7 +10,6 @@ extra-y = start.o
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
obj-$(if $(filter a320,$(SOC)),y) += a320/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
obj-$(CONFIG_S3C24X0) += s3c24x0/

9
arch/arm/cpu/arm920t/a320/Makefile
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@ -1,9 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += reset.o
obj-y += timer.o

10
arch/arm/cpu/arm920t/a320/reset.S
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@ -1,10 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
.global reset_cpu
reset_cpu:
b reset_cpu

118
arch/arm/cpu/arm920t/a320/timer.c
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@ -1,118 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <faraday/ftpmu010.h>
#include <faraday/fttmr010.h>
DECLARE_GLOBAL_DATA_PTR;
#define TIMER_CLOCK 32768
#define TIMER_LOAD_VAL 0xffffffff
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, gd->arch.timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
usec *= gd->arch.timer_rate_hz;
do_div(usec, 1000000);
return usec;
}
int timer_init(void)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
unsigned int cr;
debug("%s()\n", __func__);
/* disable timers */
writel(0, &tmr->cr);
/* use 32768Hz oscillator for RTC, WDT, TIMER */
ftpmu010_32768osc_enable();
/* setup timer */
writel(TIMER_LOAD_VAL, &tmr->timer3_load);
writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
writel(0, &tmr->timer3_match1);
writel(0, &tmr->timer3_match2);
/* we don't want timer to issue interrupts */
writel(FTTMR010_TM3_MATCH1 |
FTTMR010_TM3_MATCH2 |
FTTMR010_TM3_OVERFLOW,
&tmr->interrupt_mask);
cr = readl(&tmr->cr);
cr |= FTTMR010_TM3_CLOCK; /* use external clock */
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
gd->arch.timer_rate_hz = TIMER_CLOCK;
gd->arch.tbu = gd->arch.tbl = 0;
return 0;
}
/*
* Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
/* increment tbu if tbl has rolled over */
if (now < gd->arch.tbl)
gd->arch.tbu++;
gd->arch.tbl = now;
return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
void __udelay(unsigned long usec)
{
unsigned long long start;
ulong tmo;
start = get_ticks(); /* get current timestamp */
tmo = usec_to_tick(usec); /* convert usecs to ticks */
while ((get_ticks() - start) < tmo)
; /* loop till time has passed */
}
/*
* get_timer(base) can be used to check for timeouts or
* to measure elasped time relative to an event:
*
* ulong start_time = get_timer(0) sets start_time to the current
* time value.
* get_timer(start_time) returns the time elapsed since then.
*
* The time is used in CONFIG_SYS_HZ units!
*/
ulong get_timer(ulong base)
{
return tick_to_time(get_ticks()) - base;
}
/*
* Return the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return gd->arch.timer_rate_hz;
}

22
arch/arm/include/asm/arch-a320/a320.h
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@ -1,22 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __A320_H
#define __A320_H
/*
* Hardware register bases
*/
#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
#endif /* __A320_H */

15
board/faraday/a320evb/Kconfig
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@ -1,15 +0,0 @@
if TARGET_A320EVB
config SYS_BOARD
default "a320evb"
config SYS_VENDOR
default "faraday"
config SYS_SOC
default "a320"
config SYS_CONFIG_NAME
default "a320evb"
endif

6
board/faraday/a320evb/MAINTAINERS
View File

@ -1,6 +0,0 @@
A320EVB BOARD
M: Po-Yu Chuang <ratbert@faraday-tech.com>
S: Maintained
F: board/faraday/a320evb/
F: include/configs/a320evb.h
F: configs/a320evb_defconfig

9
board/faraday/a320evb/Makefile
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@ -1,9 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := a320evb.o
obj-y += lowlevel_init.o

59
board/faraday/a320evb/a320evb.c
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@ -1,59 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <faraday/ftsmc020.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
ftsmc020_init(); /* initialize Flash */
return 0;
}
int dram_init(void)
{
unsigned long sdram_base = PHYS_SDRAM_1;
unsigned long expected_size = PHYS_SDRAM_1_SIZE;
unsigned long actual_size;
actual_size = get_ram_size((void *)sdram_base, expected_size);
gd->ram_size = actual_size;
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return 0;
}
int board_eth_init(bd_t *bd)
{
return ftmac100_initialize(bd);
}
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->interface = FLASH_CFI_X8;
return 1;
} else
return 0;
}

106
board/faraday/a320evb/lowlevel_init.S
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@ -1,106 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <version.h>
#include <asm/macro.h>
#include <faraday/ftsdmc020.h>
/*
* parameters for the SDRAM controller
*/
#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
#define TP0_D CONFIG_SYS_FTSDMC020_TP0
#define TP1_D CONFIG_SYS_FTSDMC020_TP1
#define CR_D1 FTSDMC020_CR_IPREC
#define CR_D2 FTSDMC020_CR_ISMR
#define CR_D3 FTSDMC020_CR_IREF
#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
#define ACR_D FTSDMC020_ACR_TOC(0x18)
/*
* numeric 7 segment display
*/
.macro led, num
write32 CONFIG_DEBUG_LED, \num
.endm
/*
* Waiting for SDRAM to set up
*/
.macro wait_sdram
ldr r0, =CONFIG_FTSDMC020_BASE
1:
ldr r1, [r0, #FTSDMC020_OFFSET_CR]
cmp r1, #0
bne 1b
.endm
.globl lowlevel_init
lowlevel_init:
mov r11, lr
led 0x0
bl init_sdmc
led 0x1
/* everything is fine now */
mov lr, r11
mov pc, lr
/*
* memory initialization
*/
init_sdmc:
led 0x10
/* set SDRAM register */
write32 TP0_A, TP0_D
led 0x11
write32 TP1_A, TP1_D
led 0x12
/* set to precharge */
write32 CR_A, CR_D1
led 0x13
wait_sdram
led 0x14
/* set mode register */
write32 CR_A, CR_D2
led 0x15
wait_sdram
led 0x16
/* set to refresh */
write32 CR_A, CR_D3
led 0x17
wait_sdram
led 0x18
write32 B0_BSR_A, B0_BSR_D
led 0x19
write32 ACR_A, ACR_D
led 0x1a
mov pc, lr

2
configs/a320evb_defconfig
View File

@ -1,2 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_A320EVB=y

1
doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
cm41xx arm arm920t - -
dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>

211
include/configs/a320evb.h
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@ -1,211 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* Configuation settings for the Faraday A320 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/a320.h>
/*
* mach-type definition
*/
#define MACH_TYPE_FARADAY 758
#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY
/*
* Linux kernel tagged list
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/*
* CPU and Board Configuration Options
*/
#undef CONFIG_SKIP_LOWLEVEL_INIT
/*
* Power Management Unit
*/
#define CONFIG_FTPMU010_POWER
/*
* Timer
*/
/*
* Real Time Clock
*/
#define CONFIG_RTC_FTRTC010
/*
* Serial console configuration
*/
/* FTUART is a high speed NS 16C550A compatible UART */
#define CONFIG_BAUDRATE 38400
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 0x98200000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_CLK 18432000
/*
* Ethernet
*/
#define CONFIG_FTMAC100
#define CONFIG_BOOTDELAY 3
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PING
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
/*
* SDRAM controller configuration
*/
#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
FTSDMC020_TP0_TRP(1) | \
FTSDMC020_TP0_TRCD(1) | \
FTSDMC020_TP0_TRF(3) | \
FTSDMC020_TP0_TWR(1) | \
FTSDMC020_TP0_TCL(2))
#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
FTSDMC020_TP1_INI_REFT(8) | \
FTSDMC020_TP1_REF_INTV(0x180))
#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
FTSDMC020_BANK_DDW_X16 | \
FTSDMC020_BANK_DSZ_256M | \
FTSDMC020_BANK_MBW_32 | \
FTSDMC020_BANK_SIZE_64M)
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
/*
* Load address and memory test area should agree with
* board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
*/
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
#define CONFIG_SYS_TEXT_BASE 0
/*
* Static memory controller configuration
*/
#define CONFIG_FTSMC020
#include <faraday/ftsmc020.h>
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
FTSMC020_BANK_SIZE_1M | \
FTSMC020_BANK_MBW_8)
#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
FTSMC020_TPR_AST(3) | \
FTSMC020_TPR_CTW(3) | \
FTSMC020_TPR_ATI(0xf) | \
FTSMC020_TPR_AT2(3) | \
FTSMC020_TPR_WTC(3) | \
FTSMC020_TPR_AHT(3) | \
FTSMC020_TPR_TRNA(0xf))
#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
FTSMC020_BANK_SIZE_32M | \
FTSMC020_BANK_MBW_32)
#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
FTSMC020_TPR_CTW(3) | \
FTSMC020_TPR_ATI(0xf) | \
FTSMC020_TPR_AT2(3) | \
FTSMC020_TPR_WTC(3) | \
FTSMC020_TPR_AHT(3) | \
FTSMC020_TPR_TRNA(0xf))
#define CONFIG_SYS_FTSMC020_CONFIGS { \
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
}
/*
* FLASH and environment organization
*/
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* support JEDEC */
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx8
#define PHYS_FLASH_1 0x00000000
#define PHYS_FLASH_2 0x00400000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_BANKS 2
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#undef CONFIG_SYS_FLASH_EMPTY_INFO
/* environments */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
#define CONFIG_ENV_SIZE 0x20000
#endif /* __CONFIG_H */