fsl/ls1021qds: Add deep sleep support

Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
tang yuantian 2014-12-17 12:58:05 +08:00 committed by York Sun
parent 55d53ab45e
commit 41ba57d0c7
4 changed files with 69 additions and 1 deletions

View File

@ -124,6 +124,25 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
#define UBOOT_HEAD_LEN 0x1000
/*
* Reserved memory in SD boot deep sleep case.
* Second stage uboot binary and malloc space should be reserved.
* If the memory they occupied has not been reserved, then this
* space would be used by kernel and overwritten in uboot when
* deep sleep resume, which cause deep sleep failed.
* Since second uboot binary has a head, that space need to be
* reserved either(assuming its size is less than 0x1000).
*/
off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
UBOOT_HEAD_LEN);
if (off < 0)
printf("Failed to reserve memory for SD boot deep sleep: %s\n",
fdt_strerror(off));
#endif
#if defined(CONFIG_FSL_ESDHC)
fdt_fixup_esdhc(blob, bd);
#endif

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@ -7,6 +7,7 @@
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@ -149,6 +150,17 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
}
#endif
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
void __iomem *qixis_base = (void *)QIXIS_BASE;
/* does not provide HW signals for power management */
clrbits_8(qixis_base + 0x21, 0x2);
udelay(1);
}
#endif
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@ -159,6 +171,11 @@ phys_size_t initdram(int board_type)
#else
dram_size = fsl_ddr_sdram_size();
#endif
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
return dram_size;
}

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@ -20,6 +20,7 @@
#include <fsl_sec.h>
#include <spl.h>
#include "../common/sleep.h"
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
#ifdef CONFIG_U_QE
@ -218,6 +219,11 @@ int board_early_init_f(void)
* allow barrier transaction to DDR again */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
return 0;
}
@ -251,6 +257,11 @@ void board_init_f(ulong dummy)
get_clocks();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
@ -544,6 +555,21 @@ int board_init(void)
return 0;
}
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_LS102XA_NS_ACCESS
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
#endif
}
#endif
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);

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@ -19,6 +19,11 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
#endif
/*
* Size of malloc() pool
*/
@ -72,7 +77,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SPL_PAD_TO 0x1c000
#define CONFIG_SYS_TEXT_BASE 0x82000000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000