MIPS: handle mips64 ST0_KX bit in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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@ -23,6 +23,7 @@
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#ifdef CONFIG_32BIT
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# define MIPS_RELOC 3
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# define STATUS_SET 0
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#endif
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#ifdef CONFIG_64BIT
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@ -34,6 +35,7 @@
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((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
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# endif
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# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
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# define STATUS_SET ST0_KX
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#endif
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/*
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@ -120,7 +122,7 @@ reset:
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/* WP(Watch Pending), SW0/1 should be cleared */
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mtc0 zero, CP0_CAUSE
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setup_c0_status 0 0
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setup_c0_status STATUS_SET 0
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/* Init Timer */
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mtc0 zero, CP0_COUNT
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