dm: sh: serial: Add support driver model
This adds driver model support with this driver. This was tested by Koelsch board and Gose board. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Nobuhiro Iwamatsu
Simon Glass
parent
0f36f957f4
commit
59088e4a76
@ -1,18 +1,216 @@
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/*
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* SuperH SCIF device driver.
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
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* Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
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* Copyright (C) 2002 - 2008 Paul Mundt
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include "serial_sh.h"
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#include <serial.h>
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#include <linux/compiler.h>
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#include <dm/platform_data/serial_sh.h>
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#include "serial_sh.h"
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#if defined(CONFIG_CPU_SH7760) || \
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defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7785) || \
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defined(CONFIG_CPU_SH7786)
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static int scif_rxfill(struct uart_port *port)
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{
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return sci_in(port, SCRFDR) & 0xff;
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}
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#elif defined(CONFIG_CPU_SH7763)
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static int scif_rxfill(struct uart_port *port)
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{
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if ((port->mapbase == 0xffe00000) ||
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(port->mapbase == 0xffe08000)) {
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/* SCIF0/1*/
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return sci_in(port, SCRFDR) & 0xff;
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} else {
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/* SCIF2 */
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return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
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}
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}
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#elif defined(CONFIG_ARCH_SH7372)
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static int scif_rxfill(struct uart_port *port)
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{
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if (port->type == PORT_SCIFA)
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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else
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return sci_in(port, SCRFDR);
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}
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#else
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static int scif_rxfill(struct uart_port *port)
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{
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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}
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#endif
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static void sh_serial_init_generic(struct uart_port *port)
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{
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sci_out(port, SCSCR , SCSCR_INIT(port));
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sci_out(port, SCSCR , SCSCR_INIT(port));
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sci_out(port, SCSMR, 0);
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sci_out(port, SCSMR, 0);
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sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
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sci_in(port, SCFCR);
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sci_out(port, SCFCR, 0);
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}
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static void
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sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
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{
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if (port->clk_mode == EXT_CLK) {
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unsigned short dl = DL_VALUE(baudrate, clk);
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sci_out(port, DL, dl);
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/* Need wait: Clock * 1/dl $B!_(B 1/16 */
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udelay((1000000 * dl * 16 / clk) * 1000 + 1);
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} else {
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sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
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}
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}
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static void handle_error(struct uart_port *port)
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{
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sci_in(port, SCxSR);
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sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
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sci_in(port, SCLSR);
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sci_out(port, SCLSR, 0x00);
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}
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static int serial_raw_putc(struct uart_port *port, const char c)
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{
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/* Tx fifo is empty */
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if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
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return -EAGAIN;
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sci_out(port, SCxTDR, c);
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sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
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return 0;
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}
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static int serial_rx_fifo_level(struct uart_port *port)
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{
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return scif_rxfill(port);
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}
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static int sh_serial_tstc_generic(struct uart_port *port)
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{
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if (sci_in(port, SCxSR) & SCIF_ERRORS) {
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handle_error(port);
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return 0;
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}
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return serial_rx_fifo_level(port) ? 1 : 0;
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}
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static int serial_getc_check(struct uart_port *port)
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{
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unsigned short status;
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status = sci_in(port, SCxSR);
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if (status & SCIF_ERRORS)
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handle_error(port);
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if (sci_in(port, SCLSR) & SCxSR_ORER(port))
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handle_error(port);
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return status & (SCIF_DR | SCxSR_RDxF(port));
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}
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static int sh_serial_getc_generic(struct uart_port *port)
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{
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unsigned short status;
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char ch;
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if (!serial_getc_check(port))
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return -EAGAIN;
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ch = sci_in(port, SCxRDR);
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status = sci_in(port, SCxSR);
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sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
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if (status & SCIF_ERRORS)
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handle_error(port);
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if (sci_in(port, SCLSR) & SCxSR_ORER(port))
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handle_error(port);
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return ch;
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}
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#ifdef CONFIG_DM_SERIAL
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static int sh_serial_pending(struct udevice *dev, bool input)
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{
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struct uart_port *priv = dev_get_priv(dev);
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return sh_serial_tstc_generic(priv);
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}
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static int sh_serial_putc(struct udevice *dev, const char ch)
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{
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struct uart_port *priv = dev_get_priv(dev);
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return serial_raw_putc(priv, ch);
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}
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static int sh_serial_getc(struct udevice *dev)
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{
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struct uart_port *priv = dev_get_priv(dev);
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return sh_serial_getc_generic(priv);
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}
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static int sh_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct sh_serial_platdata *plat = dev_get_platdata(dev);
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struct uart_port *priv = dev_get_priv(dev);
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sh_serial_setbrg_generic(priv, plat->clk, baudrate);
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return 0;
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}
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static int sh_serial_probe(struct udevice *dev)
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{
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struct sh_serial_platdata *plat = dev_get_platdata(dev);
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struct uart_port *priv = dev_get_priv(dev);
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priv->membase = (unsigned char *)plat->base;
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priv->mapbase = plat->base;
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priv->type = plat->type;
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priv->clk_mode = plat->clk_mode;
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sh_serial_init_generic(priv);
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return 0;
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}
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static const struct dm_serial_ops sh_serial_ops = {
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.putc = sh_serial_putc,
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.pending = sh_serial_pending,
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.getc = sh_serial_getc,
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.setbrg = sh_serial_setbrg,
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};
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U_BOOT_DRIVER(serial_sh) = {
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.name = "serial_sh",
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.id = UCLASS_SERIAL,
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.probe = sh_serial_probe,
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.ops = &sh_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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.priv_auto_alloc_size = sizeof(struct uart_port),
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};
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#else /* CONFIG_DM_SERIAL */
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#if defined(CONFIG_CONS_SCIF0)
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# define SCIF_BASE SCIF0_BASE
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@ -41,148 +239,66 @@
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#endif
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static struct uart_port sh_sci = {
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.membase = (unsigned char*)SCIF_BASE,
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.membase = (unsigned char *)SCIF_BASE,
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.mapbase = SCIF_BASE,
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.type = SCIF_BASE_PORT,
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#ifdef CONFIG_SCIF_USE_EXT_CLK
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.clk_mode = EXT_CLK,
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#endif
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};
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static void sh_serial_setbrg(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SCIF_USE_EXT_CLK
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unsigned short dl = DL_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ);
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sci_out(&sh_sci, DL, dl);
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/* Need wait: Clock * 1/dl $B!_(B 1/16 */
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udelay((1000000 * dl * 16 / CONFIG_SYS_CLK_FREQ) * 1000 + 1);
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#else
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sci_out(&sh_sci, SCBRR,
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SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ));
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#endif
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struct uart_port *port = &sh_sci;
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sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
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}
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static int sh_serial_init(void)
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{
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sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
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sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
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sci_out(&sh_sci, SCSMR, 0);
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sci_out(&sh_sci, SCSMR, 0);
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sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
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sci_in(&sh_sci, SCFCR);
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sci_out(&sh_sci, SCFCR, 0);
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struct uart_port *port = &sh_sci;
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sh_serial_init_generic(port);
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serial_setbrg();
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return 0;
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}
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#if defined(CONFIG_CPU_SH7760) || \
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defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7785) || \
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defined(CONFIG_CPU_SH7786)
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static int scif_rxfill(struct uart_port *port)
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{
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return sci_in(port, SCRFDR) & 0xff;
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}
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#elif defined(CONFIG_CPU_SH7763)
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static int scif_rxfill(struct uart_port *port)
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{
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if ((port->mapbase == 0xffe00000) ||
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(port->mapbase == 0xffe08000)) {
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/* SCIF0/1*/
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return sci_in(port, SCRFDR) & 0xff;
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} else {
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/* SCIF2 */
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return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
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}
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}
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#elif defined(CONFIG_ARCH_SH7372)
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static int scif_rxfill(struct uart_port *port)
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{
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if (port->type == PORT_SCIFA)
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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else
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return sci_in(port, SCRFDR);
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}
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#else
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static int scif_rxfill(struct uart_port *port)
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{
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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}
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#endif
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static int serial_rx_fifo_level(void)
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{
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return scif_rxfill(&sh_sci);
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}
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static void handle_error(void)
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{
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sci_in(&sh_sci, SCxSR);
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sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci));
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sci_in(&sh_sci, SCLSR);
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sci_out(&sh_sci, SCLSR, 0x00);
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}
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static void serial_raw_putc(const char c)
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{
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while (1) {
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/* Tx fifo is empty */
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if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci))
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break;
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}
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sci_out(&sh_sci, SCxTDR, c);
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sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
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}
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static void sh_serial_putc(const char c)
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{
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if (c == '\n')
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serial_raw_putc('\r');
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serial_raw_putc(c);
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struct uart_port *port = &sh_sci;
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if (c == '\n') {
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while (1) {
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if (serial_raw_putc(port, '\r') != -EAGAIN)
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break;
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}
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}
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while (1) {
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if (serial_raw_putc(port, c) != -EAGAIN)
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break;
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}
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}
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static int sh_serial_tstc(void)
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{
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if (sci_in(&sh_sci, SCxSR) & SCIF_ERRORS) {
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handle_error();
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return 0;
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}
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struct uart_port *port = &sh_sci;
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return serial_rx_fifo_level() ? 1 : 0;
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}
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static int serial_getc_check(void)
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{
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unsigned short status;
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status = sci_in(&sh_sci, SCxSR);
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if (status & SCIF_ERRORS)
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handle_error();
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if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
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handle_error();
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return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
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return sh_serial_tstc_generic(port);
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}
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static int sh_serial_getc(void)
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{
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unsigned short status;
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char ch;
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struct uart_port *port = &sh_sci;
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int ch;
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while (!serial_getc_check())
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;
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while (1) {
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ch = sh_serial_getc_generic(port);
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if (ch != -EAGAIN)
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break;
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}
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ch = sci_in(&sh_sci, SCxRDR);
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status = sci_in(&sh_sci, SCxSR);
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sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci));
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if (status & SCIF_ERRORS)
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handle_error();
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if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
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handle_error();
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return ch;
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}
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@ -206,3 +322,4 @@ __weak struct serial_device *default_serial_console(void)
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{
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return &sh_serial_drv;
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}
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#endif /* CONFIG_DM_SERIAL */
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@ -2,18 +2,16 @@
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* Copy and modify from linux/drivers/serial/sh-sci.h
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*/
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#include <dm/platform_data/serial_sh.h>
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struct uart_port {
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unsigned long iobase; /* in/out[bwl] */
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unsigned char *membase; /* read/write[bwl] */
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unsigned long mapbase; /* for ioremap */
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unsigned int type; /* port type */
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enum sh_serial_type type; /* port type */
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enum sh_clk_mode clk_mode; /* clock mode */
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};
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#define PORT_SCI 52
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#define PORT_SCIF 53
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#define PORT_SCIFA 83
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#define PORT_SCIFB 93
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#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
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#include <asm/regs306x.h>
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#endif
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@ -526,6 +524,7 @@ SCIF_FNS(SCFDR, 0x1c, 16)
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SCIF_FNS(SCxTDR, 0x20, 8)
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SCIF_FNS(SCxRDR, 0x24, 8)
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SCIF_FNS(SCLSR, 0x00, 0)
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SCIF_FNS(DL, 0x00, 0) /* dummy */
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#elif defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_R8A7740)
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SCIF_FNS(SCSMR, 0x00, 16)
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@ -541,6 +540,7 @@ SCIF_FNS(SCRFDR, 0x3c, 16)
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SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
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SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
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SCIF_FNS(SCLSR, 0x00, 0)
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SCIF_FNS(DL, 0x00, 0) /* dummy */
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#elif defined(CONFIG_CPU_SH7723) ||\
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defined(CONFIG_CPU_SH7724)
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SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
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@ -555,6 +555,7 @@ SCIF_FNS(SCFER, 0x10, 16)
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SCIF_FNS(SCFCR, 0x18, 16)
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SCIF_FNS(SCFDR, 0x1c, 16)
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SCIF_FNS(SCLSR, 0x24, 16)
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SCIF_FNS(DL, 0x00, 0) /* dummy */
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#else
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/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
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/* name off sz off sz off sz off sz off sz*/
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@ -583,18 +584,21 @@ SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
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SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
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SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
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#else
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SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
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#if defined(CONFIG_CPU_SH7722)
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SCIF_FNS(SCSPTR, 0, 0, 0, 0)
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#else
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SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
|
||||
#endif
|
||||
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
|
||||
#endif
|
||||
#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
||||
SCIF_FNS(DL, 0, 0, 0x30, 16)
|
||||
SCIF_FNS(CKS, 0, 0, 0x34, 16)
|
||||
#endif
|
||||
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
|
||||
#else
|
||||
SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
|
||||
#endif
|
||||
#endif
|
||||
#define sci_in(port, reg) sci_##reg##_in(port)
|
||||
@ -725,14 +729,14 @@ static inline int sci_rxd_in(struct uart_port *port)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SH7723) ||\
|
||||
defined(CONFIG_CPU_SH7724)
|
||||
static inline int scbrr_calc(struct uart_port port, int bps, int clk)
|
||||
static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
|
||||
{
|
||||
if (port.type == PORT_SCIF)
|
||||
if (port->type == PORT_SCIF)
|
||||
return (clk+16*bps)/(32*bps)-1;
|
||||
else
|
||||
return ((clk*2)+16*bps)/(16*bps)-1;
|
||||
}
|
||||
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
|
||||
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
@ -742,3 +746,7 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
|
||||
#else /* Generic SH */
|
||||
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
|
||||
#endif
|
||||
|
||||
#ifndef DL_VALUE
|
||||
#define DL_VALUE(bps, clk) 0
|
||||
#endif
|
||||
|
||||
37
include/dm/platform_data/serial_sh.h
Normal file
37
include/dm/platform_data/serial_sh.h
Normal file
@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
* Copyright (c) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __serial_sh_h
|
||||
#define __serial_sh_h
|
||||
|
||||
enum sh_clk_mode {
|
||||
INT_CLK,
|
||||
EXT_CLK,
|
||||
};
|
||||
|
||||
enum sh_serial_type {
|
||||
PORT_SCI,
|
||||
PORT_SCIF,
|
||||
PORT_SCIFA,
|
||||
PORT_SCIFB,
|
||||
};
|
||||
|
||||
/*
|
||||
* Information about SCIF port
|
||||
*
|
||||
* @base: Register base address
|
||||
* @clk: Input clock rate, used for calculating the baud rate divisor
|
||||
* @clk_mode: Clock mode, set internal (INT) or external (EXT)
|
||||
* @type: Type of SCIF
|
||||
*/
|
||||
struct sh_serial_platdata {
|
||||
unsigned long base;
|
||||
unsigned int clk;
|
||||
enum sh_clk_mode clk_mode;
|
||||
enum sh_serial_type type;
|
||||
};
|
||||
#endif /* __serial_sh_h */
|
||||
Loading…
Reference in New Issue
Block a user