sunxi: video: Add DDC & EDID support
Add DDC & EDID support and use it to automatically select the native mode of the attached monitor. This can be disabled by adding edid=0 as option to the video-mode env. variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Hans de Goede
parent
518cef20f8
commit
75481607c7
@ -107,6 +107,48 @@ struct sunxi_hdmi_reg {
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u32 pad_ctrl1; /* 0x204 */
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u32 pll_ctrl; /* 0x208 */
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u32 pll_dbg0; /* 0x20c */
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u32 pll_dbg1; /* 0x210 */
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u32 hpd_cec; /* 0x214 */
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u8 res1[0x28]; /* 0x218 */
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u32 spd_pkt; /* 0x240 */
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u8 res2[0xac]; /* 0x244 */
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u32 pkt_ctrl0; /* 0x2f0 */
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u32 pkt_ctrl1; /* 0x2f4 */
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u8 res3[0x18]; /* 0x2f8 */
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u32 audio_sample_count; /* 0x310 */
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u8 res4[0xec]; /* 0x314 */
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u32 audio_tx_fifo; /* 0x400 */
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u8 res5[0xfc]; /* 0x404 */
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#ifndef CONFIG_MACH_SUN6I
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u32 ddc_ctrl; /* 0x500 */
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u32 ddc_addr; /* 0x504 */
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u32 ddc_int_mask; /* 0x508 */
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u32 ddc_int_status; /* 0x50c */
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u32 ddc_fifo_ctrl; /* 0x510 */
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u32 ddc_fifo_status; /* 0x514 */
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u32 ddc_fifo_data; /* 0x518 */
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u32 ddc_byte_count; /* 0x51c */
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u32 ddc_cmnd; /* 0x520 */
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u32 ddc_exreg; /* 0x524 */
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u32 ddc_clock; /* 0x528 */
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u8 res6[0x14]; /* 0x52c */
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u32 ddc_line_ctrl; /* 0x540 */
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#else
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u32 ddc_ctrl; /* 0x500 */
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u32 ddc_exreg; /* 0x504 */
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u32 ddc_cmnd; /* 0x508 */
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u32 ddc_addr; /* 0x50c */
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u32 ddc_int_mask; /* 0x510 */
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u32 ddc_int_status; /* 0x514 */
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u32 ddc_fifo_ctrl; /* 0x518 */
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u32 ddc_fifo_status; /* 0x51c */
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u32 ddc_clock; /* 0x520 */
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u32 ddc_timeout; /* 0x524 */
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u8 res6[0x18]; /* 0x528 */
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u32 ddc_dbg; /* 0x540 */
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u8 res7[0x3c]; /* 0x544 */
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u32 ddc_fifo_data; /* 0x580 */
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#endif
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};
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/*
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@ -182,6 +224,49 @@ struct sunxi_hdmi_reg {
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#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
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#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0)
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#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4)
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#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6)
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#define SUNXI_HMDI_DDC_CTRL_START (1 << 27)
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#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31)
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#else
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#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0)
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/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
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#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0
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#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0
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#define SUNXI_HMDI_DDC_CTRL_START (1 << 30)
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#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31)
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#endif
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0)
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#else
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#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0)
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#endif
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#define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8)
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#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16)
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#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24)
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15)
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#else
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#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31)
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#endif
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#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6
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#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HDMI_DDC_CLOCK 0x61
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#else
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/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
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#define SUNXI_HDMI_DDC_CLOCK 0x0d
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#endif
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#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8)
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#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9)
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int sunxi_simplefb_setup(void *blob);
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#endif /* _SUNXI_DISPLAY_H */
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@ -13,6 +13,7 @@
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#include <asm/arch/display.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <fdt_support.h>
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#include <video_fb.h>
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@ -25,6 +26,22 @@ struct sunxi_display {
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bool enabled;
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} sunxi_display;
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/*
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* Wait up to 200ms for value to be set in given part of reg.
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*/
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static int await_completion(u32 *reg, u32 mask, u32 val)
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{
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unsigned long tmo = timer_get_us() + 200000;
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while ((readl(reg) & mask) != val) {
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if (timer_get_us() > tmo) {
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printf("DDC: timeout reading EDID\n");
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return -ETIME;
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}
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}
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return 0;
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}
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static int sunxi_hdmi_hpd_detect(void)
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{
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struct sunxi_ccm_reg * const ccm =
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@ -72,6 +89,133 @@ static void sunxi_hdmi_shutdown(void)
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clock_set_pll3(0);
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}
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static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
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{
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struct sunxi_hdmi_reg * const hdmi =
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(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
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setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
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writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
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SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
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SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
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SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
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#ifndef CONFIG_MACH_SUN6I
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writel(n, &hdmi->ddc_byte_count);
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writel(cmnd, &hdmi->ddc_cmnd);
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#else
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writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
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#endif
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setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
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return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
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}
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static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
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{
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struct sunxi_hdmi_reg * const hdmi =
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(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
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int i, n;
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while (count > 0) {
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if (count > 16)
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n = 16;
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else
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n = count;
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if (sunxi_hdmi_ddc_do_command(
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SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
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offset, n))
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return -ETIME;
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for (i = 0; i < n; i++)
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*buf++ = readb(&hdmi->ddc_fifo_data);
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offset += n;
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count -= n;
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}
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return 0;
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}
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static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
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{
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struct edid1_info edid1;
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struct edid_detailed_timing *t =
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(struct edid_detailed_timing *)edid1.monitor_details.timing;
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struct sunxi_hdmi_reg * const hdmi =
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(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int i, r, retries = 2;
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/* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
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writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
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&hdmi->pad_ctrl1);
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writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
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&hdmi->pll_ctrl);
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writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
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/* Reset i2c controller */
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setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
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writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
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SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
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SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
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SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
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if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
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return -EIO;
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writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
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#ifndef CONFIG_MACH_SUN6I
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writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
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SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
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#endif
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do {
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r = sunxi_hdmi_ddc_read(0, (u8 *)&edid1, 128);
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if (r)
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continue;
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r = edid_check_checksum((u8 *)&edid1);
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if (r) {
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printf("EDID: checksum error%s\n",
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retries ? ", retrying" : "");
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}
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} while (r && retries--);
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/* Disable DDC engine, no longer needed */
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clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
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clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
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if (r)
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return r;
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r = edid_check_info(&edid1);
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if (r) {
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printf("EDID: invalid EDID data\n");
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return -EINVAL;
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}
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/* We want version 1.3 or 1.2 with detailed timing info */
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if (edid1.version != 1 || (edid1.revision < 3 &&
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!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
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printf("EDID: unsupported version %d.%d\n",
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edid1.version, edid1.revision);
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return -EINVAL;
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}
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/* Take the first usable detailed timing */
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for (i = 0; i < 4; i++, t++) {
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r = video_edid_dtd_to_ctfb_res_modes(t, mode);
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if (r == 0)
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break;
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}
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if (i == 4) {
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printf("EDID: no usable detailed timing found\n");
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return -ENOENT;
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}
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return 0;
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}
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/*
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* This is the entity that mixes and matches the different layers and inputs.
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* Allwinner calls it the back-end, but i like composer better.
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@ -363,9 +507,10 @@ void *video_hw_init(void)
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{
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static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
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const struct ctfb_res_modes *mode;
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struct ctfb_res_modes edid_mode;
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const char *options;
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unsigned int depth;
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int ret, hpd;
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int ret, hpd, edid;
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memset(&sunxi_display, 0, sizeof(struct sunxi_display));
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@ -375,6 +520,7 @@ void *video_hw_init(void)
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video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, &depth, &options);
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hpd = video_get_option_int(options, "hpd", 1);
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edid = video_get_option_int(options, "edid", 1);
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/* Always call hdp_detect, as it also enables various clocks, etc. */
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ret = sunxi_hdmi_hpd_detect();
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@ -385,6 +531,12 @@ void *video_hw_init(void)
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if (ret)
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printf("HDMI connected: ");
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/* Check edid if requested and we've a cable plugged in */
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if (edid && ret) {
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if (sunxi_hdmi_edid_get_mode(&edid_mode) == 0)
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mode = &edid_mode;
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}
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if (mode->vmode != FB_VMODE_NONINTERLACED) {
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printf("Only non-interlaced modes supported, falling back to 1024x768\n");
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mode = &res_mode_init[RES_MODE_1024x768];
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@ -216,6 +216,7 @@
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_STD_TIMINGS
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#define CONFIG_I2C_EDID
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/* allow both serial and cfb console. */
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#define CONFIG_CONSOLE_MUX
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