crypto/fsl - Add progressive hashing support using hardware acceleration.
Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
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4
Kconfig
4
Kconfig
@ -141,7 +141,9 @@ config FIT_SIGNATURE
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select RSA
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help
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This option enables signature verification of FIT uImages,
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using a hash signed and verified using RSA.
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using a hash signed and verified using RSA. If
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CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
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hashing is available using hardware, RSA library will use it.
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See doc/uImage.FIT/signature.txt for more details.
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config SYS_EXTRA_OPTIONS
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20
README
20
README
@ -3152,8 +3152,18 @@ CBFS (Coreboot Filesystem) support
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Enable the hash verify command (hash -v). This adds to code
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size a little.
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CONFIG_SHA1 - support SHA1 hashing
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CONFIG_SHA256 - support SHA256 hashing
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CONFIG_SHA1 - This option enables support of hashing using SHA1
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algorithm. The hash is calculated in software.
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CONFIG_SHA256 - This option enables support of hashing using
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SHA256 algorithm. The hash is calculated in software.
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CONFIG_SHA_HW_ACCEL - This option enables hardware acceleration
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for SHA1/SHA256 hashing.
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This affects the 'hash' command and also the
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hash_lookup_algo() function.
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CONFIG_SHA_PROG_HW_ACCEL - This option enables
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hardware-acceleration for SHA1/SHA256 progressive hashing.
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Data can be streamed in a block at a time and the hashing
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is performed in hardware.
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Note: There is also a sha1sum command, which should perhaps
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be deprecated in favour of 'hash sha1'.
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@ -3447,8 +3457,10 @@ FIT uImage format:
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CONFIG_FIT_SIGNATURE
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This option enables signature verification of FIT uImages,
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using a hash signed and verified using RSA. See
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doc/uImage.FIT/signature.txt for more details.
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using a hash signed and verified using RSA. If
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CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
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hashing is available using hardware, RSA library will use it.
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See doc/uImage.FIT/signature.txt for more details.
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WARNING: When relying on signed FIT images with required
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signature check the legacy image format is default
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@ -127,11 +127,21 @@ static struct hash_algo hash_algo[] = {
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SHA1_SUM_LEN,
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hw_sha1,
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CHUNKSZ_SHA1,
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#ifdef CONFIG_SHA_PROG_HW_ACCEL
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hw_sha_init,
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hw_sha_update,
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hw_sha_finish,
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#endif
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}, {
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"sha256",
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SHA256_SUM_LEN,
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hw_sha256,
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CHUNKSZ_SHA256,
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#ifdef CONFIG_SHA_PROG_HW_ACCEL
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hw_sha_init,
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hw_sha_update,
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hw_sha_finish,
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#endif
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},
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#endif
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#ifdef CONFIG_SHA1
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@ -10,6 +10,9 @@
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#include "jobdesc.h"
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#include "desc.h"
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#include "jr.h"
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#include "fsl_hash.h"
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#include <hw_sha.h>
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#include <asm-generic/errno.h>
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#define CRYPTO_MAX_ALG_NAME 80
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#define SHA1_DIGEST_SIZE 20
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@ -39,6 +42,122 @@ static struct caam_hash_template driver_hash[] = {
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},
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};
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static enum caam_hash_algos get_hash_type(struct hash_algo *algo)
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{
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if (!strcmp(algo->name, driver_hash[SHA1].name))
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return SHA1;
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else
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return SHA256;
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}
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/* Create the context for progressive hashing using h/w acceleration.
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*
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* @ctxp: Pointer to the pointer of the context for hashing
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* @caam_algo: Enum for SHA1 or SHA256
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* @return 0 if ok, -ENOMEM on error
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*/
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static int caam_hash_init(void **ctxp, enum caam_hash_algos caam_algo)
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{
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*ctxp = calloc(1, sizeof(struct sha_ctx));
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if (*ctxp == NULL) {
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debug("Cannot allocate memory for context\n");
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return -ENOMEM;
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}
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return 0;
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}
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/*
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* Update sg table for progressive hashing using h/w acceleration
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*
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* The context is freed by this function if an error occurs.
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* We support at most 32 Scatter/Gather Entries.
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*
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* @hash_ctx: Pointer to the context for hashing
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* @buf: Pointer to the buffer being hashed
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* @size: Size of the buffer being hashed
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* @is_last: 1 if this is the last update; 0 otherwise
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* @caam_algo: Enum for SHA1 or SHA256
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* @return 0 if ok, -EINVAL on error
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*/
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static int caam_hash_update(void *hash_ctx, const void *buf,
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unsigned int size, int is_last,
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enum caam_hash_algos caam_algo)
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{
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uint32_t final = 0;
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dma_addr_t addr = virt_to_phys((void *)buf);
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struct sha_ctx *ctx = hash_ctx;
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if (ctx->sg_num >= MAX_SG_32) {
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free(ctx);
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return -EINVAL;
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}
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#ifdef CONFIG_PHYS_64BIT
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ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32;
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#else
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ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0;
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#endif
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ctx->sg_tbl[ctx->sg_num].addr_lo = addr;
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sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag,
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(size & SG_ENTRY_LENGTH_MASK));
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ctx->sg_num++;
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if (is_last) {
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final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) |
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SG_ENTRY_FINAL_BIT;
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sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final);
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}
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return 0;
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}
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/*
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* Perform progressive hashing on the given buffer and copy hash at
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* destination buffer
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*
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* The context is freed after completion of hash operation.
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*
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* @hash_ctx: Pointer to the context for hashing
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* @dest_buf: Pointer to the destination buffer where hash is to be copied
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* @size: Size of the buffer being hashed
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* @caam_algo: Enum for SHA1 or SHA256
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* @return 0 if ok, -EINVAL on error
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*/
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static int caam_hash_finish(void *hash_ctx, void *dest_buf,
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int size, enum caam_hash_algos caam_algo)
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{
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uint32_t len = 0;
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struct sha_ctx *ctx = hash_ctx;
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int i = 0, ret = 0;
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if (size < driver_hash[caam_algo].digestsize) {
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free(ctx);
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return -EINVAL;
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}
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for (i = 0; i < ctx->sg_num; i++)
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len += (sec_in32(&ctx->sg_tbl[i].len_flag) &
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SG_ENTRY_LENGTH_MASK);
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inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len,
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ctx->hash,
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driver_hash[caam_algo].alg_type,
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driver_hash[caam_algo].digestsize,
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1);
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ret = run_descriptor_jr(ctx->sha_desc);
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if (ret)
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debug("Error %x\n", ret);
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else
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memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
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free(ctx);
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return ret;
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}
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int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
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unsigned char *pout, enum caam_hash_algos algo)
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{
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@ -48,7 +167,7 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
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desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
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if (!desc) {
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debug("Not enough memory for descriptor allocation\n");
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return -1;
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return -ENOMEM;
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}
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inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
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@ -75,3 +194,20 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
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if (caam_hash(pbuf, buf_len, pout, SHA1))
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printf("CAAM was not setup properly or it is faulty\n");
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}
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int hw_sha_init(struct hash_algo *algo, void **ctxp)
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{
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return caam_hash_init(ctxp, get_hash_type(algo));
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}
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int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
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unsigned int size, int is_last)
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{
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return caam_hash_update(ctx, buf, size, is_last, get_hash_type(algo));
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}
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int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
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int size)
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{
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return caam_hash_finish(ctx, dest_buf, size, get_hash_type(algo));
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}
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34
drivers/crypto/fsl/fsl_hash.h
Normal file
34
drivers/crypto/fsl/fsl_hash.h
Normal file
@ -0,0 +1,34 @@
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef _SHA_H
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#define _SHA_H
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#include <fsl_sec.h>
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#include <hash.h>
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#include "jr.h"
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/* We support at most 32 Scatter/Gather Entries.*/
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#define MAX_SG_32 32
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/*
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* Hash context contains the following fields
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* @sha_desc: Sha Descriptor
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* @sg_num: number of entries in sg table
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* @len: total length of buffer
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* @sg_tbl: sg entry table
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* @hash: index to the hash calculated
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*/
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struct sha_ctx {
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uint32_t sha_desc[64];
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uint32_t sg_num;
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uint32_t len;
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struct sg_entry sg_tbl[MAX_SG_32];
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u8 hash[HASH_MAX_DIGEST_SIZE];
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};
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#endif
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u32 jrcr;
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};
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/*
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* Scatter Gather Entry - Specifies the the Scatter Gather Format
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* related information
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*/
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struct sg_entry {
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#ifdef CONFIG_SYS_FSL_SEC_LE
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uint32_t addr_lo; /* Memory Address - lo */
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uint16_t addr_hi; /* Memory Address of start of buffer - hi */
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uint16_t reserved_zero;
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#else
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uint16_t reserved_zero;
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uint16_t addr_hi; /* Memory Address of start of buffer - hi */
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uint32_t addr_lo; /* Memory Address - lo */
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#endif
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uint32_t len_flag; /* Length of the data in the frame */
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#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
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#define SG_ENTRY_EXTENSION_BIT 0x80000000
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#define SG_ENTRY_FINAL_BIT 0x40000000
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uint32_t bpid_offset;
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#define SG_ENTRY_BPID_MASK 0x00FF0000
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#define SG_ENTRY_BPID_SHIFT 16
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#define SG_ENTRY_OFFSET_MASK 0x00001FFF
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#define SG_ENTRY_OFFSET_SHIFT 0
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};
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int sec_init(void);
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#endif
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*/
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#ifndef __HW_SHA_H
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#define __HW_SHA_H
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#include <hash.h>
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/**
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* Computes hash value of input pbuf using h/w acceleration
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@ -34,4 +34,43 @@ void hw_sha256(const uchar * in_addr, uint buflen,
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*/
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void hw_sha1(const uchar * in_addr, uint buflen,
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uchar * out_addr, uint chunk_size);
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/*
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* Create the context for sha progressive hashing using h/w acceleration
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*
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* @algo: Pointer to the hash_algo struct
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* @ctxp: Pointer to the pointer of the context for hashing
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* @return 0 if ok, -ve on error
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*/
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int hw_sha_init(struct hash_algo *algo, void **ctxp);
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/*
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* Update buffer for sha progressive hashing using h/w acceleration
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*
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* The context is freed by this function if an error occurs.
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*
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* @algo: Pointer to the hash_algo struct
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* @ctx: Pointer to the context for hashing
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* @buf: Pointer to the buffer being hashed
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* @size: Size of the buffer being hashed
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* @is_last: 1 if this is the last update; 0 otherwise
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* @return 0 if ok, -ve on error
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*/
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int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
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unsigned int size, int is_last);
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/*
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* Copy sha hash result at destination location
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*
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* The context is freed after completion of hash operation or after an error.
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*
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* @algo: Pointer to the hash_algo struct
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* @ctx: Pointer to the context for hashing
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* @dest_buf: Pointer to the destination buffer where hash is to be copied
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* @size: Size of the buffer being hashed
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* @return 0 if ok, -ve on error
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*/
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int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
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int size);
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#endif
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36
lib/Kconfig
36
lib/Kconfig
@ -29,4 +29,40 @@ config SYS_HZ
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source lib/rsa/Kconfig
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menu "Hashing Support"
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config SHA1
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bool "Enable SHA1 support"
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help
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This option enables support of hashing using SHA1 algorithm.
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The hash is calculated in software.
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The SHA1 algorithm produces a 160-bit (20-byte) hash value
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(digest).
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config SHA256
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bool "Enable SHA256 support"
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help
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This option enables support of hashing using SHA256 algorithm.
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The hash is calculated in software.
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The SHA256 algorithm produces a 256-bit (32-byte) hash value
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(digest).
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config SHA_HW_ACCEL
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bool "Enable hashing using hardware"
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help
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This option enables hardware acceleration
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for SHA1/SHA256 hashing.
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This affects the 'hash' command and also the
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hash_lookup_algo() function.
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config SHA_PROG_HW_ACCEL
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bool "Enable Progressive hashing support using hardware"
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depends on SHA_HW_ACCEL
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help
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This option enables hardware-acceleration for
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SHA1/SHA256 progressive hashing.
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Data can be streamed in a block at a time and the hashing
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is performed in hardware.
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endmenu
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endmenu
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