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Merge branch 'master' of git://git.denx.de/u-boot-ti

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This commit is contained in:
Tom Rini 2015-02-02 12:37:34 -05:00
commit 37ffffb98d
16 changed files with 253 additions and 73 deletions
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17
arch/arm/cpu/arm926ejs/davinci/spl.c
View File

@ -34,29 +34,14 @@ void putc(char c)
}
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
void board_init_f(ulong dummy)
void spl_board_init(void)
{
/* First, setup our stack pointer. */
asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
/* Second, perform our low-level init. */
#ifdef CONFIG_SOC_DM365
dm36x_lowlevel_init(0);
#endif
#ifdef CONFIG_SOC_DA8XX
arch_cpu_init();
#endif
/* Third, we clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* Finally, setup gd and move to the next step. */
gd = &gdata;
board_init_r(NULL, 0);
}
void spl_board_init(void)
{
preloader_console_init();
}

83
arch/arm/cpu/armv7/omap-common/clocks-common.c
View File

@ -437,12 +437,15 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
{
u32 offset_code;
u32 offset = volt_mv;
#ifndef CONFIG_DRA7XX
int ret = 0;
#endif
if (!volt_mv)
return;
pmic->pmic_bus_init();
#ifndef CONFIG_DRA7XX
/* See if we can first get the GPIO if needed */
if (pmic->gpio_en)
ret = gpio_request(pmic->gpio, "PMIC_GPIO");
@ -456,7 +459,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
/* Pull the GPIO low to select SET0 register, while we program SET1 */
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 0);
#endif
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
@ -467,9 +470,10 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
#ifndef CONFIG_DRA7XX
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 1);
#endif
}
static u32 optimize_vcore_voltage(struct volts const *v)
@ -505,13 +509,79 @@ static u32 optimize_vcore_voltage(struct volts const *v)
}
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
* Setup the voltages for the main SoC core power domains.
* We start with the maximum voltages allowed here, as set in the corresponding
* vcores_data struct, and then scale (usually down) to the fused values that
* are retrieved from the SoC. The scaling happens only if the efuse.reg fields
* are initialised.
* Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
* compiled conditionally. Note that the new code writes the scaled (or zeroed)
* values back to the vcores_data struct for eventual reuse. Zero values mean
* that the corresponding rails are not controlled separately, and are not sent
* to the PMIC.
*/
void scale_vcores(struct vcores_data const *vcores)
{
#if defined(CONFIG_DRA7XX)
int i;
struct volts *pv = (struct volts *)vcores;
struct volts *px;
for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
debug("%d -> ", pv->value);
if (pv->value) {
/* Handle non-empty members only */
pv->value = optimize_vcore_voltage(pv);
px = (struct volts *)vcores;
while (px < pv) {
/*
* Scan already handled non-empty members to see
* if we have a group and find the max voltage,
* which is set to the first occurance of the
* particular SMPS; the other group voltages are
* zeroed.
*/
if (px->value) {
if ((pv->pmic->i2c_slave_addr ==
px->pmic->i2c_slave_addr) &&
(pv->addr == px->addr)) {
/* Same PMIC, same SMPS */
if (pv->value > px->value)
px->value = pv->value;
pv->value = 0;
}
}
px++;
}
}
debug("%d\n", pv->value);
pv++;
}
debug("cor: %d\n", vcores->core.value);
do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
debug("mpu: %d\n", vcores->mpu.value);
do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
/* Configure MPU ABB LDO after scale */
abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
(*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
(*prcm)->prm_abbldo_mpu_setup,
(*prcm)->prm_abbldo_mpu_ctrl,
(*prcm)->prm_irqstatus_mpu_2,
OMAP_ABB_MPU_TXDONE_MASK,
OMAP_ABB_FAST_OPP);
/* The .mm member is not used for the DRA7xx */
debug("gpu: %d\n", vcores->gpu.value);
do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
debug("eve: %d\n", vcores->eve.value);
do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
debug("iva: %d\n", vcores->iva.value);
do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
/* Might need udelay(1000) here if debug is enabled to see all prints */
#else
u32 val;
val = optimize_vcore_voltage(&vcores->core);
@ -540,6 +610,7 @@ void scale_vcores(struct vcores_data const *vcores)
val = optimize_vcore_voltage(&vcores->iva);
do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
#endif
}
static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)

9
arch/arm/cpu/armv7/omap3/clock.c
View File

@ -732,11 +732,20 @@ void per_clocks_enable(void)
setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
/* Enable GP9 timer. */
setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */
setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */
setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clocks */
setbits_le32(&prcm_base->fclken1_core, 0x00002000);
setbits_le32(&prcm_base->iclken1_core, 0x00002000);
/* Enable UART2 clocks */
setbits_le32(&prcm_base->fclken1_core, 0x00004000);
setbits_le32(&prcm_base->iclken1_core, 0x00004000);
/* UART 3 Clocks */
setbits_le32(&prcm_base->fclken_per, 0x00000800);
setbits_le32(&prcm_base->iclken_per, 0x00000800);

6
arch/arm/cpu/armv7/omap3/sdrc.c
View File

@ -135,6 +135,9 @@ void do_sdrc_init(u32 cs, u32 early)
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
/* set some default timings */
timings.sharing = SDRC_SHARING;
/*
* When called in the early context this may be SPL and we will
* need to set all of the timings. This ends up being board
@ -145,6 +148,7 @@ void do_sdrc_init(u32 cs, u32 early)
* setup CS1.
*/
#ifdef CONFIG_SPL_BUILD
/* set/modify board-specific timings */
get_board_mem_timings(&timings);
#endif
if (early) {
@ -155,7 +159,7 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->sysconfig);
/* setup sdrc to ball mux */
writel(SDRC_SHARING, &sdrc_base->sharing);
writel(timings.sharing, &sdrc_base->sharing);
/* Disable Power Down of CKE because of 1 CKE on combo part */
writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,

45
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@ -320,6 +320,7 @@ struct pmic_data palmas = {
.pmic_write = omap_vc_bypass_send_value,
};
/* The TPS659038 and TPS65917 are software-compatible, use common struct */
struct pmic_data tps659038 = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
@ -394,34 +395,38 @@ struct vcores_data dra752_volts = {
};
struct vcores_data dra722_volts = {
.mpu.value = 1000,
.mpu.value = VDD_MPU_DRA72x,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = 0x23,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.eve.value = 1000,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = 0x2f,
.eve.pmic = &tps659038,
.gpu.value = 1000,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = 0x2f,
.gpu.pmic = &tps659038,
.core.value = 1000,
.core.value = VDD_CORE_DRA72x,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = 0x27,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
.iva.value = 1000,
/*
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
.gpu.value = VDD_GPU_DRA72x,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.eve.value = VDD_EVE_DRA72x,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.iva.value = VDD_IVA_DRA72x,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = 0x2f,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
};

43
arch/arm/include/asm/arch-omap3/mem.h
View File

@ -249,6 +249,49 @@ enum {
#define MICRON_RASWIDTH_200 14
#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
#define SAMSUNG_TDAL_165 5
#define SAMSUNG_TDPL_165 2
#define SAMSUNG_TRRD_165 2
#define SAMSUNG_TRCD_165 3
#define SAMSUNG_TRP_165 3
#define SAMSUNG_TRAS_165 7
#define SAMSUNG_TRC_165 10
#define SAMSUNG_TRFC_165 12
#define SAMSUNG_V_ACTIMA_165 \
ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
#define SAMSUNG_TWTR_165 1
#define SAMSUNG_TCKE_165 2
#define SAMSUNG_XSR_165 20
#define SAMSUNG_TXP_165 5
#define SAMSUNG_V_ACTIMB_165 \
ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
SAMSUNG_TXP_165, SAMSUNG_XSR_165)
#define SAMSUNG_RASWIDTH_165 14
#define SAMSUNG_V_MCFG_165(size) \
V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
/* TODO: find which register these were taken from */
#define SAMSUNG_BL_165 0x2
#define SAMSUNG_SIL_165 0x0
#define SAMSUNG_CASL_165 0x3
#define SAMSUNG_WBST_165 0x0
#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
(SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
(SAMSUNG_BL_165))
#define SAMSUNG_SHARING 0x00003700
/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
/* 15/6 + 18/6 = 5.5 -> 6 */

1
arch/arm/include/asm/arch-omap3/mmc_host_def.h
View File

@ -51,6 +51,7 @@ typedef struct t2 {
#define PBIASLITEPWRDNZ0 (1 << 1)
#define PBIASSPEEDCTRL0 (1 << 2)
#define PBIASLITEPWRDNZ1 (1 << 9)
#define PBIASLITEVMODE0 (1 << 0)
#define CTLPROGIO1SPEEDCTRL (1 << 20)

51
arch/arm/include/asm/arch-omap3/mux.h
View File

@ -15,6 +15,12 @@
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* SB_LOW - Standby mode configuration: Output low-level
* SB_HI - Standby mode configuration: Output high-level
* SB_HIZ - Standby mode configuration: Output hi-impedence
* SB_PD - Standby mode pull-down enabled
* SB_PU - Standby mode pull-up enabled
* WKEN - Wakeup input enabled
* M0 - Mode 0
*/
@ -26,6 +32,13 @@
#define EN (1 << 3)
#define DIS (0 << 3)
#define SB_LOW (1 << 9)
#define SB_HI (5 << 9)
#define SB_HIZ (2 << 9)
#define SB_PD (1 << 12)
#define SB_PU (3 << 12)
#define WKEN (1 << 14)
#define M0 0
#define M1 1
#define M2 2
@ -36,8 +49,8 @@
#define M7 7
/*
* To get the actual address the offset has to added
* with OMAP34XX_CTRL_BASE to get the actual address
* To get the actual address the offset has to be added
* to OMAP34XX_CTRL_BASE
*/
/*SDRC*/
@ -78,6 +91,33 @@
#define CONTROL_PADCONF_SDRC_DQS1 0x0074
#define CONTROL_PADCONF_SDRC_DQS2 0x0076
#define CONTROL_PADCONF_SDRC_DQS3 0x0078
#define CONTROL_PADCONF_SDRC_BA0 0x05A0
#define CONTROL_PADCONF_SDRC_BA1 0x05A2
#define CONTROL_PADCONF_SDRC_A0 0x05A4
#define CONTROL_PADCONF_SDRC_A1 0x05A6
#define CONTROL_PADCONF_SDRC_A2 0x05A8
#define CONTROL_PADCONF_SDRC_A3 0x05AA
#define CONTROL_PADCONF_SDRC_A4 0x05AC
#define CONTROL_PADCONF_SDRC_A5 0x05AE
#define CONTROL_PADCONF_SDRC_A6 0x05B0
#define CONTROL_PADCONF_SDRC_A7 0x05B2
#define CONTROL_PADCONF_SDRC_A8 0x05B4
#define CONTROL_PADCONF_SDRC_A9 0x05B6
#define CONTROL_PADCONF_SDRC_A10 0x05B8
#define CONTROL_PADCONF_SDRC_A11 0x05BA
#define CONTROL_PADCONF_SDRC_A12 0x05BC
#define CONTROL_PADCONF_SDRC_A13 0x05BE
#define CONTROL_PADCONF_SDRC_A14 0x05C0
#define CONTROL_PADCONF_SDRC_NCS0 0x05C2
#define CONTROL_PADCONF_SDRC_NCS1 0x05C4
#define CONTROL_PADCONF_SDRC_NCLK 0x05C6
#define CONTROL_PADCONF_SDRC_NRAS 0x05C8
#define CONTROL_PADCONF_SDRC_NCAS 0x05CA
#define CONTROL_PADCONF_SDRC_NWE 0x05CC
#define CONTROL_PADCONF_SDRC_DM0 0x05CE
#define CONTROL_PADCONF_SDRC_DM1 0x05D0
#define CONTROL_PADCONF_SDRC_DM2 0x05D2
#define CONTROL_PADCONF_SDRC_DM3 0x05D4
/*GPMC*/
#define CONTROL_PADCONF_GPMC_A1 0x007A
#define CONTROL_PADCONF_GPMC_A2 0x007C
@ -89,6 +129,7 @@
#define CONTROL_PADCONF_GPMC_A8 0x0088
#define CONTROL_PADCONF_GPMC_A9 0x008A
#define CONTROL_PADCONF_GPMC_A10 0x008C
#define CONTROL_PADCONF_GPMC_A11 0x0264
#define CONTROL_PADCONF_GPMC_D0 0x008E
#define CONTROL_PADCONF_GPMC_D1 0x0090
#define CONTROL_PADCONF_GPMC_D2 0x0092
@ -323,6 +364,8 @@
#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
#define CONTROL_PADCONF_JTAG_TDO 0x0A50
/*Die to Die */
#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
@ -433,6 +476,10 @@
#define CONTROL_PADCONF_SYS_BOOT8 0x0226
/* AM/DM37xx specific */
#define CONTROL_PADCONF_GPIO112 0x0134
#define CONTROL_PADCONF_GPIO113 0x0136
#define CONTROL_PADCONF_GPIO114 0x0138
#define CONTROL_PADCONF_GPIO115 0x013A
#define CONTROL_PADCONF_GPIO127 0x0A54
#define CONTROL_PADCONF_GPIO126 0x0A56
#define CONTROL_PADCONF_GPIO128 0x0A58

1
arch/arm/include/asm/arch-omap3/sys_proto.h
View File

@ -23,6 +23,7 @@ struct emu_hal_params {
/* Board SDRC timing values */
struct board_sdrc_timings {
u32 sharing;
u32 mcfg;
u32 ctrla;
u32 ctrlb;

20
arch/arm/include/asm/arch-omap5/clock.h
View File

@ -236,13 +236,20 @@
#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880
/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
#define VDD_MPU_DRA752 1090
/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
#define VDD_MPU_DRA752 1100
#define VDD_EVE_DRA752 1060
#define VDD_GPU_DRA752 1060
#define VDD_CORE_DRA752 1030
#define VDD_CORE_DRA752 1060
#define VDD_IVA_DRA752 1060
/* DRA72x voltage settings in mv for OPP_NOM per DM */
#define VDD_MPU_DRA72x 1100
#define VDD_EVE_DRA72x 1060
#define VDD_GPU_DRA72x 1060
#define VDD_CORE_DRA72x 1060
#define VDD_IVA_DRA72x 1060
/* Efuse register offsets for DRA7xx platform */
#define DRA752_EFUSE_BASE 0x4A002000
#define DRA752_EFUSE_REGBITS 16
@ -284,6 +291,13 @@
#define TPS659038_REG_ADDR_SMPS7 0x33
#define TPS659038_REG_ADDR_SMPS8 0x37
/* TPS65917 */
#define TPS65917_I2C_SLAVE_ADDR 0x58
#define TPS65917_REG_ADDR_SMPS1 0x23
#define TPS65917_REG_ADDR_SMPS2 0x27
#define TPS65917_REG_ADDR_SMPS3 0x2F
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
#define TPS62361_REG_ADDR_SET0 0x0

18
board/isee/igep00x0/igep00x0.c
View File

@ -5,6 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <status_led.h>
#include <dm.h>
#include <ns16550.h>
#include <twl4030.h>
@ -53,22 +54,13 @@ int board_init(void)
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
#endif
return 0;
}
#if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD)
void show_boot_progress(int val)
{
if (val < 0) {
/* something went wrong */
return;
}
if (!gpio_request(IGEP00X0_GPIO_LED, ""))
gpio_direction_output(IGEP00X0_GPIO_LED, 1);
}
#endif
#ifdef CONFIG_SPL_BUILD
/*
* Routine: omap_rev_string

8
board/isee/igep00x0/igep00x0.h
View File

@ -7,14 +7,6 @@
#ifndef _IGEP00X0_H_
#define _IGEP00X0_H_
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
#define IGEP00X0_GPIO_LED 27
#endif
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define IGEP00X0_GPIO_LED 16
#endif
const omap3_sysinfo sysinfo = {
DDR_STACKED,
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)

4
drivers/mmc/omap_hsmmc.c
View File

@ -134,6 +134,10 @@ static unsigned char mmc_board_init(struct mmc *mmc)
pbias_lite = readl(&t2_base->pbias_lite);
pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
#ifdef CONFIG_TARGET_OMAP3_CAIRO
/* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
pbias_lite &= ~PBIASLITEVMODE0;
#endif
writel(pbias_lite, &t2_base->pbias_lite);
writel(pbias_lite | PBIASLITEPWRDNZ1 |

1
include/configs/am335x_evm.h
View File

@ -237,6 +237,7 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \

1
include/configs/nokia_rx51.h
View File

@ -28,6 +28,7 @@
#define CONFIG_OMAP3_RX51 /* working with RX51 */
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51

18
include/configs/omap3_igep00x0.h
View File

@ -29,11 +29,21 @@
#define CONFIG_REVISION_TAG 1
/* define to enable boot progress via leds */
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define CONFIG_SHOW_BOOT_PROGRESS
/* Status LED */
#define CONFIG_STATUS_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define CONFIG_GPIO_LED
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
#define RED_LED_GPIO 27
#endif
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define RED_LED_GPIO 16
#endif
#define RED_LED_DEV 0
#define STATUS_LED_BIT RED_LED_GPIO
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT RED_LED_DEV
/* GPIO banks */
#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */