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1552 Commits

Author SHA1 Message Date
Tom Rini
81a659e10a Prepare v2021.01-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-28 16:30:06 -04:00
Tom Rini
4f1d3079b9 Merge branch '2020-10-28-mux-driver-framework'
- Add a framework for mux drivers
2020-10-28 14:50:09 -04:00
Pratyush Yadav
15995ac3f4 test: mux-cmd: Add tests for the 'mux' command
Tests tests run the three mux subcommands: list, select, and deselect,
and verify that the commands do what we expect.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-28 11:49:31 -04:00
Pratyush Yadav
05115abe8d cmd: Add a mux command
This command lets the user list, select, and deselect mux controllers
introduced with the mux framework on the fly. It has 3 subcommands:
list, select, and deselect.

List: Lists all the mux present on the system. The muxes are listed for
each chip. The chip is identified by its device name. Each chip can have
a number of mux controllers. Each is listed in sequence and is assigned
a sequential ID based on its position in the mux chip. It lists details
like ID, whether the mux is currently selected or not, the current
state, the idle state, and the number of states.

A sample output would look something like:

=> mux list
a-mux-controller:
	ID	Selected	Current State	Idle State	Num States
	0	no        	unknown   	as-is     	0x4
	1	no        	0x2       	0x2       	0x10
	2	no        	0x73      	0x73      	0x100

another-mux-controller:
	ID	Selected	Current State	Idle State	Num States
        0       no              0x1             0x1             0x4
        1       no              0x2             0x2             0x4

Select: Selects a given mux and puts it in the specified state. This
subcommand takes 3 arguments: mux chip, mux ID, state to set
the mux in. The arguments mux chip and mux ID are used to identify which
mux needs to be selected, and then it is selected to the given state.
The mux needs to be deselected before it can be selected again in
another state. The state should be a hexadecimal number.

For example:
=> mux list
a-mux-controller:
        ID      Selected        Current State   Idle State      Num States
        0       no              0x1             0x1             0x4
        1       no              0x1             0x1             0x4
=> mux select a-mux-controller 0 0x3
=> mux list
a-mux-controller:
        ID      Selected        Current State   Idle State      Num States
        0       yes             0x3             0x1             0x4
        1       no              0x1             0x1             0x4

Deselect: Deselects a given mux and puts it in its idle state. This
subcommand takes 2 arguments: the mux chip and mux ID to identify which
mux needs to be deselected. So in the above example, we can deselect mux
0 using:

=> mux deselect a-mux-controller 0
=> mux list
a-mux-controller:
        ID      Selected        Current State   Idle State      Num States
        0       no              0x1             0x1             0x4
        1       no              0x1             0x1             0x4

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-28 11:49:31 -04:00
Jean-Jacques Hiblot
739592ccbb test: Add tests for the multiplexer framework
Provide tests to check the behavior of the multiplexer framework.

Two sets of tests are added. One is using an emulated multiplexer driver
that can be used to test basic functionality like select, deselect, etc.
The other is using the mmio mux which adds tests specific to it.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-28 11:49:31 -04:00
Pratyush Yadav
4145fc189c Kconfig: Increase the pre-relocation memory
The memory is close to full and adding a syscon node in test.dts makes
it go over the limit and makes malloc() fail on startup.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-28 11:49:31 -04:00
Jean-Jacques Hiblot
35b8b92c85 drivers: mux: mmio-based syscon mux controller
This adds a driver for mmio-based syscon multiplexers controlled by
bitfields in a syscon register range.
This is heavily based on the linux mmio-mux driver.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-10-28 11:49:30 -04:00
Jean-Jacques Hiblot
90a979d788 dm: board: complete the initialization of the muxes in initr_dm()
This will probe the multiplexer devices that have a "u-boot,mux-autoprobe"
property. As a consequence they will be put in their idle state.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-10-28 11:48:55 -04:00
Jean-Jacques Hiblot
0ad40b2463 drivers: Add a new framework for multiplexer devices
Add a new subsystem that handles multiplexer controllers. The API is the
same as in Linux.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
[trini: Update some error calls to use different functions or pass
        correct arguments]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-28 11:48:32 -04:00
Tom Rini
39dd7c1d6b Merge tag 'efi-2021-01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2021-01-rc2

A software RTC driver is supplied for UEFI SCT testing.

The following UEFI related bugs are fixed:

* correct handling of daylight saving time in GetTime() and SetTime()
* handling of the gd register in function tracing on RISC-V
* disable U-Boot devices in ExitBootServices()
2020-10-28 08:35:28 -04:00
Tom Rini
a45da8f51e Merge branch '2020-10-27-further-log-enhancements'
- Allow for log message continuation.
- Test fix, build time error checking for new categories
2020-10-28 08:34:11 -04:00
Heinrich Schuchardt
2a0cbf3bca log: correct and check array size of log categories
The log command has led to NULL dereferences if an unknown category name
name was used due to missing entries in the list of category names.

Add compile time checks for the array sizes of log_cat_name and
log_lvl_name to avoid future mishaps.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 17:04:15 -04:00
Heinrich Schuchardt
0eae552d18 efi_loader: daylight saving time
Adjust the SetTime() and GetTime() runtime services to correctly convert
the daylight saving time information when communicating with the RTC.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27 21:13:16 +01:00
Ilias Apalodimas
529441ca89 efi_loader: Disable devices before handing over control
U-Boot Driver Model is supposed to remove devices with either
DM_REMOVE_ACTIVE_DMA or DM_REMOVE_OS_PREPARE flags set, before exiting.
Our bootm command does that by explicitly calling calling
"dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);" and we also disable any
USB devices.

The EFI equivalent is doing none of those at the moment. As a result
probing an fTPM driver now renders it unusable in Linux. During our
(*probe) callback we open a session with OP-TEE, which is supposed to
close with our (*remove) callback. Since the (*remove) is never called,
once we boot into Linux and try to probe the device again we are getting
a busy error response. Moreover all uclass (*preremove) functions won't
run.

So let's fix this by mimicking what bootm does and disconnect devices
when efi_exit_boot_services() is called.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27 21:13:16 +01:00
Ilias Apalodimas
19763ea0d2 efi_loader: Sort header file ordering
Order header files according to https://www.denx.de/wiki/U-Boot/CodingStyle

Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27 21:13:15 +01:00
Heinrich Schuchardt
d3d6afae3c trace: conserve gd register on RISC-V
An UEFI application may change the value of the register that gd lives in.
But some of our functions like get_ticks() access this register. So we
have to set the gd register to the U-Boot value when entering a trace
point and set it back to the application value when exiting the trace
point.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27 21:13:15 +01:00
Heinrich Schuchardt
87e9963d5a rtc: provide an emulated RTC
On a board without hardware clock this software real time clock can be
used. The build time is used to initialize the RTC. So you will have
to adjust the time either manually using the 'date' command  or use
the 'sntp' to update the RTC with the time from a network time server.
See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is
advanced according to CPU ticks.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27 21:13:15 +01:00
Heinrich Schuchardt
cbf0ffea14 Makefile: provide constant with seconds since epoch
Provide a constant U_BOOT_EPOCH with the number of seconds since
1970-01-01. This constant can be used to initialize a software
real time clock until it is updated via the 'sntp' command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27 21:13:15 +01:00
Heinrich Schuchardt
920157678b test: log: test message continuation
Provide a unit test checking that a continuation message will use the same
log level and log category as the previous message.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 13:50:53 -04:00
Heinrich Schuchardt
d094a0734c log: allow for message continuation
Some drivers use macro pr_cont() for continuing a message sent via printk.
Hence if we want to convert printk messaging to using the logging system,
we must support continuation of log messages too.

As pr_cont() does not provide a message level we need a means of
remembering the last log level.

With the patch a pseudo log level LOGL_CONT as well as a pseudo log
category LOGC_CONT are introduced. Using these results in the application
of the same log level and category as in the previous log message.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 13:50:53 -04:00
Heinrich Schuchardt
993a06b614 log: move processing_msg to global data
Replace the static variable processing_msg by a field in the global data.
Make the field bool at it can only be true or false.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27 13:50:53 -04:00
Anatolij Gustschin
986c980c82 nokia_rx51: re-enable CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV
With disabled legacy VIDEO option CONSOLE_MUX is not auto-selected
any more, re-enable it.

Fixes: 9dec5a0ea1 ("nokia_rx51: disable obsolete VIDEO config")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
2020-10-27 10:48:08 -04:00
Tom Rini
43428c6915 Merge tag 'video-for-2021.01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- disable CONFIG_VIDEO to remove DM conversion warnings
   for boards: at91sam9, eb_cpu5282, ls1021aqds, ls1021atwr,
   mx23evk, mx6sxsabresd, mx7dsabresd, nokia_rx51, picosam9g45,
   sansa_fuze_plus, xfi3
2020-10-26 17:27:38 -04:00
Anatolij Gustschin
9dec5a0ea1 nokia_rx51: disable obsolete VIDEO config
Disable VIDEO config to fix DM_VIDEO conversion
deadline warning.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-10-26 20:55:51 +01:00
Anatolij Gustschin
8c9940d5ec eb_cpu5282: fix CONFIG_DM_VIDEO build warnings
Remove CONFIG_VIDEO dependency to fix board removal warnings.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Jens Scharsig <esw@bus-elektronik.de>
2020-10-26 20:55:29 +01:00
Anatolij Gustschin
2310620960 sansa_fuze_plus: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
2020-10-26 20:55:03 +01:00
Anatolij Gustschin
8ea854a5cc xfi3: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
2020-10-26 20:54:47 +01:00
Anatolij Gustschin
beea0057d3 mx23evk: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
2020-10-26 20:54:37 +01:00
Anatolij Gustschin
33923e7270 at91sam9n12ek: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.
Boards should convert to DM_VIDEO if they need video console
support.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
2020-10-26 20:54:14 +01:00
Anatolij Gustschin
d1a2a1dc9e at91sam9: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-10-26 20:53:53 +01:00
Anatolij Gustschin
12a3e60469 picosam9g45: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Erik van Luijk <evanluijk@interact.nl>
2020-10-26 20:53:41 +01:00
Anatolij Gustschin
d63443a542 ls1021atwr: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-10-26 20:53:31 +01:00
Anatolij Gustschin
dac62ffd83 ls1021aqds: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Alison Wang <alison.wang@nxp.com>
2020-10-26 20:53:22 +01:00
Anatolij Gustschin
7490609bc5 imx: mx7dsabresd: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-10-26 20:53:09 +01:00
Anatolij Gustschin
e1c35c938d imx: mx6sxsabresd: disable obsolete VIDEO config
DM_VIDEO conversion deadline has passed, disable VIDEO config.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-10-26 20:52:58 +01:00
Tom Rini
54908d9ae1 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- No need to check before free in kendryte clk.
- Only enable OF_BOARD_FIXUP if U-Boot is configured for S-Mode.
- Reduce k210 dts DMA block size
- Move timers into drivers/timer
- Correct fu540 dts reg size of clint node
2020-10-26 08:25:37 -04:00
Pragnesh Patel
7257455e7c riscv: fu540: dts: Correct reg size of clint node
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 10:01:37 +08:00
Sean Anderson
47d7e3b5eb riscv: Move timer portions of SiFive CLINT to drivers/timer
Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 10:01:28 +08:00
Sean Anderson
7dbebebb79 timer: Add _TIMER suffix to Andes PLMT Kconfig
This matches the naming scheme of other timer drivers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 10:01:28 +08:00
Sean Anderson
79b135f1f9 riscv: Move Andes PLMT driver to drivers/timer
This is a regular timer driver, and should live with the other timer
drivers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 10:01:28 +08:00
Sean Anderson
963911e9e1 riscv: k210: Reduce DMA block size
Although the max DMA size supported by the hardware register is 22 bits (or
4M), the Linux driver for this device only supports transfers of up to 2M.
On a device with 8M total memory, I don't think it will make too much of a
difference.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 09:27:24 +08:00
Sean Anderson
32cef69da0 riscv: Only enable OF_BOARD_FIXUP for S-Mode
It is unsafe to enable OF_BOARD_FIXUP only based on OF_SEPARATE.
OF_SEPARATE may indicate that the user wishes U-Boot to use a different
device tree than one obtained via OF_PRIOR_STAGE. However, OF_SEPARATE may
also indicate that the device tree which would be obtained via
OF_PRIOR_STAGE is invalid, nonexistant, or otherwise unusable. In this
latter case, enabling OF_BOARD_FIXUP will result in corruption of the
device tree. To remedy this, only enable OF_BOARD_FIXUP if U-Boot is
configured for S-Mode.

Fixes: 1c17e55594
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-10-26 09:27:19 +08:00
Heinrich Schuchardt
8bb7496ef9 clk: kendryte: no need to check argument of free()
free() checks if its argument is NULL. No need to check it twice.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-10-26 09:27:13 +08:00
Tom Rini
c99e87f828 Merge branch '2020-10-23-misc-changes'
Highlights:
- Fix a problem with the bootm overlap tests
- Remove duplicated code in fatwrite
- Cleanup our current "misc" command code and add a new one for misc
  class devices.
- Various GPIO fixes
2020-10-24 10:49:28 -04:00
Peng Fan
16cc5ad0b4 power: regulator: add dummy helper
Add dummy helper to enabling the header could be included when
DM REGULATOR not enabled.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-10-23 16:38:33 -04:00
Peng Fan
62ee9576c6 phy: nop-phy: add clk bulk
Add clk bulk for nop-phy driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-10-23 16:38:31 -04:00
Jaehoon Chung
ef4f4f1f5f bootm: fix wrong conditions about images overlap
It doesn't need to consider start byte address.
If ramdisk size is 0x800000 and start address is 0x2700000, then it's
used until 0x02efffff, not 0x02f00000. But it's detected to overlapt RD
image, when kernel start address is 0x02f00000.
Because it's doing wrong calculation about rd_len.
This patch fixed wrong calculation address position when check
condition.

In addition, it needs to check one more condition about overlapping
entire area.

Fixes: commit fbde7589ce ("common: bootm: add checks to verify if ramdisk / fdtimage overlaps OS image")

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-23 13:33:07 -04:00
Lad Prabhakar
274227500a cmd: fat: Use do_save() for fatwrite
do_save() function defined in fs.c also supports FAT file system
re-use the same for fatwrite command.

Also fix the FAT test script to match the expected output.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-23 13:33:07 -04:00
Heinrich Schuchardt
f52e925669 test: unit tests for print_freq(), print_size()
Provide unit tests for functions print_freq() and print_size().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-23 13:33:07 -04:00
Bin Meng
3bc0db11ba cmd: Add a 'misc' command to access miscellaneous devices
Enable the command "misc" for accessing miscellaneous devices with
a MISC uclass driver. The command provides listing all MISC devices
as well as read and write functionalities via their drivers.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-10-23 13:33:07 -04:00
Bin Meng
3c7bb89718 cmd: Split out timer command from the sleep command
CONFIG_CMD_TIMER merits a single file instead of co-exist in the
sleep command file.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-10-23 13:33:07 -04:00
Bin Meng
1606085409 cmd: Rename CMD_MISC to CMD_SLEEP
The "cmd/Kconfig" has a TODO description for CMD_MISC that it should
really be named as CMD_SLEEP. Change it in the whole source tree.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-10-23 13:33:07 -04:00
Pali Rohár
ae897022d7 Makefile: Fix u-boot-nodtb.bin target
This change fixes two issues when building u-boot-nodtb.bin target:

* Remove intermediate binary u-boot-nodtb.bin from disk when static_rela
  call (which modifies u-boot-nodtb.bin binary) failed. It is required
  because previous objcopy call creates binary and static_rela finish it.

* Do not call static_rela cmd when u-boot-nodtb.bin binary was not
  created/updated by previous objcopy call.

Second fix would ensure that u-boot-nodtb.bin binary is not updated when
all prerequisites were up-to-date. And therefore final binary u-boot.bin
is not updated in case all prerequisites were not modified and were
up-to-date.

Now running 'make SOURCE_DATE_EPOCH=0 u-boot.bin' second time now does not
touch u-boot.bin binary in case nothing was modified, so GNU make can
correctly detect that everything is up-to-date.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-23 13:33:07 -04:00
Patrick Delaunay
7a462740d0 i2c: i2c-gpio: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-10-23 13:33:07 -04:00
Patrick Delaunay
a3b3c1d416 power: regulator: gpio-regulator: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-23 13:33:07 -04:00
Patrick Delaunay
2d69b08618 power: regulator: gpio-regulator: protect count value
Update the size of states_array to avoid overflow for
dev_pdata->voltages[j] and dev_pdata->states[j].

As the size of array is GPIO_REGULATOR_MAX_STATES, the size of
states_array is limited by GPIO_REGULATOR_MAX_STATES * 2 = 4
instead of 8 previously.

The value of the "count" variable is limited by the third parameter of
fdtdec_get_int_array_count.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-23 13:33:06 -04:00
Heinrich Schuchardt
86eeac7bcf post: remove redundant condition
(A && A == 0x20) is only true for (A == 0x20).

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-23 13:33:06 -04:00
Tom Rini
001ab99325 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2020-10-23 09:19:12 -04:00
Tom Rini
89a140ad30 Merge branch '2020-10-23-revert-xen-changes'
I had inadvertently merged the Xen series before everything was fully
happy with the board maintainer.  Revert the series.
2020-10-23 09:16:20 -04:00
Tom Rini
cc696f5256 Revert "serial: serial_xen: print U-Boot banner and others"
This reverts commit 18426bf022.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-23 09:16:13 -04:00
Tom Rini
c3d3104506 Revert "arch: arm/xen: add putc() for debugging"
This reverts commit 3a51b2a2c3.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-23 09:16:07 -04:00
Tom Rini
2c48370626 Revert "xen: add definitions for console_io"
This reverts commit 16389a74c5.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-23 09:16:01 -04:00
Tom Rini
467591b8d2 Revert "serial: serial_xen: add DEBUG_UART support"
This reverts commit 82e21b391b.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-23 09:15:55 -04:00
Tom Rini
18261b8552 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- sun8i emac changes (Andre)
- SCP firmware (Samuel)
2020-10-22 20:32:02 -04:00
Tom Rini
ae4fdd7b04 Merge branch '2020-10-22-misc-changes'
- Assorted updates for Xen, IPQ40xx, ASpeed, Keymile
- Assorted typo / documentation fixes
- Fix default preboot cmd to act like before with USB_STORAGE set
- A number of other bugfixes throughout the code
2020-10-22 14:36:47 -04:00
Heiko Schocher
dddfde5401 rtc: move pcf8563 to Kconfig
add Kconfig option for pcf8563 driver and
run tools/moveconfig.py

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-22 11:26:14 -04:00
Fabien Parent
0d67576713 mmc: mtk-sd: change some dev_err into dev_dbg
dev_err has been used for debugging and a few dev_err message are
printed for normal code execution. Make them dev_dbg instead.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22 11:26:14 -04:00
AKASHI Takahiro
82e21b391b serial: serial_xen: add DEBUG_UART support
By using a hypervisor call, we can implement DEBUG_UART on xen.
This will allow us to see messages even earlier than serial_init().

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2020-10-22 11:26:14 -04:00
AKASHI Takahiro
16389a74c5 xen: add definitions for console_io
Those definitions added are used with HYPERVISOR_console_io().

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22 11:26:14 -04:00
AKASHI Takahiro
3a51b2a2c3 arch: arm/xen: add putc() for debugging
This new function, xen_debug_putc(), is intended to be used to
enable CONFIG_DEBUG_UART on xen guest.

Please note that the underlying functionality in Xen is available
only when Xen is configured with !NDEBUG but is much simpler than
a generic HYPERVISOR_console_io().

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22 11:26:14 -04:00
AKASHI Takahiro
18426bf022 serial: serial_xen: print U-Boot banner and others
At present, DM_FLAG_PRE_RELOC is set only if !OF_CONTROL.
It doesn't make sense for this para-virtualized driver.

With this patch applied, you will be able to see early boot messages:

U-Boot 2020.10-00001-ge442e71a6c52-dirty (Oct 15 2020 - 11:02:25 +0900)
xenguest

Xen virtual CPU
Model: XENVM-4.15
DRAM:  128 MiB
PVBLOCK:
(XEN) gnttab_mark_dirty not implemented yet
pvblock: 0
In:    hypervisor
Out:   hypervisor
Err:   hypervisor
xenguest#

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22 11:26:14 -04:00
Chia-Wei, Wang
b2424cd2f4 cosmetic: reset: ast2500: Rename driver and configs
1. Rename AST2500 reset driver from ast2500-reset.c
   to reset-ast2500.c
2. Rename AST2500 reset kconfig option from AST2500_RESET
   to RESET_AST2500

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-22 11:26:14 -04:00
Chia-Wei, Wang
611a28ce27 reset: ast2500: Use SCU for reset control
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.

This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.

The Kconfig description is also updated accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-22 11:26:14 -04:00
Dario Binacchi
fa181d1a95 clk: ccf: replace the get_rate helper
The 12d152620d commit fixed the get_rate helper because the set_parent
one did not re-parent the clock device to the new parent. The 4d139f3838
commit allows you to remove this workaround by calling the
clk_get_parent_rate routine.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-10-22 11:26:14 -04:00
Chance.Yang
69509fb0a5 doc: dfu: fix typo in README.dfu
Fix "ram" typos for serial flash

Signed-off-by: Chance.Yang <chance.yang@vatics.com>
2020-10-22 11:26:14 -04:00
Simon Glass
7ad1e0bcf3 log: Tidy up documentation
Fix up the documentation which was lost in a merge conflict in the
conversion to RST.

Fixes: 52d3df7fef ("log: Allow LOG_DEBUG to always enable log output")

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 11:26:14 -04:00
Naoki Hayama
ef38b42364 ARM: mvebu: a38x: Fix comment typo
%s/occured/occurred/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-22 11:26:14 -04:00
Naoki Hayama
09f2107a5f fs: btrfs: Fix typo in error message
%s/occured/occurred/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Qu Wenruo <wqu@suse.com>
2020-10-22 11:26:14 -04:00
Naoki Hayama
64dbd86b56 mmc: Fix comment typo
%s/occured/occurred/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 11:26:14 -04:00
Patrick Delaunay
87459da102 Remove default value of CONFIG_PREBOOT for CONFIG_USB_STORAGE
Remove the default value "usb start" for CONFIG_USB_STORAGE as the USB
storage boot initialization is correctly managed by  distro boot command
('usb_boot' defined in include/config_distro_bootcmd.h already include
the command 'usb  start').

Fixes: 324d77998e ("Define default CONFIG_PREBOOT with right config option")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 11:26:14 -04:00
Dario Binacchi
7438d6a6c4 gpio: fix gpio_request_by_name() description
Replace 'dev->dev' with '@desc->dev' in the gpio_request_by_name function
desc parameter description.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 11:26:14 -04:00
Dario Binacchi
2d1a43be4e dm: core: improve uclass_get_device_by_phandle_id() description
Complete the devp parameter description.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 11:26:14 -04:00
Holger Brunck
0e3eb47605 km/common: change ubicopy variable
Instead having a hard coded value for "cramfsaddr" after compile time,
we change it to take the variable "cramfsaddr" for the ubicopy variable.
This makes sure that ubicopy uses the right address, even when
the value for "cramfsaddr" has changed.

CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
CC: Heiko Schocher <hs@denx.de>
CC: Tom Rini <trini@konsulko.com>
Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-10-22 11:26:08 -04:00
Holger Brunck
6a0952a332 km: adapt defines and variables for new memory layout
Due to increasing kernel image sizes we get problems when decompressing
the kernel image. To fix this we need to change the addresses where we
load and where we extract the kernel. Also we need to adapt the address
where to load the CRAMFS image and where to load the DTB file.
While at it also harmonize all boards for PPC and ARM to have the
same values. Also we add a new variable "env_version", so that the
userspace is able to detect if this is a u-boot binary with updated
values or not.

CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
CC: Heiko Schocher <hs@denx.de>
CC: Tom Rini <trini@konsulko.com>
Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Remove old values from kmp204x.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-22 11:25:33 -04:00
Heinrich Schuchardt
dcf16721c1 lib: print_freq() should output kHz not KHz
In the International System of Units (SI) the prefix kilo is abbreviated as
'k' not 'K'. 'K' is the symbol for Kelvin.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-22 09:54:54 -04:00
Robert Marko
cfec8d36ce IPQ40xx: Add PRNG support
Since we now have the driver for Qualcomm PRNG HW, lets use it and add the necessary clocks and nodes.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
033ec636fc rng: Add Qualcomm MSM PRNG driver
Add support for the hardware pseudo random number generator found in Qualcomm SoC-s.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
5297341ab1 IPQ40xx: Add support for MDIO
Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
975151d056 net: Add IPQ40xx MDIO driver
This adds the driver for the IPQ40xx built-in MDIO.
This will be needed to support future PHY driver.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
96d6036671 IPQ40xx: Add SPI support
Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
367ea426a5 spi: Add Qualcomm QUP SPI controller driver
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s.

Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW.
FIFO and Block modes are supported, no support for DMA mode is planned.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Heinrich Schuchardt
3311eda658 tools: image-host.c: use correct output format
When building on a 32bit host the following warning occurs:

tools/image-host.c: In function ‘fit_image_read_data’:
tools/image-host.c:296:56: warning: format ‘%ld’ expects argument of
type ‘long int’, but argument 3 has type ‘__off64_t’
{aka ‘long long int’} [-Wformat=]
   printf("File %s don't have the expected size (size=%ld, expected=%d)\n",
                                                      ~~^
                                                      %lld
          filename, sbuf.st_size, expected_size);
                    ~~~~~~~~~~~~
tools/image-host.c:311:62: warning: format ‘%ld’ expects argument of
type ‘long int’, but argument 4 has type ‘__off64_t’
{aka ‘long long int’} [-Wformat=]
   printf("Can't read all file %s (read %zd bytes, expexted %ld)\n",
                                                            ~~^
                                                            %lld
          filename, n, sbuf.st_size);
                       ~~~~~~~~~~~~

Fix the format strings.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:54 -04:00
Holger Brunck
5d57dfad3f km: fix license string and compatible strings
As the ownership is now Hitachi Power Grids, change the license string
and adapt the compatible string in DTS files. For kmeter1.dts we
change it to "keymile,KMETER1" for now, as this is then compliant with
what is submitted to the linux kernel. All other boards don't have
a upstreamed version in linux mainline.

Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com>
CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
CC: Heiko Schocher <hs@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-10-22 09:54:54 -04:00
Naoki Hayama
047f6ec0b7 README: Convert HTTP links to HTTPS
Convert all the other http:// links to https:// .
www.denx.de/twiki/ seems to move to www.denx.de/wiki/ ,
so change it.

I checked all links in this patch are valid.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:54 -04:00
Naoki Hayama
81a05d9bcc README: vxworks: Fix typo overwride
%s/overwride/override/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:53 -04:00
Naoki Hayama
bbb140ed38 README: sandbox: Change reference to sandbox details
doc/arch/index.rst is a list of links to each architecture.
As for the sandbox details, doc/arch/sandbox.rst looks better.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Naoki Hayama
e4eb313af0 README: Update directory hierarchy
Removed:
- /arch/openrisc

Added:
- /arch/xtensa
- /env

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:53 -04:00
Naoki Hayama
c4bd51e2ae README: Update source code location
This patch include these updates

- Git repository has moved to GitLab
- HTTPS access to the file server is allowed
- pre-built images are no longer available

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:53 -04:00
Naoki Hayama
6681bbb5e9 README: Update links to mailing list archives
This patch includes these updates

- Change http://lists.denx.de/pipermail/u-boot
  to https://lists.denx.de/pipermail/u-boot
- http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
  is broken, so remove it
- Another archive https://marc.info/?l=u-boot
  is available, so add it

Additional information:
dir.gmane.org has moved to news.gmane.io, but it only allows
access to the archive via NNTP.

- Server: news.gmane.io
- Group : gmane.comp.boot-loaders.u-boot

I don't include this information in this patch because
it's not very useful without web interfaces.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:53 -04:00
Sean Anderson
8af7bb914f timer: Return count from timer_ops.get_count
No timer drivers return an error from get_count. Instead of possibly
returning an error, just return the count directly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Sean Anderson
aff60aba6c doc: Document timer API
This adds kerneldocs for <timer.h>.

I don't know who should maintain doc/api/timer.rst, since the timer
subsystem seems to be maintained by SoC maintainers. MAINTAINERS is left
un-updated for the moment.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Heinrich Schuchardt
c670aeee3d common: rename getc() to getchar()
The sandbox is built with the SDL2 library with invokes the X11 library
which in turn calls getc(). But getc() in glibc is defined as

    int getc(FILE *)

This does not match our definition.

    int getc(void)

The sandbox crashes when called with parameter -l.

Rename our library symbol getc() to getchar().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Rasmus Villemoes
8d5d97cb28 cli_hush.c: remove broken sanity check
This code is intended do prevent one from setting a shell variable abc
by doing

  abc=123

if an environment variable named abc already exists. However, the
check is broken, since the env_get is done before the split on =, so
we look up whether an environment variable "abc=123" exists, which is
obviously never the case.

One could move the code to below the split on =, but instead, just
remove it, saving a little .text: The check has never worked as
intended (it goes all the way back to the initial git commit), and it
would anyway not guard against one first setting the shell variable,
then doing 'env set abc xyz'.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-10-22 09:54:53 -04:00
Heiko Schocher
6ebe6b387f common, autoboot: sync functionality with Kconfig description
add back again special case: -2
autoboot with no delay and no check for abort

as described in Kconfig option, see common/Kconfig
help text for option BOOTDELAY.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Naoki Hayama
898a084953 cosmetic: image: Fix comments and the order of definitions
Fix some comments about functions.
Move genimg_get_comp_name() above genimg_get_short_name() because
genimg_get_comp_name() is related to get_table_entry_name().

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Naoki Hayama
ad5fb9f2e6 mkimage: Skip adding non-existent IDs to a list
In show_valid_options(), this patch introduces checking whether
a category has an entry ID. If not, adding it to a list for output
is skipped before calling qsort().
This patch will affect all kinds of image header categories
(-A, -C, -O and -T flags).

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Naoki Hayama
02d41b01bd image: Add a function to modify category information
Add a generic function which can check whether a category has an
entry ID.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Ovidiu Panait
2dfdd0c4de Kconfig: Use hex values for CONFIG_{SPL,TPL}_SIZE_LIMIT
CONFIG_{SPL,TPL}_SIZE_LIMIT are defined as hex (SPL_SIZE_LIMIT was
converted in b51882d0 ("spl: Convert CONFIG_SPL_SIZE_LIMIT to hex"), but
there are still places that reference integer values. Change those to hex
as well. Also, update the Makefile to check for 0x0 instead of 0.

This also fixes the following build error when CONFIG_SPL_SIZE_LIMIT
is set by menuconfig to 0x0:
...
spl/u-boot-spl.bin exceeds file size limit:
  limit:  0 bytes
  actual: 0x80f0 bytes
  excess: 0x80f0 bytes

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Simon Glass
39565cc2a9 tpm: cr50: Correct logging statements
Fix up some logging statements in this file. Most of them should use
log_debug(), apart from one error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Simon Glass
acdd248bf2 i2c: designware: Use log_debug() for debugging
We don't want the debug output to be visible in a normal boot. Silence it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
2020-10-22 09:54:52 -04:00
Simon Glass
5630d2fbc5 board: Show memory for frame buffers
When debugging is enabled, show the memory allocated to video frame
buffers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Simon Glass
4a08fae196 bloblist: Place on a 4KB boundary
It is much easier to read the bloblist addresses if it starts on a 4KB
boundary. Update it to align it accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:53:31 -04:00
Simon Glass
28dc20f34a syscon: Drop the logging in syscon_get_by_driver_data()
This function can be called when it is not known whether it will find
anything. This results in confusing log messages if the device is not
found. It is better for the caller to log the failure, if necessary.

Drop the logging from this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:53:31 -04:00
Simon Glass
8021296a71 log: Add missing category names
Add some category names that were missed in recent changes. Update the
comment as a reminder.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:53:31 -04:00
Tom Rini
b90daf2743 Merge tag 'u-boot-stm32-20201021' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
- Update MAINTAINERS for ARM STM STM32MP
- Manage eth1addr on dh board with KS8851
- Limit size of cacheable DDR in pre-reloc stage in stm32mp1
- Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
2020-10-22 08:25:41 -04:00
Tom Rini
281d94b986 Merge branch '2021.01-rc' of https://github.com/lftan/u-boot
- fix Gen5 enable of EMAC via FPGA
2020-10-22 08:25:14 -04:00
Jaehoon Chung
8efad326ff samsung: common: remove the duplicated stdio print message
Remove duplicated stdio print message.
It's already displayed in common/console.c.

Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Model: Odroid XU3/XU4/HC1/HC2 based on Exynos5422
Type:  xu3
In:    serial
Out:   serial
Err:   serial

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-10-22 17:11:29 +09:00
Jonas Smedegaard
194923246c sun50i: a64: A64-Teres-I board detect builtin keyboard
A64-Teres-I board is a laptop which comes with a builtin keyboard.
The keyboard+trackpad controller pauses for 2 seconds at a firmware
prompt before loading its HID interface.

U-Boot needs to wait equally long to reliably enable the keyboard.

Signed-off-by: Jonas Smedegaard <dr@jones.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
Series-Cc: Jagan Teki <jagan@amarulasolutions.com>
Series-Cc: Lukasz Majewski <lukma@denx.de>
Series-Cc: Andre Przywara <andre.przywara@arm.com>
2020-10-22 12:03:34 +05:30
Jonas Smedegaard
22885f4ed9 sunxi: Enable ethernet on newer Olimex OLinuXino-A20-Lime2-eMMC
Olimex OLinuXino LIME2 rev. H through L uses Micrel KSZ9031 PHY.

This enables the Micrel PHY for A20-OLinuXino-Lime2-eMMC_defconfig.

Signed-off-by: Jonas Smedegaard <dr@jones.dk>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:58:40 +05:30
Samuel Holland
e72a6be4fc sunxi: binman: Add support for including SCP firmware
Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a
System Control Processor, or SCP. ARM Trusted Firmware (ATF)
communicates with the SCP over SCPI to implement the PSCI system
suspend, shutdown and reset functionality. Currently, SCP firmware is
optional; the system will boot and run without it, but system suspend
will be unavailable.

Since all communication with the SCP is mediated by ATF, the only thing
U-Boot needs to do is load the firmware into SRAM. The SCP firmware
occupies the last 16KiB of SRAM A2, immediately following ATF.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
18bd45592c binman: Add support for SCP firmware
Add an entry type for a firmware blob for a System Control Processor,
given by an entry arg. This firmware is a raw binary blob.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
68158d59d2 sunxi: binman: Update FIT component descriptions
Since commit d879616e9e ("spl: fit: simplify logic for FDT loading for
non-OS boots"), the SPL looks at the "os" properties of FIT images to
determine where to append the FDT.

The "os" property of the "firmware" image also determines how to execute
the next stage of the boot process, as in 1d3790905d ("spl: atf:
introduce spl_invoke_atf and make bl31_entry private"). For this reason,
the next stage must be specified in "firmware", not in "loadables".

To support this additional functionality, and to properly model the boot
process, where ATF runs before U-Boot, add the "os" properties and swap
the firmware/loadable images in the FIT image.

Since this description was copied as an example in commit 70248d6a2916
("binman: Support generating FITs with multiple dtbs"), update those
examples as well for correctness and consistency.

Acked-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
cf70553e2c spl: fit: Minimally parse OS properties with FIT_IMAGE_TINY
Some boards, specifically 64-bit Allwinner boards (sun50i), are
extremely limited on SPL size. One strategy that was used to make space
was to remove the FIT "os" property parsing code, because it uses a
rather large lookup table.

However, this forces the legacy FIT parsing code path, which requires
the "firmware" entry in the FIT to reference the U-Boot binary, even if
U-Boot is not the next binary in the boot sequence (for example, on
sun50i boards, ATF is run first).

This prevents the same FIT image from being used with a SPL with
CONFIG_SPL_FIT_IMAGE_TINY=n and CONFIG_SPL_ATF=y, because the boot
method selection code looks at `spl_image.os`, which is only set from
the "firmware" entry's "os" property.

To be able to use CONFIG_SPL_ATF=y, the "firmware" entry in the FIT
must be ATF, and U-Boot must be a loadable. For this to work, we need to
parse the "os" property just enough to tell U-Boot from other images, so
we can find it in the loadables list to append the FDT, and so we don't
try to append the FDT to ATF (which could clobber adjacent firmware).

So add the minimal code necessary to distinguish U-Boot/non-U-Boot
loadables with CONFIG_SPL_FIT_IMAGE_TINY=y. This adds about 300 bytes,
much less than the 7400 bytes added by CONFIG_SPL_FIT_IMAGE_TINY=n.

Acked-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
827c420c40 sunxi: binman: Use a macro for the BL31 load address
This consolidates the SoC-specific part at the top of the file to avoid
cluttering it up with preprocessor conditions.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
6b7c7ed80a sunxi: binman: Provide a default BL31 filename
Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use
binman"), if the BL31 environment variable was not defined, the firmware
would be loaded from a file "bl31.bin" in the current directory. Restore
that behavior by providing that as the default filename in case no entry
arg is provided, which will be the case if the environment variable is
unset.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
eafbdbb8eb sunxi: binman: Fix spacing between nodes
Nodes should have a blank line separating them from sibling nodes and
properties. Add the necessary lines.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
b26536ad3d binman: Only write FDT once per node
Due to an extra level of indentation, the "data" property containing the
FDT was being written repeatedly after every other property in the node.
This caused the generated FIT image to be invalid.

Move the block up one level, so the property is added exactly once.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Samuel Holland
509978e5d2 Makefile: Only define u-boot.itb rule when applicable
If neither CONFIG_SPL_FIT_SOURCE nor CONFIG_USE_SPL_FIT_GENERATOR is
enabled, U_BOOT_ITS will be undefined, and attempting to make u-boot.itb
will pass invalid arguments to mkimage, causing it to print its help
message.

Remove the rule in that case, so it is more obvious that u-boot.itb is
not something that can be made. This will reduce confusion as platforms
move away from CONFIG_USE_SPL_FIT_GENERATOR, as u-boot.itb was
previously a valid goal for those platforms.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:43:43 +05:30
Icenowy Zheng
0e3160b723 sunxi: make V3s DRAM initialization more proper
Previously, because we have no source code about the DRAM initialization
of V3s and missing some configurations (delays and MBUS QoS info), our
V3s DRAM initialization sequence is hacked from the H3 one.

As the SDK shipped with PineCube contains source code for V3s libdram,
we can retrieve these information from it and tweak some other magic
bits.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22 11:40:28 +05:30
Tom Rini
5d92dacbbe Merge tag 'efi-2021-01-rc1-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2021-01-rc1 (2)

A use after free in the UEFI network stack is fixed.
2020-10-21 19:13:05 -04:00
Marek Vasut
5675ed7cb6 Revert "Fix data abort caused by mis-aligning FIT data"
This reverts commit eb39d8ba5f.
The commit breaks booting of fitImage by SPL, the system simply hangs.
This is because on arm32, the fitImage and all of its content can be
aligned to 4 bytes and U-Boot expects just that.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Reuben Dowle <reuben.dowle@4rf.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2020-10-21 19:11:50 -04:00
Heinrich Schuchardt
fb5b167843 arm: sunxi: increase SYS_MALLOC_F_LEN
The current default of 0x400 for SYS_MALLOC_F_LEN is too small if any
additional drivers marked as DM_FLAG_PRE_RELOC are loaded before
relocation.

CONFIG_RSA=y which is needed for UEFI secure boot or for FIT image
verification loads the driver mod_exp_sw which has DM_FLAG_PRE_RELOC.

CONFIG_LOG=Y is another setting requiring additional early malloc
area, cf. log_init().

When running pine64-lts_defconfig with CONFIG_RSA=y and debug UART enabled
we see as output in main U-Boot

    alloc_simple() alloc space exhausted

With this patch the default values of SYS_MALLOC_F_LEN and
SPL_SYS_MALLOC_F_LEN on ARCH_SUNXI are raised to 0x2000.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-21 23:52:49 +05:30
Jonas Smedegaard
5108a257b7 git-mailrc: Update email address of Maxime Ripard
Update email address of Maxime Ripard in git-mailrc to match more
recently updated entry in MAINTAINERS.
commit 9bd9b2bcbe ("MAINTAINERS: Update my email address")
commit bf8f4c4400 ("MAINTAINERS: Update email address for Maxime Ripard")

Signed-off-by: Jonas Smedegaard <dr@jones.dk>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:50:11 +05:30
Andre Przywara
3940a47155 sunxi: Pine-H64: Explicitly enable PHY regulator
According to the devicetree and the schematic, the 3.3V power rail for
the PHY is enabled by GPIO PC16. It's wired as active-high, with a
pull-up resistor, so actually works already when the GPIO is in
High-Z state.

However we should not take any chances and explicitly set the GPIO pin
to high, to avoid accidentally losing the PHY power.
The existing MACPWR Kconfig allows to do this easily.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:45:50 +05:30
Andre Przywara
4f0278dac5 net: sun8i-emac: Lower MDIO frequency
When sending a command via the MDIO bus, the Designware MAC expects some
bits in the CMD register to describe the clock divider value between
the main clock and the MDIO clock.
So far we were omitting these bits, resulting in setting "00", which
means "/ 16", so ending up with an MDIO frequency of either 18.75 or
12.5 MHz.
All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek
PHYs seem to be fine with that - although it looks like to be severly
overclocked (the MDIO spec limits the frequency to 2.5 MHz).
However the external 100Mbit PHY on the Pine64 (non-plus) board is
not happy with that, Ethernet was actually never working there, as the
PHY didn't probe.

As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit
SoCs), and use 200 MHz on the H3, we need the highest divider of 128
to let the MDIO clock end up below the required 2.5 MHz.

This enables Ethernet on the Pine64(non-plus).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:45:39 +05:30
Andre Przywara
88ae8fba84 net: sun8i-emac: Make internal PHY handling more robust
The current implementation of sun8i_get_ephy_nodes() makes quite some
assumptions, in general relying on DT path names is a bad idea.
I think the idea of the code was to determine if we are using the
internal PHY, for which there are simpler and more robust methods:

Rewrite (and rename) the existing function to simply lookup the DT node
that "phy-handle" points to, using the device's DT node.
Then check whether the parent of that PHY node is using an "H3 internal
MDIO" compatible string. If we ever get another internal MDIO bus
implementation, we will probably need code adjustments anyway, so this
is good enough for now.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: rebase on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:45:23 +05:30
Andre Przywara
7edcb4e288 net: sun8i_emac: Simplify and fix error handling for RX
The error handling in recv() is somewhat broken, for instance
good_packet isn't really used, and it's hardly readable. Also we try
to check for short or too big packets, but those are actually filtered
out by the hardware.

Simplify the whole routine and improve the error handling:
- Bail out early if the current RX descriptor is not ready.
- Enable propagation of runt, huge and broken packets.
- Check for runt and huge packets, and return 0 to indicate this.
  This will force the framework to call free_pkt for cleanup.
- Avoid aligning the packet buffer for invalidation again.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:45:06 +05:30
Andre Przywara
2c5600c38c net: sun8i_emac: Fix MAC soft reset
The EMAC soft reset routine was subtly broken, using an open coded
timeout routine without any actual delay.
Remove the unneeded initial reset bit read, and call wait_for_bit_le32()
to handle the timeout correctly.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:44:52 +05:30
Andre Przywara
09501ff32e net: sun8i_emac: Fix overlong lines
When iterating over all RX/TX buffers, we were using a rather long "idx"
control variable, which lead to a nasty overlong line.

Replace "idx" with "i" to avoid this.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:44:40 +05:30
Andre Przywara
8c274ec092 net: sun8i_emac: Wrap and simplify cache maintenance operations
To meet the current alignment requirements for our cache maintenance
functions, we were explicitly aligning the *arguments* to those calls.
This is not only ugly to read, but also wrong, as we need to make sure
we are not accidentally stepping on other data.

Provide wrapper functions for the common case of cleaning or
invalidating a descriptor, to make the cache maintenance calls more
readable. This fixes a good deal of the problematic calls.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:44:27 +05:30
Andre Przywara
eaeadb50ea net: sun8i_emac: Drop unneeded cache invalidation before sending
There is no reason to invalidate a TX descriptor before we are setting
it up, as we will only write to a field.

Remove the not needed invalidate_dcache_range() call.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:44:16 +05:30
Andre Przywara
ed909de5d3 net: sun8i_emac: Reduce cache maintenance on TX descriptor init
When we initialise the TX descriptors, there is no need yet to clean
them all to memory, as they don't contain any data yet. Later we will
touch and clean each descriptor anyway.
However we tell the MAC about the beginning of the chain, so we have to
clean at least the first descriptor, to make it clear that this is empty
and there are no packets to transfer yet.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:44:02 +05:30
Andre Przywara
69853123c5 net: sun8i_emac: Improve cache maintenance on RX descriptor init
Before we initialise the RX descriptors, there is no need to *clean*
them from the cache, as we touch them for the first time.
However we should cover the case that those buffers contain dirty cache
lines, which could be evicted and written back to DRAM any time later,
in the worst case *after* the MAC has transferred a packet into them.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:43:42 +05:30
Andre Przywara
4fe8641260 net: sun8i_emac: Name magic bits and simplify read-modify-write calls
The EMAC driver contains a lot of magic bits, although the manuals
and the Linux driver have all names for them.

Define those names and use them when programming the registers.
Also this replaces a lot of readl/mask/writel operations with the much
easier-to-read setbits_le32() macro.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:43:28 +05:30
Andre Przywara
a5b2a991b3 net: sun8i_emac: Remove pointless wrapper functions
Apparently due to copying from some older or converted driver, the
sun8i_emac driver contains pointless wrapper functions to bridge
between a legacy driver and the driver model.

Since sun8i_emac is (and always was) driver model only, there is no
reason to have those confusing wrappers. Just remove them, and use
the driver model prototypes directly.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:43:10 +05:30
Andre Przywara
f20f9465db net: sun8i_emac: Simplify mdio_read/mdio_write functions
When preparing the register value for the MDIO command register, we
start with a zeroed register, so there is no need to mask off certain
bits before setting them.
Simplify the sequence, and rename the variable to a more matching
mii_cmd on the way.

Also the open-coded time-out routine can be replaced with a much safer
and easier-to-read call to wait_for_bit_le32().

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:42:51 +05:30
Andre Przywara
c35380c756 net: sun8i_emac: Don't hand out TX descriptor too early
When initialising the TX DMA descriptors, we mostly chain them up,
but of course don't know about any data or its length yet.
That means they are still invalid, and the OWN bit should NOT be set
yet.

In fact when we later tell the MAC about the beginning of the chain,
and enable TX DMA in the start() routine, the MAC will start fetching
TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA
and TX_DMA_CUR_DESC registers.

Clear the owner bit, to not give the MAC the wrong illusion that it
owns the descriptors already.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:42:36 +05:30
Andre Przywara
2808cf6c60 net: sun8i-emac: Bail out on PHY error
When phy_startup() returns with an error, because there is no link or
the user interrupted the process, we shall stop the _start() routine
and return with an error, instead of proceeding anyway.

This fixes pointless operations when there is no Ethernet cable
connected, for instance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21 23:42:11 +05:30
Patrick Delaunay
53de79fecc stm32mp: stm32prog: accept device without partition
When partitions are not available on a device the command stm32prog raises
an error but a device can have no partition to check in init_device()
and the command need to continue to the next part_id.

This patch correct an issue for ram0 target, when block_dev and mtd
are NULL.

For example with the simple flashlayout file:

Opt	Part	Name	Type	Device	Offset	Binary
-	0x01	fsbl	Binary	none	0x0	tf-a-serialboot.stm32
-	0x03	ssbl	Binary	none	0x0	u-boot.stm32
P	0x10	kernel	System	ram0	0xC2000000	uImage.bin
P	0x11	dtb	FileSytem	ram0	0xC4000000	stm32mp157f-ev1.dtb

Fixes: ffc405e63b ("stm32mp: stm32prog: add upport of partial update")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
33f5000ee8 configs: stm32mp15: activate CMD_ELF
Activate CONFIG_CMD_ELF to accept the command "bootelf".

This patch simplifies the file stm32mp defconfig, as we have
no reason to deactivate this command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
d931186312 configs: stm32mp15: activate CMD_EXPORTENV
Activate CONFIG_CMD_EXPORTENV to accept the command "env export".

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
fba7b95085 configs: stm32mp15: activate CMD_IMPORTENV
Activate CONFIG_CMD_IMPORTENV to accept the command "env import".
This command is useful in script to include some variable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
2bf692d317 MAINTAINERS: Add STM32MP1 RNG driver in stm32mp platform
Add the STM32MP1 RNG driver in the list of drivers supported by
the STMicroelectronics STM32MP15x series.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
ce52023050 MAINTAINERS: Add stm32 and stm regexp for ARM STM STM32MP platform
Add files and directories regex "stm32" and "stm" in "ARM STM STM32MP"
platform to avoid missing files or drivers supported by the
STMicroelectronics series STM32MP15x.

This patch adds the rules already used in Linux kernel for
ARM/STM32 ARCHITECTURE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
6af78d03d3 arm: stm32: cleanup arch gpio.h
Cosmetic update of gpio.h:
- remove enumerate: stm32_gpio_port, stm32_gpio_pin
  because STM32_GPIO_XXX values are unused
- move STM32_GPIOS_PER_BANK in stm32_gpio.c
  as its value is IP dependent and not arch dependent

No functional change as number of banks and number of gpio by banks
is managed by device tree since since DM migration and
commit 8f651ca60b ("pinctrl: stm32: Add get_pins_count() ops").

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Marek Vasut
e07f76b25d ARM: dts: stm32: Do not set eth1addr if KS8851 has EEPROM
In case the KS8851 has external EEPROM attached to it, do not set
eth1addr at all. The network stack will read the MAC out of the
KS8851 and set eth1addr accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
67f9f11f19 stm32mp: limit size of cacheable DDR in pre-reloc stage
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.

This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

Without security, in basic boot, the value is equal to STM32_DDR_SIZE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Alexandru Gagniuc
c981d67a04 mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilities
mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of
struct mmc_config from devicetree.
The same logic is duplicated in stm32_sdmmc2_probe(). Use
mmc_of_parse(), which is more generic.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-21 18:11:56 +02:00
Alexandru Gagniuc
f80b8ac69b mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"
"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no
additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed"
is used for MMC HS at both 26MHz and 52MHz.

Use the same approach and enable MMC_CAP(MMC_HS_52) host capability
when "cap-mmc-highspeed" is found in the devicetree. In the event an
MMC card doesn't support 52 MHz, it will be clocked at a speed based
on its EXT CSD, even on 52 MHz host controllers

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 09:57:14 +02:00
Ralph Siemsen
b0b08ce0b7 arm: socfpga: fix Gen5 enable of EMAC via FPGA
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.

The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.

Fixes: db5741f7a8 ("arm: socfpga: Convert system manager from struct to defines")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-21 11:45:54 +08:00
Tom Rini
adc0c39633 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- Assorted R-Car Gen3 updates
2020-10-20 08:02:53 -04:00
Tom Rini
f216259927 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- MediaTek USB host support
2020-10-20 08:01:46 -04:00
Lad Prabhakar
b2d7a163ab pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9
Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Lad Prabhakar
a3c1fd6393 clk: renesas: Import R8A774C0 clock tables from Linux 5.9
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Biju Das
e9d91b82fe clk: renesas: Add R8A774E1 clock tables
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Biju Das
54db9e8b8f clk: renesas: Add R8A774B1 clock tables
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Lad Prabhakar
fc5e552209 arm: dts: r8a774c0: Import DTS from Linux 5.9
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Lad Prabhakar
051f1499c9 arm: renesas: Add config option for R8A774C0 SoC
Add config support for RZ/G2E (a.k.a R8A774C0) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Biju Das
aca749a90f arm: renesas: Add config option for R8A774E1 SoC
Add config support for RZ/G2H(a.k.a R8A774E1) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
4e4c0e5e42 arm: renesas: Add config option for R8A774B1 SoC
Add config support for RZ/G2N(a.k.a R8A774B1) SoC.

Also fixed the alignment issue on R8A774A1 config.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
f4c5f97925 clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clock
Add RPC entry into the R8A774A1 clock driver tables.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
2f220c639a spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility string
Add fallback compatibility string for R-Car Gen3 and RZ/G2.

Also sorted the compatible string as per SoC ID.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Chunfeng Yun
0cd791ced9 MAINTAINERS: add USB driver to ARM MEDIATEK
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK,
and add myself as a maintainer for it.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
d2eb5a3fb8 configs: mt8512: enable fastboot and USB host related configs
Enable mtu3, xhci, tphy drivers.
Device mode: enable fastboot;
Host mode: enable USB, FAT commands, and fixed regulator,
mass storage drivers;
Due to device mode is enabled by default, comment out
the host mode config here.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
d6fa8db8b9 arm: dts: mt8512: add usb related nodes
Add usb, usb phy, and fixed regulators nodes

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
252bd2e3ca usb: gadget: Add bcdDevice for the MTU3 USB Gadget Controller
Add an entry in usb_gadget_controller_number() for the MTU3
gadget controller. It is used to bind the USB Ethernet driver.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
e09b88cd08 usb: add MediaTek USB3 DRD driver
This patch adds support for the MediaTek USB3 DRD controller,
its host side is based on xHCI, this driver supports device mode
and host mode.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
d92e866f60 usb: common: add define of usb_speed_string()
There is only declaration of usb_speed_string(), but no definition,
so add it to avoid build error when call it.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
a4de6e380f usb: add USB_SPEED_SUPER_PLUS
Add enum USB_SPEED_SUPER_PLUS for USB3.1

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
78fe97b96e dt-bindings: usb: mtu3: add bindings for MediaTek USB3 DRD
Add dt-binding for MediaTek USB3 DRD Driver which it's ported
from the Linux kernel DTS binding:
Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
Commit ID:
34d0545978b6 ("dt-bindings: usb: mtu3: fix typo of DMA clock name")

Due to Dual-Role switch is not supported in Uboot, some properties
are removed or changed.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
8faef3c756 dt-binding: usb: add bindings for some common properties
Add bindings for common properties, include maximum-speed,
dr_mode and phy_type

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Naoki Hayama
a93cff24b1 usb: musb-new: Fix typo in caution message
%s/Occured/Occurred/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-20 00:48:58 +02:00
Chance.Yang
3065680235 usb: dwc2: Fix control OUT transfer issue
In buffer DMA mode, gadget should re-configure EP 0 to received SETUP
packets when doeptsiz.xfersize is equal to a setup packet size(8 bytes)
and EP 0 is in WAIT_FOR_SETUP state.

Since EP 0 is not enabled in WAIT_FOR_SETUP state, SETUP packets is NOT
received from RxFifo and wriiten to the external memory.

Signed-off-by: Chance.Yang <chance.yang@vatics.com>
2020-10-20 00:48:58 +02:00
Heinrich Schuchardt
3fade88686 usb: xhci: avoid type conversion of void *
void * can be assigned to any pointer variable. Avoid unnecessary
conversions.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-20 00:48:58 +02:00
Patrick Wildt
42f804fbba efi_loader: fix use after free in receive path
With DM enabled the ethernet code will receive a packet, call
the push method that's set by the EFI network implementation
and then free the packet.  Unfortunately the push methods only
sets a flag that the packet needs to be handled, but the code
that provides the packet to an EFI application runs after the
packet has already been freed.

To rectify this issue, adjust the push method to accept the packet
and store it in a temporary buffer.  The EFI application then gets
the data copied from that buffer.  This way the packet is cached
until is is needed.

The DM Ethernet stack tries to receive 32 packets at once, thus
we better allocate as many buffers as the stack.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-19 22:59:53 +02:00
Patrick Wildt
36ea0cab26 net: add a define for the number of packets received as batch
With a define for the magic number of packets received as batch
we can make sure that the EFI network stack caches the same amount
of packets.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-19 22:59:53 +02:00
Tom Rini
7ec87e4192 Merge tag 'u-boot-atmel-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel features for 2021.01 cycle:

This feature set brings the rework of the clock tree for sam9x60 SoC.
This makes the clock tree fully compatible with Common Clock Framework
and allows full clock configuration in U-Boot. This means that the
sam9x60 boards can boot now using U-Boot.
This also includes the definitions for sam9x60 SiPs and a divisor fix
for the clock on sama7g5 SoC.
2020-10-19 09:29:05 -04:00
Eugen Hristev
dc470834a1 clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Eugen Hristev
dff3904254 clk: at91: clk-master: add 5th divisor for mck master
clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Nicolas Ferre
db228c5b46 ARM: at91: Add chip ID for SAM9X60 SiP
SAM9X60 SiP (System in Package) are added for SoC identification.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
42f2dfa789 ARM: dts: sam9x60: use alphabetical order
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
6973701e27 configs: sam9x60ek: update defconfigs for CCF
Update defconfigs for using common clock framework compatible
clocks.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
c37d59a170 ARM: dts: sam9x60: use CCF compatibles for PMC
Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
dbe10b6274 ARM: dts: sam9x60: use slow clock CCF compatible bindings
Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
5dff16db16 ARM: dts: sam9x60: use u-boot,dm-pre-reloc
Use u-boot,dm-pre-reloc for slow xtal and main xtal.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
ffd204f347 ARM: dts: sam9x60ek: add clock frequencies to board file
Slow Xtal and Main Xtal are board specific. Add their proper
frequency to board file.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
a64862284f clk: at91: sam9x60: add support compatible with CCF
Add SAM9X60 clock support compatible with CCF.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
53040bc4d9 board: atmel: sam9x60ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDR
Heap base address is computed based on SYS_INIT_SP_ADDR by
subtracting the SYS_MALLOC_F_LEN value in
board_init_f_init_reserve().

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Tom Rini
e3e9bfab46 Merge tag 'video-for-2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- add dw-mipi-dsi phy timings and Tx escape clock configuration
 - fix pwm backlight duty cycle calculation
 - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
2020-10-18 21:19:06 -04:00
Patrick Delaunay
8fc78fc73b configs: migrate CONFIG_BMP_16/24/32BPP to defconfigs
Done with:
./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18 15:27:01 +02:00
Patrick Delaunay
f9a48654ee configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigs
Done with:
./tools/moveconfig.py VIDEO_BMP_RLE8

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18 15:26:14 +02:00
Patrick Delaunay
0ed6c0f9cb configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigs
Done with:
./tools/moveconfig.py VIDEO_BMP_GZIP

The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN
are not activated in these defconfigs:
- trats_defconfig
- s5pc210_universal_defconfig
- trats2_defconfig

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18 15:25:28 +02:00
Dario Binacchi
76c2ff3e5f video: backlight: fix pwm's duty cycle calculation
For levels equal to the maximum value, the duty cycle must be equal to
the period.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18 15:07:33 +02:00
Dario Binacchi
f9b94055bd video: backlight: fix pwm data structure description
The description of the 'max_level' field was incorrectly assigned to the
'min_level' field.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-10-18 15:06:56 +02:00
Neil Armstrong
01c9857fa8 video: dw-mipi-dsi: permit configuring the escape clock rate
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-18 10:36:05 +02:00
Neil Armstrong
b53c122631 video: dw-mipi-dsi: driver-specific configuration of phy timings
The timing values for dw-dsi are often dependent on the used display and
according to Philippe Cornu will most likely also depend on the used phy
technology in the soc-specific implementation.

To solve this and allow specific implementations to define them as needed
add a new get_timing callback to phy_ops and call this from the dphy_timing
function to retrieve the necessary values for the specific mode.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-18 10:35:06 +02:00
Sean Anderson
3d19a7ee8c test: Fix sandbox tests failing to build
syslog_test.h is in test/log/, not include/

Fixes: 52d3df7fef ("log: Allow LOG_DEBUG to always enable log output")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-17 09:03:22 -04:00
Tom Rini
dadc1e3830 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix Octeon SPI driver for Octeon TX2
- Fix and enhance Octeon watchdog driver
- Misc minor enhancements to Octeon TX/TX2
2020-10-16 09:56:15 -04:00
Tom Rini
da09b99ea5 Merge branch '2020-10-15-further-cleanup_dev_xxx'
- Bring in the next round of dev_xxx cleanup patches.
2020-10-16 09:44:51 -04:00
Sean Anderson
4a1989c0bc dm: Don't undefine dev_xxx macros
Now that linux/compat.h does not define these macros, we do not need to
undefine them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16 09:44:27 -04:00
Sean Anderson
69dae8902b linux/compat.h: Remove redefinition of dev_xxx macros
All users of these functions now include dm/device_compat.h directly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16 09:44:27 -04:00
Tom Rini
2e84463188 usb: dwc3: Include device_compat.h in dwc3-octeon-glue.c
Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16 09:44:27 -04:00
Tom Rini
689639798a clk: at91: Include device_compat.h in compat.c
Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16 09:44:27 -04:00
Tom Rini
e1f306c07c arm: fsl-layerscape: Include device_compat.h in soc.c
Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16 09:44:27 -04:00
Sean Anderson
0b4826a9a8 usb: musb-new: mt85xx: Fix not calling dev_err with a device
This driver doesn't use DM (in the correct places), so we use a device and
not a udevice. We also need to include device_compat.h

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16 09:44:27 -04:00
Sean Anderson
e010524b5d usb: musb-new: Include device_compat.h
This was included, but was ifdef'd out. We also need dm.h for struct
udevice.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16 09:44:27 -04:00
Sean Anderson
f526aee31f usb: xhci: Include device_compat.h
This header is necessary for the dev_xxx macros.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16 09:44:27 -04:00
Sean Anderson
a5d4f86124 timer: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16 09:44:27 -04:00
Sean Anderson
7399897b6c tee: optee: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16 09:44:27 -04:00
Sean Anderson
d13da03f3b spi: fsl_qspi: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16 09:44:27 -04:00
Sean Anderson
06aaca5158 spi: nxp_fspi: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16 09:44:27 -04:00
Stefan Roese
b666714c30 arm: octeontx: Add CMD_WDT
Enable WDT command for Octeon TX/TX2 boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16 13:55:04 +02:00
Suneel Garapati
3981cdd8db watchdog: octeontx_wdt: Add support for start and stop
This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
the WDT. With this changes, the "wdt" command is now also supported
on these platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16 13:55:04 +02:00
Stefan Roese
7a78074c18 arm: octeontx: Select CLK
Clock support is needed for all Octeon TX/TX2 boards. This patch selects
CONFIG_CLK so that it is available.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16 13:55:04 +02:00
Stefan Roese
7353025dd4 mmc: octeontx_hsmmc.c: Remove test debug message
Remove a left-over debug test message from the Octeon TX / TX2
MMC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16 13:55:04 +02:00
Stefan Roese
8a35094faa spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2
Octeon TX2 sets the TB100_EN bit in the config register. We need to use
a fixed 100MHz clock for this as well to work properly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
2020-10-16 13:55:04 +02:00
Sean Anderson
8d4c596644 ram: imxrt: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15 18:36:56 -04:00
Sean Anderson
bdc1fdf6fc phy: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15 18:36:56 -04:00
Sean Anderson
d878ef736d net: ldpaa_eth: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15 18:36:56 -04:00
Sean Anderson
baed179d2f mtd: mxs_nand: Fix not calling dev_xxx with a device
This includes device_compat.h, and fixes several calls to dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15 18:36:56 -04:00
Sean Anderson
66e7348fe7 firmware: scmi: Include device_compat.h
This header is necessary for the dev_xxx macros.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-15 18:36:55 -04:00
Sean Anderson
4d55155f6c dm: syscon: Set LOG_CATEGORY
We call log_debug, but do not have a category set.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-15 18:36:55 -04:00
Sean Anderson
0f0f4e5feb clk: sifive: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15 18:36:55 -04:00
Tom Rini
9dc6aef8c9 Merge tag 'mmc-2020-10-14' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc_imx cleanup
- not send cm13 if send_status is 0.
- Add reinit API
- Add mmc HS400 for fsl_esdhc
- Several cleanup for fsl_esdhc
- Add ADMA2 for sdhci
2020-10-15 08:20:42 -04:00
Andre Heider
c87afd39d1 configs: smdkv310: get rid of unused EXYNOS4_DEFAULT_UART_OFFSET
Unused.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-10-15 13:33:22 +09:00
Andre Heider
023951038f Remove whitelist entry CONFIG_DEFAULT_CONSOLE
There're no users left.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-10-15 13:33:22 +09:00
Andre Heider
9c04265f76 treewide: configs: fold CONFIG_DEFAULT_CONSOLE
In prepartion to remove CONFIG_DEFAULT_CONSOLE, fold the current users.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-10-15 13:33:22 +09:00
Andre Heider
ac79cfc2a4 treewide: configs: get rid of unused CONFIG_DEFAULT_CONSOLE
These are all unused.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-10-15 13:33:22 +09:00
Tom Rini
0f35d96bfd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Octeon TX: Add NAND driver (Suneel)
- Octeon TX: Add NIC driver driver (Suneel)
- Octeon TX2: Add NIC driver driver (Suneel)
- Armada 8040: Add iEi Puzzle-M80 board support (Luka)
- Armada A37xx SPI: Add support for CS-GPIO (George)
- Espressobin: Use Linux model/compatible strings (Andre)
- Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre)
- Armada A37xx: Small cleanup of config header (Pali)
2020-10-14 13:51:56 -04:00
Tom Rini
6731c5a5ef Merge branch '2020-10-14-assorted-changes'
- Add support for Linux "pstore" dumps.
- Button command fixup.
- gd cleanup and documentation.
- Assorted other cleanups.
2020-10-14 13:35:05 -04:00
Heinrich Schuchardt
40a3008632 doc: Sphinx.override_domain() deprecated
Sphinx.override_domain() is deprecated since Sphinx 1.8 and removed in
Sphinx 3.

Use Sphinx.add_domain(, override=True) instead.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-14 11:16:34 -04:00
Christian Gmeiner
c90778ad70 net: e1000: add defaults for i210 TX/RX PBSIZE
Set the defaults on probe for the packet buffer size registers
for the i210.

The TX/RX PBSIZE register of the i210 resets to its default value
only at power-on - see Intel Ethernet Controller I210 Datasheet rev 3.5
chapter 8.3 'Internal Packet Buffer Size Registers'.

If something (another driver, another OS, etc.) modifies this register
from its default value, the e1000 driver doesn't function correctly. It
detects a hang of the transmitter and continuously resets the adapter.
Here we set this value to its default when resetting the i210 to
resolve this issue.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-10-14 11:16:34 -04:00
Alper Nebi Yasak
b9cca2c57a checkpatch.pl: Make CONFIG_IS_ENABLED(CONFIG_*) an error
CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix,
e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Make including the prefix
an error in checkpatch.pl so calls in the wrong format aren't
accidentally reintroduced.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14 11:16:34 -04:00
Alper Nebi Yasak
957a3e5493 treewide: Fix wrong CONFIG_IS_ENABLED() handling
CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix,
e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being
fixed every now and then, see:

    commit 71ba2cb0d6 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED")
    commit a5ada25e42 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling")
    commit 5daf6e56d3 ("common: console: Fix duplicated CONFIG in silent env callback")
    commit 48bfc31b64 ("MIPS: bootm: Fix broken boot_env_legacy codepath")

Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running
':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14 11:16:34 -04:00
Heinrich Schuchardt
467d90a37e doc: global data pointer
Add the description of the global data pointer to the generated HTML
documentation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14 11:16:34 -04:00
Heinrich Schuchardt
0c7cd15f3f global_data.h: add Sphinx documentation
Add the missing Sphinx documentation for struct global_data and
gd_board_type().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14 11:16:34 -04:00
Heinrich Schuchardt
c82a97bc5c global_data.h: convert GD_FLG_* to enum
Sphinx documentation is only available for enums not for #defines.
Anyway it is better to keep related definitions in an enum.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14 11:16:34 -04:00
Heinrich Schuchardt
73fdb9558e bootm: add {arch,board}_preboot_os() to bootm.h
Functions that are used in multiple C modules should be defined in an
include.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Michael Walle <michael@walle.cc>
2020-10-14 11:16:34 -04:00
Sean Anderson
4b2be78ab6 time: Fix get_ticks being non-monotonic
get_ticks does not always succeed. Sometimes it can be called before the
timer has been initialized. If it does, it returns a negative errno.
This causes the timer to appear non-monotonic, because the value will
become much smaller after the timer is initialized.

No users of get_ticks which I checked handle errors of this kind. Further,
functions like tick_to_time mangle the result of get_ticks, making it very
unlikely that one could check for an error without suggesting a patch such
as this one.

This patch panics if we ever get an error. There are two cases in which
this can occur. The first is if we couldn't find/probe the timer for some
reason. One reason for this is if the timer is not available so early. This
likely indicates misconfiguration. Another reason is that the timer has an
invalid/missing device tree binding. In this case, panicing is also
correct. The second case covers errors calling get_count. This can only
occur if the timer is missing a get_count function (or on RISC-V, but that
should be fixed soon).

Fixes: c8a7ba9e6a
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14 11:16:34 -04:00
Otavio Salvador
d74fcee2d8 spl: Add SPL_SERIAL as requirement for SDP_USB_SDP
The USB SDP protocol require the SPL serial support to allow the build
to succeed.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2020-10-14 11:16:34 -04:00
Otavio Salvador
f9b9b77933 spl: Avoid printing boot device if silent console is enabled
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 11:16:34 -04:00
David Woodhouse
b0493bb75a env/ext4.c: allow loading from an EXT4 partition on the MMC boot device
This parallels what I added for FAT in commit 6731bef696, allowing the
environment to be found in a specific partition on the device that the
board's mmc_get_env_dev() returns. On the Banana Pi R2 that means the
device that U-Boot was loaded from; either the internal eMMC or an SD
card.

Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2020-10-14 11:16:34 -04:00
David Woodhouse
4dee3f7851 mmc: remove duplicate mmc_get_env_dev() implementations
Since it's so trivial I could just about tolerate this when there were only
two copies of it. But now there are about to be three.

Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2020-10-14 11:16:34 -04:00
Heinrich Schuchardt
684710dc33 arm: enable DM_RNG on QEMU by default
The EFI_RNG_PROTOCOL is needed for address randomization in Linux.
We should provide it by default on QEMU.

Reported-by: François Ozog <francois.ozog@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-14 11:16:34 -04:00
Heinrich Schuchardt
a6bfd71a96 cmd/button: return button status
To make the button command useful in a shell script it should return the
status of the button:

* 0 (true) - pressed, on
* 1 (false) - not pressed, off

The button command takes only one argument. Correct maxargs.

Adjust the Python unit test.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-10-14 11:16:34 -04:00
Heinrich Schuchardt
7cd96a4728 drivers: gpio: keep output value for input on sandbox
For testing purposes keep the output value when switching to input.
This allows us to manipulate the input value via the gpio command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-10-14 11:16:34 -04:00
Heinrich Schuchardt
39916bb45f test: sharpen button label unit test
Using different strings for the device tree node labels and the label
property of buttons sharpens the button label unit test.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-10-14 11:16:34 -04:00
Frédéric Danis
9ea0a1ee93 cmd: Fixup DT to pass PStore Ramoops parameters
To simplify configuration and keep synchronized the PStore/Ramoops between
U-Boot and the Linux kernel, this commit dynamically adds the Ramoops
parameters defined in the U-Boot session to the Device Tree.

Signed-off-by: Frédéric Danis <frederic.danis@collabora.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2020-10-14 11:16:34 -04:00
Frédéric Danis
26f555a6e5 test: Add PStore command tests
Add PStore command to sandbox and sandbox64 defconfigs.
Add test checking:
- 'pstore display' of all records
- 'pstore display' only the 2nd dump record
- 'pstore save' of all records

Signed-off-by: Frédéric Danis <frederic.danis@collabora.com>
[trini: Adjust to always load files from source directory]
Signed-off-by: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2020-10-14 11:16:34 -04:00
Frédéric Danis
9744d1a547 cmd: Add command to display or save Linux PStore dumps
This patch adds a new pstore command allowing to display or save ramoops
logs (oops, panic, console, ftrace and user) generated by a previous
kernel crash.
PStore parameters can be set in U-Boot configuration file, or at run-time
using "pstore set" command. Records size should be the same as the ones
used by kernel, and should be a power of 2.
This command allows:
- to display uncompressed logs
- to save compressed or uncompressed logs, compressed logs are saved as a
  compressed stream, it may need some work to be able to decompress it,
  e.g. adding a fake header:
  "printf "\x1f\x8b\x08\x00\x00\x00\x00\x00\x00\x00" |
  cat - dmesg-ramoops-0.enc.z | gzip -dc"
- ECC part is not used to check memory corruption
- only 1st FTrace log is displayed or saved

Signed-off-by: Frédéric Danis <frederic.danis@collabora.com>
[trini: Minor updates for current design, correct spacing in rST]
Signed-off-by: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2020-10-14 11:16:19 -04:00
Michael Walle
361a422b90 mmc: fsl_esdhc: add ADMA2 support
Newer eSDHC controllers support ADMA2 descriptor tables which support
64bit DMA addresses. One notable user of addresses in the upper memory
segment is the EFI loader.

If support is enabled, but the controller doesn't support ADMA2, we
will fall back to SDMA (and thus 32 bit DMA addresses only).

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-14 14:00:44 +08:00
Michael Walle
52faec3182 mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()
Make the code cleaner and drop the old-style #ifdef constructs where it is
possible.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-14 14:00:37 +08:00
Pali Rohár
8369886b40 arm: mvebu: Remove old comments from configs/mvebu_armada-37xx.h file
These comments are relict for old, now removed config options.
So remove these obsoleted comments too.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:56:17 +02:00
Andre Heider
f1a43c84a9 arm64: dts: a3720: add support for espressobin with populated emmc
Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for
emmc, since our dtsi is still based on downstream and sdhc0 is used for
the sd card.

Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-10-14 07:56:17 +02:00
Andre Heider
03bb6a9b1e arm64: dts: armada-3720-espressobin: split common parts to .dtsi
Move most of the dts to the new common armada-3720-espressobin.dtsi
file, just like Linux, but keep the current, downstream based, version.

The dts itself is imported from Linux.

Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-10-14 07:56:17 +02:00
Andre Heider
559ae35c96 arm64: dts: armada-3720-espressobin: use Linux model/compatible strings
Fix the actual board vendor and ease synching dts files from Linux.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
George Hilliard
2df286390a spi: mvebu_a3700_spi: add support for cs-gpios
The device tree has a way to specify GPIO lines as chip selects.  From
the binding docs:

    So if for example the controller has 2 CS lines, and the cs-gpios
    property looks like this:

    cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;

    Then it should be configured so that num_chipselect = 4 with the
    following mapping:

    cs0 : &gpio1 0 0
    cs1 : native
    cs2 : &gpio1 1 0
    cs3 : &gpio1 2 0

Add support for this, while retaining backward-compatibility with
existing device trees; the driver will preserve existing behavior if a
cs-gpios list is not given, or if a particular line is specified as <0>
(native).

This implementation is inspired by similar implementations in
neighboring drivers for other platforms: atmega, mxc, etc.

Signed-off-by: George Hilliard <ghilliar@amazon.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Luka Kovacic
87c220d041 arm: mvebu: mvebu_armada-8k: Add support for initializing iEi Puzzle-M801 networking
Add support for the marvell,armada8040-puzzle-m801 compatible string
in the board/Marvell/mvebu_armada-8k/board.c file to initialize the
networking on iEi Puzzle-M801 board (2x CP1 1 Gb ports).

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Luka Kovacic
2ae2b8a2f2 arm: mvebu: Initial iEi Puzzle-M801 support
Add initial U-Boot support for the iEi Puzzle-M801 board based on the
Marvell Armada 88F8040 SoC.

Currently supported hardware:
1x USB 3.0
4x Gigabit Ethernet
2x SFP+ (with NXP PCA9555 and NXP PCA9544)
1x SATA 3.0
1x M.2 type B
1x RJ45 UART
1x SPI flash
1x EPSON RX8010 RTC

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Suneel Garapati
4684a7a43a net: Add NIC controller driver for OcteonTX2
Adds support for Network Interface controllers found on
OcteonTX2 SoC platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-10-14 07:55:56 +02:00
Suneel Garapati
0008e9a69d net: Add NIC controller driver for OcteonTX
Adds support for Network Interface controllers found on
OcteonTX SoC platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-10-14 07:55:56 +02:00
Suneel Garapati
05c7606ac9 mtd: nand: Add NAND controller driver for OcteonTX
Adds support for NAND controllers found on OcteonTX or
OcteonTX2 SoC platforms. Also includes driver to support
Hardware ECC using BCH HW engine found on these platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Tom Rini
55fca74a5b Merge branch '2020-10-12-assorted-encryption-changes'
- Fix verified boot on BE targets
- Add support for multiple required keys in verified boots
- Add support for Initialization Vectors in AES keys in FIT images
- Assorted fixes in the RSA code
2020-10-13 10:04:17 -04:00
Heinrich Schuchardt
ec71cc34c1 lib: rsa: superfluous initialization in rsa_verify()
Remove initialization of ret with unused value.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-12 21:30:38 -04:00
Rasmus Villemoes
3f8808ebaa rsa: fix retrieving public exponent on big-endian systems
Commit fdf0819afb (rsa: fix alignment issue when getting public
exponent) changed the logic to avoid doing an 8-byte access to a
possibly-not-8-byte-aligned address.

However, using rsa_convert_big_endian is wrong: That function converts
an array of big-endian (32-bit) words with the most significant word
first (aka a BE byte array) to an array of cpu-endian words with the
least significant word first. While the exponent is indeed _stored_ as
a big-endian 64-bit word (two BE words with MSW first), we want to
extract it as a cpu-endian 64 bit word. On a little-endian host,
swapping the words and byte-swapping each 32-bit word works, because
that's the same as byte-swapping the whole 64 bit word. But on a
big-endian host, the fdt32_to_cpu are no-ops, but
rsa_convert_big_endian() still does the word-swapping, breaking
verified boot.

To fix that, while still ensuring we don't do unaligned accesses, add
a little helper that first memcpy's the bytes to a local fdt64_t, then
applies fdt64_to_cpu(). [The name is chosen based on the
[bl]eXX_to_cpup in linux/byteorder/generic.h].

Fixes: fdf0819afb ("rsa: fix alignment issue when getting public exponent")
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-12 21:30:38 -04:00
Matthieu CASTET
167fb1f8dc lib: rsa: check algo match in rsa_verify_with_keynode
The algo name should match between the FIT's signature node and the
U-Boot's control FDT.

If we do not check it, U-Boot's control FDT can expect sha512 hash but
nothing will prevent to accept image with sha1 hash if the signature is correct.

Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr>
2020-10-12 21:30:38 -04:00
Philippe Reynes
54ab7cf1dd fit: cipher: aes: allow to read the IV in the FIT image
This commit add the support in u-boot to read the IV
in the FIT image instead of u-boot device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-10-12 21:30:38 -04:00
Philippe Reynes
a6982a6f76 fit: cipher: aes: allow to store the IV in the FIT image
Binaries may be encrypted in a FIT image with AES. This
algo needs a key and an IV (Initialization Vector). The
IV is provided in a file (pointer by iv-name-hint in the
ITS file) when building the ITB file.

This commits adds provide an alternative way to manage
the IV. If the property iv-name-hint is not provided in
the ITS file, the tool mkimage will generate an random
IV and store it in the FIT image.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-10-12 21:30:37 -04:00
Heinrich Schuchardt
34ca77c1e1 lib/hashtable: remove superfluous check
We assign first_deleted = 0. There is no need to check its value without
any further assignment in between.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-12 21:30:37 -04:00
Thirupathaiah Annapureddy
6a0498a5fd doc: verified-boot: add required-mode information
Add documentation about 'required-mode' property in /signature node
in U-Boot's control FDT.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-12 21:30:37 -04:00
Thirupathaiah Annapureddy
feaeee8b5f test: vboot: add tests for multiple required keys
This patch adds vboot tests to verify the support for multiple
required keys using new required-mode DTB policy.

This patch also fixes existing test where dev
key is assumed to be marked as not required, although
it is marked as required.

Note that this patch re-added sign_fit_norequire().
sign_fit_norequire() was removed as part of the following:
commit b008677daf ("test: vboot: Fix pylint errors").
This patch leverages sign_fit_norequire() to fix the
existing bug.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-12 21:30:37 -04:00
Thirupathaiah Annapureddy
182eeefcb4 vboot: add DTB policy for supporting multiple required conf keys
Currently FIT image must be signed by all required conf keys. This means
Verified Boot fails if there is a signature verification failure
using any required key in U-Boot DTB.

This patch introduces a new policy in DTB that can be set to any required
conf key. This means if verified boot passes with one of the required
keys, U-Boot will continue the OS hand off.

There were prior attempts to address this:
https://lists.denx.de/pipermail/u-boot/2019-April/366047.html
The above patch was failing "make tests".
https://lists.denx.de/pipermail/u-boot/2020-January/396629.html

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-12 21:30:37 -04:00
Tom Rini
9885313b9a Merge branch 'for-next' of https://github.com/lftan/u-boot 2020-10-12 07:55:17 -04:00
Tom Rini
47e9c70421 Merge tag 'ti-v2021.01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Minor cleanup on K3 env variables
- Fix OSPI compatible for J721e
- Drop unused property in omap-usb2-phy
- Update Maintainer for am335x-guardian board.
2020-10-12 07:26:57 -04:00
Haibo Chen
c7f4418c8b mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32
Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align
the usage, change to only use esdhc_read32/esdhc_write32.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-10-12 15:53:39 +08:00
Heinrich Schuchardt
46cb3afd39 mmc: do not check argument of free() beforehand
free() checks if its argument in NULL. No need to check it twice.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-12 15:53:20 +08:00
Michael Walle
4d6a773b1c mmc: sdhci: move the ADMA2 table handling into own module
There are other (non-SDHCI) controllers which supports ADMA2 descriptor
tables, namely the Freescale eSDHC. Instead of copying the code, move it
into an own module.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12 15:50:19 +08:00
Michael Walle
7e48a028a4 mmc: fsl_esdhc: simplify esdhc_setup_data()
First, we need the waterlevel setting for PIO mode only. Secondy, both DMA
setup code is identical for both directions, except for the data pointer.
Thus, unify them.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12 15:49:18 +08:00
Michael Walle
b1ba1460a4 mmc: fsl_esdhc: use dma-mapping API
Use the dma_{map,unmap}_single() calls. These will take care of the
flushing and invalidation of caches.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12 15:49:09 +08:00
Michael Walle
da86e8cfcb mmc: fsl_esdhc: simplify 64bit check for SDMA transfers
SDMA can only do DMA with 32 bit addresses. This is true for all
architectures (just doesn't apply to 32 bit ones). Simplify the code and
remove unnecessary CONFIG_FSL_LAYERSCAPE.

Also make the error message more concise.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12 15:48:50 +08:00
Haibo Chen
9098682200 mmc: fsl_esdhc_imx: remove the 1ms delay before sending command
This 1ms delay before sending command already exist from the beginning
of the fsl_esdhc driver added in year 2008. Now this driver has been
split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c
only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay
before sending any command. So remove this 1ms, this will save a lot
time if handling a large mmc data.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-10-12 15:48:13 +08:00
Haibo Chen
ef5ab0d13a mmc: do not send cmd13 if the parameter 'send_status' is 0 for __mmc_switch
According to the code logic in __mmc_switch, if the parameter 'send_status'
is zero, no need to send cmd13, just wait the stated timeout time, then
can return directly.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-10-12 15:48:13 +08:00
Yangbo Lu
d3c610c623 configs: lx2160ardb: enable eMMC HS400 mode support
Enable eMMC HS400 mode support on LX2160ARDB.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:47:08 +08:00
Yangbo Lu
dedd632f56 arm: dts: lx2160ardb: support eMMC HS400 mode
Add properties related to eMMC HS400 mode.

mmc-hs400-1_8v;
bus-width = <8>;

They had been already in kernel dts file since the first
lx2160ardb dts patch.

b068890 arm64: dts: add LX2160ARDB board support

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:47:07 +08:00
Yangbo Lu
78804de483 mmc: fsl_esdhc: fix eMMC HS400 stability issue
There was a fix-up for eMMC HS400 stability issue in Linux.

Patch link:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53

Description:
Currently only LX2160A eSDHC supports eMMC HS400. According to
a large number of tests, eMMC HS400 failed to work at 150MHz,
and for a few boards failed to work at 175MHz. But eMMC HS400
worked fine on 200MHz. We hadn't found the root cause but
setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain
seemed to resovle this issue. Let's use this as fixup for now.

Introduce the fix-up in u-boot since the issue could be reproduced
in u-boot too.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:47:06 +08:00
Yangbo Lu
30f6444d02 mmc: fsl_esdhc: fix mmc->clock with actual clock
Fix mmc->clock with actual clock which is divided by the
controller, and record it with priv->clock which was removed
accidentally.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:47:05 +08:00
Yangbo Lu
db8f93672b mmc: fsl_esdhc: support eMMC HS400 mode
The process for eMMC HS400 mode for eSDHC is,

1. Perform the Tuning Process at the HS400 target operating frequency.
   Latched the clock division value.
2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG].
3. Switch to High Speed mode and then set the card clock frequency to
   a value not greater than 52Mhz
4. Clear TBCTL[TB_EN],tuning block enable bit.
5. Change to 8 bit DDR Mode
6. Switch the card to HS400 mode.
7. Set TBCTL[TB_EN], tuning block enable bit.
8. Clear SYSCTL[SDCLKEN]
9. Wait for PRSSTAT[SDSTB] to be set
10. Change the clock division to latched value.Set TBCTL[HS 400 mode]
    and Set SDCLKCTL[CMD_CLK_CTRL]
11. Set SYSCTL[SDCLKEN]
12. Wait for PRSSTAT[SDSTB] to be set
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
14. Wait for delay chain to lock.
15. Set TBCTL[HS400_WNDW_ADJUST]
16. Again clear SYSCTL[SDCLKEN]
17. Wait for PRSSTAT[SDSTB] to be set
18. Set ESDHCCTL[FAF]
19. Wait for ESDHCCTL[FAF] to be cleared
20. Set SYSCTL[SDCLKEN]
21. Wait for PRSSTAT[SDSTB] to be set.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:46:34 +08:00
Yangbo Lu
d271e10581 mmc: add a mmc_hs400_prepare_ddr() interface
Add a mmc_hs400_prepare_ddr() interface for controllers
which needs preparation before switching to DDR mode for
HS400 mode.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:46:34 +08:00
Yangbo Lu
8c96880814 mmc: add a hs400_tuning flag
Some controllers may have difference between HS200 tuning
and HS400 tuning, such as different registers setting,
different procedure, or different errata.

This patch is to add a hs400_tuning flag to identify the
tuning for HS400 mode.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:46:32 +08:00
Yangbo Lu
1b5f0ba7a5 mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during init
Clean TBCTL[TB_EN] manually during init since it is not able to
be reset by reset all operation.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:46:30 +08:00
Yangbo Lu
b1a4247b41 mmc: fsl_esdhc: support tuning for eMMC HS200
Support tuning process for eMMC HS200 for eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:46:29 +08:00
Yangbo Lu
1fdefd1d0d mmc: fsl_esdhc: add a reinit() callback
Add a reinit() callback for mmc rescan.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-12 15:45:40 +08:00
Yangbo Lu
390f9bddb9 mmc: add a reinit() API
For DM_MMC, the controller re-initialization is needed to
clear old configuration for mmc rescan.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-12 15:45:39 +08:00
Vignesh Raghavendra
555ee39493 phy: omap-usb2-phy: Drop usage of "ti, dis-chg-det-quirk" DT property
"ti,dis-chg-det-quirk" property is not part of Linux kernel DT binding
documentation.  Therefore drop this and instead use soc_device_match()
to distinguish b/w AM654 SR1.0 and SR2.0 devices similar to Linux kernel
driver.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-10-12 08:11:11 +05:30
Nishanth Menon
87b4521fd8 configs: am65x_evm: Use DEFAULT_LINUX_BOOT_ENV and remove overlayaddr
Use DEFAULT_LINUX_BOOT_ENV to define the standard addresses used in rest
of TI platforms as defined in ti_armv7_common.h

This avoids the standard pitfalls we've had with kernel images and fdt
addresses stomping on each other.

As part of this process, redefine overlayaddr to be dtboaddr (defined
in ti_armv7_common.h for this very purpose) and get rid of the
definition of overlayaddr..

Signed-off-by: Nishanth Menon <nm@ti.com>
2020-10-12 08:09:53 +05:30
Nishanth Menon
a9cdba9cc1 configs: j721e_evm: Get rid of overlayaddr
Now that we dont have any further users of overlayaddr, get rid of it.

Signed-off-by: Nishanth Menon <nm@ti.com>
2020-10-12 08:09:53 +05:30
Nishanth Menon
cb56936ce5 env: ti: ufs: Use dtboaddr instead of overlayaddr
Use dtboaddr to define the overlay address common to all TI platforms
instead of creating a new overlayaddr for the purpose.

Signed-off-by: Nishanth Menon <nm@ti.com>
2020-10-12 08:09:53 +05:30
Nishanth Menon
25364f5ec8 configs: j721e_evm: Use DEFAULT_LINUX_BOOT_ENV
Use DEFAULT_LINUX_BOOT_ENV to define the standard addresses used in rest
of TI platforms as defined in ti_armv7_common.h

This avoids the standard pitfalls we've had with kernel images and fdt
addresses stomping on each other.

As part of this process, redefine overlayaddr to be dtboaddr (defined
in ti_armv7_common.h for this very purpose).. we will get rid of
overlayaddr later in the series.

Signed-off-by: Nishanth Menon <nm@ti.com>
2020-10-12 08:09:53 +05:30
Vignesh Raghavendra
85bdcf03b7 dma: ti: k3-udma: Reset the channel during release
Reset the channel completely during channel release in order to clear
teardown bit before handing over to next user or jumping to Linux.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-10-12 08:09:18 +05:30
Vignesh Raghavendra
6d7364016a configs: am335x_evm_defconfig: Enable CONFIG_OF_LIBFDT_OVERLAY
This enables applying DTBOs at U-Boot prompt before booting to kernel.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-10-12 08:08:28 +05:30
Vignesh Raghavendra
5a8a7a95a0 board: ti: j721e: Fix OSPI node compatible
Update detect_enable_hyperflash() to look for "ti,am654-ospi" compatible
to match the upstream DT node.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-10-12 08:07:41 +05:30
Moses Christopher
381c5c163c am335x, guardian: update the maintainer list
I am leaving Bosch, so replacing myself with Gireesh

Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
2020-10-12 08:03:38 +05:30
Tom Rini
726561a941 Merge branch '2020-10-10-log-improvements'
- Assorted improvements to our log functionality.
2020-10-11 15:22:05 -04:00
Heinrich Schuchardt
1ecb6beb95 doc: remove redundant doc/README.log
doc/README.log was already moved to doc/develop/logging.rst but has been
recreated by an incorrect merge.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-10 16:50:35 -04:00
Sean Anderson
a4326612ac log: syslog: Handle errors in net_init
Since the previous patch, net_init now exposes some errors, so check for
them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-10 16:50:12 -04:00
Sean Anderson
c3f0278e29 net: Expose some errors generated in net_init
net_init does not always succeed, and there is no existing mechanism to
discover errors. This patch allows callers of net_init (such as net_init)
to handle errors. The root issue is that eth_get_dev can fail, but
net_init_loop doesn't expose that. The ideal way to fix eth_get_dev would
be to return an error with ERR_PTR, but there are a lot of callers, and all
of them just check if it's NULL. Another approach would be to change the
signature to something like

int eth_get_dev(struct udevice **pdev)

but that would require rewriting all of the many callers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-10 16:50:12 -04:00
Simon Glass
c7f5b85034 log: Disable the syslog driver by default
This driver interferes with other sandbox tests since it causes log output
to be interspersed with "No ethernet found." messages. Disable this driver
by default.

Enable it for the syslog tests so that they still pass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-10 16:50:11 -04:00
Simon Glass
3d03ab6361 log: Add a way to enable/disable a log device
At present all log devices are enabled by default. Add a function to allow
devices to be disabled or enabled at runtime.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-10 16:50:11 -04:00
Simon Glass
bd180db2cc log: Drop #ifdef in log_test
This is not needed as the Makefile only builds the file if CONFIG_LOG_TEST
is enabled. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-10 16:50:11 -04:00
Simon Glass
b45203004e log: Add a flag to enable log drivers
At present there is no way to disable a log driver. But the syslog driver
causes (attempted) network traffic in sandbox every time a log message
is printed, which is often.

Add a flag to enable a log driver. Adjust struct log_device to use a short
for next_filter_num so that no more memory is used for devices. Also fix
a missing line in the struct log_driver comment while here.

To maintain compatibility, enable it for all drivers for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-10 16:50:11 -04:00
Simon Glass
26637e2e4c lib: Allow hexdump to be used in SPL
It is sometimes useful to output hex dumps in SPL. Add a config option to
allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-10 16:49:58 -04:00
Simon Glass
52d3df7fef log: Allow LOG_DEBUG to always enable log output
At present if CONFIG_LOG enabled, putting LOG_DEBUG at the top of a file
(before log.h inclusion) causes _log() to be executed for every log()
call, regardless of the build- or run-time logging level.

However there is no guarantee that the log record will actually be
displayed. If the current log level is lower than LOGL_DEBUG then it will
not be.

Add a way to signal that the log record should always be displayed and
update log_passes_filters() to handle this.

With the new behaviour, log_debug() will always log if LOG_DEBUG is
enabled.

Move log_test_syslog_nodebug() into its own file since it cannot be made
to work where it is, with LOG_DEBUG defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-10 16:49:58 -04:00
Tom Rini
0437cc4155 Merge branch '2020-10-09-kconfig-reorg'
- Re-organize a number of Kconfig related entries to be better organized
  for long term maintenance.
2020-10-09 18:10:24 -04:00
Tom Rini
0817daa760 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-09 12:22:06 -04:00
Simon Glass
1fa057be4a Kconfig: Create a new tools menu
At present MKIMAGE_DTC_PATH is in the devicetree menu but not within
'devicetree control' since it does not relate to that. As a result it
shows up in the top menu.

It actually relates to the mkimage tool, so create a new tools menu for it
and move it there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:02:26 -04:00
Simon Glass
a4c4ecf4c9 Kconfig: Move BOARD_TYPES under init options
This actually relates to something displayed on start-up, so move it into
that menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:02:26 -04:00
Simon Glass
d472d821f3 Kconfig: Move BOUNCE_BUFFER under driver options
This option does not belong at the top level. Move it under generic
driver options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:02:25 -04:00
Simon Glass
bc438b6e9a Kconfig: Move VERSION_VARIABLE under environment
This relates to the environment so should not be at the top level. Move
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:01:55 -04:00
Simon Glass
7e349e9669 Kconfig: MISC_INIT_R and BOARD_LATE_INIT -> start-up hooks
These are start-up hooks so put them under that menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:01:55 -04:00
Simon Glass
386631365d Kconfig: Move startup hooks under init options
These hooks relate to U-Boot init so move them under that menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:01:55 -04:00
Simon Glass
7df39e5b95 Kconfig: Create a new 'init options' menu
There are quite a few options at the top level relating to U-Boot init.
Move them into their own menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:01:55 -04:00
Simon Glass
832876a46a Kconfig: Move DEFAULT_FDT_FILE under boot options
This relates to booting since it is the default devicetree provided to
Linux. Move it under the 'boot options' menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:01:55 -04:00
Simon Glass
aefa34f55e Kconfig: Move SUPPORT_RAW_INITRD under boot options
This relates to booting, so move it under the 'boot images' menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:01:55 -04:00
Simon Glass
fe5db255f4 Kconfig: Move misc boot options under 'boot options'
There are a number of miscellaneous boot images at the top level of the
kconfig menu. Move these into the 'boot options' menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 12:01:54 -04:00
Simon Glass
95fd4f3330 Kconfig: Move CONFIG_BOOTDELAY under autoboot options
This option relates to autoboot, so move it there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 11:59:51 -04:00
Simon Glass
98eed0d4f9 Kconfig: Move autoboot options under boot options
At present the autoboot options are in cmd/Kconfig but they don't really
relate to commands. They relate to booting, so move this menu under the
boot menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 11:59:50 -04:00
Simon Glass
7b6baa3314 Kconfig: Move boot media under boot options
This relates to booting, so move it under the boot menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 11:59:50 -04:00
Simon Glass
75e65cc72e Kconfig: Move boot timing under boot options
This relates to booting, so move it under the boot menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 11:59:50 -04:00
Simon Glass
cf29816768 Kconfig: Move boot menu into common/
Most of the boot options are in common/Kconfig but that file is already
extremely large. Create a new Kconfig.boot to hold the boot options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 11:59:48 -04:00
Simon Glass
b81736d475 Kconfig: Add a 'Boot options' menu
There are quite a few boot-related menu options at the top level. Create a
new menu to hold these and move 'Boot images' into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09 11:57:45 -04:00
Tom Rini
0570938e3c Merge branch '2020-10-08-misc-board-improvements'
- Move ASPEED ram driver, update.
- Exhance pinctrl/gpio support, update Kendryte K210 support
- Enhance qemu_arm64 support for a single binary to work with and
  without TF-A
2020-10-09 08:58:56 -04:00
Chee Hong Ang
505dc1c679 Makefile: socfpga: Generate sfp file with 4 SPL images
Generate 'u-boot-splx4.sfp' which consist of 4 SPL images required
for booting up Cyclone5/Arria10.

By default, this 'u-boot-splx4.sfp' is generated without extra
padding after each SPL image.

For Cyclone5, 'u-boot-splx4.sfp' contains:
4 x SPL(64KB) = 256KB

For Arria10, 'u-boot-splx4.sfp' contains:
4 x SPL(256KB) = 1024KB

For Cyclone5 using NAND flash image layout for 128 KB memory blocks,
user can 'make' the following target to generate 4 SPL images with
padding:

make u-boot-spl-padx4.sfp

'u-boot-spl-padx4.sfp' contains four 128KB SPL images (each 64KB SPL is
followed by 64KB of zero-padding).
4 x (SPL(64KB) + zero-padding(64KB)) = 512KB

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:17 +08:00
Chee Hong Ang
269564ccf4 arm: socfpga: soc64: Remove CONFIG_OF_EMBED
CONFIG_OF_EMBED was primarily enabled to support the S10/Agilex
spl hex file requirements.  Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:16 +08:00
Ley Foon Tan
1d0dc5bc2d tools: socfpgaimage: Add param entry point (ep) support for Arria 10 (v1)
Add param entry point (ep) support for Arria 10 header. User can pass in
'e' option to mkimage to set the entry point. This is an optional option.

If not specified, default is 0x14.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:16 +08:00
Ley Foon Tan
963e17ab46 tools: socfpgaimage: Add check params function for Arria 10 (v1)
Add check params function for Arria 10 (header v1).

From [1] page 42, entry point offset should be 4 bytes aligned and
any value smaller than 0x14 is invalid.

Rename existing socfpgaimage_check_params() for v0.

[1]: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:15 +08:00
Ley Foon Tan
98c28a79b4 arm: dts: socfpga: arria10: Move to use generic handoff dtsi
Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include
the specify generated _handoff.h header file from qts-filter-a10.sh script.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Dalon Westergreen
ed9c0823c5 arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC
Add the qts-filter-a10.sh generated handoff header file for the Arria10
SoCDK SDMMC u-boot device tree.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Dalon Westergreen
5c0adb0a71 arm: socfpga: arria10: Add qts-filter for Arria10 socfpga
Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Chee Hong Ang
5bbeaaefec arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
Don't invoke 'SYSTEM_RESET' PSCI function because PSCI
function calls are not supported by u-boot running in EL3.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:14 +08:00
Ley Foon Tan
de84e2d8c9 arm: socfpga: mailbox: Add mailbox retry support
Resend mailbox command for 3 times with 2ms interval in between if
it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code.

Add a wrapper function mbox_send_cmd_common_retry() for retry, change
all the callers to use this wrapper function.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Ley Foon Tan
6a48f95c6b arm: socfpga: mailbox: Update mailbox response codes
Sync latest mailbox response codes from SDM firmware.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
f6dcf40759 arm: socfpga: mailbox: Support sending large mailbox command
Mailbox command which is too large to fit into the mailbox
FIFO command buffer can be sent to SDM in multiple parts.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
833230ed33 arm: socfpga: mailbox: Always read mailbox responses before returning status
Mailbox driver should always check for the length of the response
and read the response data before returning the response status to
caller.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
e3fca5072b arm: socfpga: mailbox: Refactor mailbox timeout event handling
Add miliseconds delay when waiting for mailbox event to happen
before timeout. This will ensure the timeout duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chin Liang See
e2afbee50c arm: socfpga: soc64: Document down boot_scratch_cold register usage
Document down the usage of boot_scratch_cold register to avoid
overlapping of usage in the code for S10 & Agilex.
The boot_scratch_cold register is generally used for passing
critical system info between SPL, U-Boot and Linux.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
5edf94d921 arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
Add timeout waiting for NOC idle ACK during FPGA bridge
disable/enable.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:13 +08:00
Chee Hong Ang
bd99fa59d5 arm: socfpga: agilex: Enable FPGA Full Reconfiguration support
Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
9a623cd696 fpga: intel_sdm_mb: Add watchdog reset
Ensure watchdog reset is not triggered if the fpga
reconfiguration is taking too long.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
d2170168dd fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
2473e13bb8 arm: socfpga: Use DM watchdog timer
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:12 +08:00
Chee Hong Ang
b3e2d9fccb arm: socfpga: soc64: Show reset state in SPL
Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
d7a1ff40d6 arm: socfpga: soc64: Add SDM triggered warm reset bit mask
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat
register when checking for HPS warm reset status.
Refactor the warm reset mask macro for clarity purpose.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
289ebe077a sysreset: socfpga: agilex: Enable sysreset support
Enable sysreset support for Agilex platform.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
a6510993a5 sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64
Rename the driver from S10 to SoC64 because Intel Agilex platform
also using the this SYSRESET SoCFPGA driver for S10.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chin Liang See
f833d6a4ce configs: socfpga: soc64: Avoid SPL enter infinite loop during exception
In current implementation, any exception would trigger a CPU reset.
But a bad written SPL would cause infinite loop where the system
will reload the same SPL instead of loading factory safe image.

Hence this patch is to ensure any exception will cause a hang. At this
moment, watchdog shall be triggered and Remote System Update mechanism
shall load the next production image or factory safe image.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
12cc44884b arm: socfpga: soc64: Initialize timer in SPL only
Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:11 +08:00
Chee Hong Ang
464ca99f8e arm: socfpga: soc64: Remove PHY interface setup from misc arch init
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:10 +08:00
Chee Hong Ang
d24f2bc148 clk: agilex: Additional membus writes for HPS PLL
Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09 17:53:10 +08:00
Chee Hong Ang
35d847ed90 clk: agilex: Handle clock configuration differently in SPL and U-Boot proper
Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:10 +08:00
Ley Foon Tan
d3e829b618 clk: agilex: Add clock enable support
Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:10 +08:00
Ley Foon Tan
36162a8eb8 clk: agilex: Add NAND clock support
Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09 17:53:10 +08:00
Andre Przywara
f5cb6c3081 qemu-arm64: Enable POSITION_INDEPENDENT
Now that PIE works when U-Boot is started from ROM, let's enable
CONFIG_POSITION_INDEPENDENT, which allows to load U-Boot also via
ARM Trusted-Firmware's fip.bin to DRAM, without tweaking the
configuration.

To get a writable initial stack, we need to keep the fixed initial
stack pointer, which points to DRAM in our case.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2020-10-08 11:42:36 -04:00
Andre Przywara
f8df0560b6 qemu-arm: Drop ARCH_SUPPORT_TFABOOT
CONFIG_ARCH_SUPPORT_TFABOOT was used on the qemu-arm64 platform to
guard a tweak to the flash bank configuration. U-Boot now reads the
current flash setup from the devicetree, so there is no need for
this option anymore.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-10-08 11:42:36 -04:00
Andre Przywara
3d8d9186c3 qemu-arm: Remove need to specify flash banks
Currently we hard-code the number and initial addresses of QEMU's flash
banks, even though our code is perfectly able to gather the same
information from the DTB provided by QEMU.
This is especially annoying, since we have two slightly different
U-Boot configurations ("bare-metal" vs. loaded via Arm Trusted
Firmware), which need to be selected at build time.

Drop the two hard coded alternatives, and use
CONFIG_SYS_MAX_FLASH_BANKS_DETECT instead, which relies on the DTB to
figure out the actual flash configuration at runtime.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-10-08 11:42:36 -04:00
Andre Przywara
12650e4a46 arm64: PIE: Allow fixed stack pointer
Currently selecting CONFIG_POSITION_INDEPENDENT also forces us to use an
initial stack pointer relative to the beginning of the BSS section.
This makes some sense, because this should be writable memory anyway.

However the BSS section is not cleared or used until later in the
setup process (after relocation), so memory nearby might not be
available early enough to host the initial stack. This is an issue if
U-Boot is loaded from (Flash-)ROM, for instance.

Allow CONFIG_INIT_SP_RELATIVE to be turned off by a board's config, to
be able to select a fixed stack pointer, for instance in known good
DRAM.

This will help QEMU utilising PIE, when it's loaded to (Flash-)ROM.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2020-10-08 11:42:36 -04:00
Andre Przywara
9a984f100e arm64: PIE: Skip fixups if distance is zero
When the actual offset between link and runtime address is zero, there
is no need for patching up U-Boot early when running with
CONFIG_POSITION_INDEPENDENT.

Skip the whole routine when the distance is 0.

This helps when U-Boot is loaded into ROM, or in otherwise sensitive
memory locations.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2020-10-08 11:42:36 -04:00
Andre Przywara
eabc090215 arm64: PIE: Do not skip static relocation
When we build an arm64 target and enable POSITION_INDEPENDENT, we were
skipping our build-time dynamic relocation fixup routine (STATIC_RELA).

This was probably done because we didn't need it in this case, as the
PIE fixup routine in start.S would take care of that at runtime.

However when we now skip this routine (upon detecting that the fixup
offset is 0), this might lead to uninitialised pointers.

Remove the exception, so that we always do the build-time relocation.

NOTE: GNU binutils starting with v2.27.1 do this build-time relocation
automatically, to be in-line with other architecures. So on newer
toolchains our manual fixup is actually not needed. It doesn't hurt to
have it, though, so that we keep compatibility with the popular Linaro
toolchains, which lack this feature.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2020-10-08 11:42:36 -04:00
Andre Przywara
cee2e022d2 arm: Kconfig: Explain TFABOOT
The CONFIG_TFABOOT option is more about what U-Boot DOES NOT need to do
than to support some features.

Explain a bit more in the Kconfig help text to avoid misunderstandings.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-10-08 11:42:36 -04:00
Heinrich Schuchardt
fc6ef71a66 examples: make examples/ optional
Most users don't need the standalone API examples. Distributions like SUSE
do not supply libgcc for cross-compiling and we cannot do without on ARMv8
for building examples/.

Make examples selectable via symbol CONFIG_EXAMPLES. It defaults to
yes on ARCH_QEMU to ensure that we compile the API as part of our
continuous integration.

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
2020-10-08 11:42:36 -04:00
Jack Mitchell
d9b9c91b5d wdt: designware: fix timeout calculation due to expecting KHz
The timeout calculation is based on the clk being in KHz but
the clk api returns the clk value in Hz. Convert this to KHz
to calculate the correct timeout value.

Signed-off-by: Jack Mitchell <ml@embed.me.uk>
2020-10-08 11:42:36 -04:00
Sean Anderson
0eabb2ff23 riscv: Add FPIOA and GPIO support for Kendryte K210
This patch adds the necessary configs and docs for FPIOA and GPIO support
on the K210.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-08 11:42:36 -04:00
Heinrich Schuchardt
2b5a719fc6 riscv: add DT binding for BOOT button on Maix board
Add a device tree binding for the BOOT button on the Maix board.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-08 11:42:36 -04:00
Sean Anderson
be3076e66d riscv: Add pinmux and gpio bindings for Kendryte K210
This patch adds the necessary device tree bindings.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Rick Chen <rick@andestech.com>
2020-10-08 11:42:36 -04:00
Sean Anderson
3e41c7b253 test: dm: Test for default led naming
This modifies the existing led test to check for default led naming as
added in the previous patch.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Sean Anderson
aaa3645e16 led: gpio: Default to using node name if label is absent
This more closely mirrors Linux's behaviour, and will make it easier to
transition to using function+color in the future.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Sean Anderson
b4167aa15a gpio: dw: Return output value when direction is out
dm_gpio_ops.get_value can be called when the gpio is either input or
output. The current dw code always returns the input value, which is
invalid if the direction is set to out.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-08 11:42:36 -04:00
Sean Anderson
18dbb7b335 gpio: dw: Add a trailing underscore to generated name
Previously, if there was no bank-name property, it was easy to have
confusing gpio names like "gpio1@08", instead of "gpio1@0_8". This patch
follows the example of the sifive gpio driver.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Sean Anderson
af551daf9e gpio: dw: Fix warnings about casting int to pointer
Change the type of gpio_dwabp_platdata.base from fdt_addr_t to a void
pointer, since we pass it to readl.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Sean Anderson
7224d5ccf8 pinctrl: Add support for Kendryte K210 FPIOA
The Fully-Programmable Input/Output Array (FPIOA) device controls pin
multiplexing on the K210. The FPIOA can remap any supported function to any
multifunctional IO pin. It can also perform basic GPIO functions, such as
reading the current value of a pin. However, GPIO functionality remains
largely unimplemented (in favor of the dedicated GPIO peripherals).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Sean Anderson
7f0f1806e3 test: pinmux: Add test for pin muxing
This extends the pinctrl-sandbox driver to support pin muxing, and adds a
test for that behaviour. The test is done in C and not python (like the
existing tests for the pinctrl uclass) because it needs to call
pinctrl_select_state.  Another option could be to add a command that
invokes pinctrl_select_state and then test everything in
test/py/tests/test_pinmux.py.

The pinctrl-sandbox driver now mimics the way that many pinmux devices
work.  There are two groups of pins which are muxed together, as well as
four pins which are muxed individually. I have tried to test all normal
paths. However, very few error cases are explicitly checked for.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Sean Anderson
5eee93e5b1 pinctrl: Reformat documentation in dm/pinctrl.h
This normalizes the documentation to conform to kernel-doc style [1]. It
also moves the documentation for pinctrl_ops inline, and adds argument and
return-value documentation. I have kept the usual function style for these
comments. I could not find any existing examples of function documentation
inside structs.

[1] https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Sean Anderson
9c08fbfc95 pinctrl: Add pinmux property support to pinctrl-generic
The pinmux property allows for smaller and more compact device trees,
especially when there are many pins which need to be assigned individually.
Instead of specifying an array of strings to be parsed as pins and a
function property, the pinmux property contains an array of integers
representing pinmux groups. A pinmux group consists of the pin identifier
and mux settings represented as a single integer or an array of integers.
Each individual pin controller driver specifies the exact format of a
pinmux group. As specified in the Linux documentation, a pinmux group may
be multiple integers long. However, no existing drivers use multi-integer
pinmux groups, so I have chosen to omit this feature. This makes the
implementation easier, since there is no need to allocate a buffer to do
endian conversions.

Support for the pinmux property is done differently than in Linux.  As far
as I can tell, inversion of control is used when implementing support for
the pins and groups properties to avoid allocating. This results in some
duplication of effort; every property in a config node is parsed once for
each pin in that node. This is not such an overhead with pins and groups
properties, since having multiple pins in one config node does not occur
especially often. However, the semantics of the pinmux property make such a
configuration much more appealing. A future patch could parse all config
properties at once and store them in an array. This would make it easier to
create drivers which do not function solely as callbacks from
pinctrl-generic.

This commit increases the size of the sandbox build by approximately 48
bytes.  However, it also decreases the size of the K210 device tree by 2
KiB from the previous version of this series.

The documentation has been updated from the last Linux commit before it was
split off into yaml files.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Dylan Hung
0474050d46 ram: add ddr4 dual x8 configuration
the aspeed ddr sdram controller needs to know if the memory chip mounted on
the board is dual x8 die or not. Or it may get the wrong size of the
memory space.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-08 10:58:45 -04:00
Dylan Hung
5d457f8057 ram: move aspeed ram driver into drivers/ directory
to improve the maintainability.  It is more easier to modify and add
configurations of the driver in the centralized ram driver directory.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-08 10:58:33 -04:00
Tom Rini
a58d86db46 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash
- Fix devicetree address determination seen on QEMU ARM64
- Use DMA for reads is available
2020-10-08 10:20:53 -04:00
Andre Przywara
492b9917c6 cfi_flash: Fix devicetree address determination
The cfi-flash driver uses an open-coded version of the generic
algorithm to decode and translate multiple frames of a "reg" property.

This starts off the wrong foot by using the address-cells and size-cells
properties of *this* very node, and not of the parent. This somewhat
happened to work back when we were using a wrong default size of 2,
but broke about a year ago with commit 0ba41ce1b7 ("libfdt: return
correct value if #size-cells property is not present").

Instead of fixing the reinvented wheel, just use the generic function
that does all of this properly.

This fixes U-Boot on QEMU (-arm64), which was crashing due to decoding
a wrong flash base address:
DRAM:  1 GiB
Flash: "Synchronous Abort" handler, esr 0x96000044
elr: 00000000000211dc lr : 00000000000211b0 (reloc)
elr: 000000007ff5e1dc lr : 000000007ff5e1b0
x0 : 00000000000000f0 x1 : 000000007ff5e1d8
x2 : 000000007edfbc48 x3 : 0000000000000000
x4 : 0000000000000000 x5 : 00000000000000f0
x6 : 000000007edfbc2c x7 : 0000000000000000
x8 : 000000007ffd8d70 x9 : 000000000000000c
x10: 0400000000000003 x11: 0000000000000055
     ^^^^^^^^^^^^^^^^

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-08 09:04:41 +02:00
Vignesh Raghavendra
3f891a103c mtd: cfi_mtd: Use DMA for reads
When possible use DMA for reading from CFI flash, this provides upto 5x
improvement in read performance with high speed CFI compliant flashes
like HyperFlash.

Code will gracefully fallback to CPU copy when DMA is unavailable.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-08 09:04:41 +02:00
Vignesh Raghavendra
8995a86cd6 dma: Reduce error level when DMA channel type does not exist
Caller would need gracefully handle failures of dma_get_device(),
therefore reduce pr_err() to pr_debug() when DMA device is not found.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-08 09:04:41 +02:00
Tom Rini
1c431f118c Merge tag 'mips-pull-2020-10-07' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips
- mips: octeon: add support for DDR4 memory controller
- mips: octeon: add support for DWC3 USB
- mips: octeon: add support for booting Linux
2020-10-07 17:25:25 -04:00
Stefan Roese
1471560b2c mips: octeon: octeon_common.h: Increase CONFIG_SYS_BOOTM_LEN
Increase CONFIG_SYS_BOOTM_LEN to 64MiB for Linux kernel booting.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:58 +02:00
Aaron Williams
e602dd5238 mips: octeon: Add bootoctlinux command
Octeon needs a platform specific cmd to boot the Linux kernel, as
specific parameters need to be passed and special handling for the
multiple cores (SMP) is needed.

Co-developed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
[use gd->ram_base instead of gd->bd->bi_memstart]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-10-07 20:25:58 +02:00
Aaron Williams
4b43e7e210 mips: octeon: Add bootmem support
This is needed for Linux booting, as the memory infos need to be passed
in this bootmem format to the Linux kernel.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:58 +02:00
Aaron Williams
b0ce80588d mips: octeon: Add coremask support
This patch adds the coremask handling functions.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:58 +02:00
Aaron Williams
afb4828ede mips: octeon: Add header cvmx-bootinfo.h
Add header to handle bootinfo support, needed for Octeon Linux kernel
booting.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:58 +02:00
Aaron Williams
99b937e568 mips: octeon: Add header cvmx-fuse.h
Add header to handle Octeon fuse access.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:58 +02:00
Aaron Williams
5d7282195a mips: octeon: Add header octeon-feature.h
This header includes the Octeon feature detection used in many Octeon
drivers.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:58 +02:00
Aaron Williams
b1fed50a43 mips: octeon: Add header cvmx-regs.h
This header includes common register defines and accessor functions.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
7c6f274a36 mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux booting
This patch adds the necessary lowlevel init code, to enable SMP Linux
booting. This code will be used with the platform specific Octeon Linux
boot command "bootoctlinux", which starts a configurable number of cores
into Linux.

Additionally some erratas and lowlevel register initializations are
copied from the original Cavium / Marvell U-Boot source code, enabling
booting into the Linux kernel.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
97e795ccca mips: octeon: octeon-model.h: Enable inclusion from assembler files
Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header
from assembler files.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
60b407a86a mips: octeon: octeon_ebb7304_defconfig: Enable USB support
This patch enables USB support with some helpful commands, like fs
support.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
d25d2db847 mips: octeon: Add USB DT nodes
Add the USB device tree nodes to the Octeon dts/dtsi files.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-07 20:25:57 +02:00
Stefan Roese
399b867fac mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()
As noticed while working on the USB xHCI support, Octeon needs to flush
all pending writes so that the values are present in the memory. Add
this "syncw" instruction (twice) to flush_dcache_range().

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
b28d35234c mips: octeon: Add mangle-port.h
Import platform specific mangle-port.h header, allowing a area specific
swapping, which is needed on Octeon for USB & PCI areas.

Imported from Linux v5.7.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
fd569c878b mips: octeon: cpu.c: Add table for selective swapping
Import octeon_should_swizzle_table[] which is needed for the area
specific swapping. It will be used by the platform specific
mangle-port.h header.

Imported from Linux v5.7.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
92ca2fee08 usb: xhci: octeon: Add DWC3 glue layer for Octeon
This patch adds the glue layer for the MIPS Octeon SoCs. It's ported
mainly from the Linux code.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
e68efa1ecf usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses
Octeon uses mapped addresses for virtual and physical memory. It's not
that easy to calculate the resulting addresses here. So let's remove
this BUG_ON() completely, as it's not really helpful.

Please also note, that BUG_ON() is not recommended any more in the Linux
kernel.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
72a53ac59b usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()
On MIPS platforms, mapping of the base address is needed. This patch
switches from dev_get_addr() to dev_remap_addr() to get the mapped base
address of the xHCI controller.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
63051d62b8 mips: octeon: octeon_ebb7304: Add DDR4 support
This patch adds the board specific configuration (struct) for the
Octeon 3 EBB7304 EVK. This struct is ported from the 2013er Cavium /
Marvell U-Boot repository. Also, the Octeon RAM driver is enabled in
the board defconfig for its usage.

Tested with one and two DIMMs on the EBB7304 EVK (8 & 16 GiB).

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
590d48e9d1 mips: octeon: dram.c: Add RAM driver support
This patch adds the initialization call for the Octeon RAM driver to
the Octeon platforms code. So if enabled via Kconfig, the DDR driver
will be called and the RAM will be configured and used. If the RAM
driver is not enabled, the L2 cache is still used as RAM.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
15afe725f3 ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
61674a17bc ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 2 includes the very complex Octeon 3 DDR4 configuration

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
e13bb86588 ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 1 adds the base U-Boot RAM driver, which will be instantiated by
the DT based probing.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
073e8ee5df mips: octeon: Add octeon_ddr.h header
This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
91e34fcb41 mips: octeon Add cvmx/cvmx-lmcx-defs.h header
This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
75168b4aa7 mips: octeon: Add octeon-model.h header
This header is used by the upcoming DDR driver and potentially by other
drivers ported from the 2013 Cavium / Marvell U-Boot repository.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
a23c279059 mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT node
This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi
file. It also adds the L2C DT node, as this is referenced by the DDR
driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:56 +02:00
Tom Rini
42378e3cd2 Merge tag 'dm-pull-6oct20' of git://git.denx.de/u-boot-dm
bloblist enhancement for alignment
Update ofnode/dev_read phandle function
sandbox keyboard enhancements and fixes
2020-10-06 13:59:01 -04:00
Heinrich Schuchardt
175e8322bc sandbox: avoid duplicate backslash input
When using SDL for input the SDL key codes are first converted to Linux key
codes and then to matrix entries of the cross wired keyboard.

We must not map any key code to two different places on the keyboard. So
comment out one backslash position.

Update the rest of the file from Linux 5.7.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Heinrich Schuchardt
c4216219ec sandbox: add missing SDL key scan codes
Add missing SDL key scan codes, e.g.

* shift, ctrl, meta, alt
* brace/bracket

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Patrick Delaunay
cc72f3e026 test: dm: add test for phandle access functions
Add unitary test for phandle access functions
- ofnode_count_phandle_with_args
- ofnode_parse_phandle_with_args
- dev_count_phandle_with_args
- dev_read_phandle_with_args

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Patrick Delaunay
cba487c7fc fdtdec: correct test on return of fdt_node_offset_by_phandle
The result of fdt_node_offset_by_phandle is negative for error,
so this patch corrects the check of this result in
fdtdec_parse_phandle_with_args.

This patch allows to have the same behavior with or without OF_LIVE
for the function dev_read_phandle_with_args with cell_name = NULL and
with invalid phandle.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Patrick Delaunay
89f68302ca dm: add cells_count parameter in *_count_phandle_with_args
The cell_count argument is required when cells_name is NULL.

This patch adds this parameter in live tree API
- of_count_phandle_with_args
- ofnode_count_phandle_with_args
- dev_count_phandle_with_args

This parameter solves issue when these API is used to count
the number of element of a cell without cell name. This parameter
allow to force the size cell.

For example:
  count = dev_count_phandle_with_args(dev, "array", NULL, 3);

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Patrick Delaunay
6d9949fe86 dm: update test on of_offset in ofnode_valid
Update the test for node.of_offset because an invalid offset is not
always set to -1 because the return value of the libfdt functions are:
+ an error with a value < 0
+ a valid offset with value >=0

For example, in ofnode_get_by_phandle() function, we have:
node.of_offset = fdt_node_offset_by_phandle(gd->fdt_blob, phandle);
and this function can return -FDT_ERR_BADPHANDLE (-6).

Without this patch, the added test dm_test_ofnode_get_by_phandle failed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Stefan Roese
45dbe75da6 dm: ofnode: Fix compile breakage with OF_CHECKS enabled
Include missing log.h and change _ofnode_to_np() to ofnode_to_np() so
that compiling with OF_CHECKS enabled does not break.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Simon Glass
e9b6b2c77d bloblist: Fix up a few comments
Adjust a few comments to make the meaning clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Simon Glass
4c1497e776 bloblist: Allow custom alignment for blobs
Some blobs need a larger alignment than the default. For example, ACPI
tables often start at a 4KB boundary. Add support for this.

Update the size of the test blob to allow these larger records.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Simon Glass
751b7c7963 bloblist: Tidy up the data alignment
The intention which bloblists is that each blob's data is aligned in
memory. At present it is only the headers that are aligned.

Update the code to correct this and add a little more documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Simon Glass
cdd4e30dfc bloblist: Compare addresses rather than pointers in tests
When running these tests on sandbox any failures result in very large or
long pointer values which are a pain to work with. Map them to an address
so it is easier to diagnose failures.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Simon Glass
4aed227623 bloblist: Add a command
It is helpful to be able to see basic statistics about the bloblist and
also to list its contents. Add a 'bloblist' command to handle this.

Put the display functions in the bloblist modules rather than in the
command code itself. That allows showing a list from SPL, where commands
are not available.

Also make bloblist_first/next_blob() static as they are not used outside
this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Heinrich Schuchardt
9c22adb8f9 doc/arch/sandbox.rst: reformat command line options
Reformat the command line options chapter so that the command line options
clearly stand out.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Heinrich Schuchardt
b0b3524d94 MAINTAINERS: assign doc/arch/sandbox.rst
Add doc/arch/sandbox.rst to the scope of SANDBOX.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Tom Rini
5dcf7cc590 Merge tag 'efi-2021-01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2021-01-rc1

The following bugs in the UEFI system are resolved:

* illegal free in EFI_LOAD_FILE2_PROTOCOL implementation
* incorrect documentation of EFI_LOAD_FILE2_PROTOCOL implementation
* output of CRC32 as decimal instead hexadecimal in unit test
* use EfiReservedMemoryType for no-map reserved memory
* avoid unnecessary resets in UEFI unit tests
* call EFI bootmgr even without having /EFI/boot
2020-10-06 08:36:38 -04:00
Tom Rini
987ab49366 Merge tag 'u-boot-amlogic-20201005' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- generate unique mac address from SoC serial on S400 board
- Add USB support for GXL and AXG SoCs
- Update Gadget code to use the new GXL and AXG USB glue driver
- Add a VIM3 board support to add dynamic PCIe enable in OS DT
- Fix AXG pinmux with requesting GPIOs
- Add missing GPIOA_18 for AXG pinctrl
- Add Amlogic PWM driver
2020-10-06 08:36:10 -04:00
Heinrich Schuchardt
4cbb2930bd efi_loader: consider no-map property of reserved memory
The device tree may contain a /reserved-memory node. The no-map property
of the sub-nodes signals if the memory may be accessed by the UEFI payload
or not.

In the EBBR specification (https://github.com/arm-software/ebbr) the
modeling of the reserved memory has been clarified.

If a reserved memory node in the device tree has the no-map property map,
create a EfiReservedMemoryType memory map entry else use
EfiBootServicesData.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-06 07:43:56 +02:00
Heinrich Schuchardt
4b71f6dc4e efi_loader: QEMU CONFIG_EFI_GRUB_ARM32_WORKAROUND=n
CONFIG_EFI_GRUB_ARM32 is only needed for architectures with caches that are
not managed via CP15 (or for some outdated buggy versions of GRUB). It
makes more sense to disable the setting per architecture than per defconfig.

Move QEMU's CONFIG_EFI_GRUB_ARM32_WORKAROUND=n from defconfig to Kconfig.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-06 07:43:56 +02:00
Sean Anderson
493a37fe86 efi: Fix typo in documentation
There is an extra space.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-06 07:43:56 +02:00
Michael Walle
f3866909e3 distro_bootcmd: call EFI bootmgr even without having /EFI/boot
Currently, the EFI bootmgr is only called if there is a EFI binary
inside the path for removable media is found, i.e. /EFI/boot/. This
doesn't make sense. It is the duty of the bootmgr to find out the
path and name of the EFI binary to boot. It should be called even
if there is no /EFI/boot directory.

Thus, call the bootmgr before we try to boot the EFI binary inside
the removable media path.

Also remove the ${fdtcontroladdr} parameter because the fallback is
handled in cmd/bootefi.c and that already takes care of correct settings
if the board has ACPI and thus no device tree at all.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-06 07:43:56 +02:00
Heinrich Schuchardt
eb0d1d8399 efi_selftest: avoid unnecessary reset
When we do not execute a test requiring ExitBootServices do not reset the
system after testing.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-06 07:43:56 +02:00
Heinrich Schuchardt
dc374ab08f efi_selftest: print CRC32 of initrd as hexadecimal
Print the CRC32 loaded via the EFI_LOAD_FILE2_PROTOCOL as a hexadecimal
number.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-10-06 07:43:56 +02:00
Heinrich Schuchardt
9487683821 efi_selftest: enable printing hexadecimal numbers
Add code to use %x in efi_st_print().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-06 07:43:56 +02:00
Heinrich Schuchardt
e2aff337ed efi_loader: illegal free in EFI_LOAD_FILE2_PROTOCOL
strsep() changes the address that its first argument points to.
We cannot use the changed address as argument of free().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-10-06 07:43:56 +02:00
Heinrich Schuchardt
5cd28e1760 efi_loader: description EFI_LOAD_FILE2_PROTOCOL
U-Boot offers a EFI_LOAD_FILE2_PROTOCOL which the Linux EFI stub can use to
load an initial RAM disk. Update the function comments of the
implementation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-10-06 07:43:56 +02:00
Tom Rini
b24550accd configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05 14:11:16 -04:00
Tom Rini
b7e7831e5d Merge branch 'next'
Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05 14:10:59 -04:00
Neil Armstrong
2d481b2e3e pwm: Add driver for Amlogic Meson PWM controller
This adds the driver for the PWM controller found in the Amlogic SoCs.

This PWM is only a set of Gates, Dividers and Counters:
PWM output is achieved by calculating a clock that permits calculating
two periods (low and high). The counter then has to be set to switch after
N cycles for the first half period.
The hardware has no "polarity" setting. This driver reverses the period
cycles (the low length is inverted with the high length) for
PWM_POLARITY_INVERSED.

Disabling the PWM stops the output immediately (without waiting for the
current period to complete first).

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 18:02:16 +02:00
Neil Armstrong
38c1c6f816 pinctrl: meson-axg: add missing GPIOA_18
Add the missing GPIOA_18 from the missing EE gpio list.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 18:01:40 +02:00
Neil Armstrong
0f6bef4a95 pinctrl: meson-axg-pmx: fix gpio request
The AXG pmx driver gpio request offset needs the pin base to have the
correct pin number.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2020-10-05 18:01:39 +02:00
Neil Armstrong
adbff64af7 board: amlogic: vim3: add support for dynamic PCIe enable
The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
an USB3.0 Type A connector and a M.2 Key M slot.
The PHY driving these differential lines is shared between
the USB3.0 controller and the PCIe Controller, thus only
a single controller can use it.

This adds this dynamic switching right before booting Linux
and the configuration steps in the boards documentation.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed warning by replacing min() by min_t()]
2020-10-05 17:59:45 +02:00
Neil Armstrong
cb4a7feb54 configs: vim3: use the vim3 board support
Use the newly added VIM3 board support instead of the generic W400.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
5aeecbcf81 board: amlogic: add a vim3 specific board support
The VIM3 will need a specific code to enable PCIe if enabled in the MCU,
thus add a specific board support for VIM3 & VIM3L.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
1110e49e34 ARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1
This imports the G12A & SM1 SoC and boards DT changes from the Linux
commit 9123e3a74ec7 ("Linux 5.9-rc1").

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
7570ad6b6e configs: s400: enable USB
Enable USB Host & Gadget on the Amlogic S400 board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
85a034c275 ARM: dts: meson-axg: add USB nodes for S400
Add the correcly architectured USB Glue node for Meson AXG and the
S400 board in -u-boot.dtsi until support in upstream Linux then
backported.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
e9d29b98e3 arm: meson-axg: add board_usb_init()/cleanup() for USB gadget
Add the board_usb_init()/cleanup() for USB gadget for AXG based
on the code for the G12A architecture.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
0ae8724d7e phy: meson-gxl-usb: depend on Meson AXG aswell
Enable build of meson-gxl-usb PHY for the AXG architecture aswell.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
66d9427403 phy: meson-gxl: remove invalid USB3 PHY driver
The registers which are managed by the meson-gxl-usb3 PHY driver are
actually "USB control" registers (which are "glue" registers which
manage OTG detection and routing of the OTG capable port between the
DWC2 peripheral-only controller and the DWC3 host-only controller).

Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb
driver supports the USB control registers on GXL and GXM SoCs (these
were previously managed by the meson-gxl-usb3 PHY driver).

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
7ccc73773f ARM: mach-meson: use new DWC3 glue for GXL & GXM
Use the new Amlogic GXL/GXM USB Glue instead of the set of USB3 PHY
and Simple DWC3 wrapper.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
46eddbc58f usb: dwc3: add Amlogic GXL & GXL DWC3 Glue
The USB support was initialy done with a set of PHYs and dwc3-of-simple
because the architecture of the USB complex was not understood correctly
at the time (and proper documentation was missing...).

But with the G12A family, the USB complex was correctly understood and
implemented correctly.

This adds a proper driver for the glue, based on the G12A one, but with
enough changes to require a different driver in U-Boot.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
4e7b0a3f2a ARM: dts: sync amlogic AXG/GXL/GXM DT from Linux 5.8-rc1
This imports the AXG, GXL & GXM SoC and boards DT changes from the Linux
commit b3a9e3b9622a ("Linux 5.8-rc1").

This change also removes GXL & GXM u-boot.dtsi hacks for USB gadget.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
394c6b0ff1 board: s400: generate unique mac address from SoC serial
Enable unique mac address generation from SoC serial on S400 board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Tom Rini
050acee119 Prepare v2020.10
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05 11:15:32 -04:00
Tom Rini
caebff09ef Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next
First set of u-boot-atmel features for 2021.01 cycle:

This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update.  The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
2020-10-05 10:54:27 -04:00
Tom Rini
17e76b33cc Merge tag 'u-boot-stm32-20201003' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm into next
- stm32mp: DT alignment with Linux 5.9-rc4
- stm32mp: convert drivers to APIs which support live DT
- stm32mp: gpio: minor fixes
2020-10-05 10:54:10 -04:00
Claudiu Beznea
01c35f269f cpu: at91: add driver for CPU
Add basic CPU driver use to retrieve information about CPU itself.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-05 10:45:16 +03:00
Tom Rini
fee98a3ba9 Merge branch 'rpi-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi into next 2020-10-02 12:00:39 -04:00
Ovidiu Panait
0db912de15 pinctrl: bcm283x: Store the return value of dev_read_u32_default to int
Currently, the return value of dev_read_u32_default is stored in an u32,
causing the subsequent "if (function < 0)" to always be false:

u32 function;
...
function = dev_read_u32_default(config, "brcm,function", -1);
if (function < 0) {
        debug("Failed reading function for pinconfig %s (%d)\n",
                      config->name, function);
        return -EINVAL;
}

Make "function" variable an int to fix this.

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-10-02 17:32:28 +02:00
Ovidiu Panait
e020c07a02 pinctrl: bcm283x: Read address from DT in ofdata_to_platdata
Factor out reading IP base address to ofdata_to_platdata function, which
is designed for this purpose. Also, drop the dev->priv NULL check, since
this is already done by the dm core when allocating space using
priv_auto_alloc_size feature. (in drivers/core/device.c ->
device_ofdata_to_platdata).

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-10-02 17:32:28 +02:00
Ovidiu Panait
bab9be9e0d pinctrl: bcm283x: DM_FLAG_PRE_RELOC: Remove OF_CONTROL check
Remove CONFIG_IS_ENABLED(OF_CONTROL) check from DM_FLAG_PRE_RELOC, since
this driver only supports OF_CONTROL.

drivers/pinctrl/broadcom/Kconfig:
config PINCTRL_BCM283X
    depends on ARCH_BCM283X && PINCTRL_FULL && OF_CONTROL

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-10-02 17:32:28 +02:00
Patrick Delaunay
04e29ca5bb mailbox: stm32_ipcc: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
a04616be1b video: stm32_dsi: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Yannick Fertré <yannick.fertre@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
28c6ba861c video: stm32_ltdc: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Yannick Fertré <yannick.fertre@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
10bccd0dd3 pinctrl: stm32: Add header with SPDX licence
Cosmetics: Add header with SPDX licence

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
d3bfad266c pinctrl: stm32: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
cb08e84d68 gpio: stm32: check result of ofnode_phandle_args
Add test on the size of ofnode_phandle_args result to avoid access
to uninitialized elements in args[] field.

This patch avoids the issue when gpio-ranges cell size is not 3 as
expected, for example:
	gpio-ranges = <&pinctrl 0>;
instead of
	gpio-ranges = <&pinctrl 0 112 16>;

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
15c8cbfc74 gpio: stm32: cosmetic: cleanup gpio_stm32_probe
Move the variables definition at the beggining of the function
gpio_stm32_probe().

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
62f95af92a ARM: dts: stm32mp1: DT alignment with Linux kernel v5.9-rc4
DT alignment with Linux kernel v5.9-rc4 for the STM32MP15x soc
device tree files and the STMicroelectronics boards device tree files.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 14:56:56 +02:00
Soeren Moch
0f3e2942c9 board: tbs2910: Use recommended distroboot addresses
According to doc/README.distro fdt_addr must not be set when DTB is not
available from hardware. So remove this entry.

Use address 32MB above the start of DRAM for kernel_addr_r. This way
we likely can avoid the self-relocation of the compressed kernel image
before it decompresses to offset 0x8000 from start of DRAM.

Use address 128MB above the start of DRAM for fdt_addr_r, since this is
the maximum location for the end of the kernel. So we avoid overwriting
the DTB.

Use 512k above that for ramdisk_addr_r. This should be enough for the
DTB, rest of DRAM can be used for initrd.

Place boot script / extlinux.conf at offset 0 / 1MB from start of DRAM.
This space is available for processing in U-Boot.

Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-10-02 08:42:36 -04:00
Tom Rini
bb9f59f6a2 Merge tag 'u-boot-stm32-20201002' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Fixup SPI-NOR boot on AV96 board
2020-10-02 08:42:26 -04:00
Marek Vasut
d9839417cb ARM: dts: stm32: Add missing dm-spl props for SPI NOR on AV96
The u-boot,dm-spl DT props are missing on AV96, hence the pinmux and
flash0 nodes are not included in the reduced SPL DT. This prevents
SPI NOR boot from working at all. Fix this by filling them in.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-10-02 14:18:00 +02:00
Tom Rini
7e373a1a6a Merge branch 'next' of git://git.denx.de/u-boot-usb into next
- Assorted XHCI improvements
2020-10-01 14:52:56 -04:00
Tom Rini
f352c51f57 Revert "net: smc911x: Automatically Update ethaddr with MAC"
Upon further discussion on the mailing list, we should not get in the
situation where the generic code path to set ethaddr/etc correctly does
not work.  Revert this until someone can further debug the smc911x
driver regarding this issue.

This reverts commit 387cbf096e.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-01 14:51:58 -04:00
Lad Prabhakar
e15e817f3e usb: xhci-rcar: Add support for R8A774A1 SoC
The R8A774A1 is compatible with the generic rcar-gen3-xhci controller.
This patch adds the compatibility flag, to support the xHCI controller.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
a6837a0370 usb: xhci: convert to readx_poll_sleep_timeout()
Use readx_poll_sleep_timeout() to poll the register status

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
23a54ccfb6 usb: xhci: use macros with parameter to fill ep_info2
Use macros with parameter to fill ep_info2, then some macros
for MASK and SHIFT can be removed

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
bf58cf9ab1 usb: xhci: convert to TRB_TX_TYPE()
Use TRB_TX_TYPE() instead of (TRB_DATA_OUT/IN << TRB_TX_TYPE_SHIFT)

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
4312638eaf usb: xhci: convert to TRB_LEN() and TRB_INTR_TARGET()
For normal TRB fields:
use TRB_LEN(x) instead of ((x) & TRB_LEN_MASK);
and use TRB_INTR_TARGET(x) instead of
(((x) & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT)

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
a826d76f2b usb: xhci: convert to TRB_TYPE()
Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
86d1fa17fb usb: xhci: convert to HCS_MAX_PORTS()
Use HCS_MAX_PORTS(p) instead of
((p & HCS_MAX_PORTS_MASK) >> HCS_MAX_PORTS_SHIFT)

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
740820519c usb: xhci: add quirks flag to support MediaTek xHCI 0.96
There some vendor quirks for MTK xHCI 0.96 host controller:
1. It defines some extra SW scheduling parameters for HW
   to minimize the scheduling effort for synchronous and
   interrupt endpoints. The parameters are put into reserved
   DWs of slot context and endpoint context.
2. Its TDS in  Normal TRB defines a number of packets that
   remains to be transferred for a TD after processing all
   Max packets in all previous TRBs.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
e3ea481bee usb: xhci: create one unified function to calculate TRB TD remainder
xhci versions 1.0 and later report the untransferred data remaining in a
TD a bit differently than older hosts.

We used to have separate functions for these, and needed to check host
version before calling the right function.

Now Mediatek host has an additional quirk on how it uses the TD Size
field for remaining data. To prevent yet another function for calculating
remainder we instead want to make one quirk friendly unified function.

Porting from the Linux:
c840d6ce772d("xhci: create one unified function to calculate TRB TD remainder.")
124c39371114("xhci: use boolean to indicate last trb in td remainder calculation")

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
719d7d8df4 usb: xhci: add a member hci_version in xhci_ctrl struct
Add a member to save xHCI version, it's used some times.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Tom Rini
b084d8596d Merge branch 'next' of git://git.denx.de/u-boot-sh into next 2020-10-01 10:29:39 -04:00
Tom Rini
26acc6395f Merge branch '2020-09-30-assorted-network-improvements' into next
- Generic UDP framework
- TFTP fixes
- dwc_eth_qos, smc911x, smc911x and mscc phy fixes
2020-10-01 09:46:10 -04:00
Tom Rini
4f48163201 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Espressobin: Fix compatible string check
- Espressobin: Extend README for more MAC addresses
2020-10-01 08:55:20 -04:00
Tom Rini
47e180fa63 Merge tag 'late-bugfix-for-2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c late bugfix for v2020.10
- rcar_i2c: Fix i2c read/write errors
  fixes commit 7c8f821e ("i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer")
2020-10-01 08:36:29 -04:00
Tom Rini
8e8dc04c3a Merge branch 'master' of git://git.denx.de/u-boot-sh 2020-10-01 08:36:09 -04:00
Andre Heider
05e7511fae arm: mvebu: Espressobin: Fix checks against machine compatible strings
The patches changing the compatible strings to the ones used by Linux have
not been merged yet, so fix the checks to use the current in-tree ones.

Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
2020-10-01 10:43:43 +02:00
Pali Rohár
3dee18e2c2 arm: mvebu: Espressobin: Instructions for more MAC addresses in README.marvell
Some Espressobin boards got assigned more than one MAC address. Update
instructions how to correctly store and preserve all MAC addresses.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andre Heider <a.heider@gmail.com>
2020-10-01 10:43:43 +02:00
Lad Prabhakar
86a73b0905 i2c: rcar_i2c: Fix i2c read/write errors
commit 7c8f821e5d ("i2c: rcar_i2c: Set the slave address from
rcar_i2c_xfer") blindly called rcar_i2c_set_addr() with read argument
always set to 1 during xfer which introduced read/write errors, whereas
earlier rcar_i2c_read_common() called rcar_i2c_set_addr() with read set to
1 and rcar_i2c_write_common() called rcar_i2c_set_addr() with read set 0.

Fixes: 7c8f821e5d ("i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-10-01 05:41:44 +02:00
Philippe Reynes
912ece4c3d sntp: use udp framework
This commits update the support of sntp to use
the framework udp. This change allows to remove
all the reference to sntp in the main network
file net/net.c.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 16:55:03 -04:00
Philippe Reynes
6b981a224e sandbox: enable support of generic udp protocol
This commit enable the support of the generic udp protocol.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 16:55:03 -04:00
Philippe Reynes
b43ea1bf18 net: add a generic udp protocol
This commit adds a generic udp protocol framework in the
network loop. So protocol based on udp may be implemented
without modifying the network loop (for example custom
wait magic packet).

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 16:55:03 -04:00
Patrick Delaunay
cafaa301c9 net: dwc_eth_qos: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 16:48:18 -04:00
Srinath Mannam
3151fdd7f4 phy: add support for stingray PAXB PHY controller
Add support for stingray PAXB PHY controller driver.
This driver supports maximum 8 PAXB phys using pipemux data.

Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-30 16:48:18 -04:00
Heinrich Schuchardt
ad8959138f net: use log_err() for 'No ethernet found' message
Write the 'No ethernet found' message via the log drivers. This allows
suppressing it during output via the syslog driver.

This fixes the problem reported in:

[PATCH 0/4] log: Fix the syslog spam when running tests
https://lists.denx.de/pipermail/u-boot/2020-September/426343.html

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 16:48:18 -04:00
Ley Foon Tan
f6a158b996 net: tftp: Fix load_block offset calculation
When load the last block, the "len" might not be a block size. This cause
loading the incorrect last block data.

The fix change "len" to tftp_block_size and minus one tftp_block_size
for offset calculation.

Use same offset calculation formula as in store_block().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
2020-09-30 16:48:18 -04:00
Ley Foon Tan
ae0bdf09ca net: tftp: Fix store_block offset calculation
tftp_cur_block start with 1 for first block, but tftp_cur_block counter is
start with zero when block number is rollover. The existing code
"tftp_cur_block - 1" will cause the block number become -1 in store_block()
when tftp_cur_block is 0 when tftp_cur_block is rollover.

The fix pass in tftp_cur_block to store_block() and minus the
tftp_block_size when do the offset calculation.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
2020-09-30 16:48:18 -04:00
Ley Foon Tan
6bf46367f5 net: tftp: Fix tftp_prev_block counter update
Fixes missing update to tftp_prev_block counter before increase
tftp_cur_block counter when do the tftpput operation.

tftp_prev_block counter is used in update_block_number() function to
check whether block number (sequence number) is rollover. This bug
cause the tftpput command fail to upload a large file when block
number is greater than 16-bit (0xFFFF).

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
2020-09-30 16:48:18 -04:00
Adam Ford
387cbf096e net: smc911x: Automatically Update ethaddr with MAC
The ethernet controller can read the MAC from EEPROM and display it,
but if ethaddr is not set, the ethernet is still unavailable.

This patch checks will automatically set the MAC address if it has
not already been set.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-09-30 16:48:18 -04:00
Thirupathaiah Annapureddy
66e036bab5 net: ftgmac100: Add support for board specific PHY interface address
ftgmac100 driver is using hard-coded PHY interface address of zero.
Each board can have different PHY interface address (phy_addr).
This commit modifies the driver to make use of board specific address
by leveraging CONFIG_PHY_ADDR.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-09-30 16:48:18 -04:00
Heiko Stuebner
d63c14cc3f net: phy: mscc: sync rx/tx delay settings with Linux on vsc85xx
The Linux kernel does set the clock delays to
- 0.2 ns (their default, and lowest, hardware value) if delays should
  not be enabled
- 2.0 ns (which causes the data to be sampled at exactly half way between
  clock transitions at 1000 Mbps) if delays should be enabled
depending on the interface mode

See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/mscc/mscc_main.c#n523

So instead of using arbitrary delay values like now, mimic this behaviour.

The behaviour is the same for all of vsc8530/8531/8540/8541 so move that
to a shared function while at it.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2020-09-30 16:48:18 -04:00
Heiko Stuebner
9a499b2bfa net: phy: mscc: make clock-output configurable on vsc85xx
The vsc8530/8531/8540/8541 phys have a configurable clock output that
can emit 25, 50 and 125 MHz rates, which in turn may be needed for
stable network connections.

This follows a similar change introduced into the Linux kernel at
  https://lore.kernel.org/netdev/20200609133140.1421109-2-heiko@sntech.de

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2020-09-30 16:48:18 -04:00
Tom Rini
097bbf1ba9 Merge branch '2020-09-30-add-new-apis' into next
- SCMI firmware support
- regmap, GPIO, reset API enhancements
2020-09-30 16:11:11 -04:00
Etienne Carriere
c0dd177a99 firmware: smci: sandbox test for SCMI reset controllers
Add tests for SCMI reset controllers. A test device driver
sandbox-scmi_devices.c is used to get reset resources, allowing further
resets manipulation.

Change sandbox-smci_agent to emulate 1 reset controller exposed through
an agent. Add DM test scmi_resets to test this reset controller.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:24 -04:00
Etienne Carriere
34d76fefb2 reset: add reset controller driver for SCMI agents
This change introduces a reset controller driver for SCMI agent devices.
When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent
binds a reset controller device for each SCMI reset domain protocol
devices enabled in the FDT.

SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled,
CONFIG_SCMI_AGENT is also enabled.

SCMI Reset Domain protocol is defined in the SCMI specification [1].

Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:23 -04:00
Etienne Carriere
87d4f277d4 firmware: scmi: sandbox test for SCMI clocks
Add tests for SCMI clocks. A test device driver sandbox-scmi_devices.c
is used to get clock resources, allowing further clock manipulation.

Change sandbox-smci_agent to emulate 3 clocks exposed through 2 agents.
Add DM test scmi_clocks to test these 3 clocks.
Update DM test sandbox_scmi_agent with load/remove test sequences
factorized by {load|remove}_sandbox_scmi_test_devices() helper functions.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:23 -04:00
Etienne Carriere
6038884483 clk: add clock driver for SCMI agents
This change introduces a clock driver for SCMI agent devices. When
SCMI agent and SCMI clock drivers are enabled, SCMI agent binds a
clock device for each SCMI clock protocol devices enabled in the FDT.

SCMI clock driver is embedded upon CONFIG_CLK_SCMI=y. If enabled,
CONFIG_SCMI_AGENT is also enabled.

SCMI Clock protocol is defined in the SCMI specification [1].

Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:23 -04:00
Etienne Carriere
4e5ce7ecd3 dt-bindings: arm: SCMI bindings documentation
Dump SCMI DT bindings documentation from Linux kernel source
tree v5.8-rc1.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:23 -04:00
Etienne Carriere
1e35913a26 firmware: scmi: support Arm SMCCC transport
This change implements a SMCCC transport for SCMI exchanges. This
implementation follows the Linux kernel as references implementation
for SCMI message processing, using the SMT format for communication
channel meta-data.

Use of SMCCC transport in SCMI FDT bindings are defined in the Linux
kernel DT bindings since v5.8. SMCCC with SMT is implemented in OP-TEE
from tag 3.9.0 [2].

Links: [2] https://github.com/OP-TEE/optee_os/commit/a58c4d706d23
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:23 -04:00
Etienne Carriere
240720e905 firmware: scmi: mailbox/smt agent device
This change implements a mailbox transport using SMT format for SCMI
exchanges. This implementation follows the Linux kernel and
SCP-firmware [1] as references implementation for SCMI message
processing using SMT format for communication channel meta-data.

Use of mailboxes in SCMI FDT bindings are defined in the Linux kernel
DT bindings since v4.17.

Links: [1] https://github.com/ARM-software/SCP-firmware
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:23 -04:00
Etienne Carriere
358599efd8 firmware: add SCMI agent uclass
This change introduces SCMI agent uclass to interact with a firmware
using the SCMI protocols [1].

SCMI agent uclass currently supports a single method to request
processing of the SCMI message by an identified server. A SCMI message
is made of a byte payload associated to a protocol ID and a message ID,
all defined by the SCMI specification [1]. On return from process_msg()
method, the caller gets the service response.

SCMI agent uclass defines a post bind generic sequence for all devices.
The sequence binds all the SCMI protocols listed in the FDT for that
SCMI agent device. Currently none, but later change will introduce
protocols.

This change implements a simple sandbox device for the SCMI agent uclass.
The sandbox nicely answers SCMI_NOT_SUPPORTED to SCMI messages.
To prepare for further test support, the sandbox exposes a architecture
function for test application to read the sandbox emulated devices state.
Currently supports 2 SCMI agents, identified by an ID in the FDT device
name. The simplistic DM test does nothing yet.

SCMI agent uclass is designed for platforms that embed a SCMI server in
a firmware hosted somewhere, for example in a companion co-processor or
in the secure world of the executing processor. SCMI protocols allow an
SCMI agent to discover and access external resources as clock, reset
controllers and more. SCMI agent and server communicate following the
SCMI specification [1]. This SCMI agent implementation complies with
the DT bindings defined in the Linux kernel source tree regarding
SCMI agent description since v5.8.

Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:23 -04:00
Jean-Jacques Hiblot
0ced26a494 test: dm: Add tests for regmap managed API and regmap fields
The tests rely on a dummy driver to allocate and initialize the regmaps
and the regmap fields using the managed API. The first test checks if
the regmap config fields like width, reg_offset_shift, range specifiers,
etc work. The second test checks if regmap fields behave properly (mask
and shift are ok) by peeking into the regmap.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:23 -04:00
Pratyush Yadav
8a34d3d752 test/py: allow multi-digit index in in_tree()
When more nodes are added for a uclass the index might go into two or
more digits. This means that there are less spaces printed because they
are used up by the extra digits. Update the regular expression to allow
variable-length spacing between the class name and and index.

This was discovered when adding a simple_bus node in test.dts made
test_bind_unbind_with_uclass() fail because the index went up to 10.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-09-30 11:55:23 -04:00
Jean-Jacques Hiblot
1c4db59d9b regmap: Add support for regmap fields
A regmap field is an abstraction available in Linux. It provides to access
bitfields in a regmap without having to worry about shifts and masks.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-09-30 11:55:23 -04:00
Pratyush Yadav
d8babb9598 regmap: Allow devices to specify regmap range start and size in config
Some devices need to calculate the regmap base address at runtime. This
makes it impossible to use device tree to get the regmap base. Instead,
allow devices to specify it in the regmap config. This will create a
regmap with a single range that corresponds to the start and size given
by the driver.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:22 -04:00
Pratyush Yadav
0e01a7c3f4 regmap: Add regmap_init_mem_range()
Right now, the base of a regmap can only be obtained from the device
tree. This makes it impossible for devices which calculate the base at
runtime to use a regmap. An example of such a device is the Cadence
Sierra PHY.

Allow creating a regmap with one range whose start and size can be
specified by the driver based on calculations at runtime.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:22 -04:00
Pratyush Yadav
7aa5ddffe7 regmap: Allow left shifting register offset before access
Drivers can configure it to adjust the final read/write location.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:22 -04:00
Pratyush Yadav
78aaedba9f regmap: Allow specifying read/write width
Right now, regmap_read() and regmap_write() read/write a 32-bit value
only. To write other lengths, regmap_raw_read() and regmap_raw_write()
need to be used.

This means that any driver ported from Linux that relies on
regmap_{read,write}() to know the size already has to be updated at each
callsite. This makes the port harder to maintain.

So, allow specifying the read/write width to make it easier to port the
drivers, since now the only change needed is when initializing the
regmap.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:22 -04:00
Pratyush Yadav
97d8a6970a regmap: zero out the regmap on allocation
Some fields will be introduced in the regmap structure that should be
set to 0 by default. So, once we allocate a regmap, make sure it is
zeroed out to avoid unexpected defaults for those values.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 11:55:22 -04:00
Jean-Jacques Hiblot
ffb22f6b84 regmap: Add devm_regmap_init()
Most of new linux drivers are using managed-API to allocate resources. To
ease porting drivers from linux to U-Boot, introduce devm_regmap_init() as
a managed API to get a regmap from the device tree.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-09-30 11:55:22 -04:00
Jean-Jacques Hiblot
88e6a60e4a test: gpio: Add tests for the managed API
Add a test to verify that GPIOs can be acquired/released using the managed
API. Also check that the GPIOs are released when the consumer device is
removed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-09-30 11:55:22 -04:00
Jean-Jacques Hiblot
d4b722e3a8 drivers: gpio: Add a managed API to get a GPIO from the device-tree
Add managed functions to get a gpio from the devce-tree, based on a
property name (minus the '-gpios' suffix) and optionally an index.

When the device is unbound, the GPIO is automatically released and the
data structure is freed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-09-30 11:55:22 -04:00
Jean-Jacques Hiblot
bad2433151 test: reset: Add tests for the managed API
The tests are basically the same as for the regular API. Except that
the reset are initialized using the managed API, and no freed manually.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-09-30 11:55:22 -04:00
Jean-Jacques Hiblot
139e4a1cbe drivers: reset: Add a managed API to get reset controllers from the DT
Add managed functions to get a reset_ctl from the device-tree, based on a
name or an index.
Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl)
from the device-tree.

When the device is unbound, the reset controllers are automatically
released and the data structure is freed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-09-30 11:55:22 -04:00
Etienne Carriere
5f9070a4a4 optee: copy FDT OP-TEE related nodes before generic FDT changes
Move call to optee_copy_fdt_nodes() introduced by commit 6ccb05eae0
before generic changes in kernel FDT so that platform specific changes
are not overridden by the changes made by this function.

Fixes: 6ccb05eae0 ("image: fdt: copy possible optee nodes to a loaded devicetree")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 11:31:13 -04:00
Tom Rini
01114adfc1 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next
- Disable CMD_IRQ for RISC-V.
- Update sipeed/maix doc
- Obtain reg of SiFive RAM via dev_read_addr_index() instead of regmap API.
- Cleans up RISC-V timer drivers and converts them to DM.
- Correctly handle IPIs already pending upon prior stage bootloader (on the K210)
2020-09-30 09:21:43 -04:00
Tom Rini
527fad0b24 Merge branch '2020-09-29-dev_xxx-print-improvement' into next
- Improve our dev_xxx(..) wrappers to be generally used and available
  rather than discarded at link/compile time.
2020-09-30 09:07:06 -04:00
Sean Anderson
ceb70bb870 dm: Print device name in dev_xxx like Linux
This adorns messages generated by dev_xxx with the device and driver
names. It also redirects dev_xxx to log when it is available. The names
of these functions very roughly take inspiration from Linux, but there is
no deeper correlation.

Both struct udevice and struct device are supported when logging, though
logging with struct device is no better than using log_xxx. The latter is
supported because of the large amount of existing code which logs with
struct device.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:54:07 -04:00
Sean Anderson
4d14600bf6 dm: Use symbolic constants for log levels in dev_xxx
This substitutes literal log levels with their symbolic constants.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:54:05 -04:00
Sean Anderson
4723fd58dc video: stm32: Fix not calling dev_xxx with a device
There is no member `dev` in dw_mipi_dsi, but there is one in mipi_dsi_host,
so use that.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:54:03 -04:00
Sean Anderson
7fe8cfdc77 usb: musb-new: sunxi: Fix not calling dev_err with a device
This driver does not use DM, so we need to use a struct device instead of a
struct udevice. Not ideal, but it'll have to do for now.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:54:01 -04:00
Sean Anderson
2667dacb42 usb: dwc3: Don't include asm-generic/io.h
This can conflict with asm/io.h on some archs, and it isn't needed to build
dwc3-generic.c

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:59 -04:00
Sean Anderson
44003f88a9 usb: dwc3: ti: Fix not calling dev_err with a device
This driver does not use DM, so use log_xxx instead.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:58 -04:00
Sean Anderson
df5eabcbf7 usb: dwc3: Fix not calling dev_xxx with a device
This logs with the device from struct dwc3. Some files also need to include
dm.h so fields in udevice can be accessed.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:54 -04:00
Sean Anderson
046ade8103 usb: dwc2: Fix not calling dev_xxx with a device
This adds a dev argument to some functions so dev_xxx always has a device
to log with. In one instance we must use use a different log function when
we are compiled without DM_USB.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:52 -04:00
Sean Anderson
df8395a01f usb: cdns3: Fix not calling dev_xxx with a device
ep0.c also need to include dm.h so dev_xxx can access udevice fields.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:51 -04:00
Sean Anderson
9c610289b6 sysreset: ti: Fix not calling dev_err with a device
The rst variable doesn't exist.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:48 -04:00
Sean Anderson
49dfbe924c spi: zynqmp_gqspi: Fix not calling dev_err with a device
Use `bus` instead of `dev`.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:47 -04:00
Sean Anderson
32bbe5b5d3 spi: sunxi: Fix not calling dev_err with a device
Use `bus` and not `dev`.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:45 -04:00
Sean Anderson
cc6c2904b2 soc: qualcomm: Fix not calling dev_err with a device
Remove the indirection.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:43 -04:00
Sean Anderson
d7bd29c912 remoteproc: k3: Fix not calling dev_xxx with a device
Pass a device to functions which log with one.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:42 -04:00
Sean Anderson
44f1c38a32 remoteproc: k3-r5: Fix not calling dev_xxx with a device
Usually we can get a device from the current core, but some dev_dbg calls
have been converted to debug, since we are called on a cluster.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:40 -04:00
Sean Anderson
b608c54b52 remoteproc: Remove unused function rproc_elf_sanity_check
This function is never used anywhere, and it also tries to log with a
nonexistant device.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:38 -04:00
Sean Anderson
0aeaca622a phy: usbphyc: Fix not calling dev_err with a device
Use the phy's device.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:36 -04:00
Sean Anderson
29e0969bbd phy: ti: Fix not calling dev_err with a device
`phy` doesn't exist; we need to use `x` instead.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:33 -04:00
Sean Anderson
7334517310 phy: sun4i-usb: Fix not calling dev_err with a device
This uses phy's device

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:31 -04:00
Sean Anderson
e9e1bd1f75 phy: rockchip: Fix not calling dev_err with a device
Get the device from phy, or pass the phy in.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:29 -04:00
Sean Anderson
b9442a01f5 phy: marvell: Fix not calling dev_err with a device
No need for indirection here.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:28 -04:00
Sean Anderson
143d81dc86 net: ti: cpsw: Fix not calling dev_dbg with a device
Without DM_ETH, cpsw_priv.dev is an eth_device. Just use its name instead.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:26 -04:00
Sean Anderson
ef043693c6 net: sun8i_emac: Fix not calling dev_xxx with a device
Pass a udevice into a few functions so `dev` is defined.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:24 -04:00
Sean Anderson
e2f7421522 net: sunxi: Fix not calling dev_xxx with a device
There's no dev to log with, so pass the device along with the priv data.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:22 -04:00
Sean Anderson
69876c54de linux/compat.h: Remove netdev_xxx functions
No drivers in U-Boot use these functions.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:20 -04:00
Sean Anderson
9db60ee470 net: mvpp2: Convert netdev_xxx to dev_xxx
netdev_xxx evaluates to printf in U-Boot, so there is no extra info
printed. mvpp2 one of only two drivers which use these functions in U-Boot.
Convert these functions to dev_xxx where possible (and to log_xxx where
not).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:18 -04:00
Sean Anderson
ddc48c1355 net: mvpp2: Fix not calling dev_xxx with a device
Remove some prefixes, or get the device from the phy.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:16 -04:00
Sean Anderson
c519cbf5c2 net: mvneta: Convert netdev_xxx to dev_xxx
netdev_xxx evaluates to printf in U-Boot, so there is no extra info
printed. mvneta is one of two drivers which use these functions in U-Boot.
Convert these functions to dev_xxx where possible (and to log_xxx where
not).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:14 -04:00
Sean Anderson
13cbe299d0 net: mvneta: Fix not always calling dev_err with a device
No need for indirection here.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:12 -04:00
Sean Anderson
0851bd1e75 net: mdio: Fix not calling dev_dbg with a device
The name of the device we are working on is `ethdev` and not just `dev`.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:06 -04:00
Sean Anderson
1485d64923 net: bcm6368: Fix not calling dev_info with a device
Remove the pdev indirection.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:04 -04:00
Sean Anderson
7f36806c9b nand: vybrid: Re-introduce vf610_nfc.dev
This member was presumably dropped when this driver was converted from
Linux. However, it is still used in log statements during initialization.
This patch adds the member back. In addition, allocation of struct
vf610_nfc has been moved to the callers of vf610_nfc_nand_init. This allows
it to be allocated by DM (if it is being used) and for dev to be
initialized.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:01 -04:00
Sean Anderson
15b6ab4cee nand: brcmnand: Fix not calling dev_err() with a device
There are too many levels of indirection when calling dev_err. This is an
artifact of the conversion of brcmnand_host.pdev from a struct
platform_device (which has a member `dev` pointing to a struct device) to
struct udevice.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:59 -04:00
Sean Anderson
2e8c907aba nand: atmel: Fix not calling dev_xxx with a device
Use mtd_info to get a device to log with.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:56 -04:00
Sean Anderson
fe6e209a27 mailbox: k3: Fix not calling dev_err with a device
dev needs to be gotten from mbox_chan

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:54 -04:00
Sean Anderson
e1ce790128 mmc: mtk-sd: Fix not calling dev_err with a device
This adds a udevice parameter to get_best_delay and msdc_set_mclk so they
can call dev_err properly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:52 -04:00
Sean Anderson
48a4eb802a mmc: bcm2835-host: Fix not calling dev_dbg with a device
dev needs to be qualified as a member of host.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:49 -04:00
Sean Anderson
68fd602662 mmc: Add mmc_dev()
This macro is necessary for arasan_zynqmp_dll_reset to compile.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:46 -04:00
Sean Anderson
6dcc2819ae mtd: spi-nand: Fix not calling dev_err with a device
Get it from spinand->slave->dev. Another option would be to use
spinand_to_mtd(spinand)->dev, but this is what the existing code uses.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:44 -04:00
Sean Anderson
8985e1cf91 mtd: spi: Fix logging in spi-nor-tiny
This fixes dev_xxx() not always being called with a device. In
spi_nor_reg_read, a the slave device may not always be available, so we use
bus and cs instead.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:41 -04:00
Sean Anderson
c64633644e mtd: spi: Include dm.h in spi-nor-core.c
This header is needed so struct udevice can be used in dev_xxx().

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:39 -04:00
Sean Anderson
75eed1a113 mtd: nand: sunxi: Fix not calling dev_err with a device
Usually the device is gotten from sunxi_nfc. This is a struct device and
not a struct udevice, but the whole driver seems to be written wihout DM
anyway...

In a few instances, this patch modifies functions to take an nfc to log
with. In once instance we use mtd_info's device since there is no nfc.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:36 -04:00
Sean Anderson
661c98121d mtd: nand: pxa3xx: Fix not calling dev_xxx with a device
Use the device from any mtd already available, or from the active mtd via
pxa3xx_nand_info if one is not.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:33 -04:00
Sean Anderson
b4f11dfcbd i2c: mxc: Fix dev_err being called on a nonexistant variable
The udevice we are working with is called `bus` and not `dev`.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:30 -04:00
Sean Anderson
e579230b37 firmware: ti_sci: Fix not calling dev_err with a device
This converts calls to dev_err to get the device from ti_sci_info where
appropriate.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:24 -04:00
Sean Anderson
46df2f87bd dm: syscon: Fix calling dev_dbg with an uninitialized device
We can't use dev_dbg here because we haven't bound to the device yet. Use
log_debug instead.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:52:14 -04:00
Sean Anderson
924de3216e riscv: Add some comments to start.S
This adds comments regarding the ordering and purpose of certain
instructions as I understand them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-09-30 08:54:52 +08:00
Sean Anderson
85768134b4 riscv: Ensure gp is NULL or points to valid data
This ensures constructs like `if (gd & gd->...) { ... }` work when
accessing the global data pointer. Without this change, it was possible for
a very early trap to cause _exit_trap to directly or indirectly (through
printf) to read arbitrary memory. This could cause a second trap,
preventing show_regs from being printed.

printf (and specifically puts) uses gd to determine what function to print
with. These functions in turn use gd to find the serial device, etc.
However, before accessing gd, puts first checks to see if it is non-NULL.
This indicates an existing (perhaps undocumented) assumption that either gd
is NULL or it is completely valid.

Before this patch, gd either points to unexpected data (because it retains
the value it did from the prior-stage) or points to uninitialized data
(because it has not yet been initialized by board_init_f_init_reserve)
until the hart has acquired available_harts_lock. This can cause two
problems, depending on the value of gd->flags. If GD_FLG_SERIAL_READY is
unset, then some garbage data will be printed to stdout, but there will not
be a second trap. However, if GD_FLG_SERIAL_READY is set, then puts will
try to print with serial_puts, which will likely cause a second trap.

After this patch, gd is zero up until either a hart has set it in
wait_for_gd_init, or until it is set by arch_init_gd. This prevents its
usage before its data is initialized because both handle_trap and puts
ensure that gd is nonzero before using it. After gd has been set, it is OK
to access it because its data has been cleared (and so flags is valid).

XIP cannot use locks because flash is not writable. This leaves it
vulnerable to the same class of bugs regarding already-pending IPIs as
before this series. Fixing that would require finding another method of
synchronization, which is outside the scope of this series.

Fixes: 7c6ca03eae ("riscv: additional crash information")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:52 +08:00
Sean Anderson
309995b315 riscv: Consolidate fences into AMOs for available_harts_lock
We can reduce the number of instructions needed to use available_harts_lock
by using the aq and rl suffixes for AMOs.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:52 +08:00
Sean Anderson
768502e2a7 riscv: Clear pending IPIs on initialization
Even though we no longer call smp_function if an IPI was not sent by
U-Boot, we still need to clear any IPIs which were pending from the
execution environment. Otherwise, secondary harts will busy-wait in
secondary_hart_loop, instead of relaxing.

Along with the previous commit ("riscv: Use a valid bit to ignore
already-pending IPIs"), this fixes SMP booting on the Kendryte K210.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:52 +08:00
Sean Anderson
f760c9a1fd riscv: Use a valid bit to ignore already-pending IPIs
Some IPIs may already be pending when U-Boot is started. This could be a
problem if a secondary hart tries to handle an IPI before the boot hart has
initialized the IPI device.

To be specific, the Kendryte K210 ROM-based bootloader does not clear IPIs
before passing control to U-Boot. Without this patch, the secondary hart
jumps to address 0x0 as soon as it enters secondary_hart_loop, and then
hangs in its trap handler.

This commit introduces a valid bit so secondary harts know when and IPI
originates from U-Boot, and it is safe to use the IPI API. The valid bit is
initialized to 0 by board_init_f_init_reserve. Before this, secondary harts
wait in wait_for_gd_init.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-09-30 08:54:52 +08:00
Sean Anderson
d4990a4648 riscv: Match memory barriers between send_ipi_many and handle_ipi
Without a matching barrier on the write side, the barrier in handle_ipi
does nothing. It was entirely possible for the boot hart to write to addr,
arg0, and arg1 *after* sending the IPI, because there was no barrier on the
sending side.

Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-09-30 08:54:52 +08:00
Sean Anderson
c41045411b Revert "riscv: Clear pending interrupts before enabling IPIs"
Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.

The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.

This reverts commit 9472630337.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:52 +08:00
Sean Anderson
422c3c5edf riscv: Update SiFive device tree for new CLINT driver
We currently do this in a u-boot specific dts, but hopefully we can get
these bindings added in Linux in the future.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
e89e8983dc riscv: Update Kendryte device tree for new CLINT driver
The interrupt controller property is removed from the clint binding because
the clint is not an interrupt-controller. That is, no other devices have an
interrupt which is controlled by the clint.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
a952c3a454 riscv: clk: Add CLINT clock to kendryte clock driver
Another "virtual" clock (in the sense that it isn't configurable). This
could possibly be done as a clock in the device tree, but I think this is a
bit cleaner.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
e5ca9a7523 riscv: Rework Sifive CLINT as UCLASS_TIMER driver
This converts the clint driver from the riscv-specific interface to be a
DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously
implicitly depended on the CLINT to select REGMAP.

Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb),
the SiFive CLINT is part of the device tree passed in by qemu. This device
tree doesn't have a clocks or clock-frequency property on clint, so we need
to fall back on the timebase-frequency property. Perhaps in the future we
can get a clock-frequency property added to the qemu dtb.

Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller.
RISCV_SYSCON_CLINT is retained for this purpose.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
15943bb558 riscv: Clean up initialization in Andes PLIC
This merges the PLIC initialization code from two functions into one.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:46 +08:00
Sean Anderson
e86463f8e3 riscv: Rework Andes PLMT as a UCLASS_TIMER driver
This converts the PLMT driver from the riscv-specific timer interface to be
a DM-based UCLASS_TIMER driver.

The clock-frequency/clocks properties are preferred over timebase-frequency
for two reasons. First, properties which affect a device should be located
near its binding in the device tree. Using timebase-frequency only really
makes sense when the cpu itself is the timer device. This is the case when
we read the time from a CSR, but not when there is a separate device.
Second, it lets the device use the clock subsystem which adds flexibility.
If the device is configured for a different clock speed, the timer can
adjust itself.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:45 +08:00
Sean Anderson
7616e3687e timer: Add a test for timer_timebase_fallback
To test this function, sandbox CPU must set cpu_platdata.timebase_freq on
bind. It also needs to expose a method to set the current cpu. I also make
some most members of cpu_sandbox_ops static.

On the timer side, the device tree property
sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe
falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30 08:54:45 +08:00
Sean Anderson
3576121687 timer: Add helper for drivers using timebase fallback
This function is designed to be used when a timer used to be initialized by
the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In
such a case, the timer may prefer to use the clocks and clock-frequency
properties, but should be able to fall back on using the cpu's
timebase-frequency.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:45 +08:00
Sean Anderson
c33efafaf9 riscv: Rework riscv timer driver to only support S-mode
The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.

This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-30 08:54:45 +08:00
Bin Meng
9981a8009e ram: sifive: Remove regmap dependency
The usage of regmap API in the SiFive RAM driver is not correct.
The reg address should be obtained via dev_read_addr_index() API.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:38 +08:00
Bin Meng
f8c9660bfe ram: sifive: Check return value on clk_enable()
The return value should be checked otherwise it's useless to
assign the return value to 'ret'.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:38 +08:00
Heinrich Schuchardt
08bff30d5d doc/sipeed/maix: describe RESET and BOOT button
In the boot flow description add the RESET and BOOT button as well as the
function of the DTR and RTS lines of the serial interface.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-30 08:54:31 +08:00
Heinrich Schuchardt
d53a95ba5e doc: correct kflash settings for Maix One Dock
The correct kflash parameter value for the Maix One Dock is "dan".

See:
https://github.com/sipeed/platform-kendryte210/blob/master/boards/sipeed-maix-one-dock.json#L22

Fixes: 137dc153fd ("doc: riscv: Update documentation for Sipeed MAIX boards")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-30 08:54:25 +08:00
Pragnesh Patel
c5a7e5b3dd cmd: irq: disable CMD_IRQ for riscv arch
For RISC-V arch, no need for CMD_IRQ so disable the same.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-09-30 08:54:03 +08:00
Tom Rini
421ebb713b Merge branch '2020-09-29-assorted-fixes'
- Assorted typo fixes
- Correctly migrate some CONFIG_PREBOOT cases to defconfig
- Coverity issues in squashfs
2020-09-29 13:24:50 -04:00
Heinrich Schuchardt
f644081d38 video: typo Normlly
%s/Normlly/Normally/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-29 13:19:08 -04:00
Naoki Hayama
499696e40a README: Fix typo in Board Initialisation Flow
I suppose 'these' might be 'there'.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-09-29 13:19:08 -04:00
Heinrich Schuchardt
0ed375ebb1 fs/squashfs: parameter check sqfs_read_metablock()
We should check if the incoming parameter file_mapping is not NULL instead
of checking after adding an offset.

Reported-by: Coverity CID 307210
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2020-09-29 13:19:08 -04:00
Heinrich Schuchardt
5558af16a0 mtd: fix typos in drivers/mtd/Kconfig, drivers/mtd/renesas_rpc_hf.c
Fix a typo

%s/interract/interact/

Use Samsung's capitalization of their trademarks

%s/onenand/OneNAND/
%s/Hyperflash/HyperFlash/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
[trini: Add other Hyperflash cases as noted by Stefan]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-29 13:18:31 -04:00
Peter Robinson
324d77998e Define default CONFIG_PREBOOT with right config option
The 44758771ee commit removes CONFIG_PREBOOT but actually sets the USE_PREBOOT
Kconfig option which isn't CONFIG_PREBOOT and is also a bool option which means
we regress because 'usb start' isn't run when expected, it should also be run
for devices that have USB storage because keyboards aren't the only thing we
might need the USB bus for.

Fixes: 44758771ee ("arm: move CONFIG_PREBOOT="usb start" to KConfig")
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Jonas Smedegaard <dr@jones.dk>
Cc: Neil Armstrong <narmstrong@baylibre.com>
2020-09-29 13:17:33 -04:00
Tom Rini
d44d46e9fa Merge tag 'efi-2020-10-rc6' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc6

The following UEFI related issues are fixed:

* restore the global data pointer in the RISC-V trap handler
* install EFI_RNG_PROTOCOL only if we have a random number generator
* display human readable string for EFI_RNG_PROTOCOL in efidebug command
2020-09-28 08:26:49 -04:00
Tom Rini
114c0ebcc1 Merge tag 'u-boot-amlogic-20200928' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- fix RNG driver probe & linux EFI KASLR boot on GXL, GXM, G12A, G12B & SM1 based boards
2020-09-28 08:26:34 -04:00
Claudiu Beznea
96b9a5cdf8 MAINTAINERS: add Microchip PIT64B timer
Add Microchip PIT64B timer.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-28 14:07:26 +03:00
Claudiu Beznea
ed1b726683 timer: mchp-pit64b: add support for pit64b
Add support for Microchip PIT64B timer. The timer is 64 bit length and
is used as a free running counter (in continuous mode with highest values
for period registers). The clock feeding the timer would be no more
than 12.5MHz.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-28 14:06:50 +03:00
Heinrich Schuchardt
c48e9f310b riscv: restore global data pointer in trap handler
The gp register is used to store U-Boot's global data pointer. We should
not assume that an UEFI application leaves the gp register unchanged as
the UEFI specifications does not define who is the owner of the gp and tp
registers.

So the following sequence should be followed in the trap handler:

* save the caller's gp register
* restore the global data pointer
* serve interrupts or print crash dump and reset
* restore the caller's gp register

Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-28 12:20:19 +02:00
Neil Armstrong
02d249f99e rng: meson: make core clock optional
This fixes HWRNG support on Amlogic GXL, GXM, G12A, G12B & SM1
based boards dues to the lack of the core clock in the device tree.

It was reported breaking EFI boot in the Linux EFI stub, because the
EFI_RNG_PROTOCOL didn't check for the RNG device presence before
installing itself.

The Linux amlogic,meson-rng.yaml doesn't mandate the core clock,
this the clock should be ignores if not present.

Nevertheless, the clock should be present and this should be fixed
on the Linux meson-gxl.dtsi & meson-g12-common.dtsi then synced
with U-Boot.

The change has been tested on a Khadas VIM3, which uses the common
meson-g12-common.dtsi like the Odroid-C4 & Odroid-N2 in Scott's
report, along with the RNG cmd.

Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reported-by: Scott K Logan <logans@cottsay.net>
Fixes: bc40eb278b ("drivers/rng: add Amlogic hardware RNG driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Scott K Logan <logans@cottsay.net>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-28 09:38:11 +02:00
Heinrich Schuchardt
b59c13d42f efi_loader: installation of EFI_RNG_PROTOCOL
Having an EFI_RNG_PROTOCOL without a backing RNG device leads to failure
to boot Linux 5.8.

Only install the EFI_RNG_PROTOCOL if we have a RNG device.

Reported-by: Scott K Logan <logans@cottsay.net>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-27 16:10:45 +02:00
Heinrich Schuchardt
796933510f efi_loader: efidebug display RNG protocol
Add the Random Number Generator (RNG) protocol to the GUIDs that the
'efidebug dh' protocol can replace by a text.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-27 16:10:45 +02:00
Lad Prabhakar
d03ad060fe board: renesas: ebisu: Drop CA57 check in reset_cpu()
Renesas Ebisu board is based on R-Car E3 SoC which has dual CA53 and
a CR7.

This patch drops check for cputype from reset_cpu() and also drops the
corresponding CA57 macros. While at it also dropped RST_RSTOUTCR macro
which is unused.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-09-26 17:26:01 +02:00
Biju Das
9275a963d4 net: ravb: Remove writeext function call
The micrel phy driver is already configuring this values from
device tree. So remove the redundant phy configuration call from
this driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:44 +02:00
Biju Das
3ee840cce4 board: renesas: draak: Drop CA57 reset
Renesas Draak board based on R-Car D3 has single CA53.

This patch drops check for cputype from reset_cpu() and also drops the
corresponding CA57 macros. While at it also dropped RST_RSTOUTCR macro
which is unused.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
cb1b6795df board: renesas: remove empty board_early_init_f function
Remove empty board_early_init_f function, since it is disabled
in ebisu and condor board configs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
5157b011da arm: rmobile: Use imply for BOARD_EARLY_INIT_F
Use "imply" instead of "select" for BOARD_EARLY_INIT_F config option,
and then disable it on boards which don't need it.

Updated grpeach_defconfig to disable CONFIG_BOARD_EARLY_INIT_F option for
RZA1.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
e6c8e763e9 board: renesas: Remove empty s_init function
Default s_init weak function available, so remove the
s_init empty function.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
aead065e0e arm: mach-rmobile: Mark the default s_init function as weak
Mark the default s_init function as weak, so that SoC's can
override it if needed, and it will still be discarded if unused.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
3afde5aab6 arm: dts: r8a774e1: Import DTS from Linux 5.9-rc4
Import R8A774E1 (RZ/G2H) SoC DTSI and headers from upstream Linux kernel
5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
1abdab94f1 arm: dts: r8a774b1: Import DTS from Linux 5.9-rc4
Import R8A774B1 (RZ/G2N) SoC DTSI and headers from upstream Linux kernel
5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
00407251c3 arm: dts: r8a774a1: Import DTS from Linux 5.9-rc4
Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit
f4d51dffc6c0 ("Linux 5.9-rc4")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
953a3be768 pinctrl: renesas: Fix PINCTRL_PFC_R8A774A1 help description
R8A774A1 is part of Renesas RZ/G2 series and not R-Car, reflect the same
for PINCTRL_PFC_R8A774A1 help description

Alongside, sort the PINCTRL_PFC_R8A774A1 config option as per increasing
number of the SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Biju Das
7d7913689a arm: rmobile: Identify R8A7796 r1.3 SoC
Add support to identify R8A7796 r1.3 SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26 17:25:43 +02:00
Marek Vasut
42805b17e6 ARM: rmobile: Enable dfu tftp on Gen3
Enable the fitImage update options on RCar Gen3 boards.
This permits easy update of multiple bootloader components.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-09-26 17:25:42 +02:00
Marek Vasut
16dcfbcd2b ARM: rmobile: Enable RPC on Salvator-X, ULCB, Ebisu
Enable the RPC Hyperflash driver on R8A7795,R8A7796,R8A77965
Salvator-X,ULCB and R8A77990 Ebisu. Note that to make the HF
accessible, mainline ATF is mandatory and must be built with
RCAR_RPC_HYPERFLASH_LOCKED=0 . Note that this is intended for
development and testing convenience only and must be disabled
in deployment for platform security reasons.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-09-26 17:25:42 +02:00
Tom Rini
253388acd6 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Bug fixes related to PCIe, pfe, xfi, gpio, reset, vid, env, and usb on
  layerscape products
2020-09-25 12:55:06 -04:00
Tom Rini
0ac83d080a Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Enhance the 'zboot' command to be more like 'bootm' with sub-commands
- The last series of ACPI core changes for programmatic generation of
  ACPI tables
- Add all required ACPI tables for ApolloLake and enable ACPIGEN on
  Chromebook Coral
- A feature minor enhancements to the 'hob' command
- Intel edison: Support for writing an xFSTK image via binman
2020-09-25 09:04:01 -04:00
Eugen Hristev
3710b464e4 mmc: atmel-sdhci: use mmc_of_parse to get the DT properties
Call mmc_of_parse at probe time to fetch all the host properties
from the DT.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-09-25 10:39:22 +03:00
Eugen Hristev
81f16438d4 mmc: atmel-sdhci: enable the required generic clock
The second clock of the IP block (the generic clock), must be explicitly
enabled.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Peng Fan <pengfan@nxp.com>
2020-09-25 10:39:22 +03:00
Eugen Hristev
2e00608ca4 mmc: atmel-sdhci: do not check clk_set_rate return value
clk_set_rate will return rate in case of success and zero in case of
error, however it can also return -ev, but it's an ulong function.
To avoid any issues, disregard the return value of this call.
In case this call actually fails, nothing much we can do anyway, but we
can at least try with the previous values (or DT assigned-clocks)

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-25 10:39:22 +03:00
Eugen Hristev
4cc0825875 mmc: atmel-sdhci: add sama7g5-sdhci compatibility string
Add new compatibility string for matching sama7g5 product.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-09-25 10:39:22 +03:00
Eugen Hristev
63ef81625e pinctrl: at91-pio4: add compatible for sama7g5 pinctrl block
Add new compatible to microchip,sama7g5 new SoC.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-25 10:39:22 +03:00
Eugen Hristev
558378a4cd ARM: mach-at91: add support for new SoC sama7g5
Add support for new SoC sama7g5

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-25 10:39:22 +03:00
Simon Glass
8c180d669a x86: edison: Add documentation for using am xFSTK image
Add a description of how to flash Edison using the xFSTK tool.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:29 +08:00
Simon Glass
2e3b883014 x86: edison: Generate an image suitable for xFSTK
It is useful to be able to flash Edison directly without relying on the
installed U-Boot being functional.

Add a binman image for this. It includes a 'OSIP' header (which happens to
look like an MBR / (Master-Boot Record), U-Boot binary and an environment.

I am not able to find a specification for OSIP.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:28 +08:00
Simon Glass
fb91d5675e binman: Support adding a U-Boot environment
In some cases it is useful to include a U-Boot environment region in an
image. This allows the board to start up with an environment ready to go.

Add a new entry type for this. The input is a text file containing the
environment entries, one per line, in the format:

   var=value

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:28 +08:00
Simon Glass
204aa78e04 binman: Show an error when a file is missing
The recent support for missing external binaries does not show an error
message when a file is genuinely missing (i.e. it is missing but not
marked as 'external'). This means that when -m is passed to binman, it
will never report a missing file.

Fix this and add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:28 +08:00
Simon Glass
2463f165a3 x86: Use multiple images
We already use binman's 'multiple-images' feature with Chrome OS and we
want to use it for Edison. There is no real down-side.

Adjust x86 to always use multiple-images.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25 11:27:28 +08:00
Simon Glass
308b1a960e x86: video: Show information about each video device
At present the 'bdinfo' command shows the framebuffer address, but not the
address of the copy framebuffer, if present. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
29d2d64ed5 x86: Add support for more than 8 MTRRs
At present the mtrr command only support 8 MTRRs. Some SoCs have more than
that. Update the implementation to support up to 10. Read the number of
MTRRs dynamically instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
51af144eb7 x86: Allow showing details about a HOB entry
Some HOBs include information that can be decoded. Add a -v option to the
hob command, to allow this to be displayed. Add the ability to decode a
resource descriptor.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
10536ceae9 x86: hob: Try to show a name instead of a GUID
GUIDs are one of the seven evils of the computer world. They obfuscate the
meaning and require people to look up long hex strings to decode it.

Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use.

Add a way to decode the GUIDs known to U-Boot. Add a few more to the list
for good measure.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
d11544dfa9 x86: hob: Add way to show a single hob entry
The 'hob' command currently lists all HOB entries. Add way to list a
single entry, by index.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:26 +08:00
Simon Glass
9c6aaf1347 acpi: Use I2cSerialBusV2() instead of I2cSerialBus()
Use the correct name of the ACPI structure being created.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:26 +08:00
Simon Glass
1e4073b855 acpi: Add more documentation for struct acpi_gpio
Add some documentation provided by Andy Shevchenko to describe how to
use struct acpi_gpio.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:26 +08:00
Simon Glass
49f5141ed3 x86: coral: Update config and device tree for ACPI
Enable new features and provide require device-tree config so that U-Boot
produces the correct ACPI tables on Coral.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:25 +08:00
Simon Glass
ee3cb7c648 x86: Move include of bitops out of ACPI region
At present linux/bitops.h is included in ACPI code. This is not needed and
can cause a problem in fls64.h since BITS_PER_LONG is not defined. Move
the #include into the part not used by ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:25 +08:00
Simon Glass
70c202c480 x86: Add a way to add to the e820 memory table
Some boards want to reserve extra regions of memory. Add a 'chosen'
property to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:25 +08:00
Simon Glass
2a2ebf880c acpi: Use defines for field lengths
A few fields have an open-coded length. Use the defines for this purpose
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:25 +08:00
Simon Glass
cc5e02fcbf x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()
At present this function only supports FSP-M but it is also used to read
FSP-S, in which case FSP-M may be zero. Add support for showing whichever
address is present in the FSP binary.

Also change the debug() statements to log_debug() while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:24 +08:00
Simon Glass
4558d3294d x86: fsp: Add more debugging for silicon init
If locating the FSP header hangs for whatever reason it is useful to see
where it got stuck. Add a debug print. Also show the address of the FSP-S
entry point as a sanity check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:24 +08:00
Simon Glass
96bf9be89e x86: apl: Check low-level init in FSP-S pre-init
If U-Boot is not running FSP-S it should not do the pre-init either. Add a
condition to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:24 +08:00
Simon Glass
a30898f2a1 x86: coral: Add audio descriptor files
Add files describing the various audio configurations supported on coral.
These are passed to Linux in the ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:24 +08:00
Simon Glass
2da4b6998e x86: acpi: Set the log category for x86 table generation
This file doesn't currently have a log category. Add one so that items
are logged correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:23 +08:00
Simon Glass
77bb1c69df acpi: tpm: Add a TPM1 table
This provides information about a v1 TPM in the system. Generate this
table if the TPM is present.

Add a required new bloblist type and correct the header order of one
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:23 +08:00
Simon Glass
9179c3571c acpi: tpm: Add a TPM2 table
This provides information about a v2 TPM in the system. Generate this
table if the TPM is present.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:23 +08:00
Simon Glass
4ff3591988 x86: Correct handling of MADT table CPUs
At present if hyperthreading is disabled the CPU numbering is not
sequential. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:23 +08:00
Simon Glass
26c3d3d7d5 x86: Add a header guard to asm/acpi_table.h
This file cannot currently be included in ASL files. Add a header guard
to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:22 +08:00
Simon Glass
3a25073a40 x86: Correct the assembly guard in e820.h
This is currently in the wrong place, so including the file in the device
tree fails. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:22 +08:00
Simon Glass
7c73cea442 x86: Notify the FSP of the 'end firmware' event
Send this notification when U-Boot is about to boot into Linux, as
requested by the FSP.

Currently this causes a crash with the APL FSP, so leave it disabled for
now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:22 +08:00
Simon Glass
f31b02c84e x86: Sort the MTRR table
At present the MTRR registers are programmed with the list the U-Boot
builds up in the same order. In some cases this list may be out of order.
It looks better in Linux to have the registers in order, so sort them,

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:22 +08:00
Simon Glass
aec7c1c565 x86: cpu: Report address width from cpu_get_info()
Add support for this new field in the common code used by most x86 CPU
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:21 +08:00
Simon Glass
c90b302d5f x86: fsp: Update the FSP API with the end-firmware method
This new method is intended to be called when UEFI shuts down the 'boot
services', i.e. any lingering code in the boot loader that might be used
by the OS.

Add a definition for this new method and update the comments a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:21 +08:00
Simon Glass
eaac971736 tpm: cr50: Add ACPI support
Generate ACPI information for this device so that Linux can use it
correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:21 +08:00
Simon Glass
ca60199fee x86: apl: Drop unnecessary code in PMC driver
We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this
code is not needed. Drop it, and fix a code-style nit just above.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:20 +08:00
Simon Glass
ea78675b96 x86: apl: Generate ACPI table for LPC
Add an ACPI table for the LPC on Apollo Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:20 +08:00
Simon Glass
60c0231078 x86: apl: Generate CPU tables
Add ACPI generation to the APL CPU driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:20 +08:00
Simon Glass
abb4e42b75 x86: apl: Add support for hostbridge ACPI generation
Support generating a DMAR table and add a few helper routines as well.
Also set up NHLT so that audio works.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:20 +08:00
Simon Glass
da2c1b8fd9 x86: apl: Generate required ACPI tables
Add support for generating various ACPI tables for Apollo Lake. Add a few
S3 definitions that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
022256b95b p2sb: Add some definitions used for ACPI
Allow this header to be included in ASL files by adding a header guard and
a few definitions that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
94c5ad2534 x86: apl: Allow reading hostbridge base addresses
Add a few functions to permit reading of various useful base addresses
provided by the hostbridge.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
540f0bae9b x86: acpi: Add support for additional Intel tables
Apollo Lake needs to generate a few more table types used on Intel SoCs.
Add support for these into the x86 ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
b98b91b6a9 x86: Support Atom SoCs using SWSMISCI rather than the SWSCI
Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this.
It is used on Apollo Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:18 +08:00
Simon Glass
9b3e6d4c1f x86: acpi: Add common Intel ACPI tables
Add various tables that are common to Intel CPUs. These functions can be
used by arch-specific CPU code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:18 +08:00
Simon Glass
350c7f52b9 acpi: Add more support for generating processor tables
This adds tables relating to P-States and C-States.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:18 +08:00
Simon Glass
7764a8481c x86: acpi: Add PCT and PTC tables
These are needed for the CPU tables. Add them into an x86-specific file
since we do not support them on sandbox, or include tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:18 +08:00
Simon Glass
15403289e5 acpi: Add support for generating processor tables
ACPI has a number of CPU-related tables. Add utility functions to write
out the basic packages.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:17 +08:00
Simon Glass
f37979e7b7 x86: acpi: Support generation of the DBG2 table
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table.
Adjust one of the header includes to be in the correct order, before
adding more.

Note that the DBG2 table is generic but the PCI UART is x86-specific at
present since it assumes an ns16550 UART. It can be generalised later
if necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:17 +08:00
Simon Glass
d2628984b7 x86: acpi: Support generation of the HPET table
Add an implementation of the HPET (High Precision Event Timer) ACPI
table. Since this is x86-specific, put it in an x86-specific file

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:17 +08:00
Simon Glass
6c0da2da7c x86: Add a few common Intel CPU functions
Add functions to query CPU information, needed for ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
abc585b745 x86: apl: Update iomap for ACPI
Add some more definitions to the iomap. These will be used by
ACPI-generation code as well as the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
10552377d4 x86: apl: Add power-management definitions
Add SCI and power-state definitions required by ACPI tables. Fix the
license to match the original source file.

Als update the guard on acpi_pmc.h to avoid an error when buiding ASL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
59561c7c2e x86: Add some definitions for SMM
U-Boot does not support SMM (System Management Mode) at present, but needs
a few definitions to correctly set up the ACPI table. Add these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
18d8d241be x86: acpi: Add a common routine to write WiFi info
Intel WiFi chips can use a common routine to write the information needed
by linux. Add an implementation of this.

Enable it for coral.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
c9cc37de2c x86: apl: Support writing the IntelGraphicsMem table
This table is needed by the Linux graphics driver to handle graphics
correctly. Write it to ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
e4f09f97c9 x86: Add wake sources for the acpi_gpe driver
Some devices can wake the system from sleep, e.g opening the lid on a
clamshell or moving a USB mouse.

Add a wake to specify this for USB devices and add the settings for Apollo
Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
fd42f263ce i2c: Add a generic driver to generate ACPI info
Many I2C devices produce roughly the same ACPI data with just things like
the GPIO/interrupt information being different.

This can be handled by a generic driver along with some information in the
device tree.

Add a generic i2c driver for this purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-09-25 11:27:15 +08:00
Simon Glass
bddbaf5edf x86: link: Allow more space for U-Boot
The extra ACPI code increases U-Boot above it current size limit. Move
the start earlier to provide space.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:14 +08:00
Simon Glass
23dd0ea4c7 dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio()
This function currently accepts the IRQ-polarity type. Fix it to use the
GPIO type instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:14 +08:00
Simon Glass
88490e1979 acpi: Support generating a multi-function _DSM for devices
Add a function to generate ACPI code for a _DSM method for a device.
This includes functions for starting and ending each part of the _DSM.

Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: fix the "new blank line at EOF" git warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:14 +08:00
Simon Glass
da7cff338f acpi: Add support for conditions and return values
Add functions to support generating ACPI code for condition checks and
return values.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:14 +08:00
Simon Glass
e0a896b88f acpi: Add support for writing a _PRW
A 'Power Resource for Wake' list the resources a device depends on for
wake. Add a function to generate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
99e555a79a x86: coral: Add ACPI tables for coral
This device has a large set of ACPI tables. Bring these in from coreboot
so that full functionality is available (apart from SMI).

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
7924b499a2 x86: acpi: Expand the GNVS
Expand this to 4KB so that it is possible to add custom information to it.
On Chromebooks this is used to pass verified-boot information.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
55109f1d4e x86: acpi: Support external GNVS tables
At present U-Boot puts a magic number in the ASL for the GNVS table and
searches for it later.

Add a Kconfig option to use a different approach, where the ASL files
declare the table as an external symbol. U-Boot can then put it wherever
it likes, without any magic numbers or searching.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
167c3f6e93 x86: Add a common global NVS structure
Add the definition of this structure common to Intel devices. It includes
some optional Chrome OS pieces which are used when vboot is integrated.

Drop the APL version as it is basically the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:12 +08:00
Simon Glass
97bafc9df9 x86: Add a config for the systemagent PCIEX regions size
Add a way to specify the required size for this region. This is used when
generating ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:12 +08:00
Simon Glass
4c44aa7aab x86: apl: Correct PCIE_ECAM_BASE
This value is incorrect and causes problems booting Linux. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:12 +08:00
Simon Glass
13539ba705 x86: acpi: Add DPTF asl files
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files,
taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:12 +08:00
Simon Glass
14f643d1a2 x86: acpi: apl: Add asl files for Apollo Lake
Add Apollo Lake ASL files, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:11 +08:00
Simon Glass
d9434a17e5 x86: acpi: Add base asl files for common x86 devices
Add common x86 ASL files, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-09-25 11:27:11 +08:00
Simon Glass
4d0c5762ad x86: acpi: Add cros_ec tables
Add ASL files for the Chrome OS EC, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:11 +08:00
Simon Glass
d9778ff0d3 cros: Add information about booting Chrome OS on x86
Recent versions of Chrome OS do not have a kernel in the root disk, to
save space.

With the improvements to the 'zboot' command it is fairly easy to load
the kernel from the raw partition. Add instructions on how to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:11 +08:00
Simon Glass
dc8e7a91f4 cros: Update chromium documentation
A few things have changed since this was written about 18 months ago.
Update the README.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
4f96023afd x86: zboot: Allow overriding the command line
When booting Chrome OS images the command line is stored separately
from the kernel. Add a way to specify this address so that images boot
correctly.

Also add comments to the zimage.h header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 8 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
631c2b9fc4 x86: zboot: Add an option to dump the setup information
There is a lot of information in the setup block and it is quite hard to
decode manually. Add a 'zboot dump' command to decode it into a
human-readable format.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
f82cd7b725 x86: zboot: Allow setting a separate setup base address
At present the setup block is always obtained from the image
automatically. In some cases it can be useful to use a setup block
obtained elsewhere, e.g. if the image has already been unpacked. Add an
argument to support this and update the logic to use it if provided.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 7 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
126f47c3b8 x86: zboot: Set environment variables for image locations
At present it is not possible to tell from a script where the setup block
is, or where the image was loaded to. Add environment variables for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:09 +08:00
Simon Glass
3e59759324 x86: zboot: Add an 'setup' subcommand
Add a subcommand that sets up the kernel ready for execution.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:09 +08:00
Simon Glass
1d9e4bb755 x86: zboot: Add an 'load' subcommand
Add a subcommand that loads the kernel into the right places in memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust ZBOOT_STATE_INFO value to match the command order]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:09 +08:00
Simon Glass
6f873f5fc6 x86: zboot: Add an 'info' subcommand
Add a little subcommand that prints out where the kernel was loaded and
its setup pointer. Run it by default in the normal boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:09 +08:00
Simon Glass
88f1cd6c2a x86: zboot: Add a 'go' subcommand
Split out the code that actually boots linux into a separate sub-command.
Add base_ptr to the state to support this.

Show an error if the boot fails, since this should not happen.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:08 +08:00
Simon Glass
5588e776b0 x86: zboot: Set up a sub-command structure
Add subcommands to zboot. At present there is only one called 'start'
which does the whole boot. It is the default command so is optional.

Change the 's' string variable to const while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: reduce maxargs to 6 of 'zboot start' subcommand]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:08 +08:00
Simon Glass
e9d31b302d x86: zimage: Disable interrupts just before booting
At present if an error occurs while setting up the boot, interrupts are
left disabled. Move this call later in the sequence to avoid this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:08 +08:00
Simon Glass
00630f63cc x86: zboot: Correct image type
At present U-Boot sets a loader type of 8 which means LILO version 8,
according to the spec. Update it to 0x80, which means U-Boot with no
particular version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:08 +08:00
Simon Glass
c038f3be3b x86: zboot: Move kernel-version code into a function
To help reduce the size and complexity of load_zimage(), move the code
that reads the kernel version into a separate function. Update
get_boot_protocol() to allow printing the 'Magic signature' message only
once, under control of its callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:07 +08:00
Simon Glass
30b372d419 x86: zimage: Avoid using #ifdef
Use IS_ENABLED() instead of #ifdef in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:07 +08:00
Simon Glass
e814837488 x86: zimage: Use a state struct to hold the state
At present the 'zboot' command does everything in one go. It would be
better if it supported sub-commands like bootm, so it is possible to
examine what will be booted before actually booting it.

In preparation for this, move the 'state' of the command into a struct.
This will allow it to be shared among multiple functions in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:07 +08:00
Simon Glass
6e04cb76db x86: Update the bootparam header
This header is missing a few of the newer features from the specification.
Add these as well as a link to the spec. Also use the BIT() macros where
appropriate.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:06 +08:00
Hou Zhiqiang
8ec619f8fd pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2
LX2160A rev2 uses different PCIe controller, so EP mode DT
nodes also need to be fixed up.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Kuldeep Singh
6fe7743d05 net: pfe_eth: Remove non-DM code check from pfe_spi_flash_init
CONFIG_DM_SPI_FLASH is only supported now with passing of driver
conversion deadline from non-DM to DM model. Hence, it's safe to remove
non-DM code check from pfe_spi_flash_init.

Also use CONFIG_ENV_SPI_MODE and CONFIG_ENV_SPI_MAX_HZ instead of
reading reading values from DT.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Kuldeep Singh
63d5344615 net: pfe_eth: Fix resoure leak in pfe_spi_flash_init
Fix Coverity issue: RESOURCE_LEAK.
leaked_storage: Variable addr going out of scope leaks the storage it
points to.

Fixes: e0152dbed6 ("net: pfe_eth: Use spi_flash_read API to access
flash memory")
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Wasim Khan
450d491293 arm: dts: lx2160a: Add IO range
Add IO range property to fix below error on uboot
PCI: Failed autoconfig bar 18

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Madalin Bucur
858056b0e0 driver: net: fm: add support for XFI
All the 10G ports that were working in XFI mode were described as
using XGMII (as PHY_INTERFACE_MODE_XFI was not added at the time).
Add the minimal changes required for the FMan code to support XFI.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Chaitanya Sakinam
ad8277270a ls1012a, pfe_eth: Update probe to avoid resource leak
PFE DDR addresses are now stored on to a stack varaiable rather
dynamic allocation.

Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Chaitanya Sakinam
0649ab496a ls1012a, pfe_eth: correction in delay implementation
correction in delay implementation before we exit out of tx timeout.

Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Madalin Bucur
b750695ac9 drivers: net: phy: Use Aquantia driver for AQR113C
Add support for AQR113C PHY

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Grigore Popescu
479cfd1fa6 drivers: net: ldpaa_eth: lx2160a: fix bug in checking if a DPMAC is enabled
The next DPMAC was always verified if it is enabled.  In case of
DPMAC@6, the DPMAC@7 is verified.  As DPMAC@7 is disabled, DPMAC@6 will
be considered disabled and not detected by uboot.

Signed-off-by: Grigore Popescu <grigore.popescu@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
hui.song
4e0dc38da0 armv8: dts: fsl-lx2160a: add gpio0 gpio1 gpio3 DT nodes
add gpio0 gpio1 gpio3 DT nodes to fsl-lx21600.dtsi

Signed-off-by: hui.song <hui.song_1@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Meenakshi Aggarwal
d31f3a1b62 armv8: lx2160a: fix reset sequence
Make sure that SW_RST_REQ and RST_REQ_MSK are cleared
before triggering hardware reset request.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Meenakshi Aggarwal
e5f1111a79 lx2160: Correct sd_boot environment variable
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Wasim Khan
c63edbc750 board: freescale: emc2305: Pass chip_addr to set_fan_speed
emc2305 is a common driver. It should not use platform specific
i2c address for slave device.
Pass chip_addr as agrument to emc2305_init() and set_fan_speed()
so that emc2305 driver can be used with different platforms.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Martin Kaistra
ada19fd2d2 board/freescale/lsch3: Correct entry for 0.9v
According to the reference manual of LS2088A, for a VDD voltage of
0.9V, the entry should be at 01000b.

Fixes: 4911948ec7 ("board/freescale,lsch3: Add entry for 0.9v")
Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Hou Zhiqiang
af288cb291 arm64: Layerscape: Survive LPI one-way reset workaround
The workaround of LPI one-way reset issue is broken by the series:
https://patchwork.ozlabs.org/project/uboot/list/?series=192398

This patch is to add DT node for GIC RD tables and create corresponding
reserved-memory node in kernel DT to fix it.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Ran Wang
223c19076f fsl-layerscape: enable dwc3 snooping feature
Configure DWC3’s cache type to ‘cacheable’ for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
Tom Rini
1da91d9bcd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Enable NET_RANDOM_ETHADDR on Espressobin (Acked-by Kosta)
- Espressobin & Clearfog: fdtfile enhancements
- A37xx PCI: Disable link training when unloading driver
- A37xx: increase CONFIG_SYS_BOOTM_LEN to 64MB
- Add Macronix mx25u12835f support, used on uDPU and ESPRESSObin v7
- dns325: Correct CONFIG_NR_DRAM_BANKS parameter
2020-09-24 08:34:54 -04:00
Tom Rini
67ece26d8b Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.01

arm64:
- Support for bigger U-Boot images compiled with PIE

microblaze:
- Extend support for LE/BE systems

zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode

zynqmp-r5:
- Fix MPU mapping and defconfig setting.

xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot

cmd:
- pxe: Add fixing for platforms with manual relocation support

clk:
- fixed_rate: Add DM flag to support early boot on r5

fpga:
- zynqmppl: Use only firmware interface and enable SPL build

serial:
- uartlite: Enable for ARM systems and support endians

mmc:
- zynq: Fix indentation

net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64

kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values

bindings:
- Add binding doc for vsc8531
2020-09-24 08:33:47 -04:00
Tom Rini
e119de72e3 Merge branch 'mpc85xx-for-v2021.01' into next
- Add DM_SPI, DM_SPI_FLASH support for powerpc platforms
- Add DM_ETH support on P1010RDB, P1020RDB, P2020RDB
- Remove some un-maintained powerpc platforms
- Add USB_STORAGE support in config
2020-09-24 08:30:25 -04:00
Ran Wang
893cdf0b7f configs: powerpc: add usb (host) mass storage support
commit 0cfccb5401 ("configs: Resync with savedefconfig")
removed CONFIG_USB_STORAGE from some powerpc platforms' defconfig
files, whicih would block the use case of system loading rootfs
from USB drives, add them back.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
cddffcaf4a configs: Remove P5040DS secure boot configs
Remove NXP powerpc P5040DS secure boot configs as they are
no longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
8e01439dd3 board/freescale: Remove P5020DS board support
Remove NXP powerpc P5020DS board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
d975f6a693 powerpc:Remove P4080DS secure boot configs
Remove NXP powerpc P4080DS secure boot configs as they are
no longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
c2dee50ec0 configs: Remove P3041DS secure boot configs
Remove NXP powerpc P3041DS secure boot configs as they are
no longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
63310debc9 board/freescale: Remove P1024RDB board support
Remove NXP powerpc P1024RDB board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
6d1dd76afe board/freescale: Remove P1021RDB board support
Remove NXP powerpc P1021RDB board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
53e3096cd0 board/freescale: Remove P1020MBG board support
Remove NXP powerpc P1020MBG board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
da3dd417d7 board/freescale: Remove P1020UTM board support
Remove NXP powerpc P1020UTM board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
d521cece5a board/freescale: Remove P1025RDB board support
Remove NXP powerpc P1025RDB board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
fd7331ed0d configs: Remove P1010RDB secure boot configs
Remove NXP powerpc P1010RDB secure boot configs as they are
no longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
20b1ae018f board/freescale: Remove p1023rdb board support
Remove NXP powerpc p1023rdb board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
6c9e68e860 configs: P2020RDB: Enable DM_ETH config
Enable the DM_ETH and DM_MDIO config.

On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
613e49bb91 dts: powerpc: p2020rdb: Add eTSEC DT nodes
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII switch VSC7385
    eTSEC2: Connected to SGMII PHY VSC8221
    eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
1e944259f5 configs: P1010RDB: Enable DM_ETH config
Enable the DM_ETH and DM_MDIO config.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
c5166ceb13 p1010rdb: Don't compile board_eth_init() for DM_ETH
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
4769ca67cc dts: powerpc: p1010rdb: Add eTSEC DT nodes
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII PHY AR8033
    eTSEC2: Connected to SGMII PHY AR8033
    eTSEC3: Connected to SGMII PHY AR8033

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
b1191fa8ca configs: P1020RDB: Enable DM_ETH config
Enable the DM_ETH and DM_MDIO config.

On P1020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
dfd4dfb289 p1_p2_rdb: Don't compile board_eth_init() for DM_ETH
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
247921f966 dts: powerpc: p1020rdb: Add eTSEC DT nodes
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII switch VSC7385
    eTSEC2: Connected to SGMII PHY VSC8221
    eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
993c104dbe configs: p1_p2_rdb: Add the default address of vsc7385 firmware
Add the environment 'vscfw_addr' to assign a default address for
vsc7385 firmware uploading.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
ae24d75867 fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r()
Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
5396fa62d9 mpc8xxx: Don't compile board_eth_init() for DM_ETH
The cpu_eth_init() is only used by the legacy ethernet driver framework.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
7fb568de53 net: tsec: Add the compatible string "gianfar" support
Add compatible string "gianfar" support and update the
device-tree-bindings doc.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
25a2e24e94 net: tsec: Add fixed-link PHY support
The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
b4eb9cfc09 net: tsec: convert to use DM_MDIO when DM_ETH enabled
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.

Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Reworked to fix gazerbeam config]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
16c53ce712 net: fsl_mdio: Correct the MII management register block address
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.

Fixes: 2932c5a802 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
c54f6139ed net: fsl_mdio: Change to use virtual address
Use virtual address to access the MII block registers instead
of physical address.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Vladimir Oltean
01ffe18f14 configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN
The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid
build errors, enable DM_MDIO in these boards' configs before we actually
add DM_MDIO support to tsec.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Vladimir Oltean
15c49df8d4 phy: make phy_connect_fixed work with a null mdio bus
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
f51ce945d0 configs: P1010RDB: Enable eSPI controller and SPI flash DM driver
Enable the DM_SPI and DM_SPI_FLASH in P1010RDB defconfigs except
SECBOOT defconfigs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
3f8e731599 dts: P1010RDB: Add eSPI slave DT nodes
Add DT nodes for eSPI slave device SPI flash.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
04b3821b81 dts: P1010: Add eSPI controller DT node
Add eSPI controller DT node for P1010.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
194ececc3d configs: T4240RDB: Enable ESPI driver
Enable the DM ESPI driver in T4240RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
ba2f651cfa dts: T4240RDB: Add ESPI slave device node
Add ESPI slave node for T4240RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
4f09505261 dts: T4240: Add ESPI DT nodes
Add ESPI controller DT node for T4240.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
f66833e163 configs: T2080RDB: Enable ESPI driver
Enable the DM ESPI driver in T2080RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
38572e741e dts: T2080RDB: Add ESPI slave device node
Add ESPI slave node for T2080RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
5662164406 configs: T1042D4RDB: Enable ESPI driver
Enable the DM ESPI driver in T1042D4RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
4f085f7f44 dts: T1042D4RDB: Add ESPI slave device node
Add ESPI slave node for T1042D4RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
efcba592b3 dts: T104x: Add ESPI DT nodes
Add ESPI controller DT node for T104x.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
350719c4aa configs: T1024RDB: Enable ESPI driver
Enable the DM ESPI driver in T1024RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
9ec8a585f4 dts: T1024RDB: Add ESPI slave device node
Add ESPI slave node for T1024RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
34b1c6a5f9 dts: T102x: Add ESPI DT nodes
Add ESPI controller DT node for T102x.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
ff9227b634 configs: P5040DS: Enable ESPI driver
Enable the DM ESPI driver in P5040DS defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
68de1ccc00 dts: P5040DS: Add ESPI slave device node
Add ESPI slave node for P5040DS.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
8d45082c46 dts: P5040: Add ESPI DT nodes
Add ESPI controller DT node for P5040.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
55562cb997 configs: P4080DS: Enable ESPI driver
Enable the DM ESPI driver in P4080DS defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
cbf202f3a1 dts: P4080DS: Add ESPI slave device node
Add ESPI slave node for P4080DS.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
fd54c7af0c dts: P4080: Add ESPI DT nodes
Add ESPI controller DT node for P4080.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
508121c8ef configs: P3041DS: Enable ESPI driver
Enable the DM ESPI driver in P3041DS defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
e6e00b4c59 dts: P3041DS: Add ESPI slave device node
Add ESPI slave node for P3041DS.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
e3a7239cd0 dts: P3041: Add ESPI DT nodes
Add ESPI controller DT node for P3041.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
c673942a04 configs: P2041RDB: Enable ESPI driver
Enable the DM ESPI driver in P2041RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
8cbfaf6ce9 dts: P2041RDB: Add ESPI slave device node
Add ESPI slave node for P2041RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
d4d4a3ae71 dts: P2041: Add ESPI DT nodes
Add ESPI controller DT node for P2041.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
277507369d configs: P2020RDB: Enable ESPI driver
Enable the DM ESPI driver in P2020RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
76b6db69df dts: P2020RDB: Add ESPI slave device node
Add ESPI slave node for P2020RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
c730329147 dts: P2020: Add ESPI DT nodes
Add ESPI controller DT node for P2020.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
873a033c72 configs: P1020RDB: Enable ESPI driver
Enable the DM ESPI driver in P1020RDB defconfig.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
69942590f4 dts: P1020RDB: Add ESPI slave device node
Add ESPI slave node for P1020RDB.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Xiaowei Bao
42896376e6 dts: P1020: Add ESPI DT nodes
Add ESPI controller DT node for P1020.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Chuanhua Han
2c56e7b7e7 configs: enable espi device module in T2080QDS
This patch is to enable  espi DM for T2080QDS in uboot

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Chuanhua Han
55c8760476 powerpc: dts: t2080qds: add espi slave nodes support
Add espi slave nodes  to support t2080qds.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Chuanhua Han
76eb66d80a powerpc: dts: t2080: add espi controller node support
Add espi controller node to support t2080.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Pali Rohár
5f50b88ab6 arm64: a37xx: pci: Disable link training when unloading driver
As required by PCI Express spec a delay for at least 100ms after
de-asserting PERST# signal is needed before link training is enabled.

Linux kernels prior to 5.8 version do not automatically disable link
training before de-asserting PERST# signal, therefore this requirement is
not fulfilled.

Above requirement is needed for proper detection of some Compex PCIe WiFi
cards. Otherwise Linux kernel cannot detect it.

To allow using those PCIe cards with older Linux kernel versions booted by
U-Boot compiled with U-Boot a37xx pci driver, disable link training in
U-Boot when unloading this pci driver.

Thanks to DM_FLAG_OS_PREPARE flag, U-Boot automatically unload this driver
when booting Linux kernel.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-24 10:14:06 +02:00
Tom Rini
e7e650e8bd arm: kirkwood: dns325: Correct CONFIG_NR_DRAM_BANKS parameter
Testing on a DNS-325 NAS has shown that in order for the device to work
we need to set CONFIG_NR_DRAM_BANKS to 1 and not 2.

Tested-by: Dmitry N. Kolesnikov <dk.diklab@gmail.com>
Reported-by: Dmitry N. Kolesnikov <dk.diklab@gmail.com>
Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-24 10:13:59 +02:00
Andre Heider
68e32e3443 arm: mvebu: Espressobin: Set environment variable fdtfile
Required for the generic distro mechanism.

Linux ships with 4 variants:
marvell/armada-3720-espressobin-v7-emmc.dtb
marvell/armada-3720-espressobin-v7.dtb
marvell/armada-3720-espressobin-emmc.dtb
marvell/armada-3720-espressobin.dtb

Use available information to determine the appropriate filename.

Fixes booting GRUB EFI arm64 on Fedora.

Reported-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-09-24 10:13:42 +02:00
Baruch Siach
5a3f5e61ca arm: mvebu: clearfog: don't override set fdtfile env
Only set the fdtfile environment variable when not already set.

Fixes: 867572f09e ("ARM: mvebu: clearfog: run-time selection of DT file")
Cc: Joel Johnson <mrjoel@lixil.net>
Reported-by: Andre Heider <a.heider@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Andre Heider <a.heider@gmail.com>
2020-09-24 10:13:39 +02:00
Andre Heider
073ccfab5f arm: mvebu: defconfig: espressobin: enable NET_RANDOM_ETHADDR
The hardware does not provide a MAC address. Enable this so that
network access works with just the default environment.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Konstantin Porotchkin <kostap@marvell.com>
2020-09-24 10:13:34 +02:00
Vladimir Vid
6728da5ce9 arm64: a37xx: increase CONFIG_SYS_BOOTM_LEN to 64MB
Increase max gunzip size, required for booting itb recovery images on
uDPU.

Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
[a.heider: adapt to mainline]
Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-09-24 10:13:22 +02:00
Vladimir Vid
2781c71873 mtd: spi-nor-ids: add support for Macronix mx25u12835f flash
Some of Marvell A3700 boards use mx25u12835f, specifically uDPU
and ESPRESSObin v7.

Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
[a.heider: adapt commit message to mainline]
Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-09-24 10:13:22 +02:00
Michael Walle
b7585aa9b1 pci: layerscape: Fix spurious writes and panic
The fdt_fixup_pcie_ls() scans all PCI devices and assumes that all PCI
root devices are layerscape PCIe controllers. Unfortunately, this is not
true for the LS1028A. There is one additional static PCI root complex
(this contains the networking devices) which has nothing to do with the
layerscape PCIe controllers. On recent U-Boot versions this results in
the following panic:

"Synchronous Abort" handler, esr 0x96000044
elr: 000000009602fa04 lr : 000000009602f9f4 (reloc)
elr: 00000000fbd73a04 lr : 00000000fbd739f4
x0 : 0080000002000101 x1 : 0000000000000000
x2 : 00000000fbde9000 x3 : 0000000000000001
x4 : 0000000000000000 x5 : 0000000000000030
x6 : 00000000fbdbd460 x7 : 00000000fbb3d3a0
x8 : 0000000000000002 x9 : 000000000000000c
x10: 00000000ffffffe8 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000000a2c
x14: 00000000fbb3d2cc x15: 00000000ffffffff
x16: 0000000000010000 x17: 0000000000000000
x18: 00000000fbb3fda0 x19: 0000000000000800
x20: 0000000000000000 x21: 00000001f0000000
x22: 0000000000000800 x23: 0000000000000009
x24: 00000000fbdc3c1b x25: 00000000fbdc28e5
x26: 00000000fbdcc008 x27: 00000000fbdc16e2
x28: 000000000f000000 x29: 00000000fbb3d3a0

Code: 394072a1 f94006a0 34000041 5ac00a94 (b8336814)
Resetting CPU ...

This bug already existed in former versions, but the spurious write was
never trapped, because the destination address was a valid address (by
pure luck).

Make sure the PCI root is actually one of the expected PCIe layerscape
controllers by matching its compatible string.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-23 19:33:44 +05:30
Kuldeep Singh
7679afbfe3 configs: ls1012a/ls1046a: Add CONFIG_ENV_OVERWRITE in defconfig
CONFIG_ENV_OVERWRITE disables write protection on various environment
variables like "ethaddr" and "serial".

Enable this config in LS1046A and LS1012A defconfigs. This resolves an
error while setting multiple values of "ethaddr" variable.

Before the change:
=> setenv ethaddr 00:E0:0C:00:06:0
=> setenv ethaddr 00:E0:0C:00:06:1
Error: Can't overwrite "ethaddr"
Error inserting "ethaddr" variable, errno=1

After the change:
=> setenv ethaddr 00:E0:0C:00:06:0
=> setenv ethaddr 00:E0:0C:00:06:1

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-23 19:33:44 +05:30
Mian Yousaf Kaukab
120e92d969 ls1028a: use default scan_dev_for_boot
scan_dev_for_efi is supposed to be called from scan_dev_for_boot.
However this call is missing for ls1028ardb and ls1028aqds boards. As
a result EFI boot doesn’t work. Fix this issue by removing custom
definition of scan_dev_for_boot and use the default definition
instead.

Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: andy.tang@nxp.com
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-23 19:33:43 +05:30
Michal Simek
4ab3817ff1 clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flag
fixed-rate driver is not different from clk_fixed_factor and it is required
very early in boot that's why setup flag for it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 14:29:58 +02:00
Michal Simek
fff07717ad xilinx: zynqmp-r5: Increase amount of MALLOC space
There is not enough space for early allocation. That's why increase it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 14:29:57 +02:00
T Karthik Reddy
504d179157 cmd: pxe: Add relocation to pxe_sub cmds
pxe sub commands need to be manually relocated for architectures which
enables MANUAL_RELOC as Microblaze.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-23 14:29:57 +02:00
Michal Simek
a2c87cb82a xilinx: versal: Fix compilation error when !CONFIG_NET
PXE and DHCP shouldn't be listed when commands are not enabled that's why
handle it in the same way as is done for Zynq and ZynqMP.

Fixes: ec48b6c991 ("arm64: versal: Add support for new Xilinx Versal ACAPs")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 14:29:57 +02:00
Michal Simek
e3259a700a xilinx: r5: Fix MPU setting for R5
Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a776 ("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
b76907ef90 xilinx: r5: Disable EFI loader
Xilinx ZynqMP R5 configuration is quite minimal and there is no reason to
enable EFI for it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
975bacc16e spl: Kconfig: Record proper dependency for SPL_ATF
ATF support was all the time based on FIT image support but this dependency
is not recorded anywhere.
For !SPL_FIT && SPL_ATF there is compilation error:
common/spl/spl.c: In function 'board_init_r':
common/spl/spl.c:689:26: error: 'struct spl_image_info' has no member named 'fdt_addr'
  689 |   spl_fixup_fdt(spl_image.fdt_addr);

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
7514fd3447 xilinx: Disable CONFIG_EFI_LOADER_BOUNCE_BUFFER for ZynqMP/Versal
Both SOCs shouldn't have any problem with 64bit dma accesses. Also with PIE
enabled when u-boot is placed above 4GB without any memory mapped below 4GB
address space efi_memory_init() call is failing due to missing memory node.

For this two reason disable this option for ZynqMP and Versal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
0981ef71bd mmc: zynq: Fix incorrect indentation
Trivial fix.

Fixes: d1f4e39d58 ("mmc: zynq_sdhci: Add support for SD3.0"
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
a798b8aaf3 fpga: zynqmp: Protect zynqmp_loads() for SPL
if conditions should match.

Fixes: a18d09ea38 ("fpga: zynqmp: Add secure bitstream loading for ZynqMP")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
29bd8ada52 fpga: kconfig: Rename SPL_FPGA_SUPPORT to SPL_FPGA
The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile
and zynqmp.c to simplify if/endif logic in zynqmp.c.

This change is mostly done to be able to use CONFIG_IS_ENABLED macro and
obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync.

And removing one line from Topic Miami boards which is not needed because
symbol is not enabled via Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-23 10:31:41 +02:00
Michal Simek
b7d4518eed fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macros
There is no need to use these macros because enum pm_api_id can be used
instead.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
e2572b5544 xilinx: common: Do not save fdt_blob to bss section
For SPL flow without specifying address for DT loading DTB is automatically
appended behind U-Boot code. Specifically _end symbol is used. Just behind
it there is place for bss section.
It means if early code is using static variable and there is a write to
this variable DTB file is corrupted if variable is located between DTB
start and end.
In this particular case offset of this variable from bss section start is
very small (0x40) that's why DT is currupted which breaks this boot flow.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
6cb402f38e ARM: zynqmp: Fix SPL_DM_SPI dependencies
Add missing dependencies for DM_SPI_FLASH.
Kconfig reports it as:
WARNING: unmet direct dependencies detected for SPL_DM_SPI_FLASH
  Depends on [n]: SPL [=n] && SPL_DM [=n]
  Selected by [y]:
  - ARCH_ZYNQMP [=y] && <choice> && SPL_DM_SPI [=y]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
c3f1eaa32d arm64: versal: Generate position-independent pre-relocation code
Enable position independent pre-relocation to let users options to put
u-boot to different locations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
1025bd098a xilinx: zynqmp: Add support for saving variables
Enabling saving variables to MMC(FAT), NAND, SPI based on primary bootmode.
Maybe that logic can be tuned for more complicated use cases and better
tested for different bootmodes.

Tested on zcu104 to SD(FAT) and JTAG(NOWHERE).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
4d9bc795ae xilinx: zynqmp: Get zynqmp_get_bootmode() out of CONFIG_BOARD_LATE_INIT
This function will be also used by different code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
ced4d46626 xilinx: zynqmp: Remove one static variable
There is no reason to have name variable saved in BSS section when it
doesn't need to be really used. That's why remove static from variable
definition and use strdup() to duplicate string with exact size from malloc
area instead.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
e17c5ec8e1 xilinx: zynqmp: Add missing 43/46/47dr ID codes
Add support for 43/46/47dr devices.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Ibai Erkiaga
fa793165da xilinx: zynqmp: refactor silicon name function
Current algorithm used to get the silicon name is bit complicated and
hard to follow. Updated to use more straightforward mechanism based on
the Device ID code table (Table 1-2). The full IDCODE register is used
(except device revision bits [31:28]) to get the device name and IDCODE2
value is used for identifying the variant.

Additionally to make the algorithm bit more clear it also save some space
as the devices table is slightly bit smaller.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Ashok Reddy Soma
2783e02da8 xilinx: versal: Enable AXI ethernet driver
Enable AXI ethernet driver for Versal platforms.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Ashok Reddy Soma
315a3c3377 net: xilinx: axi_emac: Typecast flush_cache arguments
flush_cache() arguments are not type casted to take care of 64 bit
systems. Use phys_addr_t to type cast for it to work properly for 32 bit
and 64 bit systems.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2020-09-23 10:31:40 +02:00
Ashok Reddy Soma
f9d3b31883 net: xilinx: axi_emac: Fix dma descriptors for 64bit and compilation warnings
There are compilation warnings showing up when we compile AXI ethernet
driver for 64bit architectures. Fix them, so that it works on both 32
and 64 bit architectures.

DMA descriptors are not taking care of 64bit addresses. To fix it,
change axidma_bd members as below:

next		==>	next_desc
reserverd1	==>	next_desc_msb
phys		==>	buf_addr
reserverd2	==>	buf_addr_msb

and update next_desc and buf_addr with lower 32 bits of the addresses,
update next_desc_msb and buf_addr_msb with upper 32 bits of the 64bit
addresses.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2020-09-23 10:31:40 +02:00
Harini Katakam
abe450322e include: dt-bindings: Add MSCC header
Add MSCC header with delay definitions for VSC8531 and associated
family devices.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
96a60c03b9 arm64: zynqmp: Change bl2_plat_get_bl31_params() guarding
It was protected just for SPL_OS_BOOT but this function is only called when
SPL_ATF is enabled that's why change macro name.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
a253092d49 nand: Kconfig: Change dependency for NAND_ARASAN
NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with
!DM that's why Kconfig it showing it as error:

WARNING: unmet direct dependencies detected for DM_MTD
  Depends on [n]: DM [=n]
  Selected by [y]:
  - NAND_ARASAN [=y] && MTD_RAW_NAND [=y]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-09-23 10:31:40 +02:00
Saeed Nowshadi
ed6d31c8a6 arm64: zynqmp: Correct value of shunt resistor for VCCINT and VCC_SOC
Value of shunt resistor for INA226s that monitor VCCINT and VCC_SOC power
rails are incorrect.  This patch corrects those values.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
2020-09-23 10:31:40 +02:00
Saeed Nowshadi
02abe1fbf3 arm64: zynqmp: Add device tree node for 2nd mux on I2C1 bus
There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1
ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and
channel 2 is connected to J288 connector for QSFP1.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
T Karthik Reddy
276504ed3e xilinx: Enable uartlite driver for Versal/ZynqMP
Add CONFIG_XILINX_UARTLITE config to versal/zynqmp defconfig to
enable uartlite driver support by default.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
T Karthik Reddy
31a359f87e serial: uartlite: Add support to work with any endianness
This endinness changes are taken from linux uartlite driver.
Reset TX fifo in control register and check TX fifo empty
flag in lower byte of the status register to detect if it
is a little endian system. Based on this check, program the
registers with le32 or be32 through out the driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Ashok Reddy Soma
592ac77342 configs: xilinx: Enable configs required for ubifs
Enable required configs for using ubifs in uboot.

UBIFS testing procedure from u-boot:
Let's say we have two partitions in dt as below and want to format
partition1 "images" with ubifs.

	partition@0 {
		label = "boot";
		reg = <0x0 0x1000000>;
	};

	partition@1 {
		label = "images";
		reg = <0x1000000 0x7000000>;
	};

We will format the partition from linux and copy some files and access
from uboot later.
First thing, in linux config disable CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
this is required as ubifs expects min LEB size as 15*1024 bytes.

Use below commands in linux to format "images" partition with ubifs.

ubiformat /dev/mtd1
ubiattach /dev/ubi_ctrl -m 1
ubimkvol /dev/ubi0 -N images -m
mount -t ubifs ubi0:images /mnt

We can copy files to /mnt and unmount it.

To access this ubifs partition from uboot, run below commands.
(Don't forget to probe device before, e.g. sf probe 0 0 0)

setenv mtdids "nor0=nor0"
setenv mtdparts "mtdparts=nor0:16m(boot),112m(images)"
ubi part images
ubifsmount ubi0:images

make sure we match "mtdparts" to whatever is given in dt w.r.t partition
sizes.

"mtdparts" command will list the mtd partitions in u-boot.

Once ubifs is mounted, we can use "ubifsls" to list the files in that
partition and use "ubifsload <addr> <filename>" to load files from ubifs
partition to DDR.

Reading information about mtd layout from DT is not supported.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
T Karthik Reddy
78d844c6ac microblaze: Add support for little/big endian in/out api's
Add read/write memory utilities for 16 and 32 bits. Add these
api's for both little and big endian systems similar to arm
architecture.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
1a005b4ae4 board: xilinx: Enable changing default DTB pick up address
U-Boot on xilinx boards is checking one address where DTB can be placed as
the first location for DTB. Originally this code was developed for Versal
where QEMU was putting generated DTB for U-Boot to use.
The patch enables changing this address which is necessary for cases where
default address is pointing to location (DDR) which is not present. The
access to this location can cause exception.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
6ba36c0e59 xilinx: kconfig: Move sourcing of board Kconfig to mach folders
Do not source xilinx board Kconfig by other boards. These configs should be
available only when Xilinx platforms are selected.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
54fdef242f xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers
Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in
PL and vice versa. That's why change dependencies and do not limit enabling
just for some platforms.

This is follow up patch based on commit 664e16ce99 ("xilinx: kconfig:
Change Kconfig dependencies for Xilinx drivers").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
7fa8d5e0ee env: kconfig: Add default option for ARCH_ZYNQ
Zynq is similar to ZynqMP u-boot feature wise that's why also enable
default option for ENV_FAT_DEVICE_AND_PART Kconfig entry.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
8c40e07aab net: gem: Add support for more PHYs on MDIO bus
Find out MDIO bus and enable MDIO access to it if this is done via
different GEM controller. Only works across GEM instances.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
6c0e59fcd9 xilinx: drivers: Use '_' instead of '-' in driver name
The most of drivers are using '_' instead of '-' in driver name. That's why
sync up these names to be aligned. It looks quite bad to see both in use.
It is visible via dm tree command.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-23 10:31:40 +02:00
Tom Rini
55004fa433 Merge tag 'mips-fixes-for-2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips
- mips: vocore2: fix SPL image generation
- mips: vocore2: fix LZMA decompression errors
- mips: vocore2: fix console output
- mips: pic32mzda: fix DTC warnings and GPIO nodes
- mips: pic32mzda: make GPIO and MMC working again
2020-09-22 22:08:16 -04:00
Mauro Condarelli
7d1538cc9b mips: vocore2: fix various issues
- fix SPL image generation
- fix incorrect console output
- increase malloc_f and malloc_r space to fix LZMA decompression errors
- increase SPI flash clock

Signed-off-by: Mauro Condarelli <mc5686@mclink.it>
[squashed to one patch, fix commit subject and description]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-09-23 00:14:56 +02:00
John Robertson
bd25f9a69f mips: dts: Fix PIC32MZDA GPIO register definitions
The GPIO bank name for banks J and K are not correct when using the
'gpio' command from the console.

The driver derives the bank name from the device tree instance string by
using the instance value and adding 'A': gpio0@xxaddrxx is Bank A,
gpio1@yyaddryy is Bank B and so on.

On the PIC32, there is no Bank I so instances 8 and 9 need to be
incremented as a minimum change.

An alternative (less opaque) implementation would be to use a bank-name
property instead but this would require modifying the driver code too.

Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23 00:14:29 +02:00
John Robertson
81b543a4e6 mips: dts: Fix PIC32MZDA GPIO register definitions
GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or
using the 'gpio' command from the console.

The root cause is a discrepancy between the driver and the device tree:
the driver code expects an absolute I/O address in the <reg> property,
while the device tree defines the address relative to a declaration in
the parent pinctrl node.

Changing the device tree to fix a driver issue would normally be wrong,
however:
- I have run the first version of U-Boot in which this driver appears
  (v2016.03) and the same problem exists, so this is not a regression;
- There is no code that references a parent device tree node that might
  suggest the intent of the author was to parse the DT as it exists now;
- The equivalent Linux PIC32 GPIO driver also uses absolute addresses
  for the GPIO <reg> property. This change brings the U-Boot DT more
  into line with Linux.

Additionally, the data sheet (Microchip ref. 60001361H) shows that the
register set to control a GPIO bank spans 0xE0 bytes, but the device
tree specified size is only 0x48 bytes.

Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23 00:14:28 +02:00
John Robertson
0723c2ddeb mips: dts: Fix device tree warnings for PIC32MZDA
Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23 00:14:28 +02:00
John Robertson
95e7141294 mips: pic32mzdask: enable CONFIG_BLK
CONFIG_BLK needs to be enabled by default to allow U-Boot to
compile after a 'make pic32mzdask_defconfig'.

Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23 00:14:21 +02:00
John Robertson
69af033fb9 mips: pic32mzdask: disable SDHCI SDCD signal workaround
The PIC32MZ DA Starter Kit does not need the card detect workaround
because the SDCD signal line is connected properly. Disable the
workaround in this case.

Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23 00:14:14 +02:00
John Robertson
10d65bf00b pinmux: pic32: add SDHCI pin config
The GPIO pins used by the SDHCI controller need to be configured to
allow the interface to work.

Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23 00:08:52 +02:00
John Robertson
6978db36aa mmc: pic32: Refresh PIC32 MMC driver
The existing driver is not compatible with the Driver Model.

This patch makes the necessary changes while also removing obsolescent
calls/properties as follows:

- fdtdec_* calls replaced with dev_read_* equivalents;
- 'clock-freq-min-max' property replaced by querying the frequency of
  the source clock 'base_clk';
- The card detect erratum workaround is applied during probe rather than
  overriding get_cd.

The card detect workaround (Microchip ref. DS80000736E, erratum #15) is
not always needed and can be disabled using a vendor specific DT
property.

Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23 00:08:52 +02:00
Tom Rini
3c1e6a6c23 Merge tag 'dm-pull-22sep20' of git://git.denx.de/u-boot-dm into next
binman enhancements for FIT
sunxi64 conversion to use binman
New 'no-map' property for reserved memory
2020-09-22 16:59:48 -04:00
Tom Rini
5949f36f08 Merge branch '2020-09-22-assorted-bugfixes'
- Fix for environment location on some PowerPC boards
- Typo / documentation fix
- Two fixes for mpc8xxx
2020-09-22 16:47:48 -04:00
Heinrich Schuchardt
e5b35f706d log: mute messages generated by log drivers
When a message is written by a log driver (e.g. via the network stack) this
may result in the generation of further messages. We cannot allow these
additional messages to be emitted as this might result in an infinite
recursion.

Up to now only the syslog driver was safeguarded. We should safeguard all
log drivers instead.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Patrick Delaunay
01d89e3d12 dm: add cells_count parameter in live DT APIs of_parse_phandle_with_args
In the live tree API ofnode_parse_phandle_with_args, the cell_count
argument must be used when cells_name is NULL.

But this argument is not provided to the live DT function
of_parse_phandle_with_args even it is provided to
fdtdec_parse_phandle_with_args.

This patch adds support of the cells_count parameter in dev_ and
of_node API to allow migration and support of live DT:
- of_parse_phandle_with_args

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Etienne Carriere
3e15c315f9 optee: add property no-map to secure reserved memory
OP-TEE reserved memory node must set property "no-map" to prevent
Linux kernel from mapping secure memory unless what non-secure world
speculative accesses of the CPU can violate the memory firmware
configuration.

Fixes: 6ccb05eae0 ("image: fdt: copy possible optee nodes to a loaded devicetree")
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2020-09-22 12:54:13 -06:00
Patrice Chotard
6613ed1e07 test: fdtdec: Add test for new no-map fdtdec_add_reserved_memory() parameter
Add a test to verify that the no-map property is added in reserved-memory
node when fdtdec_add_reserved_memory() no-map parameter is set to true.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Etienne Carriere
ccaa5747bd fdtdec: optionally add property no-map to created reserved memory node
Add boolean input argument @no_map to helper function
fdtdec_add_reserved_memory() to add or not "no-map" property
for an added reserved memory node.

Property no-map is used by the Linux kernel to not not map memory
in its static memory mapping. It is needed for example for the|
consistency of system non-cached memory and to prevent speculative
accesses to some firewalled memory.

No functional change. A later change will update to OPTEE library to
add no-map property to OP-TEE reserved memory nodes.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Simon Glass
68de0679c9 binman: sunxi: Add help message for missing sunxi ATF BL31
Add a special help message pointing to the relevant README.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Simon Glass
b238143db9 binman: Support help messages for missing blobs
When an external blob is missing it can be quite confusing for the user.
Add a way to provide a help message that is shown.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2020-09-22 12:54:13 -06:00
Simon Glass
c0f1ebe9c1 binman: Allow selecting default FIT configuration
Add a new entry argument to the fit entry which allows selection of the
default configuration to use. This is the 'default' property in the
'configurations' node.

Update the Makefile to pass in the value of DEVICE_TREE or
CONFIG_DEFAULT_DEVICE_TREE to provide this information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:54:13 -06:00
Alper Nebi Yasak
4ec40a7208 binman: Document how CROSS_COMPILE, CC, HOSTCC etc. are used in README
Explain that binman interprets these environment variables in the
"External tools" section to run target/host specific versions of the
tools, and add a new section on how to use CROSS_COMPILE to run the
tests on non-x86 machines.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Alper Nebi Yasak
29cc091842 binman: Allow resolving host-specific tools from env vars
This patch lets tools.Run() use host-specific versions with the
for_host keyword argument, based on the host-specific environment
variables (HOSTCC, HOSTOBJCOPY, HOSTSTRIP, etc.).

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Alper Nebi Yasak
1e4687aa47 binman: Use target-specific tools when cross-compiling
Currently, binman always runs the compile tools like cc, objcopy, strip,
etc. using their literal name. Instead, this patch makes it use the
target-specific versions by default, derived from the tool-specific
environment variables (CC, OBJCOPY, STRIP, etc.) or from the
CROSS_COMPILE environment variable.

For example, the u-boot-elf etype directly uses 'strip'. Trying to run
the tests with 'CROSS_COMPILE=i686-linux-gnu- binman test' on an arm64
host results in the '097_elf_strip.dts' test to fail as the arm64
version of 'strip' can't understand the format of the x86 ELF file.

This also adjusts some command.Output() calls that caused test errors or
failures to use the target versions of the tools they call. After this,
patch, an arm64 host can run all tests with no errors or failures using
a correct CROSS_COMPILE value.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Alper Nebi Yasak
5ac7687827 binman: Support cross-compiling test files to x86
These test files are currently "intended for use on x86 hosts", but most
of the tests using them can still pass when cross-compiled to x86 on an
arm64 host.

This patch enables non-x86 hosts to run the tests by specifying a
cross-compiler via CROSS_COMPILE. The list of variables it sets is taken
from the top-level Makefile. It would be possible to automatically set
an x86 cross-compiler with a few blocks like:

    ifneq ($(shell i386-linux-gnu-gcc --version 2> /dev/null),)
    CROSS_COMPILE = i386-linux-gnu-
    endif

But it wouldn't propagate to the binman process calling this Makefile,
so it's better just raise an error and expect 'binman test' to be run
with a correct CROSS_COMPILE.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Heinrich Schuchardt
36da81e0c1 dm: syscon: typo alerady
* Fix typo: %s/alerady/already/.
* Add missing 'the'.
* Reformat a comment.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Alper Nebi Yasak
76de29fc4f buildman: Use git worktrees instead of git clones when possible
This patch makes buildman create linked working trees instead of clones
of the source repository, but keeps updating the older clones of the
repository that might already exist. These worktrees share "everything
except working directory specific files such as HEAD, index, etc." with
the source repository. See the git-worktree(1) manual page for more
information.

If git-worktree isn't available, silently falls back to cloning the
repository.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
f5bbd9a3a6 sunxi: Drop the FIT-generator script
This file is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
cfa3db602c sunxi: Convert 64-bit boards to use binman
At present 64-bit sunxi boards use the Makefile to create a FIT, using
USE_SPL_FIT_GENERATOR. This is deprecated.

Update sunxi to use binman instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-22 12:50:43 -06:00
Simon Glass
bd4d0dcb27 Makefile: Support missing external blobs always
At present binman warns about missing external blobs only when the
BUILD_ROM is defined. Enable this behaviour always, since many boards
are starting to use these (e.g. ARM Trusted Firmware's BL31).

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
6cf9953bfb binman: Support generating FITs with multiple dtbs
In some cases it is useful to generate a FIT which has a number of DTB
images, selectable by configuration. Add support for this in binman,
using a simple iterator and string substitution.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
dc2f81a2c8 binman: Add support for ATF BL31
Add an entry for ARM Trusted Firmware's 'BL31' payload, which is the
device's main firmware. Typically this is U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
8795898a53 binman: Move 'external' support into base class
At present we have an Entry_blob_ext which implement a blob which holds an
external binary. We need to support other entry types that hold external
binaries, e.g. Entry_blob_named_by_arg. Move the support into the base
Entry class to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
211cfa503f libfdt: Detected out-of-space with fdt_finish()
At present the Python sequential-write interface can produce an error when
it calls fdt_finish(), since this needs to add a terminating tag to the
end of the struct section.

Fix this by automatically expanding the buffer if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
e9d336d866 binman: Fix up a few missing comments
Tidy up a few test functions which lack argument comments. Rename one that
has the same name as a different test.

Also fix up the comment for PrepareImagesAndDtbs().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
3decfa3a87 binman: Allow entry args to be required
If an entry argument is needed by an entry but the entry argument is not
present, then a strange error can occur when trying to read the file.

Fix this by allowing arguments to be required. Select this option for the
cros-ec-rw entry. If a filename is provided in the node, allow that to be
used.

Also tidy up a few related tests to make the error string easier to find,
and fully ignore unused return values.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Walter Lozano
dc447b6b3f core: improve of_match_ptr with OF_PLATDATA
Currently of_match_ptr is used to avoid referencing compatible strings
when OF_CONTROL is not enabled. This behaviour could be improved by
taking into account also OF_PLATDATA, as when this configuration is
enabled the compatible strings are not used at all.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
2b522f1e79 tools: Drop unnecessary use of __file__
There are few places where the path of the current modules is calculated
but not used. Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
9fbfaba0a7 binman: Use pkg_resources to find resources
At present we look for resources based on the path of the Python module
that wants them. Instead we should use Python's pkg_resources feature
which is designed for this purpose.

Update binman to use this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Alper Nebi Yasak
fe05701b05 binman: Build FIT image subentries with the section etype
When reading subentries of each image, the FIT entry type directly
concatenates their contents without padding them according to their
offset, size, align, align-size, align-end, pad-before, pad-after
properties.

This patch makes sure these properties are respected by offloading this
image-data building to the section etype, where each subnode of the
"images" node is processed as a section. Alignments and offsets are
respective to the beginning of each image. For example, the following
fragment can end up having "u-boot-spl" start at 0x88 within the final
FIT binary, while "u-boot" would then end up starting at e.g. 0x20088.

	fit {
		description = "example";

		images {
			kernel-1 {
				description = "U-Boot with SPL";
				type = "kernel";
				arch = "arm64";
				os = "linux";
				compression = "none";

				u-boot-spl {
				};
				u-boot {
					align = <0x10000>;
				};
			};
		};
	}

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reinstate check in testPadInSections(), squash in
   "binman: Allow FIT binaries to have missing external blobs"
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2020-09-22 12:50:43 -06:00
Alper Nebi Yasak
3fdeb14d95 binman: Respect pad-before property of section subentries
Other relevant properties (pad-after, offset, size, align, align-size,
align-end) already work since Pack() sets correct ranges for subentries'
data (.offset, .size variables), but some padding here is necessary to
align the data within this range to match the pad-before property.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Alper Nebi Yasak
8001d0b162 binman: Ignore hash*, signature* nodes in sections
Switch to str.startswith for matching like the FIT etype does since the
current version doesn't ignore 'hash-1', 'hash-2', etc.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Chris Packham
dc8368b7ee configs: powerpc: Don't set CONFIG_ENV_ADDR for QorIQ SPIFLASH
Setting CONFIG_ENV_ADDR to something other than 0 stops gd->env_addr
from being allocated dynamically. When the environment is in SPI we need
it to be allocated as we can't use a direct memory mapped address.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2020-09-22 11:26:19 -04:00
Heinrich Schuchardt
643b5e7ea3 disk: typo Terra Bytes
512 * 2^32 bytes equals 2 tebibytes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:26:19 -04:00
Heinrich Schuchardt
4061191727 doc/build/gcc.rst: add missing apt-get *install*
The install command is missing for an apt-get command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-22 11:05:32 -04:00
Rasmus Villemoes
24e8c0e3b3 gpio/mpc83xx_spisel_boot.c: include log.h
Fix build failure, it used to get this implicitly through common.h
until f7ae49fc4f (common: Drop log.h from common header).

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-09-22 11:05:32 -04:00
Rasmus Villemoes
10a6aa963c spi: mpc8xxx_spi.c: fix cs activate/deactivate
Somewhere between v2020.04 and v2020.07 the mpc8xxx_spi driver broke,
I'm guessing due to this hunk

@@ -559,6 +560,8 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
        if (ret)
                return ret;

+       /* combine the requested flags (for IN/OUT) and the descriptor flags */
+       flags |= desc->flags;
        ret = _dm_gpio_set_dir_flags(desc, flags);

from commit 695e5fd546 ("gpio: update dir_flags management"). But
the blame is mostly on the driver itself which seems rather confused:
The chip select gpios are requested with GPIOD_ACTIVE_LOW, but then in
each activate/deactivate, dm_gpio_set_dir_flags() is called with
merely GPIOD_IS_OUT, and then the driver call set_value(0) for
activate.

That used to work, but with the above hunk, the ACTIVE_LOW setting
from the request becomes persistent, so the gpio driver ends up being
asked to set the value to 1 in mpc8xxx_spi_cs_activate().

So drop the dm_gpio_set_dir_flags() calls in the activate/deactivate
functions, and use a value of 1 to mean "logically enabled".

Ideally, I think we should also drop the GPIOD_ACTIVE_LOW from the
request and make it up to the list of gpio cs in DT to indicate
whether that CS is enabled when driven low (as is of course usually
the case), but that requires changing
arch/powerpc/dts/gdsys/gazerbeam-base.dtsi among others, and I don't
have that hardware to test on. I have, however, tested our
own (mpc8309-based) hardware with this change, and I have also tested
that removing the GPIOD_ACTIVE_LOW from the request and updating our
DT as

-                       gpios = <&spisel 0 0>;
+                       gpios = <&spisel 0 GPIO_ACTIVE_LOW>;

still works.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-09-22 11:05:32 -04:00
Edgar E. Iglesias
28c851f128 arm64: Add support for larger PIE U-Boot
Linking a U-Boot larger than 1MB fails with PIE enabled:
u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end'
defined in .bss_start section in u-boot.

This extends the supported range by using adrp & add to load symbols
early while starting up.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Edgar E. Iglesias
04d13b5d09 arm64: Trap PIE builds early if load address is not 4K aligned
PIE requires a 4K aligned load address. If this is not met, trap
the startup sequence in a WFI loop rather than running into obscure
failures.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: André Przywara <andre.przywara@arm.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Edgar E. Iglesias
11f4fbf0d4 arm64: Mention 4K aligned load addresses in the PIE Kconfig help
Mention the requirement of 4K aligned load addresses in the
help section for the POSITION_INDEPENDENT option.

Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Eugen Hristev
919c4f3639 ARM: at91: common: guard ATMEL_PIT code by ifdef
Atmel PIT timer is not available for next products that
have another timer hardware block.
To be able to use the common at91 code, guard the code that uses PIT
by ifdefs.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-22 11:27:18 +03:00
Eugen Hristev
68d3ec599e board: atmel: common: introduce at91_set_eth1addr for second interface
We already have a function to retrieve the mac address from one EEPROM.
For boards with a second Ethernet interface, however, we would
require another EEPROM with a second unique MAC address.
Introduce at91_set_eth1addr which will look for a second EEPROM
and set the 'eth1addr' variable with the obtained MAC address.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
6a6fe3ed4d clk: at91: sama7g5: add clock support
Add clock support for SAMA7G5.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
7b7e226739 clk: at91: pmc: add generic clock ops
Add generic clock ops to be used by every AT91 PMC driver
built on top of CCF.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
36a9630fcb clk: at91: clk-generic: add driver compatible with ccf
Add clk-generic driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
f89268e468 clk: at91: clk-peripheral: add driver compatible with ccf
Add clk-peripheral compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
16502bfa7c clk: at91: clk-system: add driver compatible with ccf
Add clk-system driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
2a1a579bde clk: at91: clk-programmable: add driver compatible with ccf
Add clk-programmable driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
0341733570 clk: at91: clk-utmi: add support for sama7g5
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
ad4d39a964 clk: at91: clk-utmi: add driver compatible with ccf
Add clk-utmi driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
dd4d19ddfb clk: at91: clk-master: add support for sama7g5
Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
b4c4e18dbd clk: at91: clk-master: add driver compatible with ccf
Add clk-master driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
e6547a6d0c clk: at91: sam9x60-pll: add driver compatible with ccf
Add sam9x60-pll driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
f1218f0b4f clk: at91: clk-main: add driver compatible with ccf
Add clk-main driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
e9885aa7cc clk: at91: sckc: add driver compatible with ccf
Add sckc driver compatible with common clock framework. Driver
implements slow clock support for SAM9X60 compatible IPs (in this
list it is also present SAMA7G5's slow clock IP).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
653bcce408 clk: at91: move clock code to compat.c
Move clock code to compat.c to allow switching to CCF
without mixing CCF code with non CCF code. This prepares the
field for next commits.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
5d729f9629 clk: at91: pmc: add helpers for clock drivers
Add helper for clock drivers. These will be used by following
commits in the process of switching AT91 clock drivers to CCF.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
643966a8fa clk: at91: add pre-requisite headers for AT91 clock architecture
Add pre-requisite headers for AT91 clock architecture. These
are based on already present files on Linux and will be used
by following commits for AT91 CCF clock drivers.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
b364134f87 clk: get clock pointer before proceeding
clk_get_by_indexed_prop() retrieves a clock with dev member being set
with the pointer to the udevice for the clock controller driver. But
in case of CCF each clock driver has set in dev member the reference
to its parent (the root of the clock tree is a fixed clock, every
node in clock tree is a clock registered with clk_register()). In this
case the subsequent operations like dev_get_clk_ptr() on clocks
retrieved by clk_get_by_indexed_prop() will fail. For this, get the
pointer to the proper clock registered (with clk_register()) using
clk_get_by_id() before proceeding.

Fixes: 1d7993d1d0 ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
9a5d59dfc6 clk: do not disable clock if it is critical
Do not disable clock if it is a critical one.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
4d139f3838 clk: bind clk to new parent device
Clock re-parenting is not binding the clock's device to its new
parent device, it only calls the clock's ops->set_parent() API. The
changes in this commit re-parent the clock device to its new parent
so that subsequent operations like clk_get_parent() to point to the
proper parent.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
cfecbaf4e7 dm: core: add support for device re-parenting
In common clock framework the relation b/w parent and child clocks is
determined based on the udevice parent/child information. A clock
parent could be changed based on devices needs. In case this is happen
the functionalities for clock who's parent is changed are broken. Add
a function that reparent a device. This will be used in clk-uclass.c
to reparent a clock device.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
b04da9fcf7 clk: check hw and hw->dev before dereference it
Check hw and hw->dev before dereference it.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Tom Rini
2512b3b88b Merge branch '2020-09-14-generic-phy-error-trace' into next
- Add error tracing messages to the generic PHY infrastructure
2020-09-21 16:44:16 -04:00
Tom Rini
751b18b8a1 Merge branch 'master' into next
Merge in v2020.10-rc5
2020-09-21 14:25:37 -04:00
Tom Rini
ba2a0cbb05 Prepare v2020.10-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-21 13:45:23 -04:00
Tom Rini
d6b241bcd7 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-21 13:45:07 -04:00
Tom Rini
10431c4eaa Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Several ACPI bug fixes
- Intel edison: Move config SYS_MALLOC_LEN to Kconfig
- Use "emmc" in ApolloLake FSP devicetree bindings
2020-09-21 11:01:07 -04:00
Wolfgang Wallner
40edea3a07 x86: acpi: Add memset to initialize SPCR table
Add a missing memset to acpi_create_spcr().

The other acpi_create_xxxx() functions perform a memset on their
structures, acpi_create_spcr() does not and as a result the contents of
this table are partly uninitialized (and thus random after every reset).

Fixes: b288cd9600 ("x86: acpi: Generate SPCR table")
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix the tags format in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-21 16:41:36 +08:00
Wolfgang Wallner
3f6966ab2b x86: acpi: Fix calculation of DSDT length
Currently, the calculation for the length of the DSDT table includes any
bytes that are added for alignment, but those bytes are not initialized.

This is because the DSDT length is calculated after a call to
acpi_inc_align(). Split this up into the following sequence:

  * acpi_inc()
  * Calculate DSDT length
  * acpi_align()

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-21 16:41:35 +08:00
Wolfgang Wallner
674c58c7b7 x86: fsp: Replace e-mmc with emmc in devicetree bindings
The term eMMC is used inconsistently within the FSP devicetree
bindings (e-mmc and emmc), especially for "emmc-host-max-speed"
documentation and code disagree.

Change all eMMC instances within the FSP bindings to consistently
use "emmc". The term "emmc" is already used a lot within U-Boot,
while "e-mmc" is only used in the FSP bindings.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct one typo in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-21 16:41:35 +08:00
Andy Shevchenko
4364a3f852 cmd: acpi: Print revisions in hex format
The revisions are usually dates in hex-decimal format representing
YYYYmmdd. Print them in hex to see this clearly.

Before:
  ...
  FACP 000e5420 0000f4 (v06 U-BOOT U-BOOTBL 538970376 INTL 0)
  DSDT 000e4780 000ba0 (v02 U-BOOT U-BOOTBL 65536 INTL 538968870)
  ...
After:
  ...
  FACP 000e5420 0000f4 (v06 U-BOOT U-BOOTBL 20200908 INTL 0)
  DSDT 000e4780 000ba0 (v02 U-BOOT U-BOOTBL 10000 INTL 20200326)
  ...

Fixes: 0b885bcfd9 ("acpi: Add an acpi command")
Cc: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-21 16:41:35 +08:00
Andy Shevchenko
5a53441a91 x86: edison: Move config SYS_MALLOC_LEN to Kconfig
This patch moves the the config SYS_MALLOC_LEN to Kconfig
as it is already done for zynq arch in commit 01aa5b8f05
("Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq").

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-21 09:47:24 +08:00
Tom Rini
400f84c5ba Merge tag 'efi-2020-10-rc5-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc5 (2)

The following bugs are fixed:

* incorrect online help for setenv and env
* description of function efi_mem_carve_out()
* replace printf() by log_err() in stm32mp1_rng driver

A unit test is provided to check that the boot hart id is provided in the
RISC-V device-tree.
2020-09-19 08:35:20 -04:00
Tom Rini
667ab37d58 Merge branch '2020-09-18-assorted-bugfixes'
- SquashFS Coverity fixes
- bitflip fix in the alternate memtest command
- Disable networking on bcmstb boards where we didn't have any network
  drivers enabled.
2020-09-19 08:31:52 -04:00
Tom Rini
3bacb5ee76 Merge branch '2020-09-18-improve-ipq40xx-support' into next
- Assorted improvements to the Qualcomm IPQ40XX SoC
2020-09-19 08:30:54 -04:00
Maxim Uvarov
8f0ac536d4 efi: change 'env -e -i' usage syntax
'env -e -i' syntax was changed from "," to ":". Account for this also
in the documentation.

Fixes: 2b3fbcb59f ("efi_loader: use ':' as separator for setenv -i")
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Correct the usage description for setenv -e too.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-18 22:23:58 +02:00
Heinrich Schuchardt
52a8481827 efi_selftest: check for RISC-V boot-hartid in FDT
On RISC-V check that the /chosen node has a boot-hartid property.

To run the test configure with CONFIG_CMD_BOOTEFI_SELFTEST=y and issue

    setenv efi_selftest device tree
    setenv serial# myserial
    bootefi selftest

If the test succeeds, it reports the boot-hartid, e.g.

    boot-hartid: 1

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-18 22:23:58 +02:00
Heinrich Schuchardt
18161a8a4e efi_selftest: rework device tree test
Allow specifying the node on which a property is searched.
Test the device tree consistency more rigorously.
Some efi_st_printf() calls have been converted to efi_st_error().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-18 22:23:58 +02:00
Maxim Uvarov
ffbeafe7e2 efi_memory: refine overlap_only_ram description
Refine text for overlap_only_ram description to
match to what exactly flag does and aling description
with other functions.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-18 22:23:58 +02:00
Heinrich Schuchardt
cf0bf89227 rng: stm32mp1: use log() instead of printf()
The logging system provides flexible filtering and enhanced output.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2020-09-18 22:23:58 +02:00
Robert Marko
430e1dcfa4 IPQ40xx: Add USB nodes
There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
74a703a8ad usb: dwc3: Add Qualcomm DWC3 compatible string
Lot of Qualcomm SoC-s use DWC3 controller for both USB2.0 and USB3.0
ports.
Qualcomm has some custom config registers on top of the generic ones,
but for host mode these are not needed.

So lets add the neccessary compatible string.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
dec042028e phy: add driver for Qualcomm IPQ40xx USB PHY
Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs.
The driver sets up HS and SS phys.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
496a3aa5ff IPQ40xx: Add reset controller support
Since we have a driver for the reset controller, lets add the necessary node.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
8ef7df5df3 reset: Add IPQ40xx reset controller driver
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
6ef099b29e IPQ40xx: Add SMEM support
There is already existing driver for SMEM so lets enable it for IPQ40xx as well.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
5ae15415c1 IPQ40xx: clk: Use dt-bindings instead of hardcoding
Its common to use dt-bindings instead of hard-coding clocks or resets.
So lets use the imported Linux GCC bindings on IPQ40xx target.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Ralph Siemsen
9989fb18bd cmd: mem: fix range of bitflip test
The bitflip test uses two equal sized memory buffers. This is achieved
by splitting the range of memory into two pieces. The address of the
second buffer, as well as the length of each buffer, were not correctly
calculated. This caused bitflip test to access beyond the end of range.
This patch fixes the pointer arithmetic problem.

A second problem arises because u-boot "mtest" command expects the
ending address to be inclusive. When computing (end - start) this
results in missing 1 byte of the requested length. The bitflip test
expects a count rather than an "ending" address. Thus it fails to test
the last word of the requested range. Fixed by using (end - start + 1).

Added Kconfig option to optionally disable the bitflip test, since it
does add significantly to the time taken for "mtest".

Fixes: 8e434cb705 ("cmd: mem: Add bitflip
memory test to alternate mtest")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-18 16:19:58 -04:00
Thomas Fitzsimmons
e03dd8a05f configs: bcmstb: Disable networking support
Silence the "Driver Model for Ethernet drivers" migration warning for
the bcm7445 and bcm7260 ports, neither of which supports networking yet.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-09-18 16:19:58 -04:00
Joao Marcos Costa
a7dc37d38c fs/squashfs: Fix Coverity Scan defects
Fix control flow issues and null pointer dereferences.

Signed-off-by: Joao Marcos Costa <jmcosta944@gmail.com>
2020-09-18 16:19:58 -04:00
Tom Rini
98f3ee09d0 Merge tag 'u-boot-imx-20200918' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
----------------------------------------------------------------
Fixes for 2020.10
-----------------

- Toradex boards
- mx6qsabrelite: fix env offset
- esdhc_imx: waiting for clock instead of sleep
- dyn RAM calibration for entry point i.MX6

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/728274602
2020-09-18 10:42:12 -04:00
Soeren Moch
4516b535bf board: tbs2910: Disable CONFIG_ENV_VARS_UBOOT_CONFIG in defconfig
This is not required for sysboot (we defined fdtfile), let's save a few
bytes in the binary image without these variables.

Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-09-18 10:39:43 +02:00
Tom Rini
ae52e75d23 Merge tag 'for-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next
mpc83xx, keymile boards: enable DM_ETH and add DTS
  - mpc83xx: remove unneeded extern declaration in cpu_init
  - powerpc, qe: fix codingstyle issues for drivers/qe
  - powerpc, qe: add DTS support for parallel I/O ports
  - net, qe: add DM support for QE UEC ethernet
  - add DTS for all mpc83xx based boards from keymile
    mainly they are not mainlined to linux.
  - add u-boot specific dtsi
  - add stdout-path
  - add missing ucc4 par_io definitions, which were
    in board code, but not in linux DTS
  - remove not used ethernet nodes
2020-09-17 09:55:01 -04:00
Tom Rini
9de3126e80 Merge branch '2020-09-16-assorted-fixes'
- Assorted bug fixes
2020-09-17 09:53:57 -04:00
Philippe Schenker
bf46474e21 apalis-imx8qm: rename all occurences to apalis-imx8
The Toradex product is called apalis-imx8 consisting of SoM with
i.MX8QM and i.MX8QP SoCs.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:41:33 +02:00
Philippe Schenker
08b6a60ee8 colibri-imx8qxp: rename all occurences to colibri-imx8x
The Toradex product is called colibri-imx8x consisting of SoM with
i.MX8QXP and i.MX8DX SoCs.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:41:26 +02:00
Haibo Chen
f9c3a816c0 mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.

Tested-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-09-17 14:41:07 +02:00
Marek Vasut
d1a7205532 ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration
code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs
have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8.

Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-09-17 14:40:55 +02:00
Denis Pynkin
1189bd513c mx6qsabrelite: increase the environment offset
The size of the binary created with the default U-boot config is much
greater than the default offset for environment `0x60000`.
In case if that binary is used for booting via MMC it is overlapped with
the environment stored on MMC.
This leads to U-Boot corruption while saving environment with `saveenv`
command and non-bootable SabreLite board.

The offset for environment `CONFIG_ENV_OFFSET=0x60000` was added in
commit a09fea1 but did not count in the change to `0xC0000` if option
`CONFIG_ENV_IS_IN_MMC` is used.

The offset is also used for variant with environment saving onto SPI NOR
flash (with enabled option `CONFIG_ENV_IS_IN_SPI_FLASH`). In that case the
U-Boot binary flashed on SPI NOR is also corrupted after environment
saving with the original 0x60000 offset.

Signed-off-by: Denis Pynkin <denis.pynkin@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-09-17 14:40:40 +02:00
Peng Fan
0098222dac imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 support
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17 14:40:22 +02:00
Peng Fan
a3e7d51fd5 imx8m: clock_imx8mm: add missed return
Add missed return

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17 14:40:17 +02:00
Peng Fan
ece7844d8f imx8mq: fix SSCG_PLL_REFCLK_SEL_x
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16

Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17 14:40:10 +02:00
Peng Fan
d81e8cf6ea imx8mq: fix FRAC_PLL_REFCLK_SEL_MASK
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK
was wrongly set.

Reported-by: Coverity 10045172
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17 14:40:04 +02:00
Peng Fan
95bae9ff92 imx7: ccm: correct target interface num
According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1
The target interface CCM root index ranges [0,124], so the number
should be 125.

Reported-by: Coverity 18045
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17 14:39:55 +02:00
Igor Opaniuk
763a4aef09 apalis_imx6: provide fdtfile in env instead of setting it in runtime
Provide fdtfile value in default env instead of setting
it dynamically in runtime.

Fixes: 85cb2bc686("apalis/colibri imx6: provide proper fdtfile value")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Igor Opaniuk
5d54d7eeb1 colibri_imx6: provide fdtfile in env instead of setting it in runtime
Provide fdtfile value in default env instead of setting
it dynamically in runtime.

Fixes: 85cb2bc686("apalis/colibri imx6: provide proper fdtfile value")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Igor Opaniuk
327381e8b5 colibri_imx7: use preboot for fdtfile evaluation
Enable and set preboot var with fdtfile evaluation.
preboot will be checked and run immediately before starting the
CONFIG_BOOTDELAY countdown and/or running the auto-boot command resp.
entering interactive mode.

This provides possibility to use different boot cmds in interactive mode
without manual setting fdtfile value, as it it's already evaluated
before entering interactive mode.

Fixes: a62c60610f("colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Igor Opaniuk
3ab2316a99 colibri_vf: use preboot for fdtfile evaluation
Enable and set preboot var with fdtfile evaluation.
preboot will be checked and run immediately before starting the
CONFIG_BOOTDELAY countdown and/or running the auto-boot command resp.
entering interactive mode.

This provides possibility to use different boot cmds in interactive mode
without manual setting fdtfile value, as it it's already evaluated
before entering interactive mode.

Fixes: 304042c1f3("colibri_vf: set fdtfile for distroboot")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Igor Opaniuk
2f310b7f48 colibri-imx6ull: use preboot for fdtfile evaluation
Enable and set preboot var with fdtfile evaluation.
preboot will be checked and run immediately before starting the
CONFIG_BOOTDELAY countdown and/or running the auto-boot command resp.
entering interactive mode.

This provides possibility to use different boot cmds in interactive mode
without manual setting fdtfile value, as it it's already evaluated
before entering interactive mode.

Fixes: board: 31b1e17f44("toradex: add Colibri iMX6ULL support")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Igor Opaniuk
b4c9cd6875 colibri_imx7: wrap video specific funcs with ifdefs
Wrap video specific functionality with ifdefs.

Fixes: 195011b24d("colibri-imx7: fix splash logo drawing")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Igor Opaniuk
e6fd30dd9e toradex: drop legacy show_boot_logo function and use splashscreen
Drop show_boot_logo legacy function, as splashscreen functionality can
be used instead.

Fixes: d324189772("toradex: common: show boot logo")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Igor Opaniuk
1310660f5c colibri_imx7: use splashcreen value instead of legacy function
Set proper splashscreen env value instead of calling legacy function
to show embed boot logo.

Fixes: 195011b24d("colibri-imx7: fix splash logo drawing")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Igor Opaniuk
f37aab99f2 colibri-imx6ull: use splashcreen value instead of legacy function
Set proper splashscreen env value instead of calling legacy function
to show embed boot logo.

Fixes: 391c712dde("colibri-imx6ull: show boot logo")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:39:09 +02:00
Heiko Schocher
7bdfe85929 mpc83xx, keymile boards: enable DM_ETH and add DTS
enable DTS support for keymile mpc83xx based boards.

get rid of compile warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================

Therefore done:
- add DTS for all mpc83xx based boards from keymile
  mainly they are not mainlined to linux.
- add u-boot specific dtsi
- add stdout-path
- add missing ucc4 par_io definitions, which were
  in board code, but not in linux DTS
- remove not used ethernet nodes

Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>

Series-to: u-boot

Series-version: 3

Series-changes: 3
- rebase patchset to current mainline commit
  c0192950df
- update defconfig files

Series-changes: 2
- add patch which fixes Codingstyle errors in drivers/qe
- add patch which converts the mpc83xx based boards from
  keymile to DM_ETH

Cover-letter:
powerpc, mpc83xx: add DM_ETH support

This patch series adds DM ethernet support for mpc83xx based
keymile boards.

Travis build:

END
2020-09-17 06:09:54 +02:00
Heiko Schocher
6e31c62a17 net, qe: add DM support for QE UEC ethernet
add DM/DTS support for the UEC ethernet on QUICC Engine
Block.

Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com>

Series-changes: 3
- revert:
  commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled")
  as now qe works with DM and DM_ETH support.
- fix mailaddress from Holger

Series-changes: 2
- add comments from Qiang Zhao:
  - add device node documentation
  - I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c
    because using drivers/net/fsl_mdio.c leads in none existent
    udevice mdio@3320
    instead boards with DM ETH support should use now this
    driver.
- remove RFC tag

Commit-notes:

- I let the old none DM based implementation in code
  so boards should work with old implementation.
  This Code should be removed if all boards are converted
  to DM/DTS.

- add the DM based qe uec driver under drivers/net/qe

- Therefore copied the files uccf.c uccf.h uec.h from
  drivers/qe. So there are a lot of Codingstyle problems
  currently. I fix them in next version if this RFC
  patch is OK or it needs some changes.

- The dm based driver code is now under drivers/net/qe/dm_qe_uec.c
  Used a lot of functions from drivers/qe/uec.c

- seperated the PHY specific code into seperate file
  drivers/net/qe/dm_qe_uec_phy.c

END
2020-09-17 06:09:53 +02:00
Heiko Schocher
5990b05951 powerpc, qe: add DTS support for parallel I/O ports
add DM support for parallel I/O ports on QUICC Engine Block

Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>

Series-changes: 2
- remove RFC
- fixed Codingstyle errors, therefore new patch
  powerpc, mpc83xx: fix codingstyle issues for qe_io.c
- moved DM part to drivers/pinctrl

Commit-notes:
Open questions / discussion:

- I let the old none DM based implementation in code
  so boards should work with old implementation.

  This should be removed if all boards are converted to
  DM/DTS.

- Unfortunately linux DTS does not use "pinctrl-"
  properties, instead "pio-handle" properties.

  Even worser old U-Boot code initializes all pins
  defined in "const qe_iop_conf_t qe_iop_conf_tab[]"
  table in board code. As linux does the same I decided
  to also scan through all subnodes containing "pio-map"
  property and initialize them too.

  The proper solution would be to check for "pio-handle"
  when a device is probed.

END
2020-09-17 06:09:53 +02:00
Heiko Schocher
9bd6444826 powerpc, qe: fix codingstyle issues for drivers/qe
fix Codingstyle for files in drivers/qe, remaining following
check warnings:

$ ./scripts/checkpatch.pl -f drivers/qe/uec.h
CHECK: Macro argument reuse '_bd' - possible side-effects?
+#define BD_ADVANCE(_bd, _status, _base)        \
+       (((_status) & BD_WRAP) ? (_bd) = \
+        ((struct buffer_descriptor *)(_base)) : ++(_bd))

total: 0 errors, 0 warnings, 1 checks, 692 lines checked

$ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.h
total: 0 errors, 0 warnings, 0 checks, 214 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uccf.c
total: 0 errors, 0 warnings, 0 checks, 507 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uec.c
total: 0 errors, 0 warnings, 0 checks, 1434 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.c
total: 0 errors, 0 warnings, 0 checks, 927 lines checked

$ ./scripts/checkpatch.pl -f drivers/qe/qe.c
CHECK: Lines should not end with a '('
+U_BOOT_CMD(

total: 0 errors, 0 warnings, 1 checks, 830 lines checked

Signed-off-by: Heiko Schocher <hs@denx.de>
2020-09-17 06:09:53 +02:00
Heiko Schocher
1a1b4f5d6b mpc83xx: remove unneeded extern declaration in cpu_init
remove
extern void qe_init(uint qe_base);
extern void qe_reset(void);

and include fsl_qe.h instead.

Signed-off-by: Heiko Schocher <hs@denx.de>

Series-changes: 2
- new in v2
2020-09-17 06:09:53 +02:00
Heinrich Schuchardt
c6963fb88f doc: qemu: debug UART settings for QEMU ARM virt
Provide the settings for the debug UART on the QEMU ARM virt board.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-16 16:54:00 -04:00
Miquel Raynal
c4d0384a4a MAINTAINERS: add myself as reviewer for SquashFS
I also followed the development of the SquashFS support in U-Boot
as part of Joao Marcos internship, so I would also appreciate receiving
new contributions and bug reports related to this topic.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-09-16 16:54:00 -04:00
Thomas Petazzoni
42ef2edc85 MAINTAINERS: add myself as reviewer for SquashFS
As I have followed the development of the SquashFS support in U-Boot
as part of Joao Marcos work, it makes sense to get Cc'ed on
contributions/bug reports related to the squashfs support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2020-09-16 16:54:00 -04:00
Marek Vasut
81d0cef3b2 lib: fdt: Fix fdtdec_setup_mem..() conversion to livetree API
Repair incorrectly negated condition in the original patch which broke
DT memory node parsing on everything which has more than one DT memory
node, e.g. R-Car3.

In case multiple valid memory nodes are present in the DT, the original
patch would complete parsing cycle for the first memory node, then move
on to the next one, identify it as a valid, and end the parsing. The fix
is to invert the condition, to make the code behave as it did before the
livetree conversion, so it would continue parsing the subsequent memory
nodes as well.

Fixes: c2f0950c33 ("lib: fdt: Convert fdtdes_setup_mem..() to livetree API")
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2020-09-16 16:54:00 -04:00
Thirupathaiah Annapureddy
7def4e621b include: phy: fix NULL pointer check in phy_write()
phy_write() uses bus->write() instead of bus->read(). This means NULL
pointer pre-check needs to happen on bus->write instead of bus->read.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2020-09-16 16:54:00 -04:00
Baruch Siach
a8a71c9488 MAINTAINERS: update clk entry git tree
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-09-16 16:54:00 -04:00
Tom Rini
b01ba776c9 Merge tag 'efi-2020-10-rc5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc5

The following bugs are fixed:

* unaligned access in br_i32_decode()
* missing restore of global data pointer in UEFI selftest
* missing restore of global data pointer on RISC-V in UEfI subsystem
* efi_var_mem_notify_exit_boot_services() should not be __efi_runtime
2020-09-16 08:08:06 -04:00
Tom Rini
0487bb5ecd Merge tag 'u-boot-rockchip-20200916' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix rv1108 grf access issue
- make_fit_atf: ignore empty PT_LOAD segment
2020-09-16 08:07:49 -04:00
Heinrich Schuchardt
5b861eea79 rockchip: make_fit_atf: ignore empty PT_LOAD segment
The linker sometimes creates PT_LOAD segments with length (p_filesz) zero
as described in https://man7.org/linux/man-pages/man5/elf.5.html. This
leads to build failures. We should ignore empty segments.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16 16:41:30 +08:00
Kever Yang
454b792afe rockchip: rv1108: enable board early init
Enable board early init callback to init board specific hardware.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16 16:32:01 +08:00
Kever Yang
fe4931c09a rockchip: rv1108: Enable grf as pre-reloc node
The grf node will be used before relocate, enable it in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16 16:31:18 +08:00
Kever Yang
f11f138ebf rockchip: rv1108: use correct API for board callback
Use board_early_init_f() instead of mach_cpu_init() for board, the
board_early_init_f() is used for board init and after dm_initf, while
the mach_cpu_init() is used for CPU/SOC and before dm_initf()(not able
to use syscon API).

Fixes: 9cec336708 ("rockchip: evb-rv1108: Use syscon API to get grf base")
Fixes: 4aa33690fc {"rockchip: elgin-rv1108: Use syscon API to get grf base")

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16 16:31:17 +08:00
Tom Rini
bd4e8944cf Merge tag 'ti-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
- Hyperflash boot for J7200
- Update Main R5FSS lockstep mode
- R5F remoteproc support for J7200
- Minor env fixes
- Add SPI boot support for am335x-icev2
2020-09-15 15:22:00 -04:00
Faiz Abbas
5ba2883160 configs: Add spiboot support for am335x
am335x internal SRAM is too small to support the addition of
SPI bootmode to the default defconfig. Add a separate spiboot_defconfig

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Faiz Abbas
afd4f15a39 spi: omap3_spi: Read platform data in ofdata_to_platdata()
Add an ofdata_to_platdata() callback to access dts in U-boot and
access all platform data in it. This prepares the driver for supporting
both device tree as well as static platform data structures in SPL.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Faiz Abbas
41cf3cb39d arm: mach-omap2: am33xx: Add device structure for spi
Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Faiz Abbas
280af01156 spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failures
There are devices which don't use OF_CONTROL or OF_PLATDATA but instead
rely on statically defined platdata. Block dm_scan_fdt_dev() with both
configs to avoid build failures under this condition.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-09-15 18:51:53 +05:30
Faiz Abbas
38e6ddc4d7 arm: dts: am335x-icev2: Add spi node
Add spi and spi nor flash nodes for am335x-icev2.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Matwey V. Kornilov
8c444c184c am335x_evm: Allow booting from usb-storage device
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2020-09-15 18:51:53 +05:30
Matwey V. Kornilov
42b7aebe4a ti: Use devtype=mmc instead of setenv devtype mmc
If devtype variable is setted via setenv, then the following devtype=X style is
ignored. Currently, many u-boot commands use devtype variable in the latter
manner:

    mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi

Use devtype=mmc instead of setenv devtype mmc to avoid bugs with booting from
another devtype.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2020-09-15 18:51:53 +05:30
Suman Anna
a0549cc952 configs: j7200_evm_r5: Enable FS_LOADER
Enable the FS_LOADER and associated configs in the j7200_evm_r5_defconfig
so that the R5 SPL can support the loading of firmware files from a boot
media/file system.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
70377b7279 arm: dts: k3-j7200-r5: Add fs_loader node
Add a generic fs_loader node to the K3 J7200 R5 common board dts
file and use it as the chosen firmware-loader so that it can be
used for loading various firmwares from a boot media/filesystem
in R5 SPL on K3 J7200 EVM.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
615d10f736 env: ti: j721e-evm: Update R5 SPL rproc env variables for J7200
The R5 SPL on J7200 SoCs will be limited to booting just the
MCU R5FSS0 R5F core in LockStep-mode at present, so add the
two required environment variables 'addr_mcur5f0_0load' and
'name_mcur5f0_0fw' that are needed by the R5 SPL early-boot
logic. The firmware name used is also different from that on
J721E SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
f61687df0f configs: j7200_evm_a72: Enhance bootcmd to start remoteprocs
The A72 U-boot can support early booting of any of the Main or MCU R5F
remote processors from U-boot prompt to achieve various system usecases
before booting the Linux kernel. Update the default BOOTCOMMAND to provide
an automatic and easier way to start various remote processors through
added environment variables.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
d529e4a435 configs: j7200_evm_a72: Enable R5F remoteproc driver
The J7200 SoCs has two R5F sub-systems. Enable the TI K3
R5F remoteproc driver and the remoteproc command options
to allow these R5F processors to be booted from A72 U-Boot.

The Kconfigs are added using savedefconfig.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
c091bb0499 env: ti: j721e-evm: Update rproc_fw_binaries env variable for J7200
The J7200 SoCs have different number of remote processors, but reuse
the same environment settings as the J721E SoCs. The current env
variable rproc_fw_binaries is geared towards J721E SoCs and is
incorrect for J7200 SoCs. Please see the logic originally added in
commit 0b4ab9c9a7 ("env: ti: j721e-evm: Add support to boot rprocs
including R5Fs and DSPs").

Fix this by defining the DEFAULT_RPROCS macro appropriately using
the corresponding TARGET_EVM Kconfig symbol. This macro is used by
the 'rproc_fw_binaries' env variable in the common remoteproc env
header file k3_rproc.h.

The list of R5F cores to be started before loading and booting the
Linux kernel are as follows, and mainly comprises of the Main R5FSS0
cores in this order:
   Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw
   Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw

The MCU R5FSS0 is in LockStep mode and is expected to be booted by
R5 SPL, so it is not included in the list. The order of rprocs to
boot cannot be really modified as only the Main R5FSS0 cores are
involved and Core0 has to be booted first always before the
corresponding Core1.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
3f7e032f70 arm: dts: k3-j7200-main: Add MAIN domain R5F cluster nodes
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
10c4de02f0 arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
7873e9df8f armv8: K3: j7200: Add custom MMU support
The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.

The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
6aa3b740c3 remoteproc: k3-r5: Add support for J7200 R5Fs
The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The integration of
these clusters is very much similar to J721E SoCs otherwise.

The revised IP has the following two new features:
 1. TCMs are auto-initialized during module power-up, and the behavior
    is programmable through a MMR bit controlled by System Firmware.
 2. The LockStep-mode allows the Core1 TCMs to be combined with the
    Core0 TCMs effectively doubling the amount of TCMs available.
    The LockStep-mode on previous SoCs could only use the Core0 TCMs.
    This combined TCMs appear contiguous at the respective Core0 TCM
    addresses.

Add the support to these clusters in the K3 R5F remoteproc driver
using J7200 specific compatibles and revised logic accounting for
the above IP features/differences.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
ca569e9bbe dt-bindings: remoteproc: k3-r5f: Update bindings for J7200 SoCs
The K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with
2 R5F cores each, one in each of the MCU and MAIN voltage domains.

These clusters are a revised version compared to those present on
J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible
info relevant to these R5F clusters/subsystems on K3 J7200 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
a9e5caf596 env: ti: j721e-evm: Limit scope of rproc env variables used by R5 SPL
The commit 316c927135 ("include: configs: j721e_evm: Add env variables
for mcu_r5fss0_core0 & main_r5fss0_core0") added four different new env
variables 'addr_mainr5f0_0load', 'name_mainr5f0_0fw', 'addr_mcur5f0_0load'
and 'name_mcur5f0_0fw' to the generic environment, but these are only
needed and used in R5 SPL for early-booting the MCU R5FSS0 and Main
R5FSS0 Core0 on J721E SoCs.

These are not really needed for A72 U-Boot, so limit the scope of
these variables only to R5 SPL. While at this, also fix the loadaddr
variable values to include the hex prefix like with other such env
variables.

Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
3c195299a8 configs: j721e_evm: Add Main R5FSS1 Core1 to default rproc boot list
The default rproc list currently used by A72 U-Boot to boot various
remote processors include the Main R5FSS0 (Split-mode) Core1, Main
R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster
is configured for Split mode by default in the dts now, so add the
Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This
core is now booted after the Main R5FSS1 Core0 and before the DSPs.

The order of the rprocs to boot can always be changed at runtime if
desired by overwriting the 'rproc_fw_binaries' environment variable
at U-boot prompt. Note that the R5FSS Core1 cannot be booted before
its associated Core0.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
31defbd347 arm: dts: k3-j721e-main: Configure MAIN R5FSS1 for Split-mode
Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode. LockStep-mode would be available only
on SoCs efused with the appropriate bit, and Split-mode is the mode
that is available on all J721E SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Vignesh Raghavendra
f8d3d4d14a configs: j721e_evm.h: Add U-Boot image address for HyperFlash boot
Add memory mapped address location of U-Boot images in HyperFlash boot
mode.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:53 +05:30
Vignesh Raghavendra
f7fdeec4b4 configs: j7200_evm_*_defconfig: Enable HyperFlash boot related configs
Enable configs required to support HyperFlash boot and detection of
onboard mux switch for HyperFlash selection

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:53 +05:30
Vignesh Raghavendra
c07d06855e ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash
Enable HyperBus and HyperFlash to support HyperFlash boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:53 +05:30
Vignesh Raghavendra
e85382fc53 board: ti: j721e: Add support for HyperFlash detection
On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of
them can be used at any time. J7200 EVM has both HyperFlash and OSPI
flash on board. There is a user switch (SW3.1) that can be toggled to
select OSPI flash vs HyperFlash.
Read the state of this switch via wkup_gpio0_6 line and fixup the DT
nodes to select OSPI vs HyperFlash

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:52 +05:30
Vignesh Raghavendra
7ce6c8ae58 arm: mach-k3: Add HyperFlash boot mode support
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:52 +05:30
Tom Rini
4dcced1169 Merge tag 'mmc-2020-9-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- Use mmc_of_parse for msm_sdhci
- Add missing common host caps for xenon_sdhci.
2020-09-15 08:59:32 -04:00
Marek Vasut
0e12575645 Azure/GitLab/Travis: Add SH4 r2dplus machine with various PCI ethernet options
Add SH4 R2Dplus machine configured to test various U-Boot PCI ethernet
options -- RTL8139, EEPRO100, AMD PCnet, DEC Tulip.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-15 08:59:06 -04:00
Andre Heider
e79c59c0e2 mmc: xenon_sdhci: Add missing common host capabilities
Use mmc_of_parse() to set the common host properties. That includes
"bus-width", so parsing it can be removed from the driver.

But more importantly, "non-removable" is now respected, which fixes
the usage of eMMC.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Marek Behún <marek.behun@nic.cz>
2020-09-15 10:15:56 +08:00
Manivannan Sadhasivam
8505147403 mmc: msm_sdhci: Use mmc_of_parse for setting host_caps
Since the introduction of 'get_cd' callback in sdhci core,
dragonboard410c's MMC interface is broken. It turns out that 'get_cd'
callback checks for the host_caps for validating the chip select. And
since the msm_sdhci driver is not parsing the host_caps from DT, not
all of the cababilities are parsed properly. This results in the MMC
interfaces to be broken.

Hence, fix this by adding a call to 'mmc_of_parse' during driver probe.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Aníbal Limón <anibal.limon@linaro.org>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-09-15 10:13:37 +08:00
Heinrich Schuchardt
5bf12a7859 efi_selftest: restore gd before do_reset()
Before calling do_reset() in the EFI selftest we must restore the global
data pointer.

Fixes: fa63753f86 ("efi_selftest: substitute ResetSystem() by do_reset()")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-14 23:28:52 +02:00
Heinrich Schuchardt
d68d7f47a9 efi_loader: save global data pointer on RISC-V
On RISC-V the global data pointer is stored in register gp. When a UEFI
binary calls the EFI API we have to restore it.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-14 23:28:52 +02:00
Heinrich Schuchardt
6b9966e1aa riscv: define function set_gd()
Function set_gd() is needed in the UEFI sub-system if the global data
pointer is stored in a register.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-14 23:28:52 +02:00
Heinrich Schuchardt
e5a31376ac efi_loader: efi_var_mem_notify_exit_boot_services
efi_var_mem_notify_exit_boot_services() is invoked when ExitBootServices()
is called by the UEFI payload.

efi_var_mem_notify_exit_boot_services() should not be defined as
__efi_runtime as it is invoking EFI_ENTRY() and EFI_EXIT() which themselves
are not __efi_runtime.

Fixes: f1f990a8c9 ("efi_loader: memory buffer for variables")
Fixes: e01aed47d6 ("efi_loader: Enable run-time variable support for tee based variables")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-09-14 23:28:52 +02:00
Robert Reither
8479333ce7 rsa: crash in br_i32_decode() called from rsa_gen_key_prop()
Fixes problem for unaligned 32bit big-endian access in
lib/rsa/rsa-keyprop.c.

Exchanges br_i32_decode() with get_unaligned_be32().

This will keep the unaligned access for architectures capable and will do
some byte-shift magic for the not so capable ones.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-by: Robert Reither <robert.reither@external.thalesgroup.com>
Remove unused include.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-14 23:28:52 +02:00
Tom Rini
00e5fda006 Merge branch '2020-09-12-assorted-bugfixes'
- A large assortment of minor fixes
- Documentation improvements
2020-09-14 15:39:46 -04:00
Heinrich Schuchardt
185440ffc4 test: do no assume hush parser in validate_empty()
The environment variable test uses function validate_empty() to check that
a variable is not defined. If the hush parser is not enabled, we cannot
refer to a variable by $var_name but only by ${var_name}.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
2020-09-12 10:53:01 -04:00
Heinrich Schuchardt
9a97314b5b Makefile: mrproper shall delete doc/output/
HTML documentation is generated in doc/output/. This directory shall be
deleted by 'make mrproper'

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-12 10:53:01 -04:00
Heinrich Schuchardt
70e38eea3a doc: describe building with GCC
Provide a description of the U-Boot build process with GCC in the HTML
documentation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-12 10:53:01 -04:00
Heinrich Schuchardt
2974ba4f65 doc: describe source repository
Add a chapter to the HTML documentation describing how to retrieve the
U-Boot sources.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-12 10:53:01 -04:00
Mingming Lee
75fb7b9163 ARM: MediaTek: amend IC description for MediaTek MT8512
The description for MT8512  has some mistake, so correct it.

Signed-off-by: Mingming Lee <Mingming.Lee@mediatek.com>
2020-09-12 10:53:01 -04:00
Reuben Dowle
eb39d8ba5f Fix data abort caused by mis-aligning FIT data
Attempting to place device tree immediately after an image in memory can lead
to mis-aligned data accesses if that image size is not divisible by the
alignment requirements of the architecture.

Data aborts caused by this were observed on a custom Marvel A388 based system,
where the image was a uboot FIT file. The total size varies depending on the
uboot device tree size, which does not always lead to correct alignment.

The minimum alignment specified for ARM [1] and ARM64 [2] linux booting has been
used

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm/booting.rst#n126
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.rst#n45

Signed-off-by: Reuben Dowle <reuben.dowle@4rf.com>
2020-09-11 17:13:56 -04:00
T Karthik Reddy
1e2c5bb9e7 mtd: nand: Fix nand write error with bad block addresses above 32-bit
Nand writes should skip the bad blocks with "nand write" command.
In case of bad blocks with above 32-bit address, nand_block_isbad()
returns false due to truncated bad block address.

In below code segment,

	if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1)))

offset is 64-bit and mtd->erasesize is 32-bit, hence the truncation is
happening. Cast 'mtd->erasesize' with loff_t to fix this issue.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-11 17:13:56 -04:00
Pedro Aguilar
142775a52b env: Crash in 'env import' when using checksum and a specific size
This patch adds a sanity check that avoids 'size' to overflow and crash when
importing an environment that contains a checksum. Example with the wrong size
that causes the crash:

=> env import -c 0x4100000 3 v1

This assumes that v1 has already been successfully exported with
'env export -c -s 0x100 0x4100000 v1'

Signed-off-by: Pedro Aguilar <pedro.aguilar@vimar.com>
2020-09-11 17:13:56 -04:00
Heinrich Schuchardt
21d3946840 bootm: update image OS image size when decompressing
In bootm_load_os() the OS image is decompressed. In later stages of the
boot process we need the decompressed size of the image.

Update images->os.image_len after decompression.

Passing the correct size is necessary if we want to check loaded EFI
binararies for file truncation by comparing the loaded size to the header
field SizeOfImage.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-11 17:13:56 -04:00
Michal Simek
91b735d11f common: Kconfig: Add dependency for default variables strings
Kconfig provides several config options for setting up default variables
but these are unused when variables are passed to U-Boot via file.
That's why cover this dependency in Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-11 17:13:55 -04:00
Chuanjia Liu
9250d0bad5 PCI: mediatek: Release the resource when PCIe enable port fail
On the mt7623 platform, if one port enable fail and other port
enable succeed. It will hang on when using pci enum
because the resource was not released correctly.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-09-10 15:32:09 -04:00
Tom Rini
23e92c124b Merge branch '2020-09-09-assorted-soc-updates' into next
- Assorted improvements for MediaTek, Broadcom NS3 and ASPEED SoCs.
2020-09-10 14:37:45 -04:00
Thirupathaiah Annapureddy
0b65e494e9 arm: dts: fix ast2500-evb inclusion for the correct soc family
Include ast2500-evb.dtb for CONFIG_ASPEED_AST2500 instead of
for all aspeed targets.

ast2400 is based on ARM926EJ-S processor (ARMv5-architecture).
ast2500 is based on ARM1176JZS processor (ARMv6-architecture).
ast2600 is based on Cortex A7 processor (ARMv7-A architecture).
Each of the above SOC is using a different ARM CPU(s) with different ARM
architecture revision. It is not possible to support all 3 of these
families in a single binary. So there is no need to build ast2500-evb.dtb
for other SOC families.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
2020-09-10 11:17:46 -04:00
Chuanjia Liu
df85e9576c PCI: mediatek: Release the resource when PCIe enable port fail
On the mt7623 platform, if one port enable fail and other port
enable succeed. It will hang on when using pci enum
because the resource was not released correctly.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-09-10 11:17:46 -04:00
Tom Rini
3dd52dd69e Merge tag 'u-boot-amlogic-20200910' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- enables HDMI output & USB keyboard for Odroid-N2
- setups HDMI output background & enables USB keyboard
2020-09-10 09:04:02 -04:00
Anand Moon
92f10e6135 configs: odroid-c4: update for HDMI output background & USB keyboard
Enable options SYS_WHITE_ON_BLACK to permit HDMI background
screen from white to back, also enable USB_KEYBOARD.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-10 10:51:36 +02:00
Anand Moon
3b3c048697 configs: odroid-n2: update for HDMI output & USB keyboard
Enable options to permit HDMI output on Odroid-N2 G12B boards.
Enable VPU Power Domain.
Enable USB_KEYBOARD.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-10 10:51:36 +02:00
Robert Marko
a5fc58734f dt-bindings: clock: import Qualcomm IPQ4019 bindings
Import Qualcomm IPQ4019 GCC bindings from Linux.
This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-09 16:57:36 -04:00
Ryan Chen
654ae299ec cosmetic: aspeed: Modify for SPDX-License
Modify SPDX-License for furture patch warning

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09 16:57:36 -04:00
Ryan Chen
c39c9a94cb clock:aspeed: Sync with Linux kernel clock header define
v2: modify title description aspeed:clock -> clock:aspeed

Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09 16:57:35 -04:00
Ryan Chen
15b87feb2b cosmetic: aspeed: ast2500: Rename clock header
Rename the ast2500-scu.h to aspeed-clock.h.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-09-09 16:57:35 -04:00
Rayagonda Kokatanur
af071935d2 board: ns3: check bnxt chimp handshake status
Chimp is a core in Broadcom netxtream controller (bnxt).
Add support to check bnxt's chimp component status.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-09 16:57:35 -04:00
Rayagonda Kokatanur
975d2a6980 MAINTAINERS: update maintainers file for new files
Update MAINTAINERS file for new files.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-09 16:57:35 -04:00
Vladimir Olovyannikov
ff6a87560e board: ns3: kconfig: extend board kconfig with specific commands
Extend Kconfig for the board with board-specific commands selection.

Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-09 16:57:35 -04:00
Bharat Kumar Reddy Gooty
a09ca687e7 cmd: broadcom: add command for chimp handshake
Add command for chimp handshake.
Handshake is used to know chimp is loaded and booted successfully.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-09 16:57:35 -04:00
Vikas Gupta
70bf26332f cmd: broadcom: add cmd to update bnxt image env variables
Add command to update the environmental variables which
are used to read the data from QSPI offsets and load
the binaries to bnxt.

Signed-off-by: Vikas Gupta <vikas.gupta@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-09 16:57:35 -04:00
Trac Hoang
186879cdb2 cmd: broadcom: add bnxt boot command
Chimp is a core in Broadcom netxtream controller (bnxt).
Add command to load binary to chimp and boot bnxt.

Signed-off-by: Trac Hoang <trac.hoang@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-09 16:57:35 -04:00
Tom Rini
a34746b86e Merge tag 'u-boot-stm32-20200909' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- fixes on AV96 board: pull up on UART4 RX and adjust PLL4
2020-09-09 12:59:02 -04:00
Marek Vasut
b6055945d6 ARM: dts: stm32: Adjust PLL4 settings on AV96 again
PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
50 MHz generated from PLL4Q cannot be divided well enough to produce
accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz
instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz,
which is in tolerance for the SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Gerald Baeza <gerald.baeza@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-09 15:02:23 +02:00
Marek Vasut
43e2d1dd47 ARM: dts: stm32: Pull UART4 RX high on AV96
There is no dedicated pull resistor on the AV96 UART4 (console UART)
pin. In case there is no UART adapter installed on the AV96, the line
is floating and can trigger reception of garbage characters, which in
turn can abort U-Boot autoboot. Add default pull up to mitigate this
problem.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-09 15:01:53 +02:00
Patrick Delaunay
cf8df34015 arm: stm32mp: cleanup test on eth_env_set_enetaddr result
Remove the unnecessary inversion on the eth_env_set_enetaddr() result which
only make complex the code of setup_mac_address() and display an invalid
value in the associated pr_err.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2020-09-09 14:19:12 +02:00
Tom Rini
a14b71d0c2 Merge tag 'rpi-next-2020.10.2' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi
- fixes for bcmgenet
- enable USB keyboard for RPi4 32 bit
2020-09-09 08:17:53 -04:00
Matthias Brugger
40877a1a94 config: Enable USB Keyboard suuport on RPi4 32 bit
Supporting USB keyboards out of the box is both handy for development
and production. Notably if u-boot is used to boot into GRUB. This patch
adds USB keyboard support for 32 bit RPi4 config.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-09-08 16:45:01 +02:00
Jason Wessel
34873f46ba bcmgenet: Add support for rgmii-rxid
The commit 57805f2270 ("net: bcmgenet: Don't set ID_MODE_DIS when
not using RGMII") needed to be extended for the case of using the
rgmii-rxid.  The latest version of the Rasbperry Pi4 dtb files for the
5.4 now specify the rgmii-rxid.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Tested-by: Petr Tesarik <ptesarik@suse.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-09-08 16:43:48 +02:00
Jason Wessel
ac458dc823 bcmgenet: fix DMA buffer management
This commit fixes a serious issue occurring when several network
commands are run on a raspberry pi 4 board: for instance a "dhcp"
command and then one or several "tftp" commands. In this case,
packet recv callbacks were called several times on the same packets,
and send function was failing most of the time.

note: if the boot procedure is made of a single network
command, the issue is not visible.

The issue is related to management of the packet ring buffers
(producer / consumer) and DMA.
Each time a packet is received, the ethernet device stores it
in the buffer and increments an index called RDMA_PROD_INDEX.
Each time the driver outputs a received packet, it increments
another index called RDMA_CONS_INDEX.

Between each pair of network commands, as part of the driver
'start' function, previous code tried to reset both RDMA_CONS_INDEX
and RDMA_PROD_INDEX to 0. But RDMA_PROD_INDEX cannot be written from
driver side, thus its value was actually not updated, and only
RDMA_CONS_INDEX was reset to 0. This was resulting in a major
synchronization issue between the driver and the device. Most
visible behavior was that the driver seemed to receive again the
packets from the previous commands (e.g. DHCP response packets
"received" again when performing the first TFTP command).

This fix consists in setting RDMA_CONS_INDEX to the same
value as RDMA_PROD_INDEX, when resetting the driver.

The same kind of fix was needed on the TX side, and a few variables
had to be reset accordingly (c_index, tx_index, rx_index).

The rx_index and tx_index have only 256 entries so the bottom 8 bits
must be masked off.

Originated-by: Etienne Dublé <etienne.duble@imag.fr>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Tested-by: Petr Tesarik <ptesarik@suse.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-09-08 16:43:02 +02:00
Patrick Delaunay
93d3bc5f8d arm: meson: change trace level for phy errors managed by uclass
As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_debug.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-08 08:46:32 -04:00
Patrick Delaunay
c1e1dbb8f3 usb: musb-new: sunxi: change trace level for phy errors managed by uclass
As the error message is now displayed by generic phy functions,
the dev_err/pr_err can be change to dev_dbg/pr_debug.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-08 08:46:32 -04:00
Patrick Delaunay
fc8ead1a0a ata: dwc-ahci: change trace level for phy errors managed by uclass
As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_debug.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-08 08:46:32 -04:00
Patrick Delaunay
890fc370a9 usb: host: ehci-hcd: change trace level for phy errors managed by uclass
As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_debug.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-08 08:46:32 -04:00
Patrick Delaunay
3b417a7d82 usb: host: ohci: change trace level for phy errors managed by uclass
As the error message is now displayed by generic phy functions,
the dev_err can be change to dev_dbg.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-08 08:46:32 -04:00
Patrick Delaunay
f286e37c14 board: sunxi: change trace level for phy errors managed by uclass
As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_idebug.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-08 08:46:32 -04:00
Patrick Delaunay
2041ae5a5a phy: generic: add error trace to detect PHY issue in uclass
Add an error trace for PHY errors directly in generic phy
functions provided by PHY uclass.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-08 08:46:32 -04:00
Tom Rini
2a9f9d633d Merge branch '2020-09-14-btrfs-rewrite' into next
- Bring in the update to btrfs support that rewrites it based on
  btrfs-progs.
2020-09-07 21:00:47 -04:00
Qu Wenruo
b737c822c0 MAINTAINERS: Add btrfs mailing list and myself as reviewer
Since the current code base is mostly from btrfs-progs, anyone
contributing to U-Boot btrfs code could also help us to improve
btrfs-progs and btrfs kernel module.

Also add myself as designated reviewer.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 21:00:36 -04:00
Qu Wenruo
5573c20fad fs: btrfs: Cleanup the old implementation
This cleans up the now unneeded code from the old btrfs implementation.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 21:00:36 -04:00
Qu Wenruo
e8e95c7ee1 fs: btrfs: Imeplement btrfs_list_subvols() using new infrastructure
Reimplement btrfs_list_subvols() to use new code.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 21:00:36 -04:00
Qu Wenruo
f48615276b fs: btrfs: Introduce function to resolve the path of one subvolume
This patch introduces a new function, list_one_subvol(), which will
resolve the path to FS_TREE of one subvolume.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 21:00:36 -04:00
Qu Wenruo
8098da7094 fs: btrfs: Introduce function to resolve path in one subvolume
This patch introduces a new function, get_path_in_subvolume(), which
resolves inode number into path inside a subvolume.

This function will be later used for btrfs subvolume list functionality.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 21:00:36 -04:00
Qu Wenruo
e3427184f3 fs: btrfs: Implement btrfs_file_read()
This version of btrfs_file_read() has the following new features:
- Tries all mirrors
- More handling on unaligned size
- Better compressed extent handling
  The old implementation doesn't handle compressed extent with offset
  properly: we need to read out the whole compressed extent, then
  decompress the whole extent, and only then copy the requested part.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 21:00:36 -04:00
Qu Wenruo
01347f64d5 fs: btrfs: Introduce lookup_data_extent() for later use
This implements lookup_data_extent() function for the incoming
new implementation of btrfs_file_read().

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
a26a6bedaf fs: btrfs: Introduce btrfs_read_extent_inline() and btrfs_read_extent_reg()
These two functions are used to do sector aligned read, which will be
later used to implement btrfs_file_read().

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
0cc8fc65c1 fs: btrfs: Rename btrfs_file_read() and its callees to avoid name conflicts
Rename btrfs_file_read() and its callees to avoid name conflicts with
the incoming new code.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
5bbb68d5f0 fs: btrfs: Use btrfs_lookup_path() to implement btrfs_exists() and btrfs_size()
After this the only remaining function that still utilizes
__btrfs_lookup_path() is btrfs_read().

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
325dd1f642 fs: btrfs: Use btrfs_iter_dir() to replace btrfs_readdir()
Use extent buffer based infrastructure to re-implement btrfs_readdir().

Along this rework, some small corner cases fixed:
- Subvolume tree mtime
  Mtime of a subvolume tree is recorded in its root item, since there is
  no INODE_ITEM for it.
  This needs extra search from tree root.

- Output the unknown type
  If the DIR_ITEM is corrupted, at least don't try to access the memory
  out of boundary.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
c921aa20c3 fs: btrfs: Implement btrfs_lookup_path()
This is the extent buffer based path lookup routine.

To implement this, btrfs_lookup_dir_item() is crossported from
btrfs-progs, and implements btrfs_lookup_path() from scratch.

Unlike the existing __btrfs_lookup_path(), since btrfs_read_fs_root()
will check whether a root is a orphan at read time, there is no need to
check root backref, this makes the code a little easier to read.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
5bdcb37495 fs: btrfs: inode: Allow next_length() to return value > BTRFS_NAME_LEN
All existing next_length() caller handles return value > BTRFS_NAME_LEN,
so there is no need to do BTRFS_NAME_LEN check in next_length().

But still, we want to exit early if we're beyond BTRFS_NAME_LEN, so this
patch makes next_length() exit as soon as we're beyond BTRFS_NAME_LEN.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
92bc179c5f fs: btrfs: Use btrfs_readlink() to implement __btrfs_readlink()
The existing __btrfs_readlink() can be easily re-implemented using the
extent buffer based btrfs_readlink().

This is the first step to re-implement U-Boot's btrfs code.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
cafffc50ad fs: btrfs: Rename path resolve related functions to avoid name conflicts
Since the old code is using __btrfs_path/__btrfs_root which is different
from the regular extent buffer based one, we add "__" prefix for the old
implementation to avoid name conflicts for the incoming crossport.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
f06bfcf54d fs: btrfs: Crossport open_ctree_fs_info() from btrfs-progs
open_ctree_fs_info() is the main entry point to open btrfs.

This version is a simplfied version of __open_ctree_fd() of btrfs-progs,
the main differences are:
- Parameters on how to specify a block device
  Instead of @fd and @path, U-Boot uses blk_desc and disk_partition_t.

- Remove open_ctree flags
  There won't be multiple open ctree modes in U-Boot.

Otherwise functions structures are all kept the same.

With open_ctree_fs_info() implemented, also introduce the global
current_fs_info pointer to show the current opened btrfs.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
57f24f1073 fs: btrfs: Crossport btrfs_read_sys_array() and btrfs_read_chunk_tree()
These two functions play a big role in btrfs bootstrap.

The following function is removed:
- Seed device support

Although in theory we can still support multiple devices, we don't have
a facility in U-Boot to do device scan without opening them.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
29c26ae8bc fs: btrfs: Crossport btrfs_search_slot() from btrfs-progs
This patch copies the core function, btrfs_search_slot(), from
btrfs-progs.

This version has the following functionality removed:
- The ability to COW tree block
  Related code is commented out, and can be enabled in the future.

- The readahead functionality
  This is abused in kernel. Remove it completely.

With the core function in place, btrfs developers should feel at home now.

This also crossports supporting code like btrfs_previous_item() to
ctree.[ch].

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
bccee8bcb2 fs: btrfs: Crossport struct btrfs_root to ctree.h
Crossport struct btrfs_root to ctree.h from btrfs-progs, with write
related members deleted.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
207011b81e fs: btrfs: Rename btrfs_root to __btrfs_root
This is to avoid naming conflicts between extent buffer based
btrfs_root.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
33966de31f fs: btrfs: Rename struct btrfs_path to struct __btrfs_path
To avoid name conflicting between the extent buffer based btrfs_path
from btrfs-progs, rename struct btrfs_path to struct __btrfs_path.

Also rename btrfs_free_path() to __btrfs_free_path() to avoid conflicts.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
75b0817bab fs: btrfs: Crossport read_tree_block() from btrfs-progs
This is the one of the basic stone function for btrfs, which:
- Resolves the chunk mappings
- Reads data from disk
- Does various sanity check

With read_tree_block(), we can finally crossport needed btrfs btree
operations to U-Boot.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
b1f0067aba fs: btrfs: Crossport volumes.[ch] from btrfs-progs
This patch crossports volumes.[ch] from btrfs-progs, including:
- btrfs_map_block()
  The core mechanism to map btrfs logical address to physical address.
  This version includes multi-device support, along with RAID56 support.

- btrfs_scan_one_device()
  This is the function to register one btrfs device to the list.
  This is the main part of the multi-device btrfs assembling process.
  Although we're not going to support multiple devices until U-Boot
  allows us to scan one device without actually opening it.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
[trini: Use %zu in a debug print to avoid warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-07 20:57:27 -04:00
Qu Wenruo
be35942546 fs: btrfs: Crossport structure accessor into ctree.h
This brings all structure accessors from btrfs-progs/ctree.h, as in
kernel's ctree.h.

All these accessors handle the endian convert at runtime, and since all
of them are defined as static inline functions, those which aren't used
won't take space in resulting binary.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
9a9be5ec17 fs: btrfs: Crossport extent-io.[ch] from btrfs-progs
This brings the extent_io_tree infrastructure, with which we can finally
bring in proper btrfs_fs_info structure to ctree.h.

With read/write_extent_buffer() implemented we also backport
read/write_eb_member() to ctree.h.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
ab5c3046f2 fs: btrfs: Crossport extent-cache.[ch] from btrfs-progs
This patch implements an infrastructure to insert/search/merge an extent
range (with variable length).

This provides the basis for later extent buffer cache used in btrfs.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
bc621e545b fs: btrfs: Crossport rbtree-utils from btrfs-progs
This is needed for incoming extent-cache infrastructure.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
4aebb99486 fs: btrfs: Crossport btrfs_read_dev_super() from btrfs-progs
This patch uses generic code from btrfs-progs to read one super block
from block device.

To support the btrfs-progs coding style, the following is also
crossported:
- BTRFS_SETGET_FUNC for btrfs_super_block
- btrfs_check_super() function
- Move btrfs_read_superblock() to disk-io.[ch]
  Since super.c only contains pretty small amount of code, and
  the extra check will be covered in later root read patches.

Differences between this implementation and btrfs-progs:
- No sbflags/sb_bytenr support
  Since we only need to read the primary super block (like kernel),
  sbflags/sb_bytenr used by super block recovery is not needed.

This also changes the following behavior of U-Boot btrfs:
- Only reads the primary super block
  The old implementation reads all 3 super blocks, and also one
  non-existing backup.
  This is not correct, especially if there is another filesystem created
  on the device but old superblocks are not rewritten.

  Just like kernel, we only check the primary super block.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
[trini: Change error to be a define in compat.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-07 20:57:27 -04:00
Qu Wenruo
565a4147d1 fs: btrfs: Add more checksum algorithms
This mostly crossports crypto/hash.[ch] from btrfs-progs.

The differences are:
- No blake2 support
  No blake2 related library in U-Boot yet.

- Use uboot xxhash/sha256 directly
  No need to implement the code as U-Boot has already provided the
  interface.

This adds the support for the following csums:
- SHA256
- XXHASH

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Qu Wenruo
3b4b40c0d6 fs: btrfs: Sync btrfs_btree.h from kernel
This version includes all needed on-disk format from kernel.

Only need to modify the include headers for U-Boot, everything else is
untouched.

Also, since U-Boot btrfs is using a different endian convert timing (at
tree block read time), it needs some forced type conversion before
proper crossport.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 20:57:27 -04:00
Tom Rini
314b9b4a38 Merge branch 'remove-config-nr-dram-banks-v9-2020-08-26' of https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next 2020-09-07 14:31:00 -04:00
Tom Rini
96d66a9b8c Prepare v2020.10-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-07 14:17:33 -04:00
Tom Rini
a475ad7f9e configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-07 14:05:55 -04:00
Tom Rini
06193ca210 Merge tag 'efi-2020-10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc4

Bug fixes are provided in the following areas:

* convert file system debug and print messages go log messages
* convert UEFI booting messages to log messages
* UEFI related code clean up and simplification
2020-09-07 08:49:50 -04:00
Heinrich Schuchardt
d2a885720b efi_selftest: simplify Makefile
CONFIG_EFI_LOADER cannot be selected for ARMv7-M CPUs. So don't check it in
the Makefile.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-06 21:21:41 +02:00
Heinrich Schuchardt
578d7cc8fa efi_loader: remove duplicate image size check
The image size is checked in efi_load_pe(). Avoid checking it twice.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-06 21:21:41 +02:00
Heinrich Schuchardt
5b94e26f1a efi: clean up efi command
* Eliminate superfluous enum value EFI_TABLE_END.
* Use correct variable type for the memory type.
* Check validity of memory type.
* Make efi_build_mem_table static.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-06 21:21:41 +02:00
Heinrich Schuchardt
0f7878b853 efi_loader: error message if image not authenticated
Currently if the bootefi command fails due to missing authentication, the
user gets no feedback.

Write a log message 'Image not authenticated' if LoadImage() fails due to
missing authentication.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-06 21:21:41 +02:00
Heinrich Schuchardt
24586059d3 efi_loader: log function in image loader
Use log_err() for error messages.
Replace debug() by EFI_PRINT().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-06 21:21:41 +02:00
Heinrich Schuchardt
c2f010393b efi_loader: log messages for bootefi command
Write log messages when booting via the bootefi command to allow tracking
on the syslog server. Example messages are

    Booting /snp.efi

or

    Booting /MemoryMapped(0x0,0x4fe00000,0x35a40)
    Loading image failed

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-06 21:21:41 +02:00
Heinrich Schuchardt
0d32d8cf9d fs: convert error and debug messages to log
Use log functions for error and debug messages of the file-system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-06 21:21:41 +02:00
Tom Rini
e5df264e7a Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix SATA issue on Armada 3720
- Enable more SPI NOR chips in espressobin defconfig
2020-09-04 10:09:14 -04:00
Konstantin Porotchkin
3e5420e99a defconfig: espressobin: Add support for ISSI SPI flashes
Enable support of ISSI SPI flashes found on EspressoBIN boards

Change-Id: I6de61c48f108fb4f410f321b9db45887d23212e5
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/61455
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-04 14:02:00 +02:00
Konstantin Porotchkin
2f8cfd030e defconfig: espressobin: Include support for Gigadevice SPI
Include support for CONFIG_SPI_FLASH_GIGADEVICE for supporting
newly produces EspressoBin boards (v7)

Change-Id: I5d4b972cbe2ee5a9d52ce9908794ad4e1b59ee3b
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/61236
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-04 14:02:00 +02:00
zachary
7757c85199 phy: marvell: a3700: add sata comphy on lane 2 with invert option
- This patch moves sata phy powerup from dedicate phy to compphy
  and adds invert option for sata powerup routine.

Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90
Signed-off-by: zachary <zhangzg@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/53601
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: Igal Liberman <igall@marvell.com>
[a.heider: adapt to mainline]
Signed-off-by: Andre Heider <a.heider@gmail.com>
Tested-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-04 14:02:00 +02:00
Tom Rini
9bfb567e5f Merge branch 'master' of git://git.denx.de/u-boot-usb
- Mostly DFU fixes and r8152 fixes
2020-09-03 09:48:28 -04:00
Tom Rini
7f4d3c0445 Merge branch 'master' of git://git.denx.de/u-boot-sh
- SH serial bugfix
2020-09-03 09:00:35 -04:00
Tom Rini
f766e8bced Merge branch 'for-tom' of https://github.com/lftan/u-boot
- SoCFPGA bugfix
2020-09-03 08:59:16 -04:00
Chee Hong Ang
6b6307ed22 arm: socfpga: soc64: Check FPGA Config status register before bridge reset
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-09-03 11:26:07 +08:00
Tom Rini
7149077353 Azure/GitLab: Update to latest Docker container
- New base snapshot
- Fix for high UID/GID numbers on a toolchain

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-02 09:22:29 -04:00
Tom Rini
502f0489f1 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Fix parsing of "mtrr list" command
- Introduce USE_EARLY_BOARD_INIT option and remove dead codes for most
  x86 boards
2020-09-01 11:02:54 -04:00
Gary Bisson
293a6dfeb9 fastboot: getvar: fix partition-size return value
The size returned by 'getvar partition-size' should be in bytes, not in
blocks as fastboot uses that value to generate empty partition when
running format [1].

Note that the function was already returning the proper size in bytes
for NAND devices (see struct part_info details).

[1]
https://android.googlesource.com/platform/system/core/+/refs/heads/android10-release/fastboot/fastboot.cpp#1500

Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
2020-09-01 14:47:43 +02:00
yurii.pidhornyi
64af06ce91 fastboot: Fix fastboot reboot fail by changing functions order
It was revealed that when the fastboot_tx_write_str function is called
without the previously initialized fastboot_func->in_req->complete field,
a copy of in_req will be sent to the I/O requests queue without
an initialized field.

Moving a piece of code with the initializing of the
fastboot_func->in_req->complete field above transmit_tx allows to solve
this problem.

Fixes: 65c96757fe "usb: fastboot: Convert USB f_fastboot to shared fastboot"
Signed-off-by: yurii.pidhornyi <yurii.pidhornyi@globallogic.com>
2020-09-01 14:47:43 +02:00
Sherry Sun
405217a033 f_sdp: Change bInterval of interrupt endpoint to 3
Since the USB HID limits the maximum bandwidth(3072) for interrupt
endpoint transfers, when the bInterval set to 1, we can only support 3
boards to run sdp at the same time. In order to support more boards,
change the bInterval of interrupt endpoint to 3, which will not affect
the transmission speed.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-01 14:47:43 +02:00
Sherry Sun
9e06c5c55a f_sdp: Add EP1_OUT as default data receive pipe in sdp
EP0 has been used to transfer file data in sdp before, but the max
packetsize of ep0 is 64 bytes. So in order to improve the file transfer
speed, here add the EP1_OUT interrupt endpoint which max packetsize is
set to 1024 byte.

After testing, it turns out that using ep1out is twice as fast as using
ep0 while receiving data in sdp.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-01 14:47:43 +02:00
Peng Fan
27c803848b spl: add g_dnl_get_board_bcd_device_number
Add g_dnl_get_board_bcd_device_number, the new BCD value is used by uuu to distinguish
if the SPL supports the SDPV.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-09-01 14:47:43 +02:00
Peng Fan
b0e9f3e593 f_sdp: Support searching and loading FIT or container image
Add support to f_sdp to search and load iMX8 container image or iMX8M
FIT image by new UUU command SDPV.

When using the SDPV, the uuu will continue to send out data after first
level boot loader used by ROM. This means uuu won't skip to the offset
of the second boot loader, and the padding data before second boot loader
will be sent out. So we have to search the FIT header or container header
in the buffer that SDP received.

Also change to more common method to exit f_sdp handler not depending on
SPL_FIT_FOUND flag because container loader won't set this.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-01 14:47:43 +02:00
Ye Li
5dee7f0b02 f_sdp: Fix wrong usb request size
Because the buffer length of sdp usb request is 65, we have to allocate
65 bytes not 64 bytes. Otherwise there is potential buffer overflow.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-09-01 14:47:43 +02:00
Ye Li
d10d429112 f_sdp: Add high speed endpoint descriptor
Add HS endpoint descriptor for SDP. So that we can use high speed endpoint,
and the SDP device can send packet with 512 byte size.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-09-01 14:47:43 +02:00
Frank Li
0ced2faba0 sdp: call board_usb_init at spl_sdp_load_image
Need initialize UDC before run sdp download

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-01 14:47:43 +02:00
Jassi Brar
7ed4eac43d usb: max3420: add the gadget driver
MAX3420 implements FullSpeed USB Device over SPI.
Another version MAX3421, also implements USB Host mode.
This driver should be good for the device mode of max3421 as well.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-09-01 14:47:43 +02:00
Roman Kovalivskyi
0ebf9842e5 fastboot: Add default fastboot_set_reboot_flag implementation
Default implementation of fastboot_set_reboot_flag function that depends
on "bcb" commands could be used in general case if there are no need to
make any platform-specific implementation, otherwise it could be
disabled via Kconfig option FASTBOOT_USE_BCB_SET_REBOOT_FLAG.

Please note that FASTBOOT_USE_BCB_SET_REBOOT_FLAG is mutually exclusive
with some platforms which already have their own implementation of this
function.

Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
2020-09-01 14:47:43 +02:00
Roman Kovalivskyi
2b2a771b40 fastboot: Add support for 'reboot fastboot' command
Android 10 adds support for dynamic partitions and in order to support
this userspace fastboot must be used[1]. New tool fastbootd is
included into recovery.

Userspace fastboot works from recovery and is launched if:
1) - Dynamic partitioning is enabled
2) - Boot control block has 'boot-fastboot' value into command field
The bootloader is expected to load and boot into the recovery image
upon seeing boot-fastboot in the BCB command. Recovery then parses the
BCB message and switches to fastbootd mode[2].

Please note that boot script is expected to handle 'boot-fastboot'
command in BCB and load into recovery mode.

Bootloader must support 'reboot fastboot' command which should reboot
device into userspace fastboot to accomodate those changes[3].

Another command that bootloader must support[3] is 'reboot recovery'. This
command should simply reboot device into recovery mode.

[1] - https://source.android.com/devices/bootloader/fastbootd
[2] - https://source.android.com/devices/bootloader/fastbootd#unified_fastboot_and_recovery
[3] - https://source.android.com/devices/bootloader/fastbootd#modifications_to_the_bootloader

Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Change-Id: I9d2bdc9a6f6f31ea98572fe155e1cc8341e9af76
2020-09-01 14:47:43 +02:00
Roman Kovalivskyi
851737ab89 fastboot: Extend fastboot_set_reboot_flag with reboot reason
Extend fastboot_set_reboot_flag arguments with reboot reason so that
it could handle different reboot cases in future.

Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
2020-09-01 14:47:43 +02:00
Heinrich Schuchardt
73f4ebb659 dfu: fix dfu tftp on sandbox
The environment variable loadaddr is in the virtual address space of the
sandbox. To get the actual memory address where the FIT image has been
loaded we have to convert this address according to the memory mapping of
the sandbox.

Equally the addresses in the *.its file have to be converted when used in
the dfu_ram driver.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-01 14:47:43 +02:00
Heinrich Schuchardt
9337037518 configs: qemu: enable dfu testing
For testing automated updates via dfu and mtd we need the dfu and mtd
commands as well as preboot support.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-01 14:47:43 +02:00
Heinrich Schuchardt
40c79420d0 dfu: DFU_MTD depends on CMD_MTDPARTS
Function mtdparts_init() is needed for the DFU MTD driver.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-01 14:47:43 +02:00
Heinrich Schuchardt
4e620eb98b dfu: fix typo parameteres
%s/parameteres/parameters/g

Even if a line exceeds 80 characters we should not split output strings
to make debugging easier.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-01 14:47:43 +02:00
Filip Brozovic
a17c0cb85e fastboot: Support defining raw partitions without a partition table
Add support for defining raw fastboot partitions in eMMC by specifying
the offset and size in an environment variable. Optionally, the eMMC
hardware partition number may also be specified.

This makes it possible to e.g. update only part of the eMMC boot
partition, instead of having to write the entire partition.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2020-09-01 14:47:43 +02:00
Ye Li
1468a1cc72 usb: ci_udc: Add function to remove usb device
When unregister gadget driver in ci_udc, the usb device is not
removed or stop. This causes next "usb start" fails to work.

Add a new interface "usb_remove_ehci_gadget" in usb-uclass to
remove the usb device for DM driver. Using "usb_lowlevel_stop" for
non-DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-01 14:47:43 +02:00
Ye Li
213fa47dac usb: gadget: Fix controller index in UMS
The usb mass storage (f_mass_storage.c) uses fixed usb index 0,
this causes problem while CDNS3 USB controller index is 1.
Modify the API of fsg to pass the controller index.

Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-01 14:47:43 +02:00
Hayes Wang
3a41086f6a eth/r8152: support RTL8153B/RTL8154B
This is used to support RTL8153B and RTL8154B.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-09-01 14:47:36 +02:00
Hayes Wang
9f6142aa0a eth/r8152: modify rtl_clear_bp function
The original rtl_clear_bp() is used to clear the firmware of both
PLA and USB MCU. The new one could clear the firmware of PLA or
USB independently. It is unnecessary to clear firmware, if there
is no one to be updated.

Besides, clear the firmware by writing the relative registers in
bulk.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-09-01 14:47:36 +02:00
Hayes Wang
16b9417b6a eth/r8152: reset PHY after setting it
Some settings of PHY have to work after resetting PHY.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-09-01 14:47:36 +02:00
Hayes Wang
d74a76234f eth/r8152: reset bmu after disabling Tx/Rx
Reset bmu after disabling Tx/Rx. This is used to clear the FIFO of
Tx/Rx. The remained data may be transferred after Tx/Rx is re-enabled.
And it results in garbage data.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-09-01 14:47:36 +02:00
Marek Vasut
f5ba5c90d4 serial: sh: Improve FIFO empty check on RX
If the SCIF is receiving data quickly enough, it may happen that the
SCxSR_RDxF flag is cleared in sh_serial_getc_generic(), while the
FIFO still contains data. If that happens, the serial_getc_check()
reports no data in the FIFO as the flag is no longer set. Add one
more check, if the SCxSR_RDxF is not set, read out the FIFO level
and if there are still characters in the FIFO, permit reading them
out.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-09-01 14:46:41 +02:00
Simon Glass
1150a0b6bd x86: Drop nhlt_serialise()
This function is not actually used in U-Boot. Drop it.

Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 17:00:28 +08:00
Simon Glass
0a0cdeceec x86: pinctrl: Fix 'relatove' typo
Fix this typo in the Kconfig help.

Suggested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 17:00:27 +08:00
Andy Shevchenko
365a581c1c x86: qemu: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply replace the rule in it. We use stub C-file
like it's done for other boards.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 17:00:27 +08:00
Andy Shevchenko
c2addf9fc1 x86: intel: slimbootloader: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:41 +08:00
Andy Shevchenko
886bce1275 x86: intel: minnowmax: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:41 +08:00
Andy Shevchenko
9278031ae5 x86: intel: galileo: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:41 +08:00
Andy Shevchenko
b2253bcaa7 x86: intel: edison: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:40 +08:00
Andy Shevchenko
e5de5e0625 x86: intel: crownbay: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:40 +08:00
Andy Shevchenko
41a93718d8 x86: intel: cougarcanyon2: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:40 +08:00
Andy Shevchenko
d196c18bc8 x86: intel: cherryhill: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:39 +08:00
Andy Shevchenko
a97e6af422 x86: intel: bayleybay: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:39 +08:00
Andy Shevchenko
2a2470eba8 x86: efi: efi-x86_payload: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:39 +08:00
Andy Shevchenko
9f082a8adc x86: dfi: dfi-bt700: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:39 +08:00
Andy Shevchenko
85759d04cf x86: coreboot: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:38 +08:00
Andy Shevchenko
ebb2818bcb x86: congatec: conga-qeval20-qa3-e3845: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:38 +08:00
Andy Shevchenko
45e2340d53 x86: advantech: som-db5800-som-6867: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.

Cc: George McCollister <george.mccollister@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:38 +08:00
Andy Shevchenko
1d01d0c2f0 x86: Introduce USE_EARLY_BOARD_INIT option
Introduce USE_EARLY_BOARD_INIT option and select it by the actual users.

Cc: George McCollister <george.mccollister@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:38:31 +08:00
Wolfgang Wallner
cf9f38064d x86: mtrr: Fix parsing of "mtrr list" command
The command 'mtrr' does not recognize the 'list' subcommand any more
since the code restructuring in commit b2a76b3fe7 ("x86: mtrr:
Restructure so command execution is in one place").

The if-else parsing the command arguments does not take 'list' into
account: the if-branch is intended for no subcommands, the else-branch
is intended for the non-list subcommands (which all expect additional
arguments). Calling the 'mtrr list' subcommand leads to a "return
CMD_RET_USAGE" in the else-branch.

Fix this by changing the else-branch to explicitly checking for
if (cmd != 'l').

Fixes: b2a76b3fe7 ("x86: mtrr: Restructure so command execution is in one place")
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01 13:24:45 +08:00
Masahiro Yamada
23e333a5c0 MAINTAINERS: step down as maintainer of UniPhier SoCs
I am leaving Socionext. Orphan the UniPhier platform until somebody
takes the role.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-31 17:11:24 -04:00
Tom Rini
6ade057e37 Merge tag 'ti-v2020.10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Update to ABI 3.0
- Fix i2c write in eeprom driver
2020-08-31 13:06:26 -04:00
Tom Rini
123f4f84f8 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- MVEBU Espressobin fixes and enhancements (fix switch security
  issue, enable MVNETA, enable SD-card, fix COMPHY nodes, default
  env variables, etc)
- MMC Xenon: Set signal voltage and max base clock
- a37xx PCI driver: Depend on DM_GPIO and remove #ifdef's
2020-08-31 09:43:13 -04:00
Pali Rohár
64430efe69 arm: mvebu: Espressobin: Update README.marvell file
Include information about permanent ethernet MAC address and add link how
to build ATF as U-Boot on Espressobin cannot be flashed without ATF.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-31 14:45:53 +02:00
Pali Rohár
6b61066210 arm: mvebu: Espressobin: Define fdt_addr and kernel_addr env aliases
Boot scripts for existing Espressobin Linux distributions, like OpenWRT,
expect that U-Boot set fdt_addr and kernel_addr envs. So add env aliases
from fdt_addr_r and kernel_addr_r values.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
996ecfd3ec arm: mvebu: Espressobin: Change default loadaddr
Current loadaddr is not writable on Espressobin and 'loadb' command cause
rebooting board. Marvell's U-Boot already set default loadaddr to value
0x06000000 [1] and after this change 'loadb' is working fine.

[1] - 0a5b159806

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
bb40fe1f6c arm: mvebu: Espressobin: Move env load addresses
According to Marvell's U-Boot description [1] current env load addresses
overlaps with ATF RT services region and TEE. Because the ATF RT service
and TEE region is going to be marked as secure and can't be overwritten,
use different different addresses for envs.

[1] - 0a5b159806

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-31 14:45:53 +02:00
Pali Rohár
835d969c1f arm64: a37xx: pci: Depends on DM_GPIO
For proper initialization of aardvark pci driver it is required to
de-assert reset GPIO. So depeneds on DM_GPIO option.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
a65e65939e arm: mvebu: Espressobin: Setup MTD partitions when booting kernel
Due to different partition layouts in different U-Boot versions, DTS for
Espressobin in Linux does not contain any definition of MTD partitions.
See commit https://git.kernel.org/stable/c/00954566464a4 for more details.

This patch via ft_board_setup() hook fills current partition layout used by
U-Boot, so booted kernel would see correct MTD partitions layout.

U-Boot env partition is calculated from CONFIG_ENV_OFFSET option.

First partition contains secure firmware, ARM trusted firmware and U-Boot
with checksums. So it is not possible to replace just one image (e.g.
U-Boot) without updating other parts where is stored checksum of U-Boot.
Therefore there is no extra partition defined for U-Boot and first
partition is called just 'firmware'.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
4366082bfe arm: mvebu: Espressobin: Make SPI env offset compatible with Marvell's U-Boot
Espressobin board comes with Marvell's U-Boot version where U-Boot env is
stored in SPI at offset 0x3F0000. This patch changes env offset in
Espressobin defconfig file to match Marvell's U-Boot version.

Users who want to use previous or different env offset can still change it
in .config file when compiling U-Boot.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Wilson Ding
96fa3c4fda arm: dts: a37x0: enable sd card support on espressobin
Enabled SDIO slot 0 (south bridge) for SD card on
Espressobin board.

Change-Id: I51a2debf9fba276b9c4a2bc6da91328d47f443e3
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/60945
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
[pali: Define cd-gpios and enable CONFIG_DM_REGULATOR_GPIO]
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Evan Wang
91b85e25b6 mmc: xenon: set signal voltage and max base clock
- The SDIO signal voltage and max base clock frequency
  setting are missing in driver, which causes SDIO
  not working.
- The patch adds SDIO signal voltage switch support,
  which is based on regulator-gpio of vqmmc-supply, and
  sets the max base clock frequency.
- Fix the zero clock value in call to sdhci_setup_cfg()
  function.

Change-Id: I79c8860c65b8db166f4f70db56ede4097f71f1fa
Signed-off-by: Evan Wang <xswang@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/53589
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: Hua Jing <jinghua@marvell.com>
[pali: Amended fixup patch]
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
828d326216 arm64: a37xx: pci: Assert PERST# signal when unloading driver
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.

DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.

Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.

Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
563b85bd88 arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Marek Behún
545591132a arm64: dts: armada-3720-espressobin: fix COMPHY nodes
This commit fixes initialization of COMPHY on EspressoBin.

Commit 22f418935b ("phy: marvell: a3700: Use comphy_mux on Armada
37xx.") introduced usage of comphy_mux on Armada 37xx comphy driver.
The lanes are defined in comphy_a3700.c as described in functional
specification, that is:
  lane 0 is SGMII1 or USB3
  lane 1 is PCIe or SGMII0
  lane 2 is SATA or USB3

But the DTS for EspressoBin configures PCIe on lane 0 and USB3 on
lane 1, which is wrong in the sense of the specification and doesn't
work with the comphy_mux code, which is 2 years now (the aardvark driver
causes synchronous abort in U-Boot).

It worked till the above mentioned commit, because the code for powering
up PCIe PHY doesn't work with lane number at all, and the code for
powering up USB3 PHY works differently only if USB3 is on lane 2, ie.
the check goes like:
  if (lane == 2)
    something
  else
    something else
so it does not differentiate between lanes 0 and 1.

In the future I shall post patches that remove the comphy_a3700 driver
and add comphy driver which uses calls to ATF, like Linux' driver does.
This will have the advantage of same DTS bindings as Linux', but till
this is done, we need this patch.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Pali Rohár <pali@kernel.org>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
a68676535f arm: mvebu: Espressobin: Enable CONFIG_MVNETA
Espressobin uses mvneta ethernet driver.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:45:53 +02:00
Pali Rohár
48f2c8a37f arm: mvebu: Espressobin: Disallow forwarding packets between wan and lan ports
By default Topaz switch on Espressobin board forwards packets between all
ethernet ports, including CPU (port 0), wan (port 1) and lan (ports 2,3).

This default U-Boot setup is unsuitable for using Espressobin as router as
it opens security hole in forwarding all packets between wan and lan ports.
E.g. dhcp packets from wan network leaks to lan network during small time
window until U-Boot boots Linux kernel which loads network drivers which
disallows forwarding between wan and lan.

This patch fixes above problem. For Espressobin board prior putting Topaz
switch into forwarding mode, Topaz switch is reconfigured to allow
forwarding packets from wan and lan ports only to CPU port. This ensures
that packets from wan port are not forwarded to lan ports and vice-versa.
Packets from CPU port are still forwarded to all other ports, so U-Boot
network boot works with any ethernet port as before.

This problem was already discussed on Espressobin forum [1] and on
Marvell's github issue tracker [2]. As a workaround people on Espressobin
forum patched U-Boot to completely disable lan ports on Topaz switch which
prevented forwarding packets. That workaround had an issue that U-Boot was
unable to netboot via lan ports anymore. Change in this patch does not have
such issue.

This security issue has been dicussed here as well: [3].

[1] - https://web.archive.org/web/20191231164238/http://espressobin.net/forums/topic/boot-behavior-of-the-switch-and-security/
[2] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/issues/18
[3] - https://forum.armbian.com/topic/12635-espressobin-uboot-security-concerns-switch-init-portmask/

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31 14:44:14 +02:00
Michal Simek
b892b6d1e0 ti: common: Remove additional i2c read for board detection
There shouldn't be a need to call additional i2c read if above failed
already. Based on comment it should be enough to try to detect legacy
boards which are mentioned in the comment.

Fixes: 2463f6728e ("ti: common: board_detect: Allow DM I2C without CONFIG_DM_I2C_COMPAT")
Fixes: 0bea813d00 ("ARM: omap-common: Add standard access for board description EEPROM")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-31 14:40:28 +05:30
Lokesh Vutla
e66ae8e16b arm: dts: k3-am65: Update the RM resource types
Update the ringacc and udma dt nodes to use the latest RM resource types
similar to the ones used in k3-j721e dt nodes.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-31 14:39:39 +05:30
Lokesh Vutla
4986b15485 firmware: ti_sci: Drop unused structure ti_sci_rm_type_map
struct ti_sci_rm_type_map is no longer used. Drop its definition and its
declarations.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-31 14:39:39 +05:30
Lokesh Vutla
2fe03a1c82 firmware: ti_sci: drop the device ids to resource id translation table
With ABI 3.0, sysfw deprecated special resource types used for AM65x
SoC. Instead started using device id as resource type similar to the
convention used in J721E SOC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-31 14:39:38 +05:30
Tom Rini
9f04a634ef Merge branch '2020-08-27-misc-fixes'
- Fix for gd->ram_top and bootm_size calculations
- Assorted Kconfig entry cleanups / fixes.
- Make checkpatch.pl error on fdt_high/initrd_high=0xffffffff
- Resync scripts/setlocalversion
- Other minor bugfixes
2020-08-28 08:51:37 -04:00
Rasmus Villemoes
2ed1b242ab scripts/setlocalversion: sync with linux 5.8
The linux changes since v3.16 are

78283edf2c01 kbuild: setlocalversion: print error to STDERR
b24413180f56 License cleanup: add SPDX GPL-2.0 license identifier to files with no license
6147b1cf1965 scripts/setlocalversion: git: Make -dirty check more robust
8ef14c2c41d9 Revert "scripts/setlocalversion: git: Make -dirty check more robust"
ff64dd485730 scripts/setlocalversion: Improve -dirty check with git-status --no-optional-locks
7a82e3fa28f1 scripts/setlocalversion: clear local variable to make it work for sh
991b78fbd223 scripts: setlocalversion: fix a bashism
3c96bdd0ebfa scripts: setlocalversion: replace backquote to dollar parenthesis

and it's ff64dd485730 that is the motivation for this sync. It fixes
false positive "-dirty" added to the version string when building with
Yocto
(https://lists.openembedded.org/g/openembedded-core/message/137702).

There has been one U-Boot specific patch since this was synced with
linux 3.16: 81630a3b38 (scripts: setlocalversion: safely extract
variables from auto.conf using awk).  Keep these changes applied.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
[trini: Re-add 81630a3b38 and reword message]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-27 15:55:18 -04:00
Baruch Siach
7f98b4eeee image: don't exceed gd->ram_top in bootm_size
When board_get_usable_ram_top() limits gd->ram_top, env_get_bootm_size()
must not exceed that limit. Otherwise, boot_relocate_fdt() might put fdt
out of the allowed RAM range.

The similar commit 8ce1f10cf2 ("ARM: bootm: take into account
gd->ram_top") exposed this bug.

This fixes boot on Armada 8040 based Clearfog GT-8K where ram_top is set
to 0x80000000 (2GB), but bi_dram[0].size might be up to 0xc0000000
(3GB). Note the relocated fdt address (0xbfff4000) in the console output
listed below:

Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
62 bytes read in 21 ms (2 KiB/s)
1:	linux
Retrieving file: /extlinux/Image
13740544 bytes read in 1266 ms (10.4 MiB/s)
Retrieving file: /extlinux/armada-8040-clearfog-gt-8k.dtb
33368 bytes read in 31 ms (1 MiB/s)
   Booting using the fdt blob at 0x4f00000
   Loading Device Tree to 00000000bfff4000, end 00000000bffff257 ... "Synchronous Abort" handler, esr 0x96000045
elr: 000000000006e1cc lr : 0000000000068fd8 (reloc)
elr: 000000007ffa91cc lr : 000000007ffa3fd8
x0 : ffffffffffffffff x1 : 00000000bfffc258
x2 : 0000000000000000 x3 : ffffffffffff7da7
x4 : 0000000004f08258 x5 : 00000000bfff4000
x6 : 00000000bfff4000 x7 : 000000000000000f
x8 : 000000007fb23bf8 x9 : 0000000000000008
x10: 00000000bffff257 x11: 00000000bffff257
x12: 0000000000000000 x13: fffffffffffff000
x14: 00000000bfff4000 x15: 0000000000000021
x16: 000000007ff7bc38 x17: 0000000000000000
x18: 000000007fb2add0 x19: 00000000bfff4000
x20: 0000000004f00000 x21: 000000000000b258
x22: 0000000058820000 x23: 0000000000000010
x24: 000000007ffe3c40 x25: 000000007fb23cb8
x26: 00000000c0000000 x27: 0000000000000000
x28: 000000007fc3fd50 x29: 000000007fb23bd0

Code: 54000061 aa0603e0 d65f03c0 38606882 (38206822)
Resetting CPU ...

Thanks to Patrice CHOTARD who directed me to the right way.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-08-27 11:26:58 -04:00
Michal Simek
0b2b9b85d0 cmd: mem: Remove already removed CONFIG_SYS_MEMTEST_SCRATCH
The commit e519f03a18 ("cmd: mem: Remove CONFIG_SYS_MEMTEST_SCRATCH
mapping") removed CONFIG_SYS_MEMTEST_SCRATCH but commit 0914011310
("command: Remove the cmd_tbl_t typedef") has added it back. That's why
symbol is still in the tree that's why remove it again.

Fixes: 0914011310 ("command: Remove the cmd_tbl_t typedef
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-27 11:26:58 -04:00
Heinrich Schuchardt
de95930946 lib/rsa: correct check after allocation in fdt_add_bignum()
After allocating to pointer ctx we should check that pointer and not
another pointer already checked above.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-27 11:26:58 -04:00
Heinrich Schuchardt
4431a9889c test: undefined reference to 'sscanf'
Compiling with CONFIG_UNIT_TEST=y leads to:

aarch64-linux-gnu-ld.bfd:
test/lib/sscanf.c:50: undefined reference to `sscanf'

Add missing build dependency.

Fixes:e87dfb0526be ("lib: sscanf: add sscanf implementation")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-27 11:26:58 -04:00
Tom Rini
12178b51c2 checkpatch.pl: Make fdt / initrd relocation disabling an error
Entirely disabling relocation of the device tree or initrd is almost
never the right answer.  Doing this by default leads to hard to diagnose
run-time failures.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-27 11:26:58 -04:00
Michal Simek
076617847a env: Kconfig: Add missing dependency for ENV_IS_IN_EXT4
ENV_IS_IN_EXT4 also need to enable FS_EXT4 which is not covered in Kconfig.
Kconfig reports this as:
WARNING: unmet direct dependencies detected for EXT4_WRITE
  Depends on [n]: FS_EXT4 [=n]
  Selected by [y]:
  - ENV_IS_IN_EXT4 [=y] && !CHAIN_OF_TRUST [=n]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-27 11:26:58 -04:00
Michal Simek
7b56432c7b arc: Kconfig: Add missing DM dependency
ARC is selecting TIMER which depends on DM but DM is not selected and
doesn't need to be enabled. Fix it by selecting DM for ARC architecture.

Kconfig is showing this missing dependency by:
WARNING: unmet direct dependencies detected for TIMER
  Depends on [n]: DM [=n]
  Selected by [y]:
  - ARC [=y] && <choice>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-27 11:26:58 -04:00
Michal Simek
6e741cfa93 cmd: Kconfig: Change dependency for CMD_ADC
CMD_ADC selected DM_REGULATOR unconditionally without enabling DM.
That's why change select to depends on to cover it.

Kconfig is showing this issue as:
WARNING: unmet direct dependencies detected for REGMAP
  Depends on [n]: DM [=n]
  Selected by [y]:
  - DM_REGULATOR_PBIAS [=y] && DM_REGULATOR [=y]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Update CMD_ADC=y configs to enable DM_REGULATOR now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-27 11:26:39 -04:00
Michal Simek
a261fdce38 pci: kconfig: Setup proper dependency for PCIE_ROCKCHIP
There is missing dependency for PCIE_ROCKCHIP which selects
PHY_ROCKCHIP_PCIE which directly depends on ARCH_ROCKCHIP.

WARNING: unmet direct dependencies detected for PHY_ROCKCHIP_PCIE
  Depends on [n]: ARCH_ROCKCHIP [=n]
  Selected by [y]:
  - PCIE_ROCKCHIP [=y] && PCI [=y]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-27 11:20:33 -04:00
Ruben Di Battista
67e62c7468 drivers: usb: Fix config indentation
The indentation was messing up with the scripts/build-whitelist.sh that
was marking SYS_USB_EVENT_POLL_VIA_INT_QUEUE (and probably also the
other indented options) erroneously as ad-hoc configure option with the
following error:

```
Error: You must add new CONFIG options using Kconfig
The following new ad-hoc CONFIG options were detected:
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
```
2020-08-27 11:20:33 -04:00
Tom Rini
f87c80ade3 Prepare v2020.10-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-26 17:30:22 -04:00
Tom Rini
d86bf9124f configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-26 17:26:24 -04:00
Stefan Roese
bac9da46c5 asm-generic/u-boot.h: Remove bi_memstart & bi_memsize from bd_info
bi_memstart & bi_memsize are now not referenced any more. This patch
removes their definitions from the bd_info struct.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-26 09:20:05 +02:00
Stefan Roese
60ebf5fb4e cmd: bdinfo: Remove print of superseeded bi_memstart / bi_memsize values
Remove printing of the superseeded (by bi_dram[]) memory values from the
bdinfo command.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-26 09:20:00 +02:00
Stefan Roese
e516404ee5 powerpc: Remove bi_memstart & bi_memsize assignments in spl.c
Most likely these deprecated (removed) variables are not needed. Lets
remove the assignments completely from all spl.c files.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Oleksandr Zhadan and Michael Durrant
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-26 09:19:54 +02:00
Stefan Roese
063d547cac video: cfb_console.c: Use bi_dram[] values on all platforms
All platforms support bi_dram[] since quite some time. Lets remove the
and bi_memsize values completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-26 09:19:50 +02:00
Stefan Roese
0f8d400b1b xtensa: Remove local no-op dram_init_banksize()
When this no-op dram_init_banksize() is removed, the weak default will
be used instead, which correctly sets the bi_dram[] banksize values.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-26 09:19:45 +02:00
Stefan Roese
b59cc516a1 xtensa: Remove arch_setup_bdinfo()
arch_setup_bdinfo() only configures the deprecated bi_memstart &
bi_memsize values, which should not be needed any more. Lets remove
this file completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-26 09:19:40 +02:00
Stefan Roese
e207f2256f global: Move from bi_memstart/memsize -> gd->ram_base/ram_size
With the planned removal of bi_memstart & bi_memsize, this patch now
moves the references to the better suiting gd->ram_base/ram_size
variables.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-26 09:19:34 +02:00
Stefan Roese
f120aa7522 board_f: Add default values for bi_dram[] in dram_init_banksize()
Remove the bi_memstart / bi_memsize assignment in setup_bdinfo() and
make sure, that bd_dram[] is always configured in the weak default
implementation of dram_init_banksize(), when CONFIG_SYS_SDRAM_BASE is
not set.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-26 09:19:28 +02:00
Stefan Roese
4963f63fe6 image: Use gd->ram_base/_size in env_get_bootm_size()
Use only gd->ram_base/_size in env_get_bootm_size() instead of bi_dram[]
in some cases and bi_memstart in others.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-26 09:19:23 +02:00
Stefan Roese
dfaf6a5797 CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
Since commit 86cf1c8285 ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
commit 999a772d9f ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
It makes no sense to still carry code that is guarded with
"#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
all these unreferenced code paths.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-26 09:19:16 +02:00
Tom Rini
7a1a01c602 Merge tag 'u-boot-imx-20200825' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
For 2020.10
-----------

- mx6: SOCs user selectable
       Fix for imx6q_logic
       Some DM conversion
- mx7: introduce secondary boot device

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/720918010

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-25 23:12:43 -04:00
Tom Rini
9f9ecd3e4d Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel)
- Infrastructure changes to PCI uclass to support these SoC's (Suneel)
- Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel)
- Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
2020-08-25 13:38:29 -04:00
Tom Rini
ec54217ddc Merge tag 'i2c-bugfixes-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c bugfixes for v2020.10
- fix some issues with octeon_i2c driver on ARM Octeon TX2
- fix link failure with CONFIG_SPL and CONFIG_I2C_MUX_PCA954x
2020-08-25 08:19:41 -04:00
Tom Rini
e49a9d4ddb Merge tag 'u-boot-rockchip-20200820' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix rk3399 evb sdcard support
- Fix for SPL_LED support
2020-08-25 08:19:14 -04:00
Tom Rini
078656186f Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Sipeed Maix support S-mode.
- Provide command sbi.
- Use fdtdec_get_addr_size_auto_parent to get fu540 cache base address.
- Fix a compiler error with CONFIG_SPL_SMP=n.
- Fix sifive ram driver 32 compiler warnings.
- Fix kendryte/pll.h redefine nop() warning.
2020-08-25 08:18:50 -04:00
Tom Rini
8ee3a24fdc Merge branch '2020-08-24-misc-improvements'
- Squashfs compression support
- Coverity fixes
- XEN guest updates
- Finish previous MediaTek updates
- Arm Total Compute platform support
2020-08-25 08:12:05 -04:00
Stefan Roese
6944937f9c x86: qemu-x86_defconfig: Increase CONFIG_SYS_MALLOC_F_LEN
With the upcoming increase of the malloc area in U-Boot
("pci: pci-uclass: Dynamically allocate the PCI regions"), the CI QEMU
x86 test fails:

U-Boot 2020.10-rc2-g0a668f6d38 (Aug 25 2020 - 06:12:51 +0000)

alloc space exhausted
Error binding driver 'cpu_qemu': -12
Some drivers failed to bind
alloc space exhausted
initcall sequence fff6a760 failed at call fff13b3d (err=-19)

This patch now increases CONFIG_SYS_MALLOC_F_LEN to 0x1000, which is
already used on qemu-x86_64_defconfig.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 11:37:57 +02:00
Grygorii Tertychnyi
acbc1d86f1 imx8m: config: convert to bootm_size
Restrict the memory range available for image processing in the
"bootm" to 256 MiB so the kernel can access it and FDT or initrd are
not overwritten on ARM64.

Signed-off-by: Grygorii Tertychnyi <grygorii.tertychnyi@leica-geosystems.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-25 10:26:38 +02:00
Adam Ford
74d8f9d562 ARM: imx6q_logic: Fix broken booting by moving fdt_addr_r address
The loading address is too close to the kernel address, so newer kernels
may overlap memory space, so loading the device tree may corrupt zImage.

This patch moves the fdt_addr_r to 0x14000000 which is also consistent
with guidance that the kernel be allocated 32MB.  This places it
in the same place as the ramdisk, so this patch moves the ramdisk address
512KB after the fdt.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-25 10:26:31 +02:00
Fabio Estevam
821a987fec pico-imx6: Remove unneeded CONFIG_DM_MDIO
As explained in the CONFIG_DM_MDIO text inside drivers/net/Kconfig:

"Useful in particular for systems that support
DM_ETH and have a stand-alone MDIO hardware block shared by multiple
Ethernet interfaces."

i.MX6 has a single FEC instance, so there is no need to select
CONFIG_DM_MDIO.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-08-25 10:26:24 +02:00
Tom Rini
f27ffe4177 arm: mx6: Make all i.MX6 SoCs user-selectable
We have a number of platforms that are a combination of a carrier board
and System-on-Module (SoM) that in turn allows for the board to have
different SoCs on it.  In some cases, this is handled via board-specific
Kconfig options.  In other cases we make use of
CONFIG_SYS_EXTRA_OPTIONS.  This latter case however can lead to invalid
configurations as we will not in turn get options that in Kconfig are
selected by or depend on that setting.

To resolve this, make the SoC option a choice in Kconfig and make boards
depend on what they can support.  This change opens us up for further
clean-ups in the cases where a single CONFIG_TARGET_xxx can support
different SoCs and today they do not, or do not cleanly do so.

Reported-by: Matt Porter <mporter@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Soeren Moch <smoch@web.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de>
Cc: Ludwig Zenz <lzenz@dh-electronics.de>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Akshay Bhat <akshaybhat@timesys.com>
Cc: Ken Lin <Ken.Lin@advantech.com.tw>
Cc: Ian Ray <ian.ray@ge.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Cc: Simone CIANNI <simone.cianni@bticino.it>
Cc: Adam Ford <aford173@gmail.com>
Cc: Marcin Niestroj <m.niestroj@grinn-global.com>
Cc: "Eric Bénard" <eric@eukrea.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Jason Liu <jason.hui.liu@nxp.com>
Cc: Ye Li <ye.li@nxp.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Parthiban Nallathambi <parthiban@linumiz.com>
Cc: Marek Vasut <marex@denx.de>
Cc: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Niel Fourie <lusus@denx.de>
Cc: Martyn Welch <martyn.welch@collabora.com>
Cc: Richard Hu <richard.hu@technexion.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Arkadiusz Karas <arkadiusz.karas@somlabs.com>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org>
Cc: Silvio Fricke <open-source@softing.de>
Tested-by: Matt Porter <mporter@konsulko.com> [colibri_imx6]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2020-08-25 10:26:14 +02:00
Suneel Garapati
0a668f6d38 arm: octeontx2: Add support for OcteonTX2 SoC platforms
This patch adds support for all OcteonTX2 96xx/95xx
boards from Marvell.
For 96xx boards, use octeontx_96xx_defconfig and
for 95xx boards, use octeontx_95xx_defconfig.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
03c2288070 arm: octeontx: Add support for OcteonTX SoC platforms
This patch adds support for all OcteonTX 81xx/83xx
boards from Marvell.
For 81xx boards, use octeontx_81xx_defconfig and
for 83xx boards, use octeontx_83xx_defconfig.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
af6ba90048 watchdog: Add reset support for OcteonTX / TX2
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2
platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 08:01:16 +02:00
Suneel Garapati
708598997d mmc: Add MMC controller driver for OcteonTX / TX2
Adds support for MMC controllers found on OcteonTX or
OcteonTX2 SoC platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Peng Fan <peng.fan@nxp.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
638d705a54 pci: Add PCI controller driver for OcteonTX / TX2
Adds support for PCI ECAM/PEM controllers found on OcteonTX
or OcteonTX2 SoC platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
3f6f0cd8fd ata: ahci: Add BAR index quirk for Cavium PCI SATA device
For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0
instead of BAR5.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 08:01:16 +02:00
Suneel Garapati
04cd0a0fa0 arm: octeontx2: Add headers for OcteonTX2
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
387d321add arm: octeontx: Add headers for OcteonTX
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 08:01:16 +02:00
Suneel Garapati
c2f45b6588 arm: include/asm/io.h: Add 64bit clrbits and setbits helpers
Add 64bit API for clrbits and setbits.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 08:01:16 +02:00
Suneel Garapati
f0c369284d pci: pci-uclass: Check validity of ofnode
Add check if the referenced ofnode is valid.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
a3fac3f395 pci: pci-uclass: Add support for Alternate-RoutingID capability
If ARI capability is found on device, use it to update next function
number in bus scan and also helps to skip unnecessary bdf scans.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
51eeae91c5 pci: pci-uclass: Add VF BAR map support for Enhanced Allocation
Makes dm_pci_map_bar API available to map BAR for Virtual function
PCI devices which support Enhanced Allocation.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
b8852dcfcb pci: pci-uclass: Add support for Single-Root I/O Virtualization
SR-IOV - Single Root I/O Virtualization
PF - Physical Function VF - Virtual Function

If SR-IOV capability is present, use it to initialize Virtual Function
PCI device instances. pci_sriov_init function will read SR-IOV
registers to create VF devices under the PF PCI device and also bind
driver if available. This function needs to be invoked from Physical
function device driver which expects VF device support, creating
minimal impact on existing framework.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
636cc1773a pci: pci-uclass: Add support for Enhanced Allocation in Bridges
If Enhanced Allocation capability is present in bridges, use it
to read the fixed sub-ordinate bus number.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
4cf56ec07f pci: pci-uclass: Add multi entry support for memory regions
Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Trommel, Kees (Contractor)
660606091f Link failure with CONFIG_SPL and CONFIG_I2C_MUX_PCA954x
Fix for the case of a U-Boot configuration with CONFIG_SPL,
CONFIG_I2C_MUX, CONFIG_I2C_MUX_PCA954x, no CONFIG_SPL_DM and no
CONFIG_SPL_I2C_MUX. Without this fix linking of pca954x fails because
dm_write_i2c does not exist because CONFIG_SPL_DM is not defined.

Signed-off-by: Kees Trommel <kees.trommel.contractor@draeger.com>
Cc:  Heiko Schocher <hs@denx.de>
2020-08-25 06:25:42 +02:00
Stefan Roese
af03bde0fa i2c: octeon_i2c: Misc fixes for ARM Octeon TX2 support
This patch fixes a few issues noticed, when testing this new driver on
ARM Octeon TX2 again. Here the details:

- Remove "common.h" header inclusion
- Use correct THP define on Octeon TX2
- Octeon TX2 uses the same compatible as Octeon TX. We can't distinguish
  both platforms this way. Remove the unused "cavium,thunder2-99xx-twsi"
  compatible and add a check to the Octeon TX2 specific
  "cavium,thunderx-i2c" so that the correct driver data is selected.
- Removed "struct pci_device_id" definition and U_BOOT_PCI_DEVICE()
  as its not needed for the PCI based probing on Octeon TX2

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-08-25 06:21:23 +02:00
Suneel Garapati
bc30140d20 pci: pci-uclass: Make DT subnode parse optional
Parse subnode DT properties only if parent node is valid.
Otherwise, assert is triggered on ofnode_valid in ofnode_first_subnode
from dev_for_each_subnode.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Suneel Garapati
b3699a13a6 pci: pci-uclass: Fix incorrect argument in map_physmem
Fix argument ordering for map_physmem() called in dm_pci_map_ea_bar().
Additinally minor spelling correction.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Stefan Roese
e002474158 pci: pci-uclass: Dynamically allocate the PCI regions
Instead of using a fixed length pre-allocated array of regions, this
patch moves to dynamically allocating the regions based on the number
of available regions plus the necessary regions for DRAM banks.

Since MAX_PCI_REGIONS is not needed any more, its removed completely
with this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2020-08-25 05:41:09 +02:00
Stefan Roese
65f8c7edd8 ARM: renesas: Drop unnecessary function ft_board_setup()
Marek explained on IRC, that ft_board_setup() is not used / necessary
at all. So its best to just drop it completely, as it interferes with
the cleanup of CONFIG_MAX_PCI_REGIONS (completely removed).

Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 05:41:09 +02:00
Stefan Roese
3b7cd265b8 pci: pci-uclass: Remove #ifdef CONFIG_NR_DRAM_BANKS as its always set
Since the migration to Kconfig, CONFIG_NR_DRAM_BANKS is configured for
all boards. Hence we can remove the conditional compilation and the code
path that will never get compiled.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Stefan Roese
68f81b8575 dm: core: Add API to read PCI bus-range property
Add dev_read_pci_bus_range() to read bus-range property values

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 05:41:09 +02:00
Suneel Garapati
1db7ee464f fdtdec: Add API to read pci bus-range property
Add fdtdec_get_pci_bus_range to read bus-range property
values.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25 05:41:09 +02:00
Heinrich Schuchardt
c92b50a44b cmd: provide command sbi
Provide a command to display information about the SBI implementation.

The output might look like:

=> sbi
SBI 0.2
OpenSBI
Extensions:
  sbi_set_timer
  sbi_console_putchar
  sbi_console_getchar
  sbi_clear_ipi
  sbi_send_ipi
  sbi_remote_fence_i
  sbi_remote_sfence_vma
  sbi_remote_sfence_vma_asid
  sbi_shutdown
  SBI Base Functionality
  Timer Extension
  IPI Extension
  RFENCE Extension
  Hart State Management Extension

The command can be used to construct a unit test checking that the
communication with the SEE is working.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
Tested-by:  Pragnesh Patel <pragnesh.patel@openfive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
2020-08-25 09:34:47 +08:00
Heinrich Schuchardt
27cef4e4a3 configs: defconfig for Sipeed Maix in S-mode
Provide a defconfig that can be used to build U-Boot for the Maix boards
running upon OpenSBI.

Update the documentation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-08-25 09:33:54 +08:00
Heinrich Schuchardt
092f15aee5 riscv: fix building with CONFIG_SPL_SMP=n
Building with CONFIG_SPL_SMP=n results in:

arch/riscv/lib/spl.c: In function ‘jump_to_image_no_args’:
arch/riscv/lib/spl.c:33:6:
error: unused variable ‘ret’ [-Werror=unused-variable]
   33 |  int ret;
      |      ^~~

Define the variable ret as __maybe_unused.

Fixes: 191636e448 ("riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL")
Fixes: 8c59f2023c ("riscv: add SPL support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-08-25 09:33:45 +08:00
Heinrich Schuchardt
183f1e2712 clk: kendryte/pll.h: do not redefine nop()
The kendryte PLL code uses nop as barrier. The macro is not defined for
the sandbox on x86 but is defined on RISC-V.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-25 09:33:35 +08:00
Bin Meng
3ab2601052 ram: sifive: Fix compiler warnings for 32-bit
priv->info.size is of type 'size_t' but the length modifier is l.
Fix this by casting priv->info.size. Note 'z' cannot be used as
the modifier as SPL does not support that.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-08-25 09:33:16 +08:00
Bin Meng
52dc7ae749 riscv: fu540: Use correct API to get L2 cache controller base address
At present fdtdec_get_addr() is used to get L2 cache controller base
address. This only works for a fixed #address-cells and #size-cells.
Change to use fdtdec_get_addr_size_auto_parent() instead.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-08-25 09:33:16 +08:00
Tom Rini
3c0cec035e Merge tag 'efi-2020-10-rc3-3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc3 (3)

The following bug fixes are contained in this pull-request:

* ResetSystem() should no hang if not implemented.
* Device paths in Bootxxxx variables should be verified.
* Use ':' as separator for command setenv -e -i instead of ','.
* Correct comments for functions.
* Update UEFI documentation.
2020-08-24 17:28:18 -04:00
Anastasiia Lukianenko
3337b29144 xen: Code style conformity
Cleaning up the following:

ERROR: do not use assignment in if condition
#281: FILE: drivers/xen/pvblock.c:260:
+       if ((err = xenbus_switch_state(XBT_NIL, nodename,
CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "err"
#52: FILE: drivers/xen/pvblock.c:298:
+       if (err != NULL) {
ERROR: do not use assignment in if condition
#176: FILE: drivers/xen/gnttab.c:103:
+               if ((flags = nflags) & (GTF_reading | GTF_writing)) {
WARNING: Missing or malformed SPDX-License-Identifier tag in line 1
#329: FILE: include/xen/gnttab.h:1:
+/*
WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
#330: FILE: include/xen/gnttab.h:2:
+ * SPDX-License-Identifier: GPL-2.0
ERROR: do not use assignment in if condition
#630: FILE: lib/sscanf.c:558:
+                               if ((n = inr) < width) {

Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 14:11:31 -04:00
Anastasiia Lukianenko
d226b3cd25 board: xen: Remove unnecessary CONFIG_INITRD_TAG and CONFIG_CMDLINE_TAG
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 14:11:31 -04:00
Anastasiia Lukianenko
32eac63af3 board: xen: Remove CONFIG_CMD_RUN define and clean xenguest_arm64_defconfig
CONFIG_CMD_RUN is set on by default in Kconfig.
Create xenguest_arm64_defconfig by using savedefconfig to avoid unnecessary
options.

Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 14:11:31 -04:00
Anastasiia Lukianenko
607274f7f6 MAINTAINERS: Add maintainers to XEN section
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 14:11:31 -04:00
Anastasiia Lukianenko
4da1365d5c board: xen: Remove unnecessary CONFIG_BOARD_EARLY_INIT_F define and board_early_init_f function
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
35051db978 arm: dts: mt7623: add USB nodes
This adds USB nodes for MT7623/BPI-R2

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
a13666b205 arm: dts: mt7622: add USB nodes
Add DTS nodes for MT7622/BPI-R64

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
28e1b1df3b arm: dts: rename mt7622-bpi-r64.dts
rename mt7622-bpi-r64.dts to mt7622-bananapi-bpi-r64.dts
to follow naming convensions

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
9f25aa13ea clk: mt7622: add needed clocks for ssusb-node
MT7622 needs additional clock definitions to work properly

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
a7e0ef15dd ahci: mediatek: fix copyright and author-lines
after review of sam copyright should be on one line and link should
not between author lines

just remove the link and put ryder first as he is author of linux-driver

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
a300d696ca reset: drop unnecessary comment for pciesys
after review from sam this comment should be removed

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
626892a779 phy: mtk-tphy: make shared reg optional for v1
make the shared reg optional when version is v1 for sata

Suggested-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-24 14:11:31 -04:00
Joao Marcos Costa
c9875a5fe8 fs/squashfs: Fix Coverity Scan defects
Fix defects such as uninitialized variables and untrusted pointer
operations. Most part of the tainted variables and the related defects
actually comes from Linux's macro get_unaligned_le**, extensively used
in SquashFS code. Add sanity checks for those variables.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-24 14:11:31 -04:00
AKASHI Takahiro
6b0ddd1fbc virtio_blk: set log2blksz correctly
'log2blksz' in blk_desc structure must always be initialized, otherwise
it will cause a lot of weird failures in file operations.

For example, fs_set_blk_dev[_with_part]() examines a block device against
every file system with its probe function. In particular, ext4 file
system's ext4_probe() will calls fs_devread() to fetch a super block.
If log2blksz is 0, the actual 'read' size, i.e. block_len >> log2blksz, is
much bigger than a buffer's size, and it can end up with memory corruption.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Fixes: f4802209e5 ("virtio: Add block driver support")
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-24 14:11:31 -04:00
Joao Marcos Costa
91f6c1ca2e test/py: Add tests for LZO and ZSTD
Improve SquashFS tests architecture. Add 'Compression' class. LZO
algorithm may crash if the file is fragmented, so the fragments are
disabled when testing LZO.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-24 14:11:31 -04:00
Joao Marcos Costa
6dfed163bd fs/squashfs: add support for LZO decompression
Add call to lzo's lzo1x_decompress_safe() into sqfs_decompress().

U-Boot's LZO sources may still have some unsolved issues that could make the
decompression crash when dealing with fragmented files, so those should be
avoided. The "-no-fragments" option can be passed to mksquashfs.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-24 14:11:31 -04:00
Joao Marcos Costa
9c948f536f fs/squashfs: add support for ZSTD decompression
Add call to ZSTD's ZSTD_decompressDCtx(). In this use case, the caller
can upper bound the decompressed size, which will be the SquashFS data
block (or metadata block) size, so there is no need to use streaming
API. Add ZSTD's worskpace to squashfs_ctxt structure.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-24 14:11:31 -04:00
Joao Marcos Costa
cdc114415c fs/squashfs: replace sqfs_decompress() parameter
Replace 'u16 comp_type' by a reference to squashfs_ctxt structure.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-24 14:11:31 -04:00
Joao Marcos Costa
10f7cf5f12 fs/squashfs: Add init and clean-up functions to decompression
Add sqfs_decompressor_init() and sqfs_decompressor_cleanup(). These
functions are called respectively in sqfs_probe() and sqfs_close(). For
now, only ZSTD requires an initialization logic. ZSTD support will be
added in a follow-up commit.

Move squashfs_ctxt definition to sqfs_filesystem.h. This structure is
passed to sqfs_decompressor_init() and sqfs_decompressor_cleanup(), so
it can no longer be local to sqfs.c.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-24 14:11:31 -04:00
John Chau
4a1f0b80ad cmd: fix clone coverity scan
This patch fixes coverity scan MISSING_BREAK issues, and also an error
on block size check.

Signed-off-by: John Chau <john@harmon.hk>
2020-08-24 14:11:31 -04:00
Michal Simek
10e4d64e34 firmware: psci: Do not bind driver if U-Boot runs in EL3
There is no reason to bind psci driver if U-Boot runs in EL3 because
SMC/HVC instructions can't be called. That's why detect this state and
don't let user to crash from prompt by performing reset or poweroff
commands (if enabled).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-24 14:11:31 -04:00
Usama Arif
565add124d board: armltd: Add support for Total Compute platform
Total Compute is based on ARM architecture and has
the following features enabled in u-boot:
- PL011 UART
- PL180 MMC
- NOR Flash
- FIT image with Signature
- AVB

Signed-off-by: Usama Arif <usama.arif@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-24 14:11:31 -04:00
Usama Arif
e61b41517d avb: Make AVB independent of fastboot
AVB only uses CONFIG_FASTBOOT_BUF_ADDR from fastboot for memory.
This memory is used for assigning temporary buffers.
This can be assigned a new variable and used as CONFIG_AVB_BUF_ADDR.
This is to support future boards that support AVB but dont support
USB and therefore dont support FASTBOOT.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Cc: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Igor Opaniuk <igor.opaniuk@gmail.com>
[trini: Change defaults]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-24 14:11:13 -04:00
Heinrich Schuchardt
2b3fbcb59f efi_loader: use ':' as separator for setenv -i
setenv -e -i <address>,<filesize> can be used to set a UEFI variable
from memory.

For separating an address and a size we use ':' in most commands.
Let's do the same for setenv -e -i.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
15d8f008dc efi_loader: validate device path length in boot manager
Bootxxxx variables are provided by the user and therefore cannot be
trusted. We have to validate them before usage.

A device path provided by a Bootxxxx variable must have an end node within
the indicated device path length.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
5bba77e48b test: unit test for efi_dp_check_length()
Provide a unit test for function efi_dp_check_length().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
5cad4a3093 efi_loader: efi_dp_check_length()
We need to check that device paths provided via UEFI variables are not
malformed.

Provide function efi_dp_check_length() to check if a device path has an
end node within a given number of bytes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
ed0b10722c include: kernel.h: define SSIZE_MAX
Define SSIZE_MAX, the largest value fitting into a variable of type
ssize_t.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
fa63753f86 efi_selftest: substitute ResetSystem() by do_reset()
If ResetSystem() is not implemented at runtime, call do_reset() after
test completion.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
c06867d7f8 efi_selftest: add a test for ResetSystem()
The unit test will reset the system by calling the ResetSystem() runtime
service before or after ExitBootServices() according to the users choice
by setting environment variable efi_selftest to:

* 'reset system' or
* 'reset system runtime'.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
f03a879d67 efi_loader: ResetSystem() should not hang
If ResetSystem() is not implemented at runtime, it should return instead
of hanging in an endless loop. This allows the operating system to reset
the system by other means as Linux does. It also matches what EDK II
suggests in comments for functions ResetShutdown() and ResetWarm() in
OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
ebcbfc7d6d doc: update UEFI documentation
* UEFI variables can be persisted
* describe that the sequence of files loaded before bootefi matters

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
dd12c6a446 efi_loader: remove empty comment line
Remove a line leading to a warning in make htmldocs.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Heinrich Schuchardt
72e1fcacff efi_loader: document parameters of do_bootefi_exec()
Add the missing description of the load_options parameter.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-24 16:37:53 +02:00
Tom Rini
1aa3966173 Merge tag 'u-boot-clk-24Aug2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Add CCF clocks definitions for iMX6Q enet (ETH)
- Several fixes for CCF framework - the most notable is the one, which
  adds get_rate helper to clk-mux.c
- Improvements for clk command - better visibility and alignment.
2020-08-24 09:06:02 -04:00
Lukasz Majewski
ebd3f1f0d0 clk: ccf: Add missing #include <dm/uclass.h> to clk-mux.c
After adding custom get_rate helper function it was necessary to include
<dm/uclass.h> to avoid warnings about missing uclass_get_device_by_name.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Series-to: u-boot
2020-08-24 11:36:34 +02:00
Patrick Delaunay
689ca8c5d1 cmd: clk: correctly handle depth for clk dump
Update depth only when clock uclass is found to have correct display
of command "clk dump".

Without this patch, the displayed depth is the binding depth for
all the uclass and that can be strange as only clock uclass nodes
are displayed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 11:03:26 +02:00
Patrick Delaunay
cc6328412c cmd: clk: cosmetic: correct code alignment in show_clks
Correct code alignment in show_clks() function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 11:03:26 +02:00
Dario Binacchi
12d152620d clk: ccf: mux: change the get_rate helper
The previous version of the get_rate helper does not work if the mux
clock parent is changed after the probe. This error has not been
detected because this condition has not been tested. The error occurs
because the set_parent helper does not change the parent of the clock
device but only the clock selection register. Since changing the parent
of a probed device can be tricky, the new version of the get_rate helper
provides the rate of the selected clock and not that of the parent.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
e3b5d74c77 clk: ccf: mux: fix access to the sandbox register
The tests developed for the mux clock are run on the sandbox. They don't
call the clk_mux_set_parent routine and therefore they do not detect
this error.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
40559d2774 clk: ccf: mux: fix typo
Close the opening bracket.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
76eaa2d0ed clk: ccf: mux: change include order
Apply u-boot coding style on include files order.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
7b0830d41f clk: fix the console output of clk_register
The parent->name variable can be used only in case the
uclass_get_device_by_name routine returns successfully.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
16bdc85b48 clk: set flags in the ccf registration routines
The top-level framework flags are passed as parameter to the common
clock framework (ccf) registration routines without being used.
Checks of the flags setting added by the patch have been added in the
ccf test.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
cd16c57bd0 dm: test: clk: add the test for the ccf gated clock
Unlike the other clock types, in the case of the gated clock, a new
driver has been developed which does not use the registering routine
provided by the common clock framework.
The addition of the ecspi0 clock to sandbox therefore allows testing
the ccf gate clock.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 11:03:26 +02:00
Lukasz Majewski
32f462ba3b clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clock
After commit 673f659732 ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF need
to provide PTP clock.

On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux
kernel's CCF.

Code in this change models the simplest case when enet reference clock is
generated from 'osc' clock.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24 11:03:26 +02:00
Lukasz Majewski
8d540ccb11 clk: imx: Add support for pllv3 enet clock
This code has been ported from Linux kernel v5.5.5 (tag) and has been
adjusted to U-Boot's DM.

It adds support for correct recognition of IMX_PLLV3_ENET flag in the
clk-pllv3.c driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24 11:03:26 +02:00
Lukasz Majewski
d71fac8479 clk: imx6: Add definition for IMX6QDL_CLK_ENET clock
After commit 673f659732 ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF
need to provide IMX6QDL_CLK_ENET.

This change defines the missing clock in i.MX6Q's CCF.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24 11:03:26 +02:00
Heinrich Schuchardt
6befc1f900 clk: ICS8N3QV01 remove superfluous code
Do not calculate a unused value of n which is overwritten in both branches
of the subsequent if statement.

Identified by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-08-24 11:03:26 +02:00
Tom Rini
d584648dad Merge tag 'dm-pull-22aug20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
replace devfdt_get_addr_ptr() with dev_read_addr_ptr()
binman fixes for portage
various minor fixes
'bind' command improvements
2020-08-23 16:06:38 -04:00
Tom Rini
c84341f5ac Merge branch '2020-08-21-stdio-cleanup'
- Clean up common/stdio.c and migrate some related options to Kconfig
2020-08-23 15:53:10 -04:00
Simon Glass
4225f2f520 stdio: Tidy up the coding style
Bring the coding style in this file up to the current level.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-23 13:43:10 -04:00
Simon Glass
18c587d099 stdio: Drop brackets around &devs.list
These brackets are not needed. Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-23 13:43:10 -04:00
Simon Glass
5d4b6b1748 stdio: Update to use compiler for Kconfig checks
Drop use of the preprocessor where possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-23 13:43:10 -04:00
Simon Glass
3bcd0ced15 stdio: Drop #ifdefs in the header file
These prevent the use of IS_ENABLED() and are unnecessary. Drop them and
fix a few code-style nits nearby.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-23 13:43:10 -04:00
Simon Glass
3ca0609adc stdio: Tidy up use of CONFIG_SYS_DEVICE_NULLDEV
Now that this is in Kconfig we can move the logic at the top of the file
to Kconfig, and use if() instead of #if. Update the file with these
changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-23 13:43:10 -04:00
Simon Glass
7e15638d60 Convert CONFIG_SYS_DEVICE_NULLDEV to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_DEVICE_NULLDEV

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-23 13:43:10 -04:00
Simon Glass
35bd70c510 Convert CONFIG_SPLASH_SCREEN et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPLASH_SCREEN
   CONFIG_SPLASH_SCREEN_ALIGN
   CONFIG_SPLASHIMAGE_GUARD
   CONFIG_SPLASH_SOURCE

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-23 13:43:10 -04:00
Simon Glass
a38cc1726b moveconfig: Skip binary and ELF files
Add a few more file extensions to the list of files that should not be
processed. This avoids unicode errors, for example.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-23 13:43:10 -04:00
Tom Rini
a7fc1e12ad Convert CONFIG_NETCONSOLE to Kconfig
This converts the following to Kconfig:
   CONFIG_NETCONSOLE

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-23 13:06:36 -04:00
Ovidiu Panait
a402035028 sandbox: u-boot.lds: Remove bogus __bss_start symbol
The sections described in the sandbox linker script are inserted before
data section via "INSERT BEFORE .data;". Running readelf -S on sandbox
u-boot binary shows that the bss section is located after the data
section:

  Section Headers:
  [Nr] Name              Type             Address           Offset
       Size              EntSize          Flags  Link  Info  Align
  ...
  [25] .u_boot_list      PROGBITS         000000000041d1c8  0021d1c8
       000000000000dd90  0000000000000000  WA       0     0     8
  [26] _u_boot_sandbox_g PROGBITS         000000000042af58  0022af58
       00000000000000a0  0000000000000000  WA       0     0     8
  [27] .data             PROGBITS         000000000042b000  0022b000
       000000000000f708  0000000000000000  WA       0     0     32
  [28] .bss              NOBITS           000000000043a720  0023a708
       0000000000018930  0000000000000000  WA       0     0     32

This means that the __bss_start assignment in the linker script is bogus,
as the actual bss section start is located elsewhere. Remove this
assignment, as the __bss_start symbol is not used on sandbox anyway.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-22 08:54:51 -06:00
Ovidiu Panait
78237828a3 board_f: Remove dead code from init_func_i2c
Since commit 69153988a6 ("i2c: Finish dropping use of CONFIG_I2C_HARD")
init_func_i2c is wrapped only by "#if defined(CONFIG_SYS_I2C)". Because
of this, the second ifdef within becomes pointless:

 #if defined(CONFIG_SYS_I2C)
 static int init_func_i2c(void)
 <snip>
     #ifdef CONFIG_SYS_I2C
         ...
     #else
         ...
     #endif
 <snip>
 }
 #endif

Remove the dead #else preprocessor code.

Fixes: 69153988a6 ("i2c: Finish dropping use of CONFIG_I2C_HARD")
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-22 08:54:51 -06:00
Simon Glass
02c102074d binman: Add a setup script for Python
Allow binman to be installed by adding a suitable setup.py script.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:53:38 -06:00
Simon Glass
946ec85037 dtoc: Add a setup script for Python
Allow dtoc to be installed by adding a suitable setup.py script.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:53:38 -06:00
Simon Glass
07237988dc binman: Correct some import statements
Some of these were not converted when binman moved to use absolute paths.
Fix them.

Also drop the import of 'test' which is a directory, not a module.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:53:38 -06:00
Simon Glass
87d43329ef binman: Move GetEntryModules() to control
When binman is installed its main program is in a different directory
to its modules. This means that __file__ is different and we cannot use
it to obtain the path to etype/ from main.py

To fix this, move the function to the 'control' module, since it is
installed with all the other modules, including the etype/ directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:53:38 -06:00
Masahiro Yamada
702e57e113 treewide: convert devfdt_get_addr_ptr() to dev_read_addr_ptr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To help this tedious work, this commit converts devfdt_get_addr_ptr()
to dev_read_addr_ptr() by coccinelle. I also removed redundant casts
because dev_read_addr_ptr() returns an opaque pointer.

To generate this commit, I ran the following semantic patch
excluding include/dm/.

  <smpl>
  @@
  type T;
  expression dev;
  @@
  -(T *)devfdt_get_addr_ptr(dev)
  +dev_read_addr_ptr(dev)
  @@
  expression dev;
  @@
  -devfdt_get_addr_ptr(dev)
  +dev_read_addr_ptr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:53:37 -06:00
Masahiro Yamada
1450bff3e4 ata: mvebu: use dev_read_addr() to get base address
It is strange to use devfdt_get_addr_ptr(), then cast the pointer
back to ulong because you could use devfdt_get_addr() without casting.

Convert it to dev_read_addr(), which is capable to CONFIG_OF_LIVE.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-22 08:51:44 -06:00
Masahiro Yamada
0cbf3e08fc gpio: at91: use dev_read_addr() to get base address
It is strange to use devfdt_get_addr_ptr(), then cast the pointer
back to uint32 because you could use devfdt_get_addr() without casting.

Convert it to dev_read_addr(), which is capable to CONFIG_OF_LIVE.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:51:44 -06:00
Ovidiu Panait
6e64830f0b test: dm: Add test case for devfdt_get_addr_ptr
Add flat tree test case to cover devfdt_get_addr_ptr function.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:51:43 -06:00
Ovidiu Panait
3fe69d3764 dm: core: Fix devfdt_get_addr_ptr return value
According to the description of devfdt_get_addr_ptr, this function should
return NULL on failure, but currently it returns (void *)FDT_ADDR_T_NONE.

Fix this by making devfdt_get_addr_ptr return NULL on failure, as
described in the function comments. Also, update the drivers currently
checking (void *)FDT_ADDR_T_NONE to check for NULL.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 07:59:14 -06:00
Patrice Chotard
02291d83fd doc: add bind/unbind command documentation
Add documentation in doc/drivel-model for the bind/unbind command.
Part of this documentation is extracted from original patch commit
message:
commit 49c752c93a ("cmd: Add bind/unbind commands to bind a device to a driver from the command line")

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 07:58:39 -06:00
Patrice Chotard
e37d4c4fd2 test/py: Update test_bind
As bind-test is now binded at sandbox startup and no more by
test_bind.py, bind-test nodes are not located at the end of
"dm tree" output, but can be located everywhere in the tree, so
bind-test output could either be:

 simple_bus    0  [   ]   generic_simple_bus    |-- bind-test
 phy           0  [   ]   phy_sandbox           |   |-- bind-test-child1
 simple_bus    1  [   ]   generic_simple_bus    |   `-- bind-test-child2

or:

 simple_bus    5  [   ]   generic_simple_bus    `-- bind-test
 phy           2  [   ]   phy_sandbox               |-- bind-test-child1
 simple_bus    6  [   ]   generic_simple_bus        `-- bind-test-child2

in_tree() function need to be updated to take care of that change.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 07:58:39 -06:00
Patrice Chotard
1f0d5885db sandbox: dts: Add compatible string for bind-test node
Usage of lists_bind_fdt() in bind command imposes to add
a compatible string for bind-test node.

Others impacts are:
  - bind-test node is binded at sandbox start, so no need to bind it
    in test_bind_unbind_with_node() test.
  - As explained just above, after sandbox start, now a phy exist.
    In test/dm/phy.c, it was verified that a third phy didn't exist,
    now we must verified that a fourth phy doesn't exist.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 07:58:39 -06:00
Patrice Chotard
cfa3ed4390 sandbox: phy: add driver_data for bind test cmd
Add driver data to existing compatible string "sandbox,phy".
Add an additional compatible string without driver_data

This will verify that bind command parses, finds and passes the
correct driver data to device_bind_with_driver_data() by using
driver_data in the second sandbox_phy_ids table entry.
In sandbox_phy_bind() a check is added to validate driver_data
content.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 07:58:39 -06:00
Patrice Chotard
84f8e36f03 cmd: bind: allow to bind driver with driver data
Initial implementation invokes device_bind_with_driver_data()
with driver_data parameter equal to 0.
For driver with driver data, the bind command can't bind
correctly this driver or even worse causes data abort as shown below:

As example, for debug purpose on STM32MP1 platform, ethernet
(dwc_eth_qos.c) driver needed to be unbinded/binded.
This driver is using driver data:

static const struct udevice_id eqos_ids[] = {
    {
        .compatible = "nvidia,tegra186-eqos",
        .data = (ulong)&eqos_tegra186_config
    },
    {
        .compatible = "snps,dwmac-4.20a",
        .data = (ulong)&eqos_stm32_config
    },

    { }
};

After unbinding/binding this driver and probing it (with the dhcp command),
we got a prefetch abort as below:

STM32MP> unbind eth ethernet@5800a000
STM32MP> bind /soc/ethernet@5800a000 eth_eqos
STM32MP> dhcp
prefetch abort
pc : [<4310801c>]          lr : [<ffc8f4ad>]
reloc pc : [<035ba01c>]    lr : [<c01414ad>]
sp : fdaf19b0  ip : ffcea83c     fp : 00000001
r10: ffcfd4a0  r9 : fdaffed0     r8 : 00000000
r7 : ffcff304  r6 : fdc63220     r5 : 00000000  r4 : fdc5b108
r3 : 43108020  r2 : 00003d39     r1 : ffcea544  r0 : fdc63220
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
Code: data abort
pc : [<ffc4f9c0>]          lr : [<ffc4f9ad>]
reloc pc : [<c01019c0>]    lr : [<c01019ad>]
sp : fdaf18b8  ip : 00000000     fp : 00000001
r10: ffcd69b2  r9 : fdaffed0     r8 : ffcd69aa
r7 : 00000000  r6 : 00000008     r5 : 4310801c  r4 : fffffffc
r3 : 00000001  r2 : 00000028     r1 : 00000000  r0 : 00000006
Flags: NzCv  IRQs on  FIQs on  Mode SVC_32 (T)
Code: 2f00 d1e9 2c00 dce9 (f855) 2024
Resetting CPU ...

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 07:58:39 -06:00
Heinrich Schuchardt
ae6b33dcc3 dm: fix ofnode_read_addr/size_cells()
In the case of the live tree ofnode_read_addr_cells() and
ofnode_read_size_cells() return the #address-cells and #size-cells defined
in the parent node. With the patch the same is done for a non-live tree.

The only consumer of these functions is currently the CFI flash driver.

This patch fixes the incorrect parsing of the device tree leading to
'saveenv' failing on qemu_arm64_defconfig.

For testing qemu-system-aarch64 has to be called with

    -drive if=pflash,format=raw,index=1,file=envstore.img

to provide the flash memory. envstore.img must be 64 MiB large.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-22 07:58:39 -06:00
Kever Yang
b5b81f2490 rockchip: firefly-rk3288: Fix the code support for SPL_LED
Fix the build error for the wrong code when CONFIG_SPL_LED is enabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-08-21 19:56:19 +08:00
Kever Yang
e2f8ba8a5f rockchip: rk3188: Fix the code support for SPL_LED
Fix the build error for the wrong code when CONFIG_SPL_LED is enabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-08-21 19:56:19 +08:00
Kever Yang
5c5435093a rockchip: config: evb-rk3399: Add rockchip dwmmc support
This enable support for SD card on evb-rk3399.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-08-21 19:56:19 +08:00
Kever Yang
d6092e3229 rockchip: dts: rk3399-evb: add sdmmc node
The sdmmc node is missing after the dts sync patch:
  167efc2c7a arm64: dts: rk3399: Sync v5.7-rc1 from Linux
But we still need it for boot from SD card, so add it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-08-21 19:56:19 +08:00
Tom Rini
2e6132d835 Merge tag 'xilinx-for-v2020.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2020.10-rc3

- Fix fdtfile variable setup
- Fix bootm_*/fdt_high/initrd_high variables handling
- Fix Kconfig dependencies for Xilinx drivers
- Fix booting u-boot from lowest memory
- Fix firmware payload argument count for Versal
- Fix dfu configurations
- Fix mio_bank property handling
- Fix and align code around ID detection
- Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG
- Simplify logic around reading MAC from eeprom
- Decrease malloc length for zynqmp mini qspi
- Enable preboot for ZynqMP and Versal

i2c:
- Fix i2c eeprom partitions handling

mmc:
- Fix logic around HS mode enabling and use proper functions
2020-08-20 14:46:43 -04:00
Tom Rini
2a4484a5c5 Merge branch '2020-08-19-mediatek-updates'
- Assorted updates for MediaTek platforms
2020-08-20 08:38:10 -04:00
Michal Simek
29af2ac48c clk: versal: Move pm_query_id out of clock driver
There is no reason to have firmware specific structure in clock driver.
Move it to generic location and also initialize enum values which is based
on https://lore.kernel.org/linux-arm-kernel/20200318125003.GA2727094@kroah.com/
recommended way to go to make sure that values guaranteed by compiler.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 10:57:46 +02:00
Michal Simek
b5a3387dc1 mmc: sdhci: Use upper/lower_32_bits macros
Instead of recasting and shifting use macros which are designed for taking
upper/lower 32bit value from 64bit variable.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:58:59 +02:00
Faiz Abbas
620bb46ead mmc: sdhci: Enable high speed conditional on the corresponding bit
The capabilities register has a field to indicate whether the host
supports high speed mode or not. Add high speed host_caps based on
this bit instead of enabling it by default.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilnx.com>
Tested-by: Michal Simek <michal.simek@xilnx.com>
(zcu104 with sdhci-caps-mask = <0 0x200000>;)
2020-08-20 09:58:59 +02:00
Michal Simek
2570cc6430 xilinx: common: Change bootm_size variable setting
Linux kernel for arm32 requires dtb and initrd to be placed in low memory
to work properly. This requirement is described in chapter 4b) and 5) in
Linux documentation (Documentation/arm/booting.rst).

There is an issue on arm32 with 2GB of memory that bootm_size is bigger
than Linux lowmem (for example with VMSPLIT_3G). That's why limit bootm
size on these systems not to be above 768MB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:58:16 +02:00
Michal Simek
ca0f616530 xilinx: common: Check return value from variable setup
env_set..() can failed that's why check return status and report it back to
make sure that user is aware that's something went wrong.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:58:16 +02:00
Michal Simek
653809f43f xilinx: common: Get rid of initrd_high variable setup
When bootm_low/bootm_size are setup properly there is no need to setup any
initrd_high address. Location for initrd is determined through LMB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:58:16 +02:00
Michal Simek
0bfb43dfc1 xilinx: common: Get rid of fdt_high variable
There is no need to setup this variable if bootm_low and bootm_size
variable are properly setup. If fdt_high variable is missing U-Boot is
asking LMB to return free memory which is not used.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:58:16 +02:00
Michal Simek
9fea3b18d6 xilinx: Change logic around zynq_board_read_rom_ethaddr()
There is no reason to build private function when
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET is not defined. There is already weak
function which handles default case properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Michal Simek
62b96262b6 xilinx: Add support for ENV_VARS_UBOOT_RUNTIME_CONFIG
Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG to enable/disable updating
variables with run time information.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Michal Simek
d5c42ec31b xilinx: versal: Enable i2c misc eeprom driver
Enable this driver to be able to work with i2c based eeproms on Versal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Ibai Erkiaga
de4f748ef5 xilinx: zynqmp: fix incorrect map not align with IPI HW
Current IPI module register description is not align with IPI HW. The
registers with the wrong offset are not used so it does not cause real
issues. This patch aligns the register description.

Additionally comments added to explain why recv function does not check
any flag prior copying rx data.

Fixes: 660b0c77d8 ("mailbox: zynqmp: ipi mailbox driver")
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Ibai Erkiaga
050f10f103 xilinx: zynqmp: remove chip_id function
Remove chip_id function and integrate the firmware call in the
zynqmp_get_silicon_idcode_name function. The change avoids querying the
firmware twice and makes the code bit more clear.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Ibai Erkiaga
4b2ad7b111 xilinx: zynqmp: get chip ID at EL3
Modify the board init function to allow getting the chip ID when U-Boot
proper is executed at EL3.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Ibai Erkiaga
21c2fc7c6a xilinx: zynqmp: get chip ID using firmware driver
Current implementation for getting chip ID uses either raw access on EL3
or a SMC call to get the silicon information. Following change
simplifies the code using always the firmware driver.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Ibai Erkiaga
2eabb6bfea xilinx: zynqmp: merge firmware calls for EL2 and EL3
This patch merges ZynqMP firmware calls under xilinx_pm_request in order
to make trainsparent the EL. Calls at EL3 are send through IPI messages
and EL2 through SMC calls.

The EL2 call uses fixed payload and arg size as the EL3 call. The
firmware is capable to handle PMUFW_PAYLOAD_ARG_CNT bytes but the
firmware API is limited by the SMC call size.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Ibai Erkiaga
f6cccbb5f2 xilinx: zynqmp: synchronize firmware call return payload
Removes duplicated definition of PAYLOAD_ARG_CNT and define it in the
firmware driver. Additionally fixes payload buffer declarations without
macro usage

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Michal Simek
e8deb22185 mmc: zynq: Fix default value for xlnx,mio-bank
DT binding is saying that default value is 0 not -1 that's why fix it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-08-20 09:49:20 +02:00
Michal Simek
01a6da1661 xilinx: Fix xlnx,mio_bank property
s/xlnx,mio_bank/xlnx,mio-bank/g

DT binding is describing mio-bank not mio_bank that's why fix all DTSes and
also driver itself.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-08-20 09:49:20 +02:00
Michal Simek
f692b479f0 i2c: eeprom: Use reg property instead of offset and size
Remove adhoc dt binding for fixed-partition definition for i2c eeprom.
fixed-partition are using reg property instead of offset/size pair.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-20 09:49:20 +02:00
Michal Simek
2d06361a11 xilinx: zynqmp: Enable DFU tftp support
Enable DFU tftp support for firmware update. Fill dfu_ram_tftp variable to
have command present for showing how to use it.

boot FIT image has been created from below fragment. Key part is that type
of image has to be firmware. Also based on experiment load property is
completely ignored and base addresses are taken from dfu_alt_info variable.

$ cat update_uboot.its
/dts-v1/;

/ {
	description = "Automatic U-Boot update";
	#address-cells = <1>;

	images {
		Image {
			description = "Kernel";
			data = /incbin/("/tftpboot/Image");
			compression = "none";
			arch = "arm64";
			type = "firmware";
			os = "linux";
			load = <0x80000>;
			entry = <0x80000>;
			hash-1 {
				algo = "sha1";
			};
		};
		system.dtb {
			description = "DTB";
			data = /incbin/("/tftpboot/system.dtb");
			compression = "none";
			arch = "arm64";
			type = "firmware";
			load = <0>;
			hash-1 {
				algo = "sha1";
			};
		};
	};
};

$ mkimage -f update_uboot.its /tftpboot/boot

When U-Boot starts get IP address and server IP.
dhcp
setenv serverip 192.168.0.105

And then run prepared command.
run dfu_ram_tftp

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Michal Simek
9643000e14 xilinx: Align dfu ram with booti command
Image should be loaded to 0x80000 address and not to $kernel_addr_r.
Also kernel_addr, fdt_addr and fdt_size in zynqmp case are not defined
that's why define it to be aligned with Versal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Ashok Reddy Soma
8d00d224c9 arm64: zynqmp: Reduce malloc memory for mini QSPI configuration
Mini U-boot runs on lower foot print of 256KB OCM. Hence 8K memory
for malloc may not be required. Reduce it by 1.5K.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Michal Simek
22b6bb6ccd xilinx: versal: Use lowest memory for U-Boot
Find and use the lowest memory for Versal to make sure that we keep u-boot
as low as possible and never use memory above u-boot's maximum VA mapping.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Michal Simek
c2f0950c33 lib: fdt: Convert fdtdes_setup_mem..() to livetree API
Convert fdtdec_setup_mem_size_base(), get_next_memory_node(),
fdtdec_setup_memory_banksize() and fdtdec_setup_mem_size_base_lowest() to
livetree API.

Tested on ZynqMP zcu104 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-20 09:49:20 +02:00
Michal Simek
7fce739665 lib: fdt: Introduce fdtdec_setup_mem_size_base_lowest()
New function should be called from board dram_init() because it initialized
gd->ram_base/ram_size. It finds the lowest available memory.

On systems with multiple memory nodes finding out the first memory node by
fdtdec_setup_mem_size_base() is not enough because this memory can be above
actual U-Boot VA mapping. Currently only mapping till 39bit is supported
(Full 44bit mapping was removed by commit 7985cdf74b ("arm64: Remove
non-full-va map code")).
If DT starts with the first memory node above 39bit address then system can
be unpredictable.

The function is available only when multiple memory bank support is
enabled.

Calling fdtdec_setup_memory_banksize() from dram_init() is not possible
because fdtdec_setup_memory_banksize() is saving dram information to bd
structure which is placed on stack but not initialized at this time. Also
stack is placed at location setup in dram_init().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-20 09:49:20 +02:00
Ibai Erkiaga
11b1dcec09 versal: fix versal PM ret payload size
The PM return payload size is defined as 4 bytes for Versal arquitecture
while the PM calls implemented both in the Versal clock driver and
ZynqMP firmware driver expects 5 bytes length.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
T Karthik Reddy
526a67eb35 xilinx: versal: Add new versal loadpdi command
Versal loadpdi command is used for loading secure & non-secure
pdi images.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Igor Lantsman
1b208d59ba arm64: zynqmp: Fix set_fdtfile() not to break u-boots DTB
Origin function was calling strsep which replaced delimiter ',' by a null
byte ('\0'). Operation was done directly on FDT which ends up with the
following behavior:

ZynqMP>  printenv fdtfile
fdtfile=xilinx/zynqmp.dtb
ZynqMP> fdt addr $fdtcontroladdr
ZynqMP> fdt print / compatible
compatible = "xlnx", "zynqmp"

As is visible fdtfile was correctly composed but a null byte caused that
xlnx was separated from zynqmp.
This hasn't been spotted because in all Xilinx DTs there are at least 3
compatible string and only the first one was affected by this issue.
But for systems which only had one compatible string "xlnx,zynqmp" it was
causing an issue when U-Boot's DT was used by Linux kernel.

The patch removes strsep calling and strchr is called instead which just
locate the first char after deliminator ',' (variable called "name").
And using this pointer in fdtfile composing.

Fixes: 91d7e0c47f ("arm64: zynqmp: Create fdtfile from compatible string")
Reported-by: Igor Lantsman <igor.lantsman@opsys-tech.com>
Signed-off-by: Igor Lantsman <igor.lantsman@opsys-tech.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:49:20 +02:00
Michal Simek
834de89842 xilinx: Enable preboot feature for ZynqMP and Versal
Enable preboot functionality for ZynqMP and Versal platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:46:55 +02:00
Michal Simek
664e16ce99 xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers
Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in
PL and vice versa. That's why change dependencies and do not limit enabling
just for some platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-08-20 09:46:55 +02:00
Michal Simek
c8da6513c0 xilinx: Setup bootm variables
On system with PL DDR which is placed before PS DDR in DT
env_get_bootm_size() and env_get_bootm_low() without specifying bootm_low
and bootm_size variables are taking by default gd->bd->bi_dram[0].start and
gd->bd->bi_dram[0].size. As you see 0 means bank 0 which doesn't need to be
PS ddr and even can be memory above 39bit VA which is what U-Boot supports
now.
That's why setup bootm variables based on ram_base/ram_size setting to make
sure that boot images are placed to the same location as U-Boot is placed.
This location should be by default location where OS can boot from.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 09:46:55 +02:00
Frank Wunderlich
7cf8537d5e dts: r64: add sata- and asm_sel nodes
asm_sel is for switching between sata and pcie mode
on r64 there is GPIO90 connected to ASM1480 which
switches RX/TX pairs to PCIe/SATA connector
output-low means sata-controller is active

with 2020-10 now reg is also needed for the phy itself

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:15 -04:00
Frank Wunderlich
38bff327d7 ahci: mediatek: add ahci driver
add AHCI driver ported from linux

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:15 -04:00
Frank Wunderlich
fee276ee31 reset: add basic reset controller for pciesys
bind reset controller to pciesys

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:15 -04:00
Frank Wunderlich
ffbcde248d phy: mtk-tphy: add PHY_TYPE_SATA
add support for PHY_TYPE_SATA to Mediateks TPHY driver

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-19 17:38:15 -04:00
Frank Wunderlich
362e5e1e19 arm: dts: mt7622: add SATA reset constants
add reset constants used for SATA to header file

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:14 -04:00
Frank Wunderlich
f08c2c2d87 arm: dts: mt7622: add PCIe nodes for BananaPi-R64
this patch adds PCIe-Nodes for BananaPi R64

original nodes from Chuanjia Liu for mt7622-rfb

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:14 -04:00
Frank Wunderlich
8ad2fc413f dts: r64: add r64 dts
add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:14 -04:00
Frank Wunderlich
35d0fdbf17 arm: dts: add watchdog-node for mt7622
adding a watchdog-node to mt7622 dtsi

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:37:37 -04:00
Chuanjia Liu
b5d4cbbf13 configs: mt7622: add PCIe controller related configs
Add PCIe command and related configs

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Signed-off-by: Henry Yen <henry.yen@mediatek.com>
2020-08-19 17:37:37 -04:00
Chuanjia Liu
bb9d3ad521 arm: dts: mediatek: add PCIe node for MT7622
This patch adds PCIe node in dts for Mediatek MT7622 Soc.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Signed-off-by: Henry Yen <henry.yen@mediatek.com>
2020-08-19 17:37:37 -04:00
Chuanjia Liu
91ee45d806 PCI: mediatek: Add PCIe support for MT7622
This patch adds PCIe support for the Mediatek MT7622 SOC.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Signed-off-by: Henry Yen <henry.yen@mediatek.com>
2020-08-19 17:37:37 -04:00
Chuanjia Liu
0cc587dd86 arm: dts: mediatek: add pciesys support for MT7622 SoC
This patch adds pciesys support in dts for MediaTek MT7622 SoC.

Signed-off-by: Henry Yen <henry.yen@mediatek.com>
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
2020-08-19 17:37:37 -04:00
Chuanjia Liu
c5bfe694e7 clk: mediatek: add pciesys support for MT7622 SoC
This patch adds pciesys support in clock driver for
MediaTek MT7622 SoC.

Signed-off-by: Henry Yen <henry.yen@mediatek.com>
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
2020-08-19 17:37:37 -04:00
Chunfeng Yun
324220da63 pinctrl: mediatek: mt8512: fix the wrong start address of ranges
The start address of dout, pullen and pullsel ragnes are wrong,
so fix up them.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-19 17:37:37 -04:00
Tom Rini
ba989cf1ca Merge tag 'uniphier-v2020.10-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2020.10 (2nd)

 - minor code cleanups

 - sync DT with Linux
2020-08-18 21:28:49 -04:00
Wig Cheng
4992090ed4 pico-imx6ul: convert ethernet function to DM_ETH
- Remove pinmux definition from pico-imx6ul.c
- Enable NET_RANDOM_ETHADDR for temporary solution, because micrel_ksz8xxx
driver does not support DM_ETH yet, so cannot read MAC address directly.

Before enable DM_ETH:
  Net:   FEC [PRIME]

After enable DM_ETH:
  Net:
  Warning: using random MAC address - ca:3f:43:8f:67:d4
  eth1: ethernet@20b4000

Here is the test commands:
  => dhcp
  BOOTP broadcast 1
  DHCP client bound to address 10.88.88.94 (139 ms)
  *** ERROR: `serverip' not set
  Cannot autoload with TFTPGET
  => ping 8.8.8.8
  Using ethernet@20b4000 device
  host 8.8.8.8 is alive

Signed-off-by: Wig Cheng <wig.cheng@technexion.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-18 10:10:25 +02:00
Wig Cheng
d9d77a5209 configs: pico-imx6ul: convert DM_VIDEO
It's due to the warning messages issue after compiled:

  ===================== WARNING ======================
  This board does not use CONFIG_DM_VIDEO Please update
  the board to use CONFIG_DM_VIDEO before the v2019.07 release.
  Failure to update by the deadline may result in board removal.
  See doc/driver-model/migration.rst for more info.
  ====================================================

Enable DM_VIDEO can fix it on the stage of compilation.

Signed-off-by: Wig Cheng <wig.cheng@technexion.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-18 10:10:25 +02:00
Wig Cheng
6e861c35e7 configs: pico-imx6ul: convert DM_USB
Here is the test commands:

  => ums 0 mmc 0
  UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x710000

Signed-off-by: Wig Cheng <wig.cheng@technexion.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-18 10:10:25 +02:00
Matthias Schiffer
0c2b03cace tools/imximage: fix DCD Blocks message output order
The correct order is load address, offset, length. The order was
accidentally switched a while ago; make it match the HAB Blocks output and
what CST expects again.

Fixes: e97bdfa5da ("tools/imximage: share DCD information via Kconfig")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2020-08-18 10:10:25 +02:00
Masahiro Yamada
65282edbdf ARM: dts: uniphier: resync DT with Linux 5.9-rc1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18 02:01:14 +09:00
Masahiro Yamada
351b74cb6d ARM: uniphier: use FIELD_GET() to get access to revision register fields
Define register fields as macros, and use FIELD_GET().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18 02:01:14 +09:00
Masahiro Yamada
26f0c8600e serial: uniphier: fix typo in comment
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18 02:01:14 +09:00
Masahiro Yamada
055e5ad287 ARM: uniphier: remove unneeded header inclusion from board_late_init.c
<nand.h> is unneeded since commit 9248a78f40 ("ARM: UniPhier: remove
Denali NAND controller fixup code").

<linux/io.h> is uneeded since commit 1320fa2e55 ("ARM: uniphier:
remove workaround for the NAND write protect").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18 02:01:14 +09:00
Masahiro Yamada
2dbb6beb00 ARM: uniphier: remove unused uniphier_pin_init()
This function is unused since commit 862274913f ("bus:
uniphier-system-bus: move hardware init from board files").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18 02:01:14 +09:00
Masahiro Yamada
184831f656 ARM: uniphier: rename include guard of include/configs/uniphier.h
Make the include guard match to the file name.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18 02:01:14 +09:00
Marek Vasut
af50d92ae7 ARM: imx: ddr: Add deskew register programming
Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers,
which are optional, but can be used to fill in the byte lane delays.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-08-17 17:55:49 +02:00
Marek Vasut
4b44bea701 ARM: imx: Add support for reading out the primary/secondary bmode to MX7
Implement the 'getprisec' subcommand of 'bmode' command for i.MX7 by
reading out the SRC GPR10 bit 30. This bit is either set by the BootROM
if it switched to the secondary copy due to primary copy being corrupted
OR it can be overridden by the user.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-08-17 17:55:31 +02:00
Marek Vasut
3c0fbbfd95 ARM: imx: Add support for reading out the primary/secondary bmode
Add new 'getprisec' subcommand to 'bmode' command, which sets the return
value of the 'bmode' command to either 0 if the system booted from primary
copy or to 1 if the system booted from secondary copy. This can be used
e.g. in 'test' command to determine which copy of the system is running.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-08-17 17:55:17 +02:00
Marek Vasut
5ec83561c4 ARM: imx: Add support for switching primary/secondary boot mode to bmode
The i.MX6/i.MX7 is capable of booting a secondary "redundant" system
image in case the primary one is corrupted. The user can force this
boot mode as well by explicitly setting SRC GPR10 bit 30. This can be
potentially useful when upgrading the bootloader itself. Expose this
functionality to the user.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-08-17 17:54:01 +02:00
Marek Vasut
c72372d38c ARM: imx: Add bmode support for iMX7
Add the basic differentiation between i.MX6 and i.MX7 into the bmode
command, the mechanism really works almost the same on both platforms.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-08-17 17:53:55 +02:00
Tom Rini
789bfb5266 Merge tag 'efi-2020-10-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc3 (2)

This series includes bug fixes for:

* UEFI secure boot - images with multiple signatures
* UEFI secure boot - support for intermediate certificates
* corrections for UEFI unit tests
* missing loadaddr on MAIX board
2020-08-15 09:01:01 -04:00
Tom Rini
c0192950df Merge branch '2020-08-14-assorted-updates'
- Xen guest and some paravirt driver support.
- Aspeed SoC updates
- Broadcom IPROC PCIe RC driver
2020-08-14 15:48:56 -04:00
Michal Simek
698383fe8e cmd: demo: Remove duplicated help message for list subcommand
There is no need to show demo list description twice when help demo is
performed. The patch removes duplicated entry.

Current state:
=> help demo
demo - Driver model (dm) demo operations

Usage:
demo list                     List available demo devices
demo hello <num> [<char>]     Say hello
demo light [<num>]            Set or get the lights
demo status <num>             Get demo device status
demo list                     List available demo devices

Fixes: a02af4aeec ("dm: demo: Add a simple GPIO demonstration")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14 15:18:30 -04:00
Anastasiia Lukianenko
8071348de4 doc: xen: Add Xen guest ARM64 board documentation
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 15:18:30 -04:00
Oleksandr Andrushchenko
d17f6698b8 board: xen: De-initialize before jumping to Linux
Free resources used by Xen board before jumping to Linux kernel.

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14 15:18:30 -04:00
Anastasiia Lukianenko
53d725c74e xen: pvblock: Print found devices indices
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14 15:18:30 -04:00
Anastasiia Lukianenko
3a739cc6c9 xen: pvblock: Implement front-back protocol and do IO
Implement Xen para-virtual frontend to backend communication
and actually read/write disk data.

This is based on mini-os implementation of the para-virtual block
frontend driver.

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 15:18:30 -04:00
Anastasiia Lukianenko
17c96f8851 xen: pvblock: Read XenStore configuration and initialize
Read essential virtual block device configuration data from XenStore,
initialize front ring and event channel.
Update block device description with actual block size.

Use code for XenStore from mini-os.

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 15:18:30 -04:00
Anastasiia Lukianenko
a99931319e xen: pvblock: Enumerate virtual block devices
Enumerate Xen virtual block devices found in XenStore and
instantiate pvblock devices.

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14 15:18:30 -04:00
Anastasiia Lukianenko
722bc5b5d9 xen: pvblock: Add initial support for para-virtualized block driver
Add initial infrastructure for Xen para-virtualized block device.
This includes compile-time configuration and the skeleton for
the future driver implementation.
Add new class UCLASS_PVBLOCK which is going to be a parent for
virtual block devices.
Add new interface type IF_TYPE_PVBLOCK.

Implement basic driver setup by reading XenStore configuration.

Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
2020-08-14 15:18:30 -04:00
Oleksandr Andrushchenko
c850674ff7 xen: Port Xen grant table driver from mini-os
Make required updates to run on u-boot.

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 15:18:30 -04:00
Oleksandr Andrushchenko
60e49ff1f8 xen: Port Xen bus driver from mini-os
Make required updates to run on u-boot and strip test code.

Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
2020-08-14 15:18:30 -04:00
Andrii Anisov
e87dfb0526 lib: sscanf: add sscanf implementation
Port sscanf implementation from mini-os and introduce new
Kconfig option to enable it: CONFIG_SSCANF. Disable by default.

Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
2020-08-14 15:18:30 -04:00
Oleksandr Andrushchenko
242587dca4 linux/compat.h: Add wait_event_timeout macro
Add  wait_event_timeout - sleep until a condition gets true or a
timeout elapses.

This is a stripped version of the same from Linux kernel with the
following u-boot specific modifications:
- no wait queues supported
- use u-boot timer to detect timeouts
- check for Ctrl-C pressed during wait

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
[trini: Drop atomic_read from gadget/ether.c as this has existed for a
        while and now causes problems]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-14 15:18:30 -04:00
Peng Fan
384d5cfe5d serial: serial_xen: Add Xen PV serial driver
Add support for Xen para-virtualized serial driver. This
driver fully supports serial console for the virtual machine.

Please note that as the driver is initialized late, so no banner
nor memory size is visible.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14 15:18:30 -04:00
Oleksandr Andrushchenko
673fd82c50 xen: Port Xen event channel driver from mini-os
Make required updates to run on u-boot. Strip functionality
not needed by U-boot.

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 15:18:30 -04:00
Oleksandr Andrushchenko
486544161f xen: Port Xen hypervisor related code from mini-os
Port hypervisor related code from Mini-OS. This is referencing the code
of Mini-OS from [1] by Huang Shijie and Volodymyr Babchuk which is for
ARM64.
Update essential arch code to support required bit operations, memory
barriers etc.

Copyright for the bits ported belong to at least the following authors,
please see related files for details:

Copyright (c) 2002-2003, K A Fraser
Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge
Copyright (c) 2014, Karim Allah Ahmed <karim.allah.ahmed@gmail.com>

[1] - https://github.com/zyzii/mini-os.git

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
[trini: Drop wmb() from musb-net/linux-compat.h now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-14 15:18:30 -04:00
Andrii Anisov
770a8eef3e board: Introduce xenguest_arm64 board
Introduce a minimal Xen guest board running as a virtual
machine under Xen Project's hypervisor [1], [2].

Part of the code is ported from Xen mini-os and also uses
work initially done by different authors from NXP: please see
relevant files for their copyrights.

[1] https://xenbits.xen.org
[2] https://wiki.xenproject.org/

Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 15:18:27 -04:00
Heinrich Schuchardt
a4bda5ebab riscv: load addresses for Sipeed MAIX
Define default load addresses and the device tree name for the Sipeed MAIX.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-14 17:22:50 +02:00
Oleksandr Andrushchenko
365d88ac7e xen: Add essential and required interface headers
Add essential and required Xen interface headers only taken from
the stable Linux kernel stable/linux-5.7.y at commit
66dfe4522160 Linux 5.7.5.

These are better suited for U-boot than the original headers
from Xen as they are the stripped versions of the same.

At the same time use public protocols from Xen RELEASE-4.13.1, at
commit 6278553325a9 update Xen version to 4.13.1
as those have more comments in them.

Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-08-14 09:46:40 -04:00
Peng Fan
751897301d Kconfig: Introduce CONFIG_XEN
Introduce CONFIG_XEN to make U-Boot could be used as bootloader
for a virtual machine.

Without bootloader, we could successfully boot up android on XEN, but
we need need bootloader to support A/B, dm verify and etc.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 09:46:40 -04:00
Anastasiia Lukianenko
824ed85b77 Add MIT License
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14 09:46:40 -04:00
Chia-Wei, Wang
2c00c2e024 configs: evb-ast2500: Convert to OF_SEPARATE
Switch DTB provider form OF_EMBED to OF_SEPARATE
to avoid the compile warning message:

  ==================== WARNING ======================
  CONFIG_OF_EMBED is enabled. This option should only
  be used for debugging purposes. Please use
  CONFIG_OF_SEPARATE for boards in mainline.
  See doc/README.fdt-control for more info.
  ====================================================

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14 09:46:40 -04:00
Chia-Wei, Wang
353eedb8a0 configs: evb-ast2500: Move BOOTCOMMAND from header to defconfig
Move the BOOTCOMMAND definition from the board inclusion
header to the default configuration file.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14 09:46:40 -04:00
Chia-Wei, Wang
98ef128b56 include/configs: aspeed: Remove hardcoded variables
The hardcoded platform variables such as DRAM base address are not
common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces
those hardcoded with macros defined in a newly added header, where
the basic SoC HW information are assigned accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14 09:46:40 -04:00
Chia-Wei, Wang
c16f518a79 cosmetic: aspeed: ast2500: Rename board file
Rename the ast2500-board.c to board_common.c and
place the renamed file under the ast2500 folder.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14 09:46:40 -04:00
Chia-Wei, Wang
611fe09577 aspeed: ast2500: Add lowlevel_init assembly
The original lowlevel_init function of AST2500 is written
in C. However, the C runtime environment is not ready until
_main execution.

This patch adds the assembly version of the lowlevel_init
function. Additional initialization to DRAM configuration
and LPC reset source are also added.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14 09:46:40 -04:00
Chia-Wei, Wang
aff987c457 MAINTAINERS: Add maintainers for Aspeed SoCs
Update maintainers for Aspeed SoC platforms.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14 09:46:40 -04:00
Srinath Mannam
4848704aef drivers: pcie: add Broadcom IPROC PCIe RC driver
Add support for IPROC PAXC PCIe RC driver.

Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14 09:43:21 -04:00
Rayagonda Kokatanur
143eb5b1ca drivers: pci: add api to get dma regions
Add api to get dma regions.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-08-14 09:43:21 -04:00
Tom Rini
fe5c777df2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Fix HiFive Unleashed the broken problem by call fix_fdt() before
  reserve_fdt().  Please refer to
  https://www.mail-archive.com/u-boot@lists.denx.de/msg379444.html for
  master u-boot broken for HiFive Unleashed.
- Add unaligned exception cmd.
- Refine sifive/fu540 spl flow.
- Add  additional crash information for efi.
- Update sipeed/maix doc.
- Two minor refine.
2020-08-14 08:38:01 -04:00
AKASHI Takahiro
0274e50e05 test/py: efi_secboot: modify 'multiple signatures' test case
The test case 5 in test_signed (multiple signatures) must be modified
and aligned with the change introduced in the previous commit
("efi_loader: signature: correct a behavior against multiple signatures").

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2020-08-14 12:34:33 +02:00
AKASHI Takahiro
52956e535e efi_loader: signature: correct a behavior against multiple signatures
Under the current implementation, all the signatures, if any, in
a signed image must be verified before loading it.

Meanwhile, UEFI specification v2.8b section 32.5.3.3 says,
    Multiple signatures are allowed to exist in the binary’s certificate
    table (as per PE/COFF Section “Attribute Certificate Table”). Only
    one hash or signature is required to be present in db in order to pass
    validation, so long as neither the SHA-256 hash of the binary nor any
    present signature is reflected in dbx.

This patch makes the semantics of signature verification compliant with
the specification mentioned above.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-14 12:28:25 +02:00
Pragnesh Patel
313981c2d9 common/board_f: make sure to call fix_fdt() before reserve_fdt()
There may be a chance that board specific fix_fdt() will change the
size of FDT blob so it's safe to call reserve_fdt() after fix_fdt()
otherwise global data (gd) will overwrite with FDT blob values.

Fixes: a8492e25ac ("riscv: Expand the DT size before copy reserved memory node")

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-08-14 14:39:47 +08:00
Heinrich Schuchardt
7c6ca03eae riscv: additional crash information
If an exception occurs, the relocated program counter and return address
are required for an analysis.

With this patch you get:

    => exception undefined

    Unhandled exception: Illegal instruction
    EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e
    EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted

We can use the relocated addresses to find the involved functions in
u.boot.map:

    .text.do_undefined
                0x0000000080007908        0x8 cmd/built-in.o
    .text.cmd_process
                0x000000008000dfcc      0x11a common/built-in.o
                0x000000008000dfcc                cmd_process

If an exception occurs in an UEFI binary additionally the load addresses of
the UEFI binaries are needed. With this patch:

    => setenv efi_selftest exception
    => bootefi selftest

    Unhandled exception: Illegal instruction
    EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e
    EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted

    UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest'
    UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi'

The value pc=0x18a matches the position of the illegal instruction in
efi_selftest_miniapp_exception.efi (loaded as /bug.efi);

    asm volatile (".word 0xffffffff\n");

    00000180   93 85 C5 11  1C 64 22 85  82 97 FF FF  FF FF 1C 64

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14 14:39:41 +08:00
Heinrich Schuchardt
db3585d181 cmd: exception: unaligned data access on RISC-V
The command 'exception' can be used to test the handling of exceptions.

Currently the exception command only allows to create an illegal
instruction exception on RISC-V.

Provide a sub-command 'exception unaligned' to cause a misaligned load
address exception.

Adjust the online help for 'exception undefined'.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14 14:39:34 +08:00
Heinrich Schuchardt
3a85e03f83 doc: riscv: debug UART for MAIX
Provide the required settings for the debug UART.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-08-14 14:39:28 +08:00
Heinrich Schuchardt
137dc153fd doc: riscv: Update documentation for Sipeed MAIX boards
The MAIXDUINO runs fine with the sipeed_maix_bitm_defconfig but a different
board id parameter should be passed to kflash.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-08-14 14:39:20 +08:00
Heinrich Schuchardt
6a43e3a167 riscv: sifive: fu540: redundant initialization
We should not initialize a variable if the value is overwritten before
being read.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14 14:39:14 +08:00
Heinrich Schuchardt
023dba1366 riscv: remove redundant logical constraint.
After

    if (ret) return ret;

we know that ret is zero. Don't check it again.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14 14:39:09 +08:00
Bin Meng
3581811dc2 riscv: sifive/fu540: Move SPL related functions to spl.c
It's better to keep all SPL related functions in the same spl.c.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
50856c3f0f riscv: sifive/fu540: Drop NET_RANDOM_ETHADDR
This option was enabled during the earlier U-Boot porting time. Now
we already have the OTP driver in place and the unique MAC address
is read from the OTP, there is no need to turn on this option.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
ff8e88a6d7 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level
All FU540 driver related options should be in the SoC level Kconfig.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
d6a01704b0 riscv: sifive/fu540: spl: Rename soc_spl_init()
spl_soc_init() seems to be a better name, as all SPL functions
names start from the spl_ prefix.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
c4295ec849 riscv: sifive/fu540: spl: Drop our own version of board_init_f()
Use the generic board_init_f() provided by the RISC-V library codes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
71672b784c riscv: Call spl_board_init_f() in the generic SPL board_init_f()
The generic SPL version of board_init_f() should give a call to
board specific codes to initialize board in the SPL phase.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
AKASHI Takahiro
f68a6d5835 efi_loader: variable: fix secure state initialization
Under the new file-based variable implementation, the secure state
is always and falsely set to 0 (hence, the secure boot gets disabled)
after the reboot even if PK (and other signature database) has already
been enrolled in the previous boot.

This is because the secure state is set up *before* loading non-volatile
variables' values from saved data.

This patch fixes the order of variable initialization and secure state
initialization.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Fixes: 5f7dcf079d ("efi_loader: UEFI variable persistence")
2020-08-13 22:37:42 +02:00
AKASHI Takahiro
e1174c566a test/py: efi_secboot: add test for intermediate certificates
In this test case, an image may have a signature with additional
intermediate certificates. A chain of trust will be followed and all
the certificates in the middle of chain must be verified before loading.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2020-08-13 22:37:36 +02:00
AKASHI Takahiro
57be8cdce3 test/py: efi_secboot: small rework for adding a new test
It won't be very useful to customize HELLO_PATH and EFI_SECBOOT_IMAGE_NAME
under the current code base. So just remove them.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2020-08-13 22:37:36 +02:00
AKASHI Takahiro
1115edd846 efi_loader: signature: rework for intermediate certificates support
In this commit, efi_signature_verify(with_sigdb) will be re-implemented
using pcks7_verify_one() in order to support certificates chain, where
the signer's certificate will be signed by an intermediate CA (certificate
authority) and the latter's certificate will also be signed by another CA
and so on.

What we need to do here is to search for certificates in a signature,
build up a chain of certificates and verify one by one. pkcs7_verify_one()
handles most of these steps except the last one.

pkcs7_verify_one() returns, if succeeded, the last certificate to verify,
which can be either a self-signed one or one that should be signed by one
of certificates in "db". Re-worked efi_signature_verify() will take care
of this step.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2020-08-13 22:37:36 +02:00
AKASHI Takahiro
0658bb29b0 efi_loader: variable: keep temporary buffer during the authentication
This is a bug fix; Setting an authenticated variable may fail due to
a memory corruption in the authentication.

A temporary buffer will, if needed, be allocated to parse a variable's
authentication data, and some portion of buffer, specifically signer's
certificates, will be referenced by efi_signature_verify().

So the buffer should be kept valid until the authentication process
is finished.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-13 22:37:36 +02:00
Heinrich Schuchardt
bc78d22d0f cmd/efidebug: missing initialization of load_options
Variable load_options must be initialized to NULL to avoid a segmentation
fault when freeing the memory this variable points to.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-13 22:37:36 +02:00
Tom Rini
cdcf591d9b Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix dtc warnings for some MVEBU boards
2020-08-13 08:25:25 -04:00
Tom Rini
6808dc62d7 Merge tag 'u-boot-stm32-20200813' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Use IS_ENABLED to prevent ifdef in board_key_check for STM32MP
  - Add STM32 FMC2 EBI controller driver
  - Fix dwc3-sti-glue which allows STiH410-B2260 to boot again
  - Add fitImage its entry for 587-200 DHCOR SoM
  - Add both PDK2 and DRC02 DT into DHCOM fitImage its
  - Fix DHCOM KS8851 ethernet MAC address
  - Remove stm32mp1 board.c file
  - Use const for struct node_info in board stm32mp1.c file
2020-08-13 08:11:27 -04:00
Stefan Roese
ac5cd429e3 arm: mvebu: armada-3720-turris-mox.dts: Fix dtc warning
Fix this dtc warning:
Warning (avoid_default_addr_size)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Behún <marek.behun@nic.cz>
2020-08-13 12:07:05 +02:00
Stefan Roese
fcede1e5f6 arm: mvebu: armada-388-gp.dts: Fix dtc warnings
Fix these dtc warnings:
Warning (reg_format)
Warning (avoid_default_addr_size)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
2020-08-13 12:07:05 +02:00
Stefan Roese
cc2afbd47b arm: mvebu: armada-xp-maxbcm.dts: Fix dtc warning
Fix this dtc warning:
Warning (avoid_default_addr_size)

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-13 12:07:05 +02:00
Stefan Roese
092cb733e9 arm: mvebu: armada-xp-theadorable.dts: Fix dtc warning
Fix this dtc warning:
Warning (avoid_default_addr_size)

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-13 12:07:05 +02:00
Patrick Delaunay
d0a3c4f9db board: stm32mp1: use const for struct node_info
Use const for the variable nodes in ft_board_setup,
this patch follow fdt_fixup_mtdparts prototype and no more use stack.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 10:10:33 +02:00
Patrick Delaunay
5eafc1d3d9 board: stm32mp1: remove board.c
Remove the file board/st/stm32mp1/board.c which is not more
compiled since commit 156732cc8939 ("board: stm32mp1: move the
function board_debug_uart_init in spl.c")

Fixes: 4fb46816c7 ("board: stm32mp1: move the function board_debug_uart_init in spl.c")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 10:04:14 +02:00
Marek Vasut
9ff770b497 ARM: dts: stm32: Update eth1addr from EEPROM if eth1 present
The STM32MP1 DHCOM has two ethernet interfaces, the on-SoM DWMAC and KS8851.
Set eth1addr for the KS8851 to a MAC address of the DWMAC incremented by 1.
The MAC of the DWMAC is set from on-SoM EEPROM already, but the MAC address
of KS8851 was left uninitialized, so fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:56:44 +02:00
Marek Vasut
b2a2911dad ARM: stm32: Add fitImage its entry for 587-200 DHCOR SoM
The new 587-200 DHCOR SoM is compatible with the 587-100 prototype,
hence just replicate the entries, as there is no pattern matching.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:56:01 +02:00
Marek Vasut
49650c7511 ARM: stm32: Add both PDK2 and DRC02 DT into DHCOM fitImage its
Include both PDK2 and DRC02 DTs in the DHCOM fitImage .its and implement
support in SPL to select the correct configuration entry for U-Boot by
using the machine compatible string from SPL DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:55:58 +02:00
Christophe Kerello
acdaae6390 ARM: dts: stm32: add FMC2 EBI support for stm32mp157c
This patch adds FMC2 External Bus Interface support on stm32mp157c.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:35 +02:00
Christophe Kerello
de1fb5fb00 configs: stm32mp: add CONFIG_STM32_FMC2_EBI
This patch enables the support of FMC2 EBI.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:35 +02:00
Christophe Kerello
300669acd3 board: stm32mp1: update fdt fixup partitions table
This patch adds "st,stm32mp1-fmc2-nfc" compatible string in the
fdt fixup partitions table.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:35 +02:00
Christophe Kerello
82bf7729a2 mtd: rawnand: stm32_fmc2: get resources from parent node
FMC2 EBI support has been added. Common resources (registers base
address and clock) can now be shared between the 2 drivers using
"st,stm32mp1-fmc2-nfc" compatible string. It means that the
common resources should now be found in the parent device when EBI
node is available.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:34 +02:00
Christophe Kerello
6d47598629 memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver
The driver adds the support for the STMicroelectronics FMC2 EBI controller
found on STM32MP SOCs.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:34 +02:00
Christophe Kerello
834b85c9e8 mtd: rawnand: stm32_fmc2: use clrsetbits_le32
This patch uses clrsetbits_le32 function instead of multiple instructions.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:34 +02:00
Christophe Kerello
158f2d44a7 mtd: rawnand: stm32_fmc2: use FIELD_PREP/FIELD_GET macros
This patch removes custom macros and uses FIELD_PREP and FIELD_GET macros.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:34 +02:00
Christophe Kerello
7a6b328841 mtd: rawnand: stm32_fmc2: cosmetic change to use nfc instead of fmc2 where relevant
This patch renames functions and local variables.
This cleanup is done to get all functions starting by stm32_fmc2_nfc
in the FMC2 raw NAND driver when all functions will start by
stm32_fmc2_ebi in the FMC2 EBI driver.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:34 +02:00
Christophe Kerello
4a470044e1 mtd: rawnand: stm32_fmc2: use FMC2_TIMEOUT_5S for timeouts
FMC2_TIMEOUT_5S will be used each time that we need to wait.
It was seen, during stress tests in an overloaded system,
that we could be close to 1 second, even if we never met this
value. To be safe, FMC2_TIMEOUT_MS is set to 5 seconds.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:34 +02:00
Christophe Kerello
a3899b373f mtd: rawnand: stm32_fmc2: remove useless inline comments
Remove inline comments that are useless since function label are
self explanatory.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:34 +02:00
Christophe Kerello
e99e812e12 mtd: rawnand: stm32_fmc2: fix a buffer overflow
The chip select defined in the device tree could only be 0 or 1.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:53:34 +02:00
Patrick Delaunay
9a2b0540dc arm: stm32mp: stm32prog: use IS_ENABLED to prevent ifdef
Use IS_ENABLED to prevent ifdef in stm32prog command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
4e9e358fe8 arm: stm32mp: bsec: use IS_ENABLED to prevent ifdef
Use IS_ENABLED to prevent ifdef in bsec driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
06f624f28c board: stm32mp1: use IS_ENABLED to prevent ifdef in ft_board_setup
Use IS_ENABLED to prevent ifdef in ft_board_setup.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
ebfd592f16 board: stm32mp1: use IS_ENABLED to prevent ifdef in env functions
Use IS_ENABLED to prevent ifdef in env functions:
- env_get_location
- env_ext4_get_intf
- mmc_get_env_dev

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
72b099897a board: stm32mp1: use IS_ENABLED to prevent ifdef in board_late_init
Use IS_ENABLED to prevent ifdef in board_late_init.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
e817c8eca5 board: stm32mp1: use IS_ENABLED to prevent ifdef in dk2_i2c1_fix
Use IS_ENABLED to prevent ifdef in dk2_i2c1_fix.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
75f9b190e4 board: stm32mp1: use IS_ENABLED to prevent ifdef in set_dfu_alt_inf
Use CONFIG_IS_ENABLED to prevent ifdef in set_dfu_alt_inf.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
3434bbe698 board: stm32mp1: use IS_ENABLED to prevent ifdef in sysconf_init
Use IS_ENABLED to prevent ifdef in sysconf_init.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
feb6179ffe board: stm32mp1: use IS_ENABLED to prevent ifdef in board_check_usb_power
Use IS_ENABLED to prevent ifdef in board_check_usb_power.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:49 +02:00
Patrick Delaunay
6a8713bbe3 board: stm32mp1: use IS_ENABLED to prevent ifdef in g_dnl_board_usb_cable_connected
Use IS_ENABLED to prevent ifdef in g_dnl_board_usb_cable_connected
and in g_dnl_bind_fixup

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:48 +02:00
Patrick Delaunay
00bac2abcd board: stm32mp1: use IS_ENABLED to prevent ifdef in board_key_check
Use IS_ENABLED to prevent ifdef in board_key_check

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:52:48 +02:00
Patrice Chotard
f3858ce029 usb: host: dwc3-sti-glue: Fix ofnode_valid() parameter
node varaible is used as iterator into ofnode_for_each_subnode()
loop, when exiting of it, node is no more a valid ofnode.
Use dwc3_node instead as parameter of ofnode_valid()

Fixes: ac28e59a57 ("usb: Migrate to support live DT for some driver")
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
2020-08-13 09:19:18 +02:00
Frank Wunderlich
dbfca734d0 Makefile: fix annoying sunxi hack message
every compilation shows this error

 Hack for sunxi which doesn't have a proper binman definition for
 64-bit boards

not only for sunxi-boards/arm64

fix this by changing to real comments

Fixes: 9f55ee259d0c ("Makefile: sunxi: Don't use binman to build ATF image")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-12 08:06:00 -04:00
Tom Rini
c25344ff9a Merge tag 'ti-v2020.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Added support for J7200 evm
- DM_ETH and DM_USB migrations for omap3
- USB DFU and mass storage support for AM65x evm
- RTI watchdog support for K3 devices
- Fix an issue with L3 cache on K3 devices
2020-08-11 23:03:46 -04:00
Vignesh Raghavendra
db6451ec0e arm: dts: k3-j7200-common-proc-board: Enable CPSW2G port
Enable CPSW2G port to support networking in U-Boot

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
4bb4b06983 ARM: dts: k3-j7200-mcu-wakeup: Add CPSW2G support
Add MCU NAVSS, UDMA and CPSW2G DT nodes.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
28e29fbb4f ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodes
J7200 SoM has Cypress HyperFlash connected to HyperBus interface, add DT
entries for the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
9e8a9b6457 ARM: dts: k3-j7200: Add wkup gpio node
Add wkup_gpio0 node required for detecting whether board mux is set
HyperFlash.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
d2bc9875eb board: ti: j721e: Add support for HyperFlash detection
On J7200 SoC OSPI0 and HypeFlash are muxed at HW level and only one of
them can be used at any time. J7200 EVM has both HyperFlash and OSPI
flash on board. There is a user switch (SW3.1) that can be toggled to
select OSPI flash vs HyperFlash.
Read the state of this switch via wkup_gpio0_6 line and fixup the DT
nodes to select OSPI0 vs HyperFlash

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
86c9bd4eb7 arm: dts: k3-j7200: Add USB related DT entries
Add USB related DT entries to enable USB device mode.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
f8c1e893c8 configs: j7200_evm_a72: Add Initial support
Add initial A72 defconfig support.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
02dff65efe configs: j7200_evm_r5: Add initial support
Add initial R5 defconfig support

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-11 20:34:46 +05:30
Dave Gerlach
7cc9855f31 arm: dts: k3-j7200: Add R5 specific dts support
Add the basic a72 basic dts for j7200. Following nodes were supported:
- UART
- MMC SD
- I2C
- TISCI communication
- LPDDR with 1600MTs configuration.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
a7551cf05d arm: dts: k3-j7200: Add dts support
Add the basic a72 dts for j7200. Following nodes were supported:
- UART
- MMC SD
- I2C
- TISCI communication

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Kishon Vijay Abraham I
837933a620 soc: soc_ti_k3: Add device identification for J7200 SoC
Add device identification for J7200 SoC

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
6e802ef540 ram: k3-j721e: Relax version checks for memory controller
k3-j721e ddr driver sanity checks for product id and version number.
Version number gets changed for every minor update in the IP. So discard
the version check and just sanity check for product id.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
2cf09d7bed board: ti: j7200: Add board detection support for j7200
Add board detection support for j7200 common processor board.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
cf1d6867f7 board: ti: j7200: Introduce support for j7200 build targets
j7200-evm has minor differences with j721e-evm based on the IPs
available in the SoC. Introduce separate build targets for j7200-evm
to incorporate the differences.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
01dbe366ba arm: mach-k3: j7200: Detect if ROM has already loaded sysfw
Detect if sysfw is already loaded by ROM and pass this information to
sysfw loader. Based on this information sysfw loader either loads the
sysfw image from boot media or just receives the boot notification
message form sysfw.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
9c8f41beea arm: mach-k3: j7200: Add support for storing extended boot info from ROM
Starting J7200 SoC, ROM supports for loading sysfw directly from boot
image. ROM passes this information on number of images that are loaded
to bootloader at certain location. Add support for storing this
information before it gets corrupted.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
30de1ba0d3 arm: mach-k3: j7200: Add support for SOC detection
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.

Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
  capable dual Cortex-R5F MCUs and a Centralized Device Management and
  Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
  throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
  in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
  20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
  I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
  management.

See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1

Add support for detection J7200 SoC

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
73108dcd7f arm: mach-k3: j721e: Fix unlocking control module registers
In main control mmr there is no partition 4 and partition 6 is available
only on J721e. Fix the same in ctrl_mmr_unlock function

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
2a18be77de arm: mach-k3: j721e: Add detection for j721e
Add an api soc_is_j721e(), and use it to enable certain functionality
that is available only on j721e. This detection is needed when DT is not
available.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
dc57a554a5 arm: mach-k3: sysfw-loader: Add support for rom loading sysfw image
Starting J7200 SoC, ROM supports for loading sysfw directly from boot
image. In such cases, SPL need not load sysfw from boot media, but need
to receive boot notification message from sysfw. So separate out
remoteproc calls for system controller from sysfw loader and just
receive the boot notification if sysfw is already loaded.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
58ccd6105c arm: mach-k3: Move mmr_unlock to a common location
mmr_unlock api is common for all k3 devices. Move it to a common
location.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Jean-Jacques Hiblot
d099db2829 arm: mach-k3: Fix platform hang when SPL_MULTI_DTB_FIT is not enabled
If SPL_MULTI_DTB_FIT is not enabled, then CONFIG_SPL_OF_LIST is not defined
And in turn tispl.bin ends up not embedding any DTB.
Fixing it by using CONFIG_DEFAULT_DEVICE_TREE if SPL_OF_LIST is empty.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-11 20:34:46 +05:30
Suman Anna
0526460a50 board: ti: j721e: Update fdt fixup logic for interconnect nodes
The DT nodes on J721E SoCs currently use a node name "interconnect" for
the various interconnects. This name is not following the DT schema, and
should simply be "bus". Update the fdt fixup logic to use both the current
and the expected corrected path names so that this logic won't be broken
with newer kernels.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
b29a7cd09d board: ti: j721e: Probe eeprom only when CONFIG_TI_I2C_BOARD_DETECT is defined
Guard all eeprom probe with TI_I2C_BOARD_DETECT to avoid reading eeprom
when eeprom is not available

Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
6b889389b6 board: ti: board_detect: Add stub functions for EEPROM detection apis
Current usage of eeprom apis produce a build failure when
CONFIG_TI_I2C_BOARD_DETECT is not defined. Add stub function for these
apis to avoid build failures.

Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
49b2830c85 configs: Add new config for supporting USB mass storage boot
Because of space constraints, create a new USB defconfig for R5 to
faciliate booting from USB mass storage devices

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
cc445d70b0 configs: Add defconfig for USB DFU bootmode
Because of space constraints, create a new USB defconfig for R5 to
faciliate booting in USB peripheral (DFU) bootmode

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
eb5bf2f3b6 configs: am65x_evm_a53: Enable USB Mass storage and DFU boot modes
Enable configs to facilitate booting from USB Mass Storage devices
as well as USB peripheral boot

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
b528c725e7 configs: am65x_evm: Add support for DFU related configs
Add offset and environment related configs used for booting
from DFU.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
c20aee3e28 arm: dts: k3-am654-base-board: Add support for USB0 in SPL
Add nodes for USB0 in SPL to enable USB host boot mode

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
5251eb13bd arm: dts: k3-am654-r5-base-board: Add USB0 nodes
Add USB0 nodes and set them to host mode to support USB host and
peripheral boot modes

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
897e83f0a5 arm: mach-k3: am6_init: Add support for USB boot mode
Add support for identifying USB host and device boot modes

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
403fc5c9cf arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes
U-boot only supports either USB host or device mode for a node at a
time in dts. To support both host and dfu bootmodes, set "peripheral"
as the default dr_mode but fixup property to "host" if host bootmode
is detected.

This needs to happen before the dwc3 generic layer binds the usb device
to a host or device driver. Therefore, add an fdtdec_setup_board()
implementation to fixup the dt based on the boot mode.

Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe
in both the host and device cases. This is required for accessing the
interface at USB 2.0 speeds.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
febb47ac61 arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate config
Gate mmc related system related configurations with DM_MMC to avoid build
errors when MMC is not enabled

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
f5838b1542 arm: mach-k3: sysfw-loader: Add support to load SYSFW from USB
Add support for loading system firmware from a USB mass storage device

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
f9916b6d3b armv7R: K3: am654: Use full malloc in SPL both pre and post reloc
In order to be able to use things like file system drivers early on in
SPL (before relocation) in a memory-constrained environment when DDR is
not yet available we cannot use the simple malloc scheme which does not
implement the freeing of previously allocated memory blocks. To address
this issue go ahead and enable the use of the full malloc by manually
initializing the required functionality inside board_init_f by creating
a full malloc pool inside the pre-relocation malloc pool.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
39388aebed spl: usb: Only init usb once
usb_init() may be called multiple times for fetching multiple images
from SPL. Skip reinitializing USB if its already been done

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
c3ab97c1dd spl: usb: Create an API spl_usb_load()
Create a new API spl_usb_load() that takes the filename as a parameter
instead of taking the default U-boot PAYLOAD_NAME

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Suman Anna
fc4c380233 board: ti: am65x: Update fdt fixup logic for interconnect nodes
The DT nodes on AM65x SoCs currently use a node name "interconnect" for
the various interconnects. This name is not following the DT schema, and
should simply be "bus". Update the fdt fixup logic to use both the
current and the expected corrected path names so that this logic won't
be broken with newer kernels.

The logic also corrects the crypto node name as the DT node
unit-addresses are all expected to be lower case.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:45 +05:30
Faiz Abbas
7d6f45a210 mmc: am654_sdhci: Use MMC_MODES_END value instead of hardcoded value
The hardcoded array size leads to array overflows with changes in
speed modes enum in mmc core. Use MMC_MODES_END for otap_del_sel
array declaration to fix this.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-08-11 20:34:45 +05:30
Suman Anna
f3f2018f66 arm: dts: k3-j721e: Fix interconnect node names
The various CBASS interconnect nodes on K3 J721E SoCs are defined
using the node name "interconnect". This is not a valid node name
as per the dt-schema. Fix these node names to use the standard name
used for SoC interconnects, "bus".

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:45 +05:30
Suman Anna
58edc6f686 arm: dts: k3-am65: Fix interconnect node names
The various CBASS interconnect nodes on K3 AM65x SoCs are defined
using the node name "interconnect". This is not a valid node name
as per the dt-schema. Fix these node names to use the standard name
used for SoC interconnects, "bus".

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:45 +05:30
Derald D. Woods
5297a956cb ARM: omap3: evm: Complete DM_ETH and DM_USB migrations
This commit completes the migrations for DM_ETH and DM_USB. The board
is now consistent with omap3_beagle and other remaining OMAP3 boards.

Cc: Tom Rini <trini@konsulko.com>
Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
2020-08-11 20:34:45 +05:30
Tom Rini
b298720900 Merge tag 'efi-2020-10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc3

Bugs in the UEFI sub-system are fixed:

* use the optional data of the BootXXXX variables as load options
* simplify function public_key_verify_signature()
* amend a copyright notice
2020-08-11 08:56:52 -04:00
Andrew F. Davis
864e285739 arm: mach-k3: Clean non-coherent lines out of L3 cache
When switching on or off the ARM caches some care must be taken to ensure
existing cache line allocations are not left in an inconsistent state.
An example of this is when cache lines are considered non-shared by
and L3 controller even though the lines are shared. To prevent these
and other issues all cache lines should be cleared before enabling
or disabling a coherent master's cache. ARM cores and many L3 controllers
provide a way to efficiently clean out all cache lines to allow for
this, unfortunately there is no such easy way to do this on current K3
MSMC based systems.

We could explicitly clean out every valid external address tracked by
MSMC (all of DRAM), or we could attempt to identify only the set of
addresses accessed by a given boot stage and flush only those
specifically. This patch attempts the latter. We start with cleaning the
SPL load address. More addresses can be added here later as they are
identified.

Note that we perform a flush operation for both the flush and invalidate
operations, this is not a typo. We do this to avoid the situation that
some ARM cores will promote an invalidate to a clean+invalidate, but only
emit the invalidation operation externally, leading to a loss of data.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Tested-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 10:18:27 +05:30
Jan Kiszka
e1c3668594 arm: dts: k3: Add RTI watchdogs
Add DT entries for main domain watchdog0 and 1 instances on the J721e
well as RTI1-based watchdog on the AM65x. RTI0 does not work for this
purpose on the AM65x, so leave it out.

On AM65x, we mark the power-domain as shared because RTI firmware such
as https://github.com/siemens/k3-rti-wdt may request it as well in order
to prevent accidental shutdown of the watchdog.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2020-08-11 10:18:27 +05:30
Jan Kiszka
d388f360ed watchdog: Add support for K3 RTI watchdog
This is based on the Linux kernel driver for the RTI watchdog.

To actually reset the system on an AM65x, it requires firmware running
on the R5 that accepts the NMI and issues the actual system reset via
TISCI. Kind of an iTCO, except that this watchdog hardware has support
for no-way-out, and only for that.

On the J721E, reset works without extra firmware help when routing the
RTI interrupt via the ESM.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2020-08-11 10:18:27 +05:30
Tom Rini
c045207f96 Prepare v2020.10-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-10 16:10:09 -04:00
Heinrich Schuchardt
0ad64007fe efi_loader: set load options in boot manager
Up to now we used the value of the bootargs environment variable as load
options in the boot manager. This is not correct. The data has to be taken
from the Boot#### variable.

Let the boot manager copy the optional data of the EFI_LOAD_OPTION as load
options to the loaded image protocol.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-08 19:03:24 +02:00
Heinrich Schuchardt
1064d04920 efi_loader: factor out efi_set_load_options()
The bootefi bootmgr command has to set the load options for a loaded image
from the value of BootXXXX variable. If the boot manager is not used, the
value is set from the environment variable bootargs (or efi_selftest).

Factor out a common function efi_set_load_options().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-08 19:03:24 +02:00
AKASHI Takahiro
dd92aad81c efi_loader: add copyright notice
Some amount of code was moved/derived from efi_variable.c regarding
UEFI secure boot, in particluar in the commit 012c56ac76 ("efi_loader:
restructure code for TEE variables").
So add the orignal author's copyright notice.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-08 19:03:24 +02:00
Heinrich Schuchardt
9bdbc8ef98 lib/crypto: simplify public_key_verify_signature
The variable region is filled but never used. Remove it.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-08 19:03:12 +02:00
2610 changed files with 171839 additions and 20777 deletions

View File

@@ -2,7 +2,7 @@ variables:
windows_vm: vs2017-win2016 windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04 ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15 macos_vm: macOS-10.15
ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200713-05Aug2020 ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020
# Add '-u 0' options for Azure pipelines, otherwise we get "permission # Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root. # since our $(ci_runner_image) user is not root.
@@ -253,6 +253,18 @@ jobs:
qemu_x86_64: qemu_x86_64:
TEST_PY_BD: "qemu-x86_64" TEST_PY_BD: "qemu-x86_64"
TEST_PY_TEST_SPEC: "not sleep" TEST_PY_TEST_SPEC: "not sleep"
r2dplus_i82557c:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id i82557c_qemu"
r2dplus_pcnet:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id pcnet_qemu"
r2dplus_rtl8139:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id rtl8139_qemu"
r2dplus_tulip:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id tulip_qemu"
xilinx_zynq_virt: xilinx_zynq_virt:
TEST_PY_BD: "xilinx_zynq_virt" TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_ID: "--id qemu" TEST_PY_ID: "--id qemu"

View File

@@ -2,7 +2,7 @@
# Grab our configured image. The source for this is found at: # Grab our configured image. The source for this is found at:
# https://gitlab.denx.de/u-boot/gitlab-ci-runner # https://gitlab.denx.de/u-boot/gitlab-ci-runner
image: trini/u-boot-gitlab-ci-runner:bionic-20200713-05Aug2020 image: trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020
# We run some tests in different order, to catch some failures quicker. # We run some tests in different order, to catch some failures quicker.
stages: stages:
@@ -359,6 +359,34 @@ qemu-x86_64 test.py:
TEST_PY_TEST_SPEC: "not sleep" TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn <<: *buildman_and_testpy_dfn
r2dplus_i82557c test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id i82557c_qemu"
<<: *buildman_and_testpy_dfn
r2dplus_pcnet test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id pcnet_qemu"
<<: *buildman_and_testpy_dfn
r2dplus_rtl8139 test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id rtl8139_qemu"
<<: *buildman_and_testpy_dfn
r2dplus_tulip test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id tulip_qemu"
<<: *buildman_and_testpy_dfn
xilinx_zynq_virt test.py: xilinx_zynq_virt test.py:
tags: [ 'all' ] tags: [ 'all' ]
variables: variables:

View File

@@ -646,6 +646,34 @@ matrix:
QEMU_TARGET="x86_64-softmmu" QEMU_TARGET="x86_64-softmmu"
TOOLCHAIN="i386" TOOLCHAIN="i386"
BUILD_ROM="yes" BUILD_ROM="yes"
- name: "test/py r2dplus_i82557c"
env:
- TEST_PY_BD="r2dplus"
TEST_PY_ID="--id i82557c_qemu"
QEMU_TARGET="sh4-softmmu"
BUILDMAN="sh -x arm"
TOOLCHAIN="sh"
- name: "test/py r2dplus_pcnet"
env:
- TEST_PY_BD="r2dplus"
TEST_PY_ID="--id pcnet_qemu"
QEMU_TARGET="sh4-softmmu"
BUILDMAN="sh -x arm"
TOOLCHAIN="sh"
- name: "test/py r2dplus_rtl8139"
env:
- TEST_PY_BD="r2dplus"
TEST_PY_ID="--id rtl8139_qemu"
QEMU_TARGET="sh4-softmmu"
BUILDMAN="sh -x arm"
TOOLCHAIN="sh"
- name: "test/py r2dplus_tulip"
env:
- TEST_PY_BD="r2dplus"
TEST_PY_ID="--id tulip_qemu"
QEMU_TARGET="sh4-softmmu"
BUILDMAN="sh -x arm"
TOOLCHAIN="sh"
- name: "test/py xilinx_zynq_virt" - name: "test/py xilinx_zynq_virt"
env: env:
- TEST_PY_BD="xilinx_zynq_virt" - TEST_PY_BD="xilinx_zynq_virt"

370
Kconfig
View File

@@ -105,6 +105,24 @@ config CC_COVERAGE
config CC_HAS_ASM_INLINE config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null) def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null)
config XEN
bool "Select U-Boot be run as a bootloader for XEN Virtual Machine"
help
Enabling this option will make U-Boot be run as a bootloader
for XEN [1] Virtual Machine.
Xen is a virtual machine monitor (VMM) or a type-1 hypervisor with support
for para-virtualization. Xen can organize the safe execution of several
virtual machines on the same physical system with performance close to
native. It is used as the basis for a number of different commercial and
open source applications, such as: server virtualization, Infrastructure
as a Service (IaaS), desktop virtualization, security applications,
embedded and hardware appliances.
Xen has a special VM called Domain-0 that runs the Dom0 kernel and allows
Xen to use the device drivers for the Domain-0 kernel by default.
[1] - https://xenproject.org/
config DISTRO_DEFAULTS config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions" bool "Select defaults suitable for booting general purpose Linux distributions"
select AUTO_COMPLETE select AUTO_COMPLETE
@@ -178,11 +196,11 @@ config SYS_MALLOC_F_LEN
hex "Size of malloc() pool before relocation" hex "Size of malloc() pool before relocation"
depends on SYS_MALLOC_F depends on SYS_MALLOC_F
default 0x1000 if AM33XX default 0x1000 if AM33XX
default 0x2800 if SANDBOX default 0x4000 if SANDBOX
default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \ default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \ ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
ARCH_LS1046A || ARCH_QEMU) ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI)
default 0x400 default 0x400
help help
Before relocation, memory is very limited on many platforms. Still, Before relocation, memory is very limited on many platforms. Still,
@@ -404,346 +422,16 @@ config SYS_SRAM_SIZE
default 0x10000 if TARGET_TRICORDER default 0x10000 if TARGET_TRICORDER
default 0x0 default 0x0
config EXAMPLES
bool "Compile API examples"
depends on !SANDBOX
default y if ARCH_QEMU
help
U-Boot provides an API for standalone applications. Examples are
provided in directory examples/.
endmenu # General setup endmenu # General setup
menu "Boot images"
config ANDROID_BOOT_IMAGE
bool "Enable support for Android Boot Images"
default y if FASTBOOT
help
This enables support for booting images which use the Android
image format header.
config FIT
bool "Support Flattened Image Tree"
select MD5
select SHA1
help
This option allows you to boot the new uImage structure,
Flattened Image Tree. FIT is formally a FDT, which can include
images of various types (kernel, FDT blob, ramdisk, etc.)
in a single blob. To boot this new uImage structure,
pass the address of the blob to the "bootm" command.
FIT is very flexible, supporting compression, multiple images,
multiple configurations, verification through hashing and also
verified boot (secure boot using RSA).
if FIT
config FIT_EXTERNAL_OFFSET
hex "FIT external data offset"
default 0x0
help
This specifies a data offset in fit image.
The offset is from data payload offset to the beginning of
fit image header. When specifies a offset, specific data
could be put in the hole between data payload and fit image
header, such as CSF data on i.MX platform.
config FIT_ENABLE_SHA256_SUPPORT
bool "Support SHA256 checksum of FIT image contents"
default y
select SHA256
help
Enable this to support SHA256 checksum of FIT image contents. A
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
the image contents have not been corrupted.
config FIT_ENABLE_SHA384_SUPPORT
bool "Support SHA384 checksum of FIT image contents"
default n
select SHA384
help
Enable this to support SHA384 checksum of FIT image contents. A
SHA384 checksum is a 384-bit (48-byte) hash value used to check that
the image contents have not been corrupted. Use this for the highest
security.
config FIT_ENABLE_SHA512_SUPPORT
bool "Support SHA512 checksum of FIT image contents"
default n
select SHA512
help
Enable this to support SHA512 checksum of FIT image contents. A
SHA512 checksum is a 512-bit (64-byte) hash value used to check that
the image contents have not been corrupted.
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on DM
select HASH
select RSA
select RSA_VERIFY
select IMAGE_SIGN_INFO
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA. If
CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
hashing is available using hardware, then the RSA library will use
it. See doc/uImage.FIT/signature.txt for more details.
WARNING: When relying on signed FIT images with a required signature
check the legacy image format is disabled by default, so that
unsigned images cannot be loaded. If a board needs the legacy image
format support in this case, enable it using
CONFIG_LEGACY_IMAGE_FORMAT.
config FIT_SIGNATURE_MAX_SIZE
hex "Max size of signed FIT structures"
depends on FIT_SIGNATURE
default 0x10000000
help
This option sets a max size in bytes for verified FIT uImages.
A sane value of 256MB protects corrupted DTB structures from overlapping
device memory. Assure this size does not extend past expected storage
space.
config FIT_ENABLE_RSASSA_PSS_SUPPORT
bool "Support rsassa-pss signature scheme of FIT image contents"
depends on FIT_SIGNATURE
default n
help
Enable this to support the pss padding algorithm as described
in the rfc8017 (https://tools.ietf.org/html/rfc8017).
config FIT_CIPHER
bool "Enable ciphering data in a FIT uImages"
depends on DM
select AES
help
Enable the feature of data ciphering/unciphering in the tool mkimage
and in the u-boot support of the FIT image.
config FIT_VERBOSE
bool "Show verbose messages when FIT images fail"
help
Generally a system will have valid FIT images so debug messages
are a waste of code space. If you are debugging your images then
you can enable this option to get more verbose information about
failures.
config FIT_BEST_MATCH
bool "Select the best match for the kernel device tree"
help
When no configuration is explicitly selected, default to the
one whose fdt's compatibility field best matches that of
U-Boot itself. A match is considered "best" if it matches the
most specific compatibility entry of U-Boot's fdt's root node.
The order of entries in the configuration's fdt is ignored.
config FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by U-Boot"
depends on TI_SECURE_DEVICE
help
Allows doing any sort of manipulation to blobs after they got extracted
from FIT images like stripping off headers or modifying the size of the
blob, verification, authentication, decryption etc. in a platform or
board specific way. In order to use this feature a platform or board-
specific implementation of board_fit_image_post_process() must be
provided. Also, anything done during this post-processing step would
need to be comprehended in how the images were prepared before being
injected into the FIT creation (i.e. the blobs would have been pre-
processed before being added to the FIT image).
if SPL
config SPL_FIT
bool "Support Flattened Image Tree within SPL"
depends on SPL
select SPL_OF_LIBFDT
config SPL_FIT_PRINT
bool "Support FIT printing within SPL"
depends on SPL_FIT
help
Support printing the content of the fitImage in a verbose manner in SPL.
config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
depends on SPL_DM
select SPL_FIT
select SPL_CRYPTO_SUPPORT
select SPL_HASH_SUPPORT
select SPL_RSA
select SPL_RSA_VERIFY
select SPL_IMAGE_SIGN_INFO
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
of the build. This contains U-Boot along with information as to
where it should be loaded. This option instead enables generation
of a FIT (Flat Image Tree) which provides more flexibility. In
particular it can handle selecting from multiple device tree
and passing the correct one to U-Boot.
config SPL_LOAD_FIT_ADDRESS
hex "load address of fit image"
depends on SPL_LOAD_FIT
default 0x0
help
Specify the load address of the fit image that will be loaded
by SPL.
config SPL_LOAD_FIT_APPLY_OVERLAY
bool "Enable SPL applying DT overlays from FIT"
depends on SPL_LOAD_FIT
select OF_LIBFDT_OVERLAY
help
The device tree is loaded from the FIT image. Allow the SPL is to
also load device-tree overlays from the FIT image an apply them
over the device tree.
config SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ
depends on SPL_LOAD_FIT_APPLY_OVERLAY
default 0x10000
hex "size of temporary buffer used to load the overlays"
help
The size of the area where the overlays will be loaded and
uncompress. Must be at least as large as biggest overlay
(uncompressed)
config SPL_LOAD_FIT_FULL
bool "Enable SPL loading U-Boot as a FIT (full fitImage features)"
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
of the build. This contains U-Boot along with information as to
where it should be loaded. This option instead enables generation
of a FIT (Flat Image Tree) which provides more flexibility. In
particular it can handle selecting from multiple device tree
and passing the correct one to U-Boot.
config SPL_FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by the SPL"
depends on SPL_LOAD_FIT
help
Allows doing any sort of manipulation to blobs after they got extracted
from the U-Boot FIT image like stripping off headers or modifying the
size of the blob, verification, authentication, decryption etc. in a
platform or board specific way. In order to use this feature a platform
or board-specific implementation of board_fit_image_post_process() must
be provided. Also, anything done during this post-processing step would
need to be comprehended in how the images were prepared before being
injected into the FIT creation (i.e. the blobs would have been pre-
processed before being added to the FIT image).
config SPL_FIT_SOURCE
string ".its source file for U-Boot FIT image"
depends on SPL_FIT
help
Specifies a (platform specific) FIT source file to generate the
U-Boot FIT image. This could specify further image to load and/or
execute.
config USE_SPL_FIT_GENERATOR
bool "Use a script to generate the .its script"
default y if SPL_FIT
config SPL_FIT_GENERATOR
string ".its file generator script for U-Boot FIT image"
depends on USE_SPL_FIT_GENERATOR
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP
default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
Specifies a (platform specific) script file to generate the FIT
source file used to build the U-Boot FIT image file. This gets
passed a list of supported device tree file stub names to
include in the generated image.
endif # SPL
endif # FIT
config LEGACY_IMAGE_FORMAT
bool "Enable support for the legacy image format"
default y if !FIT_SIGNATURE
help
This option enables the legacy image format. It is enabled by
default for backward compatibility, unless FIT_SIGNATURE is
set where it is disabled so that unsigned images cannot be
loaded. If a board needs the legacy image format support in this
case, enable it here.
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
depends on OF_LIBFDT
help
This causes U-Boot to call ft_board_setup() before booting into
the Operating System. This function can set up various
board-specific information in the device tree for use by the OS.
The device tree is then passed to the OS.
config OF_SYSTEM_SETUP
bool "Set up system-specific details in device tree before boot"
depends on OF_LIBFDT
help
This causes U-Boot to call ft_system_setup() before booting into
the Operating System. This function can set up various
system-specific information in the device tree for use by the OS.
The device tree is then passed to the OS.
config OF_STDOUT_VIA_ALIAS
bool "Update the device-tree stdout alias from U-Boot"
depends on OF_LIBFDT
help
This uses U-Boot's serial alias from the aliases node to update
the device tree passed to the OS. The "linux,stdout-path" property
in the chosen node is set to point to the correct serial node.
This option currently references CONFIG_CONS_INDEX, which is
incorrect when used with device tree as this option does not
exist / should not be used.
config SYS_EXTRA_OPTIONS
string "Extra Options (DEPRECATED)"
help
The old configuration infrastructure (= mkconfig + boards.cfg)
provided the extra options field. If you have something like
"HAS_BAR,BAZ=64", the optional options
#define CONFIG_HAS
#define CONFIG_BAZ 64
will be defined in include/config.h.
This option was prepared for the smooth migration from the old
configuration to Kconfig. Since this option will be removed sometime,
new boards should not use this option.
config HAVE_SYS_TEXT_BASE
bool
depends on !NIOS2 && !XTENSA
depends on !EFI_APP
default y
config SYS_TEXT_BASE
depends on HAVE_SYS_TEXT_BASE
default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
hex "Text Base"
help
The address in memory that U-Boot will be running from, initially.
config SYS_CLK_FREQ
depends on ARC || ARCH_SUNXI || MPC83xx
int "CPU clock frequency"
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
config ARCH_FIXUP_FDT_MEMORY
bool "Enable arch_fixup_memory_banks() call"
default y
help
Enable FDT memory map syncup before OS boot. This feature can be
used for booting OS with different memory setup where the part of
the memory location should be used for different purpose.
endmenu # Boot images
source "api/Kconfig" source "api/Kconfig"
source "common/Kconfig" source "common/Kconfig"
@@ -765,3 +453,5 @@ source "fs/Kconfig"
source "lib/Kconfig" source "lib/Kconfig"
source "test/Kconfig" source "test/Kconfig"
source "tools/Kconfig"

View File

@@ -149,5 +149,6 @@ BSD 3-clause "New" or "Revised" License BSD-3-Clause Y bsd-3-clause.txt http:/
IBM PIBS (PowerPC Initialization and IBM-pibs ibm-pibs.txt IBM PIBS (PowerPC Initialization and IBM-pibs ibm-pibs.txt
Boot Software) license Boot Software) license
ISC License ISC Y isc.txt https://spdx.org/licenses/ISC ISC License ISC Y isc.txt https://spdx.org/licenses/ISC
MIT License MIT Y mit.txt https://spdx.org/licenses/MIT.html
SIL OPEN FONT LICENSE (OFL-1.1) OFL-1.1 Y OFL.txt https://spdx.org/licenses/OFL-1.1.html SIL OPEN FONT LICENSE (OFL-1.1) OFL-1.1 Y OFL.txt https://spdx.org/licenses/OFL-1.1.html
X11 License X11 x11.txt https://spdx.org/licenses/X11.html X11 License X11 x11.txt https://spdx.org/licenses/X11.html

20
Licenses/mit.txt Normal file
View File

@@ -0,0 +1,20 @@
MIT License
Copyright (c) 2020 EPAM Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

View File

@@ -148,6 +148,18 @@ F: include/configs/meson64_android.h
F: doc/board/amlogic/ F: doc/board/amlogic/
N: meson N: meson
ARM ASPEED
M: Ryan Chen <ryan_chen@aspeedtech.com>
M: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
R: Aspeed BMC SW team <BMC-SW@aspeedtech.com>
S: Maintained
F: arch/arm/mach-aspeed/
F: arch/arm/include/asm/arch-aspeed/
F: board/aspeed/
F: drivers/clk/aspeed/
F: drivers/pinctrl/aspeed/
N: aspeed
ARM BROADCOM BCM283X ARM BROADCOM BCM283X
M: Matthias Brugger <mbrugger@suse.com> M: Matthias Brugger <mbrugger@suse.com>
S: Maintained S: Maintained
@@ -225,6 +237,13 @@ M: Luka Kovacic <luka.kovacic@sartura.hr>
M: Luka Perkov <luka.perkov@sartura.hr> M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained S: Maintained
F: arch/arm/mach-ipq40xx/ F: arch/arm/mach-ipq40xx/
F: include/dt-bindings/clock/qcom,ipq4019-gcc.h
F: include/dt-bindings/reset/qcom,ipq4019-reset.h
F: drivers/reset/reset-ipq4019.c
F: drivers/phy/phy-qcom-ipq4019-usb.c
F: drivers/spi/spi-qup.c
F: drivers/net/mdio-ipq4019.c
F: drivers/rng/msm_rng.c
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de> M: Stefan Roese <sr@denx.de>
@@ -250,6 +269,7 @@ F: arch/arm/include/asm/arch-pxa/
ARM MEDIATEK ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com> M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com> M: Weijie Gao <weijie.gao@mediatek.com>
M: Chunfeng Yun <chunfeng.yun@mediatek.com>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com> R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained S: Maintained
F: arch/arm/mach-mediatek/ F: arch/arm/mach-mediatek/
@@ -266,6 +286,8 @@ F: drivers/power/domain/mtk-power-domain.c
F: drivers/ram/mediatek/ F: drivers/ram/mediatek/
F: drivers/spi/mtk_snfi_spi.c F: drivers/spi/mtk_snfi_spi.c
F: drivers/timer/mtk_timer.c F: drivers/timer/mtk_timer.c
F: drivers/usb/host/xhci-mtk.c
F: drivers/usb/mtu3/
F: drivers/watchdog/mtk_wdt.c F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c F: drivers/net/mtk_eth.c
F: drivers/reset/reset-mediatek.c F: drivers/reset/reset-mediatek.c
@@ -279,7 +301,9 @@ S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git T: git https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git
F: arch/arm/mach-at91/ F: arch/arm/mach-at91/
F: board/atmel/ F: board/atmel/
F: drivers/cpu/at91_cpu.c
F: drivers/misc/microchip_flexcom.c F: drivers/misc/microchip_flexcom.c
F: drivers/timer/mchp-pit64b-timer.c
ARM NEXELL S5P4418 ARM NEXELL S5P4418
M: Stefan Bosch <stefan_b@posteo.net> M: Stefan Bosch <stefan_b@posteo.net>
@@ -412,6 +436,7 @@ F: drivers/power/regulator/stpmic1.c
F: drivers/ram/stm32mp1/ F: drivers/ram/stm32mp1/
F: drivers/remoteproc/stm32_copro.c F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32-reset.c F: drivers/reset/stm32-reset.c
F: drivers/rng/stm32mp1_rng.c
F: drivers/rtc/stm32_rtc.c F: drivers/rtc/stm32_rtc.c
F: drivers/serial/serial_stm32.* F: drivers/serial/serial_stm32.*
F: drivers/spi/stm32_qspi.c F: drivers/spi/stm32_qspi.c
@@ -425,6 +450,8 @@ F: include/dt-bindings/pinctrl/stm32-pinfunc.h
F: include/dt-bindings/reset/stm32mp1-resets.h F: include/dt-bindings/reset/stm32mp1-resets.h
F: include/stm32_rcc.h F: include/stm32_rcc.h
F: tools/stm32image.c F: tools/stm32image.c
N: stm
N: stm32
ARM STM STV0991 ARM STM STV0991
@@ -494,9 +521,7 @@ F: arch/arm/mach-u8500/
F: drivers/timer/nomadik-mtu-timer.c F: drivers/timer/nomadik-mtu-timer.c
ARM UNIPHIER ARM UNIPHIER
M: Masahiro Yamada <yamada.masahiro@socionext.com> S: Orphan (Since 2020-09)
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier.git
F: arch/arm/mach-uniphier/ F: arch/arm/mach-uniphier/
F: configs/uniphier_*_defconfig F: configs/uniphier_*_defconfig
N: uniphier N: uniphier
@@ -589,6 +614,8 @@ F: tools/binman/
BTRFS BTRFS
M: Marek Behun <marek.behun@nic.cz> M: Marek Behun <marek.behun@nic.cz>
R: Qu Wenruo <wqu@suse.com>
L: linux-btrfs@vger.kernel.org
S: Maintained S: Maintained
F: cmd/btrfs.c F: cmd/btrfs.c
F: fs/btrfs/ F: fs/btrfs/
@@ -609,7 +636,7 @@ F: drivers/mtd/jedec_flash.c
CLOCK CLOCK
M: Lukasz Majewski <lukma@denx.de> M: Lukasz Majewski <lukma@denx.de>
S: Maintained S: Maintained
T: git git://git.denx.de/u-boot-dfu.git T: git https://gitlab.denx.de/u-boot/custodians/u-boot-clk.git
F: drivers/clk/ F: drivers/clk/
F: drivers/clk/imx/ F: drivers/clk/imx/
@@ -651,6 +678,7 @@ S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
F: doc/api/efi.rst F: doc/api/efi.rst
F: doc/uefi/* F: doc/uefi/*
F: drivers/rtc/emul_rtc.c
F: include/capitalization.h F: include/capitalization.h
F: include/charset.h F: include/charset.h
F: include/cp1250.h F: include/cp1250.h
@@ -911,13 +939,17 @@ S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/ F: arch/riscv/
F: cmd/riscv/ F: cmd/riscv/
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c F: tools/prelink-riscv.c
RISC-V KENDRYTE RISC-V KENDRYTE
M: Sean Anderson <seanga2@gmail.com> M: Sean Anderson <seanga2@gmail.com>
S: Maintained S: Maintained
F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
F: doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt
F: drivers/clk/kendryte/ F: drivers/clk/kendryte/
F: drivers/pinctrl/kendryte/
F: include/kendryte/ F: include/kendryte/
RNG RNG
@@ -941,6 +973,8 @@ SANDBOX
M: Simon Glass <sjg@chromium.org> M: Simon Glass <sjg@chromium.org>
S: Maintained S: Maintained
F: arch/sandbox/ F: arch/sandbox/
F: doc/arch/sandbox.rst
F: include/dt-bindings/*/sandbox*.h
SH SH
M: Marek Vasut <marek.vasut+renesas@gmail.com> M: Marek Vasut <marek.vasut+renesas@gmail.com>
@@ -973,6 +1007,8 @@ F: include/spmi/
SQUASHFS SQUASHFS
M: Joao Marcos Costa <joaomarcos.costa@bootlin.com> M: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
R: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
R: Miquel Raynal <miquel.raynal@bootlin.com>
S: Maintained S: Maintained
F: fs/squashfs/ F: fs/squashfs/
F: include/sqfs.h F: include/sqfs.h
@@ -993,6 +1029,10 @@ F: arch/arm/dts/ns3-board.dts
F: arch/arm/dts/ns3.dtsi F: arch/arm/dts/ns3.dtsi
F: arch/arm/cpu/armv8/bcmns3 F: arch/arm/cpu/armv8/bcmns3
F: arch/arm/include/asm/arch-bcmns3/ F: arch/arm/include/asm/arch-bcmns3/
F: cmd/broadcom/Makefile
F: cmd/broadcom/chimp_boot.c
F: cmd/broadcom/nitro_image_load.c
F: cmd/broadcom/chimp_handshake.c
TDA19988 HDMI ENCODER TDA19988 HDMI ENCODER
M: Liviu Dudau <liviu.dudau@foss.arm.com> M: Liviu Dudau <liviu.dudau@foss.arm.com>
@@ -1085,6 +1125,22 @@ T: git https://gitlab.denx.de/u-boot/custodians/u-boot-x86.git
F: arch/x86/ F: arch/x86/
F: cmd/x86/ F: cmd/x86/
XEN
M: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
M: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
S: Maintained
F: arch/arm/cpu/armv8/xen/
F: arch/arm/include/asm/xen.h
F: arch/arm/include/asm/xen/
F: cmd/pvblock.c
F: drivers/serial/serial_xen.c
F: drivers/xen/
F: include/pvblock.h
F: include/xen/
F: include/xen.h
F: lib/sscanf.c
F: test/lib/sscanf.c
XTENSA XTENSA
M: Max Filippov <jcmvbkbc@gmail.com> M: Max Filippov <jcmvbkbc@gmail.com>
S: Maintained S: Maintained

View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
VERSION = 2020 VERSION = 2021
PATCHLEVEL = 10 PATCHLEVEL = 01
SUBLEVEL = SUBLEVEL =
EXTRAVERSION = -rc1 EXTRAVERSION = -rc1
NAME = NAME =
@@ -795,6 +795,7 @@ libs-y += drivers/usb/eth/
libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/ libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/ libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
libs-y += drivers/usb/host/ libs-y += drivers/usb/host/
libs-y += drivers/usb/mtu3/
libs-y += drivers/usb/musb/ libs-y += drivers/usb/musb/
libs-y += drivers/usb/musb-new/ libs-y += drivers/usb/musb-new/
libs-y += drivers/usb/phy/ libs-y += drivers/usb/phy/
@@ -859,13 +860,13 @@ else
BOARD_SIZE_CHECK = BOARD_SIZE_CHECK =
endif endif
ifneq ($(CONFIG_SPL_SIZE_LIMIT),0) ifneq ($(CONFIG_SPL_SIZE_LIMIT),0x0)
SPL_SIZE_CHECK = @$(call size_check,$@,$$(tools/spl_size_limit)) SPL_SIZE_CHECK = @$(call size_check,$@,$$(tools/spl_size_limit))
else else
SPL_SIZE_CHECK = SPL_SIZE_CHECK =
endif endif
ifneq ($(CONFIG_TPL_SIZE_LIMIT),0) ifneq ($(CONFIG_TPL_SIZE_LIMIT),0x0)
TPL_SIZE_CHECK = @$(call size_check,$@,$(CONFIG_TPL_SIZE_LIMIT)) TPL_SIZE_CHECK = @$(call size_check,$@,$(CONFIG_TPL_SIZE_LIMIT))
else else
TPL_SIZE_CHECK = TPL_SIZE_CHECK =
@@ -884,7 +885,7 @@ cmd_static_rela = \
tools/relocate-rela $(3) $(4) $$start $$end tools/relocate-rela $(3) $(4) $$start $$end
else else
quiet_cmd_static_rela = quiet_cmd_static_rela =
cmd_static_rela = cmd_static_rela = true
endif endif
# Always append INPUTS so that arch config.mk's can add custom ones # Always append INPUTS so that arch config.mk's can add custom ones
@@ -923,11 +924,6 @@ INPUTS-$(CONFIG_REMAKE_ELF) += u-boot.elf
INPUTS-$(CONFIG_EFI_APP) += u-boot-app.efi INPUTS-$(CONFIG_EFI_APP) += u-boot-app.efi
INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi
# Build a combined spl + u-boot image for sunxi
ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_ARM64)$(CONFIG_SPL),yyy)
INPUTS-y += u-boot-sunxi-with-spl.bin
endif
# Generate this input file for binman # Generate this input file for binman
ifeq ($(CONFIG_SPL),) ifeq ($(CONFIG_SPL),)
INPUTS-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin INPUTS-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
@@ -1024,13 +1020,9 @@ PHONY += inputs
inputs: $(INPUTS-y) inputs: $(INPUTS-y)
all: .binman_stamp inputs all: .binman_stamp inputs
# Hack for sunxi which doesn't have a proper binman definition for
# 64-bit boards
ifneq ($(CONFIG_ARCH_SUNXI)$(CONFIG_ARM64),yy)
ifeq ($(CONFIG_BINMAN),y) ifeq ($(CONFIG_BINMAN),y)
$(call if_changed,binman) $(call if_changed,binman)
endif endif
endif
# Timestamp file to make sure that binman always runs # Timestamp file to make sure that binman always runs
.binman_stamp: FORCE .binman_stamp: FORCE
@@ -1317,9 +1309,13 @@ init_sp_bss_offset_check: u-boot.dtb FORCE
fi fi
endif endif
shell_cmd = { $(echo-cmd) $(cmd_$(1)); }
quiet_cmd_objcopy_uboot = OBJCOPY $@
cmd_objcopy_uboot = $(cmd_objcopy) && $(call shell_cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE)) || rm -f $@
u-boot-nodtb.bin: u-boot FORCE u-boot-nodtb.bin: u-boot FORCE
$(call if_changed,objcopy) $(call if_changed,objcopy_uboot)
$(call cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE))
$(BOARD_SIZE_CHECK) $(BOARD_SIZE_CHECK)
u-boot.ldr: u-boot u-boot.ldr: u-boot
@@ -1330,13 +1326,17 @@ u-boot.ldr: u-boot
# binman # binman
# --------------------------------------------------------------------------- # ---------------------------------------------------------------------------
# Use 'make BINMAN_DEBUG=1' to enable debugging # Use 'make BINMAN_DEBUG=1' to enable debugging
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
quiet_cmd_binman = BINMAN $@ quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
--toolpath $(objtree)/tools \ --toolpath $(objtree)/tools \
$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \ $(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
build -u -d u-boot.dtb -O . \ build -u -d u-boot.dtb -O . -m --allow-missing \
$(if $(BUILD_ROM),,-m --allow-missing) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
-a atf-bl31-path=${BL31} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
$(BINMAN_$(@F)) $(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@@ -1446,11 +1446,13 @@ else
MKIMAGEFLAGS_u-boot.itb = -E MKIMAGEFLAGS_u-boot.itb = -E
endif endif
ifdef U_BOOT_ITS
u-boot.itb: u-boot-nodtb.bin \ u-boot.itb: u-boot-nodtb.bin \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
$(U_BOOT_ITS) FORCE $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage) $(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK) $(BOARD_SIZE_CHECK)
endif
u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage) $(call if_changed,mkimage)
@@ -1580,21 +1582,30 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat) $(call if_changed,pad_cat)
ifneq ($(CONFIG_ARCH_SOCFPGA),) ifneq ($(CONFIG_ARCH_SOCFPGA),)
quiet_cmd_gensplx4 = GENSPLX4 $@
cmd_gensplx4 = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
spl/u-boot-spl.sfp spl/u-boot-spl.sfp > $@ || rm -f $@
spl/u-boot-splx4.sfp: spl/u-boot-spl.sfp FORCE
$(call if_changed,gensplx4)
quiet_cmd_socboot = SOCBOOT $@ quiet_cmd_socboot = SOCBOOT $@
cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ cmd_socboot = cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ u-boot-with-spl.sfp: spl/u-boot-splx4.sfp u-boot.img FORCE
u-boot.img > $@ || rm -f $@
u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
$(call if_changed,socboot) $(call if_changed,socboot)
quiet_cmd_socnandboot = SOCNANDBOOT $@ quiet_cmd_gensplpadx4 = GENSPLPADX4 $@
cmd_socnandboot = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \ cmd_gensplpadx4 = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \
cat spl/u-boot-spl.sfp spl/u-boot-spl.pad \ cat spl/u-boot-spl.sfp spl/u-boot-spl.pad \
spl/u-boot-spl.sfp spl/u-boot-spl.pad \ spl/u-boot-spl.sfp spl/u-boot-spl.pad \
spl/u-boot-spl.sfp spl/u-boot-spl.pad \ spl/u-boot-spl.sfp spl/u-boot-spl.pad \
spl/u-boot-spl.sfp spl/u-boot-spl.pad \ spl/u-boot-spl.sfp spl/u-boot-spl.pad > $@ || \
u-boot.img > $@ || rm -f $@ spl/u-boot-spl.pad rm -f $@ spl/u-boot-spl.pad
u-boot-with-nand-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE u-boot-spl-padx4.sfp: spl/u-boot-spl.sfp FORCE
$(call if_changed,gensplpadx4)
quiet_cmd_socnandboot = SOCNANDBOOT $@
cmd_socnandboot = cat u-boot-spl-padx4.sfp u-boot.img > $@ || rm -f $@
u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE
$(call if_changed,socnandboot) $(call if_changed,socnandboot)
endif endif
@@ -1626,13 +1637,6 @@ u-boot-x86-reset16.bin: u-boot FORCE
endif # CONFIG_X86 endif # CONFIG_X86
ifneq ($(CONFIG_ARCH_SUNXI),)
ifeq ($(CONFIG_ARM64),y)
u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
$(call if_changed,cat)
endif
endif
OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI) OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI)
u-boot-app.efi: u-boot FORCE u-boot-app.efi: u-boot FORCE
$(call if_changed,zobjcopy) $(call if_changed,zobjcopy)
@@ -1866,6 +1870,7 @@ define filechk_timestamp.h
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_EPOCH %s'; \
else \ else \
return 42; \ return 42; \
fi; \ fi; \
@@ -1875,6 +1880,7 @@ define filechk_timestamp.h
LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \
fi) fi)
endef endef
@@ -2025,7 +2031,7 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
# Directories & files removed with 'make mrproper' # Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \ MRPROPER_DIRS += include/config include/generated spl tpl \
.tmp_objdiff .tmp_objdiff doc/output
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \ MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \ ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
drivers/video/fonts/*.S drivers/video/fonts/*.S

106
README
View File

@@ -51,31 +51,28 @@ In case you have questions about, problems with or contributions for
U-Boot, you should send a message to the U-Boot mailing list at U-Boot, you should send a message to the U-Boot mailing list at
<u-boot@lists.denx.de>. There is also an archive of previous traffic <u-boot@lists.denx.de>. There is also an archive of previous traffic
on the mailing list - please search the archive before asking FAQ's. on the mailing list - please search the archive before asking FAQ's.
Please see http://lists.denx.de/pipermail/u-boot and Please see https://lists.denx.de/pipermail/u-boot and
http://dir.gmane.org/gmane.comp.boot-loaders.u-boot https://marc.info/?l=u-boot
Where to get source code: Where to get source code:
========================= =========================
The U-Boot source code is maintained in the Git repository at The U-Boot source code is maintained in the Git repository at
git://www.denx.de/git/u-boot.git ; you can browse it online at https://gitlab.denx.de/u-boot/u-boot.git ; you can browse it online at
http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary https://gitlab.denx.de/u-boot/u-boot
The "snapshot" links on this page allow you to download tarballs of The "Tags" links on this page allow you to download tarballs of
any version you might be interested in. Official releases are also any version you might be interested in. Official releases are also
available for FTP download from the ftp://ftp.denx.de/pub/u-boot/ available from the DENX file server through HTTPS or FTP.
directory. https://ftp.denx.de/pub/u-boot/
ftp://ftp.denx.de/pub/u-boot/
Pre-built (and tested) images are available from
ftp://ftp.denx.de/pub/u-boot/images/
Where we come from: Where we come from:
=================== ===================
- start from 8xxrom sources - start from 8xxrom sources
- create PPCBoot project (http://sourceforge.net/projects/ppcboot) - create PPCBoot project (https://sourceforge.net/projects/ppcboot)
- clean up code - clean up code
- make it easier to add custom boards - make it easier to add custom boards
- make it possible to add other [PowerPC] CPUs - make it possible to add other [PowerPC] CPUs
@@ -84,10 +81,10 @@ Where we come from:
* S-Record download * S-Record download
* network boot * network boot
* ATA disk / SCSI ... boot * ATA disk / SCSI ... boot
- create ARMBoot project (http://sourceforge.net/projects/armboot) - create ARMBoot project (https://sourceforge.net/projects/armboot)
- add other CPU families (starting with ARM) - add other CPU families (starting with ARM)
- create U-Boot project (http://sourceforge.net/projects/u-boot) - create U-Boot project (https://sourceforge.net/projects/u-boot)
- current project page: see http://www.denx.de/wiki/U-Boot - current project page: see https://www.denx.de/wiki/U-Boot
Names and Spelling: Names and Spelling:
@@ -139,12 +136,12 @@ Directory Hierarchy:
/mips Files generic to MIPS architecture /mips Files generic to MIPS architecture
/nds32 Files generic to NDS32 architecture /nds32 Files generic to NDS32 architecture
/nios2 Files generic to Altera NIOS2 architecture /nios2 Files generic to Altera NIOS2 architecture
/openrisc Files generic to OpenRISC architecture
/powerpc Files generic to PowerPC architecture /powerpc Files generic to PowerPC architecture
/riscv Files generic to RISC-V architecture /riscv Files generic to RISC-V architecture
/sandbox Files generic to HW-independent "sandbox" /sandbox Files generic to HW-independent "sandbox"
/sh Files generic to SH architecture /sh Files generic to SH architecture
/x86 Files generic to x86 architecture /x86 Files generic to x86 architecture
/xtensa Files generic to Xtensa architecture
/api Machine/arch independent API for external apps /api Machine/arch independent API for external apps
/board Board dependent files /board Board dependent files
/cmd U-Boot commands functions /cmd U-Boot commands functions
@@ -154,6 +151,7 @@ Directory Hierarchy:
/doc Documentation (don't expect too much) /doc Documentation (don't expect too much)
/drivers Commonly used device drivers /drivers Commonly used device drivers
/dts Contains Makefile for building internal U-Boot fdt. /dts Contains Makefile for building internal U-Boot fdt.
/env Environment files
/examples Example code for standalone applications, etc. /examples Example code for standalone applications, etc.
/fs Filesystem code (cramfs, ext2, jffs2, etc.) /fs Filesystem code (cramfs, ext2, jffs2, etc.)
/include Header Files /include Header Files
@@ -212,7 +210,7 @@ board. This allows feature development which is not board- or architecture-
specific to be undertaken on a native platform. The sandbox is also used to specific to be undertaken on a native platform. The sandbox is also used to
run some of U-Boot's tests. run some of U-Boot's tests.
See doc/arch/index.rst for more details. See doc/arch/sandbox.rst for more details.
Board Initialisation Flow: Board Initialisation Flow:
@@ -266,7 +264,7 @@ board_init_f():
version as needed. version as needed.
- preloader_console_init() can be called here in extremis - preloader_console_init() can be called here in extremis
- should set up SDRAM, and anything needed to make the UART work - should set up SDRAM, and anything needed to make the UART work
- these is no need to clear BSS, it will be done by crt0.S - there is no need to clear BSS, it will be done by crt0.S
- for specific scenarios on certain architectures an early BSS *can* - for specific scenarios on certain architectures an early BSS *can*
be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing
of BSS prior to entering board_init_f()) but doing so is discouraged. of BSS prior to entering board_init_f()) but doing so is discouraged.
@@ -608,7 +606,7 @@ The following options need to be configured:
This setting is mandatory for all boards that have only one This setting is mandatory for all boards that have only one
machine type and must be used to specify the machine type machine type and must be used to specify the machine type
number as it appears in the ARM machine registry number as it appears in the ARM machine registry
(see http://www.arm.linux.org.uk/developer/machines/). (see https://www.arm.linux.org.uk/developer/machines/).
Only boards that have multiple machine types supported Only boards that have multiple machine types supported
in a single configuration file and the machine type is in a single configuration file and the machine type is
runtime discoverable, do not have to use this setting. runtime discoverable, do not have to use this setting.
@@ -620,7 +618,7 @@ The following options need to be configured:
serverip, gatewayip, hostname, othbootargs. serverip, gatewayip, hostname, othbootargs.
It loads the vxWorks image pointed bootfile. It loads the vxWorks image pointed bootfile.
Note: If a "bootargs" environment is defined, it will overwride Note: If a "bootargs" environment is defined, it will override
the defaults discussed just above. the defaults discussed just above.
- Cache Configuration: - Cache Configuration:
@@ -1250,60 +1248,6 @@ The following options need to be configured:
Enables an 'i2c edid' command which can read EDID Enables an 'i2c edid' command which can read EDID
information over I2C from an attached LCD display. information over I2C from an attached LCD display.
- Splash Screen Support: CONFIG_SPLASH_SCREEN
If this option is set, the environment is checked for
a variable "splashimage". If found, the usual display
of logo, copyright and system information on the LCD
is suppressed and the BMP image at the address
specified in "splashimage" is loaded instead. The
console is redirected to the "nulldev", too. This
allows for a "silent" boot where a splash screen is
loaded very quickly after power-on.
CONFIG_SPLASHIMAGE_GUARD
If this option is set, then U-Boot will prevent the environment
variable "splashimage" from being set to a problematic address
(see doc/README.displaying-bmps).
This option is useful for targets where, due to alignment
restrictions, an improperly aligned BMP image will cause a data
abort. If you think you will not have problems with unaligned
accesses (for example because your toolchain prevents them)
there is no need to set this option.
CONFIG_SPLASH_SCREEN_ALIGN
If this option is set the splash image can be freely positioned
on the screen. Environment variable "splashpos" specifies the
position as "x,y". If a positive number is given it is used as
number of pixel from left/top. If a negative number is given it
is used as number of pixel from right/bottom. You can also
specify 'm' for centering the image.
Example:
setenv splashpos m,m
=> image at center of screen
setenv splashpos 30,20
=> image at x = 30 and y = 20
setenv splashpos -10,m
=> vertically centered image
at x = dspWidth - bmpWidth - 9
- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
If this option is set, additionally to standard BMP
images, gzipped BMP images can be displayed via the
splashscreen support or the bmp command.
- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
If this option is set, 8-bit RLE compressed BMP images
can be displayed via the splashscreen support or the
bmp command.
- MII/PHY support: - MII/PHY support:
CONFIG_PHY_CLOCK_FREQ (ppc4xx) CONFIG_PHY_CLOCK_FREQ (ppc4xx)
@@ -3075,7 +3019,7 @@ Building U-Boot has been tested in several native build environments
and in many different cross environments. Of course we cannot support and in many different cross environments. Of course we cannot support
all possibly existing versions of cross development tools in all all possibly existing versions of cross development tools in all
(potentially obsolete) versions. In case of tool chain problems we (potentially obsolete) versions. In case of tool chain problems we
recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK) recommend to use the ELDK (see https://www.denx.de/wiki/DULG/ELDK)
which is extensively used to build and test U-Boot. which is extensively used to build and test U-Boot.
If you are not using a native environment, it is assumed that you If you are not using a native environment, it is assumed that you
@@ -3467,6 +3411,10 @@ List of environment variables (most likely not complete):
mempos - Index position of the last match found by the 'ms' command, mempos - Index position of the last match found by the 'ms' command,
in units of the size (.b, .w, .l) of the search in units of the size (.b, .w, .l) of the search
zbootbase - (x86 only) Base address of the bzImage 'setup' block
zbootaddr - (x86 only) Address of the loaded bzImage, typically
BZIMAGE_LOAD_ADDR which is 0x100000
The following image location variables contain the location of images The following image location variables contain the location of images
used in booting. The "Image" column gives the role of the image and is used in booting. The "Image" column gives the role of the image and is
@@ -4225,7 +4173,7 @@ consider minicom to be broken, and recommend not to use it. Under
Unix, I recommend to use C-Kermit for general purpose use (and Unix, I recommend to use C-Kermit for general purpose use (and
especially for kermit binary protocol download ("loadb" command), and especially for kermit binary protocol download ("loadb" command), and
use "cu" for S-Record download ("loads" command). See use "cu" for S-Record download ("loads" command). See
http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3. https://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
for help with kermit. for help with kermit.
@@ -4393,7 +4341,7 @@ On ARM, the following registers are used:
Note: on ARM, only R_ARM_RELATIVE relocations are supported. Note: on ARM, only R_ARM_RELATIVE relocations are supported.
On Nios II, the ABI is documented here: On Nios II, the ABI is documented here:
http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf https://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
==> U-Boot will use gp to hold a pointer to the global data ==> U-Boot will use gp to hold a pointer to the global data
@@ -4544,7 +4492,7 @@ int main(int argc, char *argv[])
while (learning) { while (learning) {
Read the README file in the top level directory; Read the README file in the top level directory;
Read http://www.denx.de/twiki/bin/view/DULG/Manual; Read https://www.denx.de/wiki/bin/view/DULG/Manual;
Read applicable doc/README.*; Read applicable doc/README.*;
Read the source, Luke; Read the source, Luke;
/* find . -name "*.[chS]" | xargs grep -i <keyword> */ /* find . -name "*.[chS]" | xargs grep -i <keyword> */
@@ -4625,7 +4573,7 @@ Since the number of patches for U-Boot is growing, we need to
establish some rules. Submissions which do not conform to these rules establish some rules. Submissions which do not conform to these rules
may be rejected, even when they contain important and valuable stuff. may be rejected, even when they contain important and valuable stuff.
Please see http://www.denx.de/wiki/U-Boot/Patches for details. Please see https://www.denx.de/wiki/U-Boot/Patches for details.
Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>; Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
see https://lists.denx.de/listinfo/u-boot see https://lists.denx.de/listinfo/u-boot

View File

@@ -57,7 +57,7 @@ static int API_getc(va_list ap)
if ((c = (int *)va_arg(ap, uintptr_t)) == NULL) if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL; return API_EINVAL;
*c = getc(); *c = getchar();
return 0; return 0;
} }

View File

@@ -24,8 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
int platform_sys_info(struct sys_info *si) int platform_sys_info(struct sys_info *si)
{ {
platform_set_mr(si, gd->bd->bi_memstart, platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
gd->bd->bi_memsize, MR_ATTR_DRAM);
return 1; return 1;
} }

View File

@@ -42,7 +42,7 @@ int platform_sys_info(struct sys_info *si)
si->bar = 0; si->bar = 0;
#endif #endif
platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM); platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM); platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);

View File

@@ -12,6 +12,7 @@ config ARC
bool "ARC architecture" bool "ARC architecture"
select ARC_TIMER select ARC_TIMER
select CLK select CLK
select DM
select HAVE_PRIVATE_LIBGCC select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL select SUPPORT_OF_CONTROL
select TIMER select TIMER

View File

@@ -12,17 +12,18 @@ config ARM64
if ARM64 if ARM64
config POSITION_INDEPENDENT config POSITION_INDEPENDENT
bool "Generate position-independent pre-relocation code" bool "Generate position-independent pre-relocation code"
select INIT_SP_RELATIVE
help help
U-Boot expects to be linked to a specific hard-coded address, and to U-Boot expects to be linked to a specific hard-coded address, and to
be loaded to and run from that address. This option lifts that be loaded to and run from that address. This option lifts that
restriction, thus allowing the code to be loaded to and executed restriction, thus allowing the code to be loaded to and executed from
from almost any address. This logic relies on the relocation almost any 4K aligned address. This logic relies on the relocation
information that is embedded in the binary to support U-Boot information that is embedded in the binary to support U-Boot
relocating itself to the top-of-RAM later during execution. relocating itself to the top-of-RAM later during execution.
config INIT_SP_RELATIVE config INIT_SP_RELATIVE
bool "Specify the early stack pointer relative to the .bss section" bool "Specify the early stack pointer relative to the .bss section"
default n if ARCH_QEMU
default y if POSITION_INDEPENDENT
help help
U-Boot typically uses a hard-coded value for the stack pointer U-Boot typically uses a hard-coded value for the stack pointer
before relocation. Enable this option to instead calculate the before relocation. Enable this option to instead calculate the
@@ -76,7 +77,7 @@ config GIC_V3_ITS
config STATIC_RELA config STATIC_RELA
bool bool
default y if ARM64 && !POSITION_INDEPENDENT default y if ARM64
config DMA_ADDR_T_64BIT config DMA_ADDR_T_64BIT
bool bool
@@ -767,8 +768,11 @@ config ARCH_IPQ40XX
select DM select DM
select DM_GPIO select DM_GPIO
select DM_SERIAL select DM_SERIAL
select DM_RESET
select MSM_SMEM
select PINCTRL select PINCTRL
select CLK select CLK
select SMEM
select OF_CONTROL select OF_CONTROL
imply CMD_DM imply CMD_DM
@@ -929,20 +933,20 @@ config ARCH_OWL
config ARCH_QEMU config ARCH_QEMU
bool "QEMU Virtual Platform" bool "QEMU Virtual Platform"
select ARCH_SUPPORT_TFABOOT
select DM select DM
select DM_SERIAL select DM_SERIAL
select OF_CONTROL select OF_CONTROL
select PL01X_SERIAL select PL01X_SERIAL
imply CMD_DM imply CMD_DM
imply DM_RNG
imply DM_RTC imply DM_RTC
imply RTC_PL031 imply RTC_PL031
config ARCH_RMOBILE config ARCH_RMOBILE
bool "Renesas ARM SoCs" bool "Renesas ARM SoCs"
select BOARD_EARLY_INIT_F if !RZA1
select DM select DM
select DM_SERIAL select DM_SERIAL
imply BOARD_EARLY_INIT_F
imply CMD_DM imply CMD_DM
imply FAT_WRITE imply FAT_WRITE
imply SYS_THUMB_BUILD imply SYS_THUMB_BUILD
@@ -991,7 +995,7 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
imply CMD_DM imply CMD_DM
imply CMD_MTDPARTS imply CMD_MTDPARTS
imply CRC32_VERIFY imply CRC32_VERIFY
@@ -1085,6 +1089,7 @@ config ARCH_VERSAL
select DM_SERIAL select DM_SERIAL
select OF_CONTROL select OF_CONTROL
imply BOARD_LATE_INIT imply BOARD_LATE_INIT
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
config ARCH_VF610 config ARCH_VF610
bool "Freescale Vybrid" bool "Freescale Vybrid"
@@ -1120,6 +1125,7 @@ config ARCH_ZYNQ
imply CMD_CLK imply CMD_CLK
imply CMD_DM imply CMD_DM
imply CMD_SPL imply CMD_SPL
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
imply FAT_WRITE imply FAT_WRITE
config ARCH_ZYNQMP_R5 config ARCH_ZYNQMP_R5
@@ -1150,7 +1156,8 @@ config ARCH_ZYNQMP
select OF_CONTROL select OF_CONTROL
select SPL_BOARD_INIT if SPL select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL select SPL_CLK if SPL
select SPL_DM_SPI if SPI select SPL_DM if SPL
select SPL_DM_SPI if SPI && SPL_DM
select SPL_DM_SPI_FLASH if SPL_DM_SPI select SPL_DM_SPI_FLASH if SPL_DM_SPI
select SPL_DM_MAILBOX if SPL select SPL_DM_MAILBOX if SPL
select SPL_FIRMWARE if SPL select SPL_FIRMWARE if SPL
@@ -1159,6 +1166,7 @@ config ARCH_ZYNQMP
select ZYNQMP_IPI select ZYNQMP_IPI
imply BOARD_LATE_INIT imply BOARD_LATE_INIT
imply CMD_DM imply CMD_DM
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
imply FAT_WRITE imply FAT_WRITE
imply MP imply MP
imply DM_USB_GADGET imply DM_USB_GADGET
@@ -1195,6 +1203,15 @@ config TARGET_VEXPRESS64_JUNO
select USB select USB
select DM_USB select DM_USB
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
select ARM64
select PL01X_SERIAL
select DM
select DM_SERIAL
select DM_MMC
select DM_GPIO
config TARGET_LS2080A_EMU config TARGET_LS2080A_EMU
bool "Support ls2080a_emu" bool "Support ls2080a_emu"
select ARCH_LS2080A select ARCH_LS2080A
@@ -1725,6 +1742,26 @@ config ARCH_ROCKCHIP
imply TPL_SYSRESET imply TPL_SYSRESET
imply USB_FUNCTION_FASTBOOT imply USB_FUNCTION_FASTBOOT
config ARCH_OCTEONTX
bool "Support OcteonTX SoCs"
select CLK
select DM
select ARM64
select OF_CONTROL
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
config ARCH_OCTEONTX2
bool "Support OcteonTX2 SoCs"
select CLK
select DM
select ARM64
select OF_CONTROL
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
config TARGET_THUNDERX_88XX config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx" bool "Support ThunderX 88xx"
select ARM64 select ARM64
@@ -1749,6 +1786,14 @@ config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform" bool "Support Cortina Presidio ASIC Platform"
select ARM64 select ARM64
config TARGET_XENGUEST_ARM64
bool "Xen guest ARM64"
select ARM64
select XEN
select OF_CONTROL
select LINUX_KERNEL_IMAGE_HEADER
select XEN_SERIAL
select SSCANF
endchoice endchoice
config ARCH_SUPPORT_TFABOOT config ARCH_SUPPORT_TFABOOT
@@ -1759,8 +1804,13 @@ config TFABOOT
depends on ARCH_SUPPORT_TFABOOT depends on ARCH_SUPPORT_TFABOOT
default n default n
help help
Enabling this will make a U-Boot binary that is capable of being Some platforms support the setup of secure registers (for instance
booted via TF-A (Trusted Firmware for Cortex-A). for CPU errata handling) or provide secure services like PSCI.
Those services could also be provided by other firmware parts
like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
does not need to (and cannot) execute this code.
Enabling this option will make a U-Boot binary that is relying
on other firmware layers to provide secure functionality.
config TI_SECURE_DEVICE config TI_SECURE_DEVICE
bool "HS Device Type Support" bool "HS Device Type Support"
@@ -1815,6 +1865,10 @@ source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-octeontx/Kconfig"
source "arch/arm/mach-octeontx2/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig" source "arch/arm/mach-imx/mx2/Kconfig"
@@ -1893,11 +1947,15 @@ source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-nexell/Kconfig" source "arch/arm/mach-nexell/Kconfig"
source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig" source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig" source "board/bosch/guardian/Kconfig"
source "board/CarMediaLab/flea3/Kconfig" source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig" source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig" source "board/Marvell/gplugd/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
source "board/armadeus/apf27/Kconfig" source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig" source "board/armltd/vexpress64/Kconfig"
@@ -1951,10 +2009,8 @@ source "board/tcl/sl50/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_pxa270/Kconfig"
source "board/variscite/dart_6ul/Kconfig" source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig" source "board/vscom/baltos/Kconfig"
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/phytium/durian/Kconfig" source "board/phytium/durian/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
source "arch/arm/Kconfig.debug" source "arch/arm/Kconfig.debug"

View File

@@ -80,6 +80,8 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += u8500 machine-$(CONFIG_ARCH_U8500) += u8500
machine-$(CONFIG_ARCH_OCTEONTX) += octeontx
machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSAL) += versal machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQ) += zynq

View File

@@ -40,3 +40,4 @@ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
obj-$(CONFIG_XEN) += xen/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* Copyright 2017-2019 NXP * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc. * Copyright 2014-2015 Freescale Semiconductor, Inc.
*/ */
@@ -1229,13 +1229,15 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(ulong addr) void __efi_runtime reset_cpu(ulong addr)
{ {
#ifdef CONFIG_ARCH_LX2160A
/* clear the RST_REQ_MSK and SW_RST_REQ */
out_le32(rstcr, 0x0);
/* initiate the sw reset request */
out_le32(rstcr, 0x1);
#else
u32 val; u32 val;
#ifdef CONFIG_ARCH_LX2160A
val = in_le32(rstcr);
val |= 0x01;
out_le32(rstcr, val);
#else
/* Raise RESET_REQ_B */ /* Raise RESET_REQ_B */
val = scfg_in32(rstcr); val = scfg_in32(rstcr);
val |= 0x02; val |= 0x02;

View File

@@ -36,6 +36,9 @@
#ifdef CONFIG_TFABOOT #ifdef CONFIG_TFABOOT
#include <env_internal.h> #include <env_internal.h>
#endif #endif
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS) #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#endif #endif
@@ -43,7 +46,22 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_GIC_V3_ITS #ifdef CONFIG_GIC_V3_ITS
int ls_gic_rd_tables_init(void *blob) int ls_gic_rd_tables_init(void *blob)
{ {
int ret; struct fdt_memory lpi_base;
fdt_addr_t addr;
fdt_size_t size;
int offset, ret;
offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000");
addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg",
0, &size, false);
lpi_base.start = addr;
lpi_base.end = addr + size - 1;
ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false);
if (ret) {
debug("%s: failed to add reserved memory\n", __func__);
return ret;
}
ret = gic_lpi_tables_init(); ret = gic_lpi_tables_init();
if (ret) if (ret)
@@ -897,6 +915,38 @@ __weak int fsl_board_late_init(void)
return 0; return 0;
} }
#define DWC3_GSBUSCFG0 0xc100
#define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16
#define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
<< DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
void enable_dwc3_snooping(void)
{
int ret;
u32 val;
struct udevice *bus;
struct uclass *uc;
fdt_addr_t dwc3_base;
ret = uclass_get(UCLASS_USB, &uc);
if (ret)
return;
uclass_foreach_dev(bus, uc) {
if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
dwc3_base = devfdt_get_addr(bus);
if (dwc3_base == FDT_ADDR_T_NONE) {
dev_err(bus, "dwc3 regs missing\n");
continue;
}
val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
writel(val, dwc3_base + DWC3_GSBUSCFG0);
}
}
}
int board_late_init(void) int board_late_init(void)
{ {
#ifdef CONFIG_CHAIN_OF_TRUST #ifdef CONFIG_CHAIN_OF_TRUST
@@ -934,6 +984,9 @@ int board_late_init(void)
fspi_ahb_init(); fspi_ahb_init();
#endif #endif
if (IS_ENABLED(CONFIG_DM))
enable_dwc3_snooping();
return fsl_board_late_init(); return fsl_board_late_init();
} }
#endif #endif

View File

@@ -59,6 +59,23 @@ reset:
save_boot_params_ret: save_boot_params_ret:
#if CONFIG_POSITION_INDEPENDENT #if CONFIG_POSITION_INDEPENDENT
/* Verify that we're 4K aligned. */
adr x0, _start
ands x0, x0, #0xfff
b.eq 1f
0:
/*
* FATAL, can't continue.
* U-Boot needs to be loaded at a 4K aligned address.
*
* We use ADRP and ADD to load some symbol addresses during startup.
* The ADD uses an absolute (non pc-relative) lo12 relocation
* thus requiring 4K alignment.
*/
wfi
b 0b
1:
/* /*
* Fix .rela.dyn relocations. This allows U-Boot to be loaded to and * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
* executed at a different address than it was linked at. * executed at a different address than it was linked at.
@@ -66,9 +83,12 @@ save_boot_params_ret:
pie_fixup: pie_fixup:
adr x0, _start /* x0 <- Runtime value of _start */ adr x0, _start /* x0 <- Runtime value of _start */
ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */ ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
sub x9, x0, x1 /* x9 <- Run-vs-link offset */ subs x9, x0, x1 /* x9 <- Run-vs-link offset */
adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */ beq pie_fixup_done
adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */ adrp x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
add x2, x2, #:lo12:__rel_dyn_start
adrp x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
add x3, x3, #:lo12:__rel_dyn_end
pie_fix_loop: pie_fix_loop:
ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */ ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */ ldr x4, [x2], #8 /* x4 <- addend */

View File

@@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) 2018 NXP
# (C) 2020 EPAM Systems Inc.
obj-y += lowlevel_init.o hypercall.o

View File

@@ -0,0 +1,79 @@
/* SPDX-License-Identifier: GPL-2.0
*
* hypercall.S
*
* Xen hypercall wrappers
*
* Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation; or, when distributed
* separately from the Linux kernel or incorporated into other
* software packages, subject to the following license:
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this source file (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify,
* merge, publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
/*
* The Xen hypercall calling convention is very similar to the procedure
* call standard for the ARM 64-bit architecture: the first parameter is
* passed in x0, the second in x1, the third in x2, the fourth in x3 and
* the fifth in x4.
*
* The hypercall number is passed in x16.
*
* The return value is in x0.
*
* The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
* hypercall tag.
*
* Parameter structs passed to hypercalls are laid out according to
* the ARM 64-bit EABI standard.
*/
#include <xen/interface/xen.h>
#define XEN_HYPERCALL_TAG 0xEA1
#define HYPERCALL_SIMPLE(hypercall) \
.globl HYPERVISOR_##hypercall; \
.align 4,0x90; \
HYPERVISOR_##hypercall: \
mov x16, #__HYPERVISOR_##hypercall; \
hvc XEN_HYPERCALL_TAG; \
ret; \
#define HYPERCALL0 HYPERCALL_SIMPLE
#define HYPERCALL1 HYPERCALL_SIMPLE
#define HYPERCALL2 HYPERCALL_SIMPLE
#define HYPERCALL3 HYPERCALL_SIMPLE
#define HYPERCALL4 HYPERCALL_SIMPLE
#define HYPERCALL5 HYPERCALL_SIMPLE
.text
HYPERCALL2(xen_version);
HYPERCALL3(console_io);
HYPERCALL3(grant_table_op);
HYPERCALL2(sched_op);
HYPERCALL2(event_channel_op);
HYPERCALL2(hvm_op);
HYPERCALL2(memory_op);

View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0+
*
* (C) 2017 NXP
* (C) 2020 EPAM Systems Inc.
*/
#include <config.h>
.align 8
.global rom_pointer
rom_pointer:
.space 32
/*
* Routine: save_boot_params (called after reset from start.S)
*/
.global save_boot_params
save_boot_params:
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
adr x1, rom_pointer
stp x0, x2, [x1], #16
stp x3, x4, [x1], #16
/* Returns */
b save_boot_params_ret
.global restore_boot_params
restore_boot_params:
adr x1, rom_pointer
ldp x0, x2, [x1], #16
ldp x3, x4, [x1], #16
ret

View File

@@ -202,6 +202,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
dtb-$(CONFIG_ARCH_MVEBU) += \ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \ armada-3720-db.dtb \
armada-3720-espressobin.dtb \ armada-3720-espressobin.dtb \
armada-3720-espressobin-emmc.dtb \
armada-3720-turris-mox.dtb \ armada-3720-turris-mox.dtb \
armada-3720-uDPU.dtb \ armada-3720-uDPU.dtb \
armada-375-db.dtb \ armada-375-db.dtb \
@@ -218,6 +219,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-8040-clearfog-gt-8k.dtb \ armada-8040-clearfog-gt-8k.dtb \
armada-8040-db.dtb \ armada-8040-db.dtb \
armada-8040-mcbin.dtb \ armada-8040-mcbin.dtb \
armada-8040-puzzle-m801.dtb \
armada-xp-crs305-1g-4s.dtb \ armada-xp-crs305-1g-4s.dtb \
armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs305-1g-4s-bit.dtb \
armada-xp-crs326-24g-2s.dtb \ armada-xp-crs326-24g-2s.dtb \
@@ -938,7 +940,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
@@ -955,11 +957,14 @@ dtb-$(CONFIG_STM32MP15x) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \ mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \
mt7622-bananapi-bpi-r64.dtb \
mt7623n-bananapi-bpi-r2.dtb \ mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \ mt7629-rfb.dtb \
mt8512-bm1-emmc.dtb \ mt8512-bm1-emmc.dtb \
@@ -978,6 +983,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb

View File

@@ -436,3 +436,53 @@
reg = <3>; reg = <3>;
}; };
}; };
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_default>;
sn65hvs882@1 {
compatible = "pisosr-gpio";
gpio-controller;
#gpio-cells = <2>;
load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
reg = <1>;
spi-max-frequency = <1000000>;
spi-cpol;
};
spi_nor: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64", "jedec,spi-nor";
spi-max-frequency = <80000000>;
m25p,fast-read;
reg = <0>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x80000>;
read-only;
};
partition@1 {
label = "u-boot";
reg = <0x80000 0x100000>;
read-only;
};
partition@2 {
label = "u-boot-env";
reg = <0x180000 0x20000>;
read-only;
};
partition@3 {
label = "misc";
reg = <0x1A0000 0x660000>;
};
};
};

View File

@@ -159,6 +159,6 @@
&pcie0 { &pcie0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>; pinctrl-0 = <&pcie_pins>;
reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };

View File

@@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
* Copyright (C) 2018 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
*
*/
/*
* Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
*/
/dts-v1/;
#include "armada-3720-espressobin.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
"marvell,armada3720", "marvell,armada3710";
};
/* U11 */
&sdhci1 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
mmccard: mmccard@0 {
compatible = "mmc-card";
reg = <0>;
};
};

View File

@@ -1,150 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* /*
* Device Tree file for Marvell Armada 3720 community board * Device Tree file for Globalscale Marvell ESPRESSOBin Board
* (ESPRESSOBin)
* Copyright (C) 2016 Marvell * Copyright (C) 2016 Marvell
* *
* Gregory CLEMENT <gregory.clement@free-electrons.com> * Romain Perier <romain.perier@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
* *
* This file is dual-licensed: you can use it either under the terms */
* of the GPL or the X11 license, at your option. Note that this dual /*
* licensing only applies to this file, and not this project as a * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/ */
/dts-v1/; /dts-v1/;
#include "armada-372x.dtsi" #include "armada-3720-espressobin.dtsi"
/ { / {
model = "Marvell Armada 3720 Community Board ESPRESSOBin"; model = "Globalscale Marvell ESPRESSOBin Board";
compatible = "marvell,armada-3720-espressobin", "marvell,armada3720", "marvell,armada3710"; compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
i2c0 = &i2c0;
spi0 = &spi0;
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
};
&comphy {
max-lanes = <3>;
phy0 {
phy-type = <PHY_TYPE_PEX0>;
phy-speed = <PHY_SPEED_2_5G>;
};
phy1 {
phy-type = <PHY_TYPE_USB3_HOST0>;
phy-speed = <PHY_SPEED_5G>;
};
phy2 {
phy-type = <PHY_TYPE_SATA0>;
phy-speed = <PHY_SPEED_5G>;
};
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii";
phy_addr = <0x1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
/* CON3 */
&sata {
status = "okay";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};
/* Exported on the micro USB connector CON32 through an FTDI */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/* CON29 */
&usb2 {
status = "okay";
};
/* CON31 */
&usb3 {
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
status = "okay";
}; };

View File

@@ -0,0 +1,167 @@
/*
* Device Tree file for Marvell Armada 3720 community board
* (ESPRESSOBin)
* Copyright (C) 2016 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-372x.dtsi"
/ {
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
i2c0 = &i2c0;
spi0 = &spi0;
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
vcc_sd_reg0: regulator@0 {
compatible = "regulator-gpio";
regulator-name = "vcc_sd0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-type = "voltage";
states = <1800000 0x1
3300000 0x0>;
gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
};
};
&comphy {
max-lanes = <3>;
phy0 {
phy-type = <PHY_TYPE_USB3_HOST0>;
phy-speed = <PHY_SPEED_5G>;
};
phy1 {
phy-type = <PHY_TYPE_PEX0>;
phy-speed = <PHY_SPEED_2_5G>;
};
phy2 {
phy-type = <PHY_TYPE_SATA0>;
phy-speed = <PHY_SPEED_5G>;
};
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii";
phy_addr = <0x1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
/* CON3 */
&sata {
status = "okay";
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
bus-width = <4>;
cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vcc_sd_reg0>;
status = "okay";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};
/* Exported on the micro USB connector CON32 through an FTDI */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/* CON29 */
&usb2 {
status = "okay";
};
/* CON31 */
&usb3 {
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
};

View File

@@ -100,6 +100,8 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>; pinctrl-0 = <&i2c1_pins>;
status = "okay"; status = "okay";
#address-cells = <1>;
#size-cells = <0>;
rtc@6f { rtc@6f {
compatible = "microchip,mcp7941x"; compatible = "microchip,mcp7941x";
@@ -170,6 +172,6 @@
&pcie0 { &pcie0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>; pinctrl-0 = <&pcie_pins>;
reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "disabled"; status = "disabled";
}; };

View File

@@ -72,6 +72,8 @@
pinctrl-0 = <&spi0_pins>; pinctrl-0 = <&spi0_pins>;
status = "okay"; status = "okay";
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
spi-flash@0 { spi-flash@0 {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;

View File

@@ -0,0 +1,389 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 Marvell International Ltd.
* Copyright (C) 2020 Sartura Ltd.
*/
#include "armada-8040.dtsi" /* include SoC device tree */
/ {
model = "iEi-Puzzle-M801";
compatible = "marvell,armada8040-puzzle-m801",
"marvell,armada8040";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &i2c0;
i2c1 = &cpm_i2c0;
i2c2 = &cpm_i2c1;
i2c3 = &i2c_switch;
spi0 = &spi0;
gpio0 = &ap_gpio0;
gpio1 = &cpm_gpio0;
gpio2 = &cpm_gpio1;
gpio3 = &sfpplus_gpio;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
simple-bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb3h0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&cpm_xhci_vbus_pins>;
regulator-name = "reg-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <500000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
};
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
rtc@32 {
compatible = "epson,rx8010";
reg = <0x32>;
};
};
&uart0 {
status = "okay";
};
&ap_pinctl {
/*
* MPP Bus:
* AP SPI0 [0-3]
* AP I2C [4-5]
* AP GPIO [6]
* AP UART 1 RX/TX [7-8]
* AP GPIO [9-10]
* AP GPIO [12]
* UART0 [11,19]
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 3 3 3 3 3 3 3 3 3 0
0 3 0 0 0 0 0 0 0 3 >;
};
&cpm_pinctl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
* [11] CLKOUT_MPP_11 (out)
* [23] LINK_RD_IN_CP2CP (in)
* [25] CLKOUT_MPP_25 (out)
* [29] AVS_FB_IN_CP2CP (in)
* [32,34] SMI
* [33] MSS power down
* [35-38] CP0 I2C1 and I2C0
* [39] MSS CKE Enable
* [40,41] CP0 UART1 TX/RX
* [42,43] XSMI (controls two 10G phys)
* [47] USB VBUS EN
* [48] FAN PWM
* [49] 10G port 1 interrupt
* [50] 10G port 0 interrupt
* [51] 2.5G SFP TX fault
* [52] PCIe reset out
* [53] 2.5G SFP mode
* [54] 2.5G SFP LOS
* [55] Micro SD card detect
* [56-61] Micro SD
* [62] CP1 SFI SFP FAULT
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0 7 0xa 7 2 2 2 2 0xa
7 7 8 8 0 0 0 0 0 0
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
};
cpm_pcie_reset_pins: cpm-pcie-reset-pins {
marvell,pins = < 52 >;
marvell,function = <0>;
};
};
&cpm_sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&cpm_sdhci_pins>;
bus-width= <4>;
status = "okay";
};
&cpm_pcie0 {
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_pcie_reset_pins>;
marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};
&cpm_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cpm_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
sfpplus_gpio: gpio@21 {
compatible = "nxp,pca9555";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
&cpm_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&cpm_i2c1_pins>;
status = "okay";
clock-frequency = <100000>;
i2c_switch: i2c-switch@70 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
};
};
&cpm_sata0 {
status = "okay";
};
&cpm_ethernet {
pinctrl-names = "default";
status = "okay";
};
&cpm_mdio {
status = "okay";
cpm_ge_phy0: ethernet-phy@1 {
reg = <0>;
};
cpm_ge_phy1: ethernet-phy@2 {
reg = <1>;
};
};
&cpm_eth0 {
status = "okay";
phy-mode = "sfi";
};
&cpm_eth1 {
status = "okay";
phy-mode = "sgmii";
phy = <&cpm_ge_phy0>;
};
&cpm_eth2 {
status = "okay";
phy-mode = "sgmii";
phy = <&cpm_ge_phy1>;
};
&cpm_comphy {
/*
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: SGMII2
* Lane 2: SATA0
* Lane 3: SGMII1
* Lane 4: SFI (10G)
* Lane 5: SATA1
*/
phy0 {
phy-type = <PHY_TYPE_PEX0>;
};
phy1 {
phy-type = <PHY_TYPE_SGMII2>;
phy-speed = <PHY_SPEED_1_25G>;
};
phy2 {
phy-type = <PHY_TYPE_SATA0>;
};
phy3 {
phy-type = <PHY_TYPE_SGMII1>;
phy-speed = <PHY_SPEED_1_25G>;
};
phy4 {
phy-type = <PHY_TYPE_SFI>;
};
phy5 {
phy-type = <PHY_TYPE_SATA1>;
};
};
&cps_mdio {
status = "okay";
cps_ge_phy0: ethernet-phy@3 {
reg = <1>;
};
cps_ge_phy1: ethernet-phy@4 {
reg = <0>;
};
};
&cps_pcie0 {
num-lanes = <2>;
pinctrl-names = "default";
status = "okay";
};
&cps_usb3_0 {
vbus-supply = <&reg_usb3h0_vbus>;
status = "okay";
};
&cps_utmi0 {
status = "okay";
};
&cps_ethernet {
status = "okay";
};
&cps_eth0 {
status = "okay";
phy-mode = "sfi";
};
&cps_eth1 {
status = "okay";
phy = <&cps_ge_phy0>;
phy-mode = "sgmii";
};
&cps_eth2 {
status = "okay";
phy = <&cps_ge_phy1>;
phy-mode = "sgmii";
};
&cps_pinctl {
/*
* MPP Bus:
* [0-5] TDM
* [6,7] CP1_UART 0
* [8] CP1 10G SFP LOS
* [9] CP1 10G PHY RESET
* [10] CP1 10G SFP TX Disable
* [11] CP1 10G SFP Mode
* [12] SPI1 CS1n
* [13] SPI1 MISO (TDM and SPI ROM shared)
* [14] SPI1 CS0n
* [15] SPI1 MOSI (TDM and SPI ROM shared)
* [16] SPI1 CLK (TDM and SPI ROM shared)
* [24] CP1 2.5G SFP TX Disable
* [26] CP0 10G SFP TX Fault
* [27] CP0 10G SFP Mode
* [28] CP0 10G SFP LOS
* [29] CP0 10G SFP TX Disable
* [30] USB Over current indication
* [31] 10G Port 0 phy reset
* [32-62] = 0xff: Keep default CP1_shared_pins:
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0
0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0
0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff>;
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@u-boot {
reg = <0x00000000 0x001f0000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x001f0000 0x00010000>;
label = "u-boot-env";
};
partition@ubi1 {
reg = <0x00200000 0x03f00000>;
label = "ubi1";
};
partition@ubi2 {
reg = <0x04100000 0x03f00000>;
label = "ubi2";
};
};
};
};
&cps_comphy {
/*
* CP1 Serdes Configuration:
* Lane 0: PCIe0 (x2)
* Lane 1: PCIe0 (x2)
* Lane 2: USB HOST 0
* Lane 3: SGMII1
* Lane 4: SFI (10G)
* Lane 5: SGMII2
*/
phy0 {
phy-type = <PHY_TYPE_PEX0>;
};
phy1 {
phy-type = <PHY_TYPE_PEX0>;
};
phy2 {
phy-type = <PHY_TYPE_USB3_HOST0>;
};
phy3 {
phy-type = <PHY_TYPE_SGMII1>;
phy-speed = <PHY_SPEED_1_25G>;
};
phy4 {
phy-type = <PHY_TYPE_SFI>;
};
phy5 {
phy-type = <PHY_TYPE_SGMII2>;
phy-speed = <PHY_SPEED_1_25G>;
};
};

View File

@@ -177,6 +177,9 @@
}; };
mdio { mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
}; };

View File

@@ -107,6 +107,8 @@
}; };
mdio { mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
}; };

View File

@@ -1,4 +1,5 @@
#include <dt-bindings/clock/ast2500-scu.h> // SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/reset/ast2500-reset.h> #include <dt-bindings/reset/ast2500-reset.h>
#include "ast2500.dtsi" #include "ast2500.dtsi"
@@ -15,7 +16,6 @@
rst: reset-controller { rst: reset-controller {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-reset"; compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
@@ -25,8 +25,8 @@
reg = <0x1e6e0000 0x174 reg = <0x1e6e0000 0x174
0x1e6e0200 0x1d4 >; 0x1e6e0200 0x1d4 >;
#reset-cells = <1>; #reset-cells = <1>;
clocks = <&scu PLL_MPLL>; clocks = <&scu ASPEED_CLK_MPLL>;
resets = <&rst AST_RESET_SDRAM>; resets = <&rst ASPEED_RESET_SDRAM>;
}; };
ahb { ahb {
@@ -39,16 +39,16 @@
compatible = "aspeed,ast2500-sdhci"; compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>; reg = <0x1e740100>;
#reset-cells = <1>; #reset-cells = <1>;
clocks = <&scu BCLK_SDCLK>; clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst AST_RESET_SDIO>; resets = <&rst ASPEED_RESET_SDIO>;
}; };
sdhci1: sdhci@1e740200 { sdhci1: sdhci@1e740200 {
compatible = "aspeed,ast2500-sdhci"; compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>; reg = <0x1e740200>;
#reset-cells = <1>; #reset-cells = <1>;
clocks = <&scu BCLK_SDCLK>; clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst AST_RESET_SDIO>; resets = <&rst ASPEED_RESET_SDIO>;
}; };
}; };
@@ -56,23 +56,23 @@
}; };
&uart1 { &uart1 {
clocks = <&scu PCLK_UART1>; clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
}; };
&uart2 { &uart2 {
clocks = <&scu PCLK_UART2>; clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
}; };
&uart3 { &uart3 {
clocks = <&scu PCLK_UART3>; clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
}; };
&uart4 { &uart4 {
clocks = <&scu PCLK_UART4>; clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
}; };
&uart5 { &uart5 {
clocks = <&scu PCLK_UART5>; clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
}; };
&timer { &timer {
@@ -80,9 +80,9 @@
}; };
&mac0 { &mac0 {
clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
}; };
&mac1 { &mac1 {
clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
}; };

View File

@@ -51,7 +51,7 @@
/* microSD card slot */ /* microSD card slot */
&sdhci1 { &sdhci1 {
status = "okay"; status = "okay";
xlnx,mio_bank = <1>; xlnx,mio-bank = <1>;
clock-frequency = <199998000>; clock-frequency = <199998000>;
max-frequency = <50000000>; max-frequency = <50000000>;
no-1-8-v; no-1-8-v;

View File

@@ -51,6 +51,6 @@
/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */ /* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
&sdhci0 { &sdhci0 {
status = "okay"; status = "okay";
xlnx,mio_bank = <0>; xlnx,mio-bank = <0>;
clock-frequency = <199998000>; clock-frequency = <199998000>;
}; };

View File

@@ -12,8 +12,8 @@
#include "fsl-imx8qm-apalis-u-boot.dtsi" #include "fsl-imx8qm-apalis-u-boot.dtsi"
/ { / {
model = "Toradex Apalis iMX8QM"; model = "Toradex Apalis iMX8";
compatible = "toradex,apalis-imx8qm", "fsl,imx8qm"; compatible = "toradex,apalis-imx8", "fsl,imx8qm";
chosen { chosen {
bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200"; bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
@@ -38,7 +38,7 @@
<&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
<&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>; <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>;
apalis-imx8qm { apalis-imx8 {
pinctrl_gpio12: gpio12grp { pinctrl_gpio12: gpio12grp {
fsl,pins = < fsl,pins = <
/* Apalis GPIO1 */ /* Apalis GPIO1 */

View File

@@ -9,8 +9,8 @@
#include "fsl-imx8qxp-colibri-u-boot.dtsi" #include "fsl-imx8qxp-colibri-u-boot.dtsi"
/ { / {
model = "Toradex Colibri iMX8QXP"; model = "Toradex Colibri iMX8X";
compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp"; compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
chosen { chosen {
bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200"; bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
@@ -32,7 +32,7 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>; pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
colibri-imx8qxp { colibri-imx8x {
pinctrl_lpuart0: lpuart0grp { pinctrl_lpuart0: lpuart0grp {
fsl,pins = < fsl,pins = <
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020

View File

@@ -44,6 +44,12 @@
IRQ_TYPE_LEVEL_LOW)>; IRQ_TYPE_LEVEL_LOW)>;
}; };
gic_lpi_base: syscon@0x80000000 {
compatible = "gic-lpi-base";
reg = <0x0 0x80000000 0x0 0x100000>;
max-gic-redistributors = <2>;
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |

View File

@@ -26,6 +26,12 @@
interrupts = <1 9 0x4>; interrupts = <1 9 0x4>;
}; };
gic_lpi_base: syscon@0x80000000 {
compatible = "gic-lpi-base";
reg = <0x0 0x80000000 0x0 0x100000>;
max-gic-redistributors = <8>;
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */

View File

@@ -26,6 +26,12 @@
interrupts = <1 9 0x4>; interrupts = <1 9 0x4>;
}; };
gic_lpi_base: syscon@0x80000000 {
compatible = "gic-lpi-base";
reg = <0x0 0x80000000 0x0 0x100000>;
max-gic-redistributors = <8>;
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */

View File

@@ -80,6 +80,8 @@
&esdhc1 { &esdhc1 {
status = "okay"; status = "okay";
mmc-hs200-1_8v; mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
}; };
&fspi { &fspi {

View File

@@ -43,6 +43,12 @@
interrupts = <1 9 0x4>; interrupts = <1 9 0x4>;
}; };
gic_lpi_base: syscon@0x80000000 {
compatible = "gic-lpi-base";
reg = <0x0 0x80000000 0x0 0x200000>;
max-gic-redistributors = <16>;
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
@@ -193,6 +199,28 @@
num-cs = <6>; num-cs = <6>;
}; };
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 4>;
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 4>;
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 { gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio"; compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>; reg = <0x0 0x2320000 0x0 0x10000>;
@@ -204,6 +232,17 @@
#interrupt-cells = <2>; #interrupt-cells = <2>;
}; };
gpio3: gpio@2330000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 4>;
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
watchdog@23a0000 { watchdog@23a0000 {
compatible = "arm,sbsa-gwdt"; compatible = "arm,sbsa-gwdt";
reg = <0x0 0x23a0000 0 0x1000>, reg = <0x0 0x23a0000 0 0x1000>,
@@ -297,7 +336,8 @@
#size-cells = <2>; #size-cells = <2>;
device_type = "pci"; device_type = "pci";
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
pcie@3500000 { pcie@3500000 {
@@ -312,7 +352,8 @@
device_type = "pci"; device_type = "pci";
num-lanes = <2>; num-lanes = <2>;
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
pcie@3600000 { pcie@3600000 {
@@ -326,7 +367,8 @@
#size-cells = <2>; #size-cells = <2>;
device_type = "pci"; device_type = "pci";
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
pcie@3700000 { pcie@3700000 {
@@ -340,7 +382,8 @@
#size-cells = <2>; #size-cells = <2>;
device_type = "pci"; device_type = "pci";
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
pcie@3800000 { pcie@3800000 {
@@ -354,7 +397,8 @@
#size-cells = <2>; #size-cells = <2>;
device_type = "pci"; device_type = "pci";
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
pcie@3900000 { pcie@3900000 {
@@ -368,7 +412,8 @@
#size-cells = <2>; #size-cells = <2>;
device_type = "pci"; device_type = "pci";
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
}; };
fsl_mc: fsl-mc@80c000000 { fsl_mc: fsl-mc@80c000000 {

View File

@@ -24,15 +24,15 @@
&eeprom { &eeprom {
partitions { partitions {
compatible = "fixed-partitions"; compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
vpd { vpd@0 {
offset = <0>; reg = <0 1022>;
size = <1022>;
}; };
bootcount: bootcount { bootcount: bootcount@1022 {
offset = <1022>; reg = <1022 2>;
size = <2>;
}; };
}; };
}; };

View File

@@ -23,15 +23,15 @@
&eeprom { &eeprom {
partitions { partitions {
compatible = "fixed-partitions"; compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
vpd { vpd@0 {
offset = <0>; reg = <0 1022>;
size = <1022>;
}; };
bootcount: bootcount { bootcount: bootcount {
offset = <1022>; reg = <1022 2>;
size = <2>;
}; };
}; };
}; };

View File

@@ -135,7 +135,7 @@
<0x0 0x2a500000 0x0 0x40000>; <0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>; ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,dma-ring-reset-quirk; ti,dma-ring-reset-quirk;
ti,sci = <&dmsc>; ti,sci = <&dmsc>;
ti,sci-dev-id = <195>; ti,sci-dev-id = <195>;
@@ -153,11 +153,11 @@
ti,sci-dev-id = <194>; ti,sci-dev-id = <194>;
ti,ringacc = <&mcu_ringacc>; ti,ringacc = <&mcu_ringacc>;
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
<0x2>; /* TX_CHAN */ <0xd>; /* TX_CHAN */
ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */ ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
<0x4>; /* RX_CHAN */ <0xa>; /* RX_CHAN */
ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */ ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
}; };
}; };
@@ -230,4 +230,13 @@
}; };
}; };
}; };
mcu_rti1: rti@40610000 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x40610000 0x0 0x100>;
clocks = <&k3_clks 135 0>;
power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
assigned-clocks = <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 135 4>;
};
}; };

View File

@@ -62,7 +62,7 @@
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
}; };
cbass_main: interconnect@100000 { cbass_main: bus@100000 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
@@ -87,7 +87,7 @@
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
cbass_mcu: interconnect@28380000 { cbass_mcu: bus@28380000 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
@@ -104,7 +104,7 @@
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
cbass_wakeup: interconnect@42040000 { cbass_wakeup: bus@42040000 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

View File

@@ -139,6 +139,12 @@
u-boot,dm-spl; u-boot,dm-spl;
}; };
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
u-boot,dm-spl;
};
}; };
&main_pmx1 { &main_pmx1 {
@@ -250,3 +256,24 @@
&chipid { &chipid {
u-boot,dm-spl; u-boot,dm-spl;
}; };
&dwc3_0 {
status = "okay";
u-boot,dm-spl;
};
&usb0_phy {
status = "okay";
u-boot,dm-spl;
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "peripheral";
u-boot,dm-spl;
};
&scm_conf {
u-boot,dm-spl;
};

View File

@@ -278,3 +278,38 @@
#size-cells = <1>; #size-cells = <1>;
}; };
}; };
&main_pmx0 {
u-boot,dm-spl;
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
u-boot,dm-spl;
};
};
&dwc3_0 {
status = "okay";
u-boot,dm-spl;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&usb0_phy {
status = "okay";
u-boot,dm-spl;
/delete-property/ clocks;
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "peripheral";
u-boot,dm-spl;
};
&scm_conf {
u-boot,dm-spl;
};

View File

@@ -0,0 +1,161 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
aliases {
ethernet0 = &cpsw_port1;
};
};
&chipid {
u-boot,dm-spl;
};
&cbass_main {
u-boot,dm-spl;
};
&main_navss {
u-boot,dm-spl;
};
&cbass_mcu_wakeup {
u-boot,dm-spl;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
u-boot,dm-spl;
};
};
&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
u-boot,dm-spl;
};
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&wkup_pmx0 {
u-boot,dm-spl;
};
&main_pmx0 {
u-boot,dm-spl;
};
&main_uart0 {
u-boot,dm-spl;
};
&mcu_uart0 {
u-boot,dm-spl;
};
&main_sdhci0 {
u-boot,dm-spl;
};
&main_sdhci1 {
u-boot,dm-spl;
};
&wkup_i2c0_pins_default {
u-boot,dm-spl;
};
&wkup_i2c0 {
u-boot,dm-spl;
};
&main_i2c0 {
u-boot,dm-spl;
};
&main_i2c0_pins_default {
u-boot,dm-spl;
};
&exp2 {
u-boot,dm-spl;
};
&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x8>;
reg-names = "cpsw_nuss", "mac_efuse";
cpsw-phy-sel@40f04040 {
compatible = "ti,am654-cpsw-phy-sel";
reg= <0x0 0x40f04040 0x0 0x4>;
reg-names = "gmii-sel";
};
};
&main_usbss0_pins_default {
u-boot,dm-spl;
};
&usbss0 {
u-boot,dm-spl;
ti,usb2-only;
};
&usb0 {
dr_mode = "peripheral";
u-boot,dm-spl;
};
&wkup_gpio_pins_default {
u-boot,dm-spl;
};
&wkup_gpio0 {
u-boot,dm-spl;
};
&mcu_fss0_hpb0_pins_default {
u-boot,dm-spl;
};
&fss {
u-boot,dm-spl;
};
&hbmc {
u-boot,dm-spl;
flash@0,0 {
u-boot,dm-spl;
};
};
&hbmc_mux {
u-boot,dm-spl;
};

View File

@@ -0,0 +1,202 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-j7200-som-p0.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
aliases {
remoteproc0 = &mcu_r5fss0_core0;
remoteproc1 = &mcu_r5fss0_core1;
remoteproc2 = &main_r5fss0_core0;
remoteproc3 = &main_r5fss0_core1;
};
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
};
wkup_gpio_pins_default: wkup-gpio-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
>;
};
mcu_cpsw_pins_default: mcu_cpsw_pins_default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
mcu_mdio_pins_default: mcu_mdio1_pins_default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
>;
};
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
};
};
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "disabled";
};
&main_uart0 {
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&main_uart2 {
/* MAIN UART 2 is used by R5F firmware */
status = "disabled";
};
&main_uart3 {
/* UART not brought out */
status = "disabled";
};
&main_uart4 {
/* UART not brought out */
status = "disabled";
};
&main_uart5 {
/* UART not brought out */
status = "disabled";
};
&main_uart6 {
/* UART not brought out */
status = "disabled";
};
&main_uart7 {
/* UART not brought out */
status = "disabled";
};
&main_uart8 {
/* UART not brought out */
status = "disabled";
};
&main_uart9 {
/* UART not brought out */
status = "disabled";
};
&wkup_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_sdhci0 {
/* eMMC */
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_sdhci1 {
/* SD card */
ti,driver-strength-ohm = <50>;
disable-wp;
no-1-8-v;
sdhci-caps-mask = <0x8000000F 0x0>;
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
exp1: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
exp2: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
};
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
};
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};
&davinci_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
};

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,383 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J7200 SoC Family Main Domain peripherals
*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x0 0x70000000 0x0 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x70000000 0x100000>;
atf-sram@0 {
reg = <0x0 0x20000>;
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01900000 0x00 0x100000>; /* GICR */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
main_navss: navss@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
secure_proxy_main: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x32c00000 0x00 0x100000>,
<0x00 0x32400000 0x00 0x100000>,
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
};
main_pmx0: pinmux@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x0 0x11c000 0x0 0x2b4>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 2>;
clock-names = "fclk";
};
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 2>;
clock-names = "fclk";
};
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 2>;
clock-names = "fclk";
};
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 2>;
clock-names = "fclk";
};
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 2>;
clock-names = "fclk";
};
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 2>;
clock-names = "fclk";
};
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 2>;
clock-names = "fclk";
};
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 2>;
clock-names = "fclk";
};
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 2>;
clock-names = "fclk";
};
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 2>;
clock-names = "fclk";
};
main_sdhci0: sdhci@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x8>;
ti,otap-del-sel-hs400 = <0x0>;
ti,strobe-sel = <0x77>;
ti,trm-icp = <0x8>;
bus-width = <8>;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
dma-coherent;
};
main_sdhci1: sdhci@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
dma-coherent;
};
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x2000000 0x0 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 187 1>;
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x2010000 0x0 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 188 1>;
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@2020000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x2020000 0x0 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 189 1>;
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@2030000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x2030000 0x0 0x100>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 190 1>;
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c4: i2c@2040000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x2040000 0x0 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 191 1>;
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c5: i2c@2050000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x2050000 0x0 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 192 1>;
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c6: i2c@2060000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x2060000 0x0 0x100>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 193 1>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
};
usbss0: cdns_usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
dma-coherent;
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
clock-names = "usb2_refclk", "lpm_clk";
assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb0: usb@6000000 {
compatible = "cdns,usb3";
reg = <0x00 0x6000000 0x00 0x10000>,
<0x00 0x6010000 0x00 0x10000>,
<0x00 0x6020000 0x00 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
interrupt-names = "host",
"peripheral",
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j7200-r5fss";
lockstep-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@5c00000 {
compatible = "ti,j7200-r5f";
reg = <0x5c00000 0x00010000>,
<0x5c10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <245>;
ti,sci-proc-ids = <0x06 0xFF>;
resets = <&k3_reset 245 1>;
firmware-name = "j7200-main-r5f0_0-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
main_r5fss0_core1: r5f@5d00000 {
compatible = "ti,j7200-r5f";
reg = <0x5d00000 0x00008000>,
<0x5d10000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <246>;
ti,sci-proc-ids = <0x07 0xFF>;
resets = <&k3_reset 246 1>;
firmware-name = "j7200-main-r5f0_1-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
};
};

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@@ -0,0 +1,312 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
dmsc: dmsc@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x0 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clocks {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
chipid: chipid@43000014 {
compatible = "ti,am654-chipid";
reg = <0x0 0x43000014 0x0 0x4>;
};
wkup_pmx0: pinmux@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
ranges = <0x0 0x00 0x41c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 2>;
clock-names = "fclk";
};
wkup_i2c0: i2c@42120000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x42120000 0x0 0x100>;
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 197 1>;
power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
};
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 2>;
clock-names = "fclk";
};
fss: system-controller@47000000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x47000000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
hbmc_mux: hbmc-mux {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4 0x2>; /* HBMC select */
};
hbmc: hyperbus@47034000 {
compatible = "ti,am654-hbmc";
reg = <0x0 0x47034000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
clocks = <&k3_clks 102 5>;
assigned-clocks = <&k3_clks 102 5>;
assigned-clock-rates = <333333333>;
};
};
mcu_i2c0: i2c@40b00000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x40b00000 0x0 0x100>;
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 194 1>;
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
};
mcu_i2c1: i2c@40b10000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x0 0x40b10000 0x0 0x100>;
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 195 1>;
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
};
cbass_mcu_navss: mcu-navss {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <232>;
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
};
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
#dma-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <236>;
ti,ringacc = <&mcu_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>; /* TX_HCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
};
wkup_gpio0: gpio@42110000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x0 0x42110000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
ti,ngpio = <84>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
};
mcu_conf: scm_conf@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x40f00000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-cpsw-phy-sel";
reg = <0x4040 0x4>;
reg-names = "gmii-sel";
#phy-cells = <1>;
};
};
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x46000000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges;
dma-coherent;
clocks = <&k3_clks 18 21>;
clock-names = "fck";
power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
dmas = <&mcu_udmap 0xf000>,
<&mcu_udmap 0xf001>,
<&mcu_udmap 0xf002>,
<&mcu_udmap 0xf003>,
<&mcu_udmap 0xf004>,
<&mcu_udmap 0xf005>,
<&mcu_udmap 0xf006>,
<&mcu_udmap 0xf007>,
<&mcu_udmap 0x7000>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
ti,label = "port1";
ti,syscon-efuse = <&mcu_conf 0x200>;
phys = <&phy_gmii_sel 1>;
};
};
davinci_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x0 0xf00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 18 21>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts {
clocks = <&k3_clks 18 2>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j7200-r5fss";
lockstep-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,j7200-r5f";
reg = <0x41000000 0x00010000>,
<0x41010000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <250>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 250 1>;
firmware-name = "j7200-mcu-r5f0_0-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,j7200-r5f";
reg = <0x41400000 0x00008000>,
<0x41410000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <251>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 251 1>;
firmware-name = "j7200-mcu-r5f0_1-fw";
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
};
};

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@@ -0,0 +1,263 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j7200-som-p0.dtsi"
#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
#include "k3-j721e-ddr.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
chosen {
stdout-path = &main_uart0;
tick-timer = &timer1;
firmware-loader = &fs_loader0;
};
fs_loader0: fs_loader@0 {
u-boot,dm-pre-reloc;
compatible = "u-boot,fs-loader";
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
u-boot,dm-spl;
};
clk_200mhz: dummy_clock_200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
u-boot,dm-spl;
};
clk_19_2mhz: dummy_clock_19_2mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
u-boot,dm-spl;
};
};
&memorycontroller {
power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
<&k3_pds 90 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
};
&cbass_mcu_wakeup {
mcu_secproxy: secproxy@2a380000 {
u-boot,dm-spl;
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>,
<0x0 0x2a480000 0x0 0x80000>;
reg-names = "rt", "scfg", "target_data";
#mbox-cells = <1>;
};
sysctrler: sysctrler {
u-boot,dm-spl;
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
};
};
&dmsc {
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
&wkup_pmx0 {
u-boot,dm-spl;
wkup_uart0_pins_default: wkup_uart0_pins_default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
>;
};
mcu_uart0_pins_default: mcu_uart0_pins_default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */
J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */
J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
};
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
wkup_gpio_pins_default: wkup-gpio-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
>;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_uart0_pins_default: main_uart0_pins_default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
>;
};
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
};
};
&wkup_uart0 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
};
&mcu_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
status = "okay";
clock-frequency = <96000000>;
};
&main_uart0 {
status = "okay";
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};
&main_sdhci0 {
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
ti,driver-strength-ohm = <50>;
non-removable;
bus-width = <8>;
};
&main_sdhci1 {
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
ti,driver-strength-ohm = <50>;
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
exp1: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
exp2: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
};
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
};
&hbmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
<0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x0 0x0 0x4000000>;
};
};
#include "k3-j7200-common-proc-board-u-boot.dtsi"

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@@ -0,0 +1,62 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j7200.dtsi"
/ {
memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
alignment = <0x1000>;
no-map;
};
};
};
&wkup_pmx0 {
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
};
&hbmc {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
<0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x0 0x0 0x4000000>;
};
};

177
arch/arm/dts/k3-j7200.dtsi Normal file
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@@ -0,0 +1,177 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J7200 SoC Family
*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 J7200 SoC";
compatible = "ti,j7200";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
serial5 = &main_uart3;
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
serial9 = &main_uart7;
serial10 = &main_uart8;
serial11 = &main_uart9;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &mcu_i2c1;
i2c3 = &main_i2c0;
i2c4 = &main_i2c1;
i2c5 = &main_i2c2;
i2c6 = &main_i2c3;
i2c7 = &main_i2c4;
i2c8 = &main_i2c5;
i2c9 = &main_i2c6;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a72";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a72";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <2048>;
next-level-cache = <&msmc_l3>;
};
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a72_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@100000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT */
/* MCUSS_WKUP Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>; /* FSS OSPI0 data region 3 */
};
};
};
/* Now include the peripherals for each bus segments */
#include "k3-j7200-main.dtsi"
#include "k3-j7200-mcu-wakeup.dtsi"

View File

@@ -302,7 +302,7 @@
main_r5fss1: r5fss@5e00000 { main_r5fss1: r5fss@5e00000 {
compatible = "ti,j721e-r5fss"; compatible = "ti,j721e-r5fss";
lockstep-mode = <1>; lockstep-mode = <0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x5e00000 0x00 0x5e00000 0x20000>, ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
@@ -543,4 +543,22 @@
clocks = <&k3_clks 193 0>; clocks = <&k3_clks 193 0>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
}; };
watchdog0: watchdog@2200000 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x2200000 0x0 0x100>;
clocks = <&k3_clks 252 1>;
power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 252 1>;
assigned-clock-parents = <&k3_clks 252 5>;
};
watchdog1: watchdog@2210000 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x2210000 0x0 0x100>;
clocks = <&k3_clks 253 1>;
power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 253 1>;
assigned-clock-parents = <&k3_clks 253 5>;
};
}; };

View File

@@ -131,7 +131,7 @@
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
}; };
cbass_main: interconnect@100000 { cbass_main: bus@100000 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
@@ -164,7 +164,7 @@
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: interconnect@28380000 { cbass_mcu_wakeup: bus@28380000 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;

View File

@@ -3,6 +3,8 @@
* Copyright (c) 2017 Amlogic, Inc. All rights reserved. * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/ */
#include "meson-axg-u-boot.dtsi"
/* wifi module */ /* wifi module */
&sd_emmc_b { &sd_emmc_b {
status = "disabled"; status = "disabled";
@@ -12,3 +14,13 @@
&sd_emmc_c { &sd_emmc_c {
status = "okay"; status = "okay";
}; };
&usb {
status = "okay";
dr_mode = "otg";
vbus-supply = <&usb_pwr>;
};
&usb2_phy1 {
phy-supply = <&vcc_5v>;
};

View File

@@ -0,0 +1,62 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
/ {
soc {
usb: usb@ffe09080 {
compatible = "amlogic,meson-gxl-usb-ctrl";
reg = <0x0 0xffe09080 0x0 0x20>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "usb_ctrl", "ddr";
resets = <&reset RESET_USB_OTG>;
dr_mode = "otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy1";
dwc2: usb@ff400000 {
compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
reg = <0x0 0xff400000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1>;
clock-names = "otg";
phys = <&usb2_phy1>;
dr_mode = "peripheral";
g-rx-fifo-size = <192>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <128 128 16 16 16>;
};
dwc3: usb@ff500000 {
compatible = "snps,dwc3";
reg = <0x0 0xff500000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
};
};
};
};
&apb {
usb2_phy1: phy@9020 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x9020 0x0 0x20>;
clocks = <&clkc CLKID_USB>;
clock-names = "phy";
resets = <&reset RESET_USB_OTG>;
reset-names = "phy";
status = "okay";
};
};

View File

@@ -1735,18 +1735,18 @@
}; };
sram: sram@fffc0000 { sram: sram@fffc0000 {
compatible = "amlogic,meson-axg-sram", "mmio-sram"; compatible = "mmio-sram";
reg = <0x0 0xfffc0000 0x0 0x20000>; reg = <0x0 0xfffc0000 0x0 0x20000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0x0 0xfffc0000 0x20000>; ranges = <0 0x0 0xfffc0000 0x20000>;
cpu_scp_lpri: scp-shmem@13000 { cpu_scp_lpri: scp-sram@13000 {
compatible = "amlogic,meson-axg-scp-shmem"; compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13000 0x400>; reg = <0x13000 0x400>;
}; };
cpu_scp_hpri: scp-shmem@13400 { cpu_scp_hpri: scp-sram@13400 {
compatible = "amlogic,meson-axg-scp-shmem"; compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13400 0x400>; reg = <0x13400 0x400>;
}; };

View File

@@ -52,6 +52,39 @@
secure-monitor = <&sm>; secure-monitor = <&sm>;
}; };
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
opp-124999998 {
opp-hz = /bits/ 64 <124999998>;
opp-microvolt = <800000>;
};
opp-249999996 {
opp-hz = /bits/ 64 <249999996>;
opp-microvolt = <800000>;
};
opp-285714281 {
opp-hz = /bits/ 64 <285714281>;
opp-microvolt = <800000>;
};
opp-399999994 {
opp-hz = /bits/ 64 <399999994>;
opp-microvolt = <800000>;
};
opp-499999992 {
opp-hz = /bits/ 64 <499999992>;
opp-microvolt = <800000>;
};
opp-666666656 {
opp-hz = /bits/ 64 <666666656>;
opp-microvolt = <800000>;
};
opp-799999987 {
opp-hz = /bits/ 64 <799999987>;
opp-microvolt = <800000>;
};
};
psci { psci {
compatible = "arm,psci-1.0"; compatible = "arm,psci-1.0";
method = "smc"; method = "smc";
@@ -185,8 +218,10 @@
interrupt-names = "macirq"; interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>, clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>, <&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>; <&clkc CLKID_MPLL2>,
clock-names = "stmmaceth", "clkin0", "clkin1"; <&clkc CLKID_FCLK_DIV2>;
clock-names = "stmmaceth", "clkin0", "clkin1",
"timing-adjustment";
rx-fifo-depth = <4096>; rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>; tx-fifo-depth = <2048>;
status = "disabled"; status = "disabled";
@@ -2360,21 +2395,7 @@
interrupt-names = "job", "mmu", "gpu"; interrupt-names = "job", "mmu", "gpu";
clocks = <&clkc CLKID_MALI>; clocks = <&clkc CLKID_MALI>;
resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
operating-points-v2 = <&gpu_opp_table>;
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<800000000>,
<0>; /* Do Nothing */
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
}; };

View File

@@ -9,6 +9,7 @@
#include "meson-g12b-s922x.dtsi" #include "meson-g12b-s922x.dtsi"
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h> #include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-toacodec.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h> #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ { / {
@@ -20,6 +21,14 @@
ethernet0 = &ethmac; ethernet0 = &ethmac;
}; };
dioo2133: audio-amplifier-0 {
compatible = "simple-audio-amplifier";
enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
VCC-supply = <&vcc_5v>;
sound-name-prefix = "U19";
status = "okay";
};
chosen { chosen {
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
@@ -209,11 +218,42 @@
sound { sound {
compatible = "amlogic,axg-sound-card"; compatible = "amlogic,axg-sound-card";
model = "G12B-ODROID-N2"; model = "G12B-ODROID-N2";
audio-aux-devs = <&tdmout_b>; audio-widgets = "Line", "Lineout";
audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
<&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
<&dioo2133>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1", "TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1", "TDMOUT_B IN 2", "FRDDR_C OUT 1",
"TDM_B Playback", "TDMOUT_B OUT"; "TDM_B Playback", "TDMOUT_B OUT",
"TDMOUT_C IN 0", "FRDDR_A OUT 2",
"TDMOUT_C IN 1", "FRDDR_B OUT 2",
"TDMOUT_C IN 2", "FRDDR_C OUT 2",
"TDM_C Playback", "TDMOUT_C OUT",
"TDMIN_A IN 4", "TDM_B Loopback",
"TDMIN_B IN 4", "TDM_B Loopback",
"TDMIN_C IN 4", "TDM_B Loopback",
"TDMIN_LB IN 1", "TDM_B Loopback",
"TDMIN_A IN 5", "TDM_C Loopback",
"TDMIN_B IN 5", "TDM_C Loopback",
"TDMIN_C IN 5", "TDM_C Loopback",
"TDMIN_LB IN 2", "TDM_C Loopback",
"TODDR_A IN 0", "TDMIN_A OUT",
"TODDR_B IN 0", "TDMIN_A OUT",
"TODDR_C IN 0", "TDMIN_A OUT",
"TODDR_A IN 1", "TDMIN_B OUT",
"TODDR_B IN 1", "TDMIN_B OUT",
"TODDR_C IN 1", "TDMIN_B OUT",
"TODDR_A IN 2", "TDMIN_C OUT",
"TODDR_B IN 2", "TDMIN_C OUT",
"TODDR_C IN 2", "TDMIN_C OUT",
"TODDR_A IN 6", "TDMIN_LB OUT",
"TODDR_B IN 6", "TDMIN_LB OUT",
"TODDR_C IN 6", "TDMIN_LB OUT",
"U19 INL", "ACODEC LOLP",
"U19 INR", "ACODEC LORP",
"Lineout", "U19 OUTL",
"Lineout", "U19 OUTR";
assigned-clocks = <&clkc CLKID_MPLL2>, assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL0>,
@@ -236,8 +276,20 @@
sound-dai = <&frddr_c>; sound-dai = <&frddr_c>;
}; };
/* 8ch hdmi interface */
dai-link-3 { dai-link-3 {
sound-dai = <&toddr_a>;
};
dai-link-4 {
sound-dai = <&toddr_b>;
};
dai-link-5 {
sound-dai = <&toddr_c>;
};
/* 8ch hdmi interface */
dai-link-6 {
sound-dai = <&tdmif_b>; sound-dai = <&tdmif_b>;
dai-format = "i2s"; dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>; dai-tdm-slot-tx-mask-0 = <1 1>;
@@ -246,22 +298,56 @@
dai-tdm-slot-tx-mask-3 = <1 1>; dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>; mclk-fs = <256>;
codec { codec-0 {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
}; };
codec-1 {
sound-dai = <&toacodec TOACODEC_IN_B>;
};
};
/* i2s jack output interface */
dai-link-7 {
sound-dai = <&tdmif_c>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
mclk-fs = <256>;
codec-0 {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
};
codec-1 {
sound-dai = <&toacodec TOACODEC_IN_C>;
};
}; };
/* hdmi glue */ /* hdmi glue */
dai-link-4 { dai-link-8 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec { codec {
sound-dai = <&hdmi_tx>; sound-dai = <&hdmi_tx>;
}; };
}; };
/* acodec glue */
dai-link-9 {
sound-dai = <&toacodec TOACODEC_OUT>;
codec {
sound-dai = <&acodec>;
};
};
}; };
}; };
&acodec {
AVDD-supply = <&vddao_1v8>;
status = "okay";
};
&arb { &arb {
status = "okay"; status = "okay";
}; };
@@ -476,14 +562,54 @@
status = "okay"; status = "okay";
}; };
&tdmif_c {
status = "okay";
};
&tdmin_a {
status = "okay";
};
&tdmin_b {
status = "okay";
};
&tdmin_c {
status = "okay";
};
&tdmin_lb {
status = "okay";
};
&tdmout_b { &tdmout_b {
status = "okay"; status = "okay";
}; };
&tdmout_c {
status = "okay";
};
&toacodec {
status = "okay";
};
&tohdmitx { &tohdmitx {
status = "okay"; status = "okay";
}; };
&toddr_a {
status = "okay";
};
&toddr_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
&uart_AO { &uart_AO {
status = "okay"; status = "okay";
pinctrl-0 = <&uart_ao_a_pins>; pinctrl-0 = <&uart_ao_a_pins>;

View File

@@ -8,6 +8,7 @@
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h> #include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/meson-aiu.h>
/ { / {
adc-keys { adc-keys {
@@ -29,6 +30,13 @@
spi0 = &spifc; spi0 = &spifc;
}; };
dio2133: analog-amplifier {
compatible = "simple-audio-amplifier";
sound-name-prefix = "AU2";
VCC-supply = <&vcc5v>;
enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
};
chosen { chosen {
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
@@ -96,14 +104,14 @@
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
green { led-green {
color = <LED_COLOR_ID_GREEN>; color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DISK_ACTIVITY; function = LED_FUNCTION_DISK_ACTIVITY;
gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity"; linux,default-trigger = "disk-activity";
}; };
blue { led-blue {
color = <LED_COLOR_ID_BLUE>; color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS; function = LED_FUNCTION_STATUS;
gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>;
@@ -175,6 +183,69 @@
regulator-settling-time-up-us = <200>; regulator-settling-time-up-us = <200>;
regulator-settling-time-down-us = <50000>; regulator-settling-time-down-us = <50000>;
}; };
sound {
compatible = "amlogic,gx-sound-card";
model = "GXL-LIBRETECH-S9XX-PC";
audio-aux-devs = <&dio2133>;
audio-widgets = "Speaker", "7J4-14 LEFT",
"Speaker", "7J4-11 RIGHT";
audio-routing = "AU2 INL", "ACODEC LOLN",
"AU2 INR", "ACODEC LORN",
"7J4-14 LEFT", "AU2 OUTL",
"7J4-11 RIGHT", "AU2 OUTR";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
codec-1 {
sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
dai-link-3 {
sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
codec-0 {
sound-dai = <&acodec>;
};
};
};
};
&acodec {
AVDD-supply = <&vddio_ao18>;
status = "okay";
};
&aiu {
status = "okay";
}; };
&cec_AO { &cec_AO {
@@ -360,8 +431,9 @@
status = "okay"; status = "okay";
}; };
&usb0 { &usb {
status = "okay"; status = "okay";
dr_mode = "host";
}; };
&usb2_phy0 { &usb2_phy0 {

View File

@@ -278,6 +278,17 @@
#reset-cells = <1>; #reset-cells = <1>;
}; };
aiu: audio-controller@5400 {
compatible = "amlogic,aiu";
#sound-dai-cells = <2>;
sound-name-prefix = "AIU";
reg = <0x0 0x5400 0x0 0x2ac>;
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "i2s", "spdif";
status = "disabled";
};
uart_A: serial@84c0 { uart_A: serial@84c0 {
compatible = "amlogic,meson-gx-uart"; compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x84c0 0x0 0x18>; reg = <0x0 0x84c0 0x0 0x18>;
@@ -398,20 +409,20 @@
}; };
sram: sram@c8000000 { sram: sram@c8000000 {
compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; compatible = "mmio-sram";
reg = <0x0 0xc8000000 0x0 0x14000>; reg = <0x0 0xc8000000 0x0 0x14000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0x0 0xc8000000 0x14000>; ranges = <0 0x0 0xc8000000 0x14000>;
cpu_scp_lpri: scp-shmem@0 { cpu_scp_lpri: scp-sram@0 {
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; compatible = "amlogic,meson-gxbb-scp-shmem";
reg = <0x13000 0x400>; reg = <0x13000 0x400>;
}; };
cpu_scp_hpri: scp-shmem@200 { cpu_scp_hpri: scp-sram@200 {
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; compatible = "amlogic,meson-gxbb-scp-shmem";
reg = <0x13400 0x400>; reg = <0x13400 0x400>;
}; };
}; };
@@ -626,6 +637,8 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
#sound-dai-cells = <0>;
sound-name-prefix = "HDMITX";
status = "disabled"; status = "disabled";
/* VPU VENC Input */ /* VPU VENC Input */

View File

@@ -29,7 +29,7 @@
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
stat { led-stat {
label = "nanopi-k2:blue:stat"; label = "nanopi-k2:blue:stat";
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
default-state = "on"; default-state = "on";

View File

@@ -49,7 +49,7 @@
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
blue { led-blue {
label = "c2:blue:alive"; label = "c2:blue:alive";
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";

View File

@@ -60,6 +60,29 @@
}; };
}; };
&aiu {
compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
clocks = <&clkc CLKID_AIU_GLUE>,
<&clkc CLKID_I2S_OUT>,
<&clkc CLKID_AOCLK_GATE>,
<&clkc CLKID_CTS_AMCLK>,
<&clkc CLKID_MIXER_IFACE>,
<&clkc CLKID_IEC958>,
<&clkc CLKID_IEC958_GATE>,
<&clkc CLKID_CTS_MCLK_I958>,
<&clkc CLKID_CTS_I958>;
clock-names = "pclk",
"i2s_pclk",
"i2s_aoclk",
"i2s_mclk",
"i2s_mixer",
"spdif_pclk",
"spdif_aoclk",
"spdif_mclk",
"spdif_mclk_sel";
resets = <&reset RESET_AIU>;
};
&aobus { &aobus {
pinctrl_aobus: pinctrl@14 { pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl"; compatible = "amlogic,meson-gxbb-aobus-pinctrl";

View File

@@ -5,7 +5,3 @@
*/ */
#include "meson-gxl-u-boot.dtsi" #include "meson-gxl-u-boot.dtsi"
&dwc2 {
status = "okay";
};

View File

@@ -8,6 +8,7 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/sound/meson-aiu.h>
#include "meson-gxl-s905x.dtsi" #include "meson-gxl-s905x.dtsi"
@@ -97,6 +98,15 @@
regulator-always-on; regulator-always-on;
}; };
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
vddio_boot: regulator-vddio_boot { vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT"; regulator-name = "VDDIO_BOOT";
@@ -105,6 +115,66 @@
vin-supply = <&vcc_3v3>; vin-supply = <&vcc_3v3>;
regulator-always-on; regulator-always-on;
}; };
sound {
compatible = "amlogic,gx-sound-card";
model = "GXL-LIBRETECH-S805X-AC";
audio-widgets = "Speaker", "9J5-3 LEFT",
"Speaker", "9J5-2 RIGHT";
audio-routing = "9J5-3 LEFT", "ACODEC LOLN",
"9J5-2 RIGHT", "ACODEC LORN";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
codec-1 {
sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
dai-link-3 {
sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
codec-0 {
sound-dai = <&acodec>;
};
};
};
};
&acodec {
AVDD-supply = <&vddio_ao18>;
status = "okay";
};
&aiu {
status = "okay";
}; };
&cec_AO { &cec_AO {
@@ -243,6 +313,7 @@
pinctrl-names = "default"; pinctrl-names = "default";
}; };
&usb0 { &usb {
status = "okay"; status = "okay";
dr_mode = "host";
}; };

View File

@@ -5,7 +5,3 @@
*/ */
#include "meson-gxl-u-boot.dtsi" #include "meson-gxl-u-boot.dtsi"
&dwc2 {
status = "okay";
};

View File

@@ -5,7 +5,3 @@
*/ */
#include "meson-gxl-u-boot.dtsi" #include "meson-gxl-u-boot.dtsi"
&dwc2 {
status = "okay";
};

View File

@@ -207,3 +207,7 @@
pinctrl-0 = <&uart_ao_b_pins>; pinctrl-0 = <&uart_ao_b_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
}; };
&usb {
dr_mode = "peripheral";
};

View File

@@ -5,7 +5,3 @@
*/ */
#include "meson-gxl-u-boot.dtsi" #include "meson-gxl-u-boot.dtsi"
&dwc2 {
status = "okay";
};

View File

@@ -8,6 +8,7 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/sound/meson-aiu.h>
#include "meson-gxl-s905x.dtsi" #include "meson-gxl-s905x.dtsi"
@@ -21,6 +22,13 @@
ethernet0 = &ethmac; ethernet0 = &ethmac;
}; };
dio2133: analog-amplifier {
compatible = "simple-audio-amplifier";
sound-name-prefix = "AU2";
VCC-supply = <&hdmi_5v>;
enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
};
chosen { chosen {
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
@@ -54,14 +62,14 @@
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
system { led-system {
label = "librecomputer:system-status"; label = "librecomputer:system-status";
gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
default-state = "on"; default-state = "on";
panic-indicator; panic-indicator;
}; };
blue { led-blue {
label = "librecomputer:blue"; label = "librecomputer:blue";
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
@@ -124,6 +132,68 @@
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>; vin-supply = <&vcc_3v3>;
}; };
sound {
compatible = "amlogic,gx-sound-card";
model = "GXL-LIBRETECH-S905X-CC";
audio-aux-devs = <&dio2133>;
audio-widgets = "Line", "Lineout";
audio-routing = "AU2 INL", "ACODEC LOLN",
"AU2 INR", "ACODEC LORN",
"Lineout", "AU2 OUTL",
"Lineout", "AU2 OUTR";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
codec-1 {
sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
dai-link-3 {
sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
codec-0 {
sound-dai = <&acodec>;
};
};
};
};
&acodec {
AVDD-supply = <&vddio_ao18>;
status = "okay";
};
&aiu {
status = "okay";
}; };
&cec_AO { &cec_AO {
@@ -272,8 +342,9 @@
pinctrl-names = "default"; pinctrl-names = "default";
}; };
&usb0 { &usb {
status = "okay"; status = "okay";
dr_mode = "host";
}; };
&usb2_phy0 { &usb2_phy0 {

View File

@@ -195,8 +195,9 @@
pinctrl-names = "default"; pinctrl-names = "default";
}; };
&usb0 { &usb {
status = "okay"; status = "okay";
dr_mode = "host";
}; };
&usb2_phy0 { &usb2_phy0 {

View File

@@ -5,19 +5,3 @@
*/ */
#include "meson-gx-u-boot.dtsi" #include "meson-gx-u-boot.dtsi"
&usb0 {
dwc2: usb@c9100000 {
compatible = "snps,dwc2";
reg = <0x0 0xc9100000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "ddr";
phys = <&usb3_phy>, <&usb2_phy1>;
dr_mode = "peripheral";
g-rx-fifo-size = <192>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <128 128 16 16 16>;
status = "disabled";
};
};

View File

@@ -14,29 +14,57 @@
compatible = "amlogic,meson-gxl"; compatible = "amlogic,meson-gxl";
soc { soc {
usb0: usb@c9000000 { usb: usb@d0078080 {
status = "disabled"; compatible = "amlogic,meson-gxl-usb-ctrl";
compatible = "amlogic,meson-gxl-dwc3"; reg = <0x0 0xd0078080 0x0 0x20>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
clocks = <&clkc CLKID_USB>; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "usb_general"; clock-names = "usb_ctrl", "ddr";
resets = <&reset RESET_USB_OTG>; resets = <&reset RESET_USB_OTG>;
reset-names = "usb_otg";
dwc3: dwc3@c9000000 { dr_mode = "otg";
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
dwc2: usb@c9100000 {
compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
reg = <0x0 0xc9100000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1>;
clock-names = "otg";
phys = <&usb2_phy1>;
dr_mode = "peripheral";
g-rx-fifo-size = <192>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <128 128 16 16 16>;
};
dwc3: usb@c9000000 {
compatible = "snps,dwc3"; compatible = "snps,dwc3";
reg = <0x0 0xc9000000 0x0 0x100000>; reg = <0x0 0xc9000000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host"; dr_mode = "host";
maximum-speed = "high-speed"; maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk; snps,dis_u2_susphy_quirk;
phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
}; };
}; };
acodec: audio-controller@c8832000 {
compatible = "amlogic,t9015";
reg = <0x0 0xc8832000 0x0 0x14>;
#sound-dai-cells = <0>;
sound-name-prefix = "ACODEC";
clocks = <&clkc CLKID_ACODEC>;
clock-names = "pclk";
resets = <&reset RESET_ACODEC>;
status = "disabled";
};
crypto: crypto@c883e000 { crypto: crypto@c883e000 {
compatible = "amlogic,gxl-crypto"; compatible = "amlogic,gxl-crypto";
reg = <0x0 0xc883e000 0x0 0x36>; reg = <0x0 0xc883e000 0x0 0x36>;
@@ -49,6 +77,29 @@
}; };
}; };
&aiu {
compatible = "amlogic,aiu-gxl", "amlogic,aiu";
clocks = <&clkc CLKID_AIU_GLUE>,
<&clkc CLKID_I2S_OUT>,
<&clkc CLKID_AOCLK_GATE>,
<&clkc CLKID_CTS_AMCLK>,
<&clkc CLKID_MIXER_IFACE>,
<&clkc CLKID_IEC958>,
<&clkc CLKID_IEC958_GATE>,
<&clkc CLKID_CTS_MCLK_I958>,
<&clkc CLKID_CTS_I958>;
clock-names = "pclk",
"i2s_pclk",
"i2s_aoclk",
"i2s_mclk",
"i2s_mixer",
"spdif_pclk",
"spdif_aoclk",
"spdif_mclk",
"spdif_mclk_sel";
resets = <&reset RESET_AIU>;
};
&apb { &apb {
usb2_phy0: phy@78000 { usb2_phy0: phy@78000 {
compatible = "amlogic,meson-gxl-usb2-phy"; compatible = "amlogic,meson-gxl-usb2-phy";
@@ -71,18 +122,6 @@
reset-names = "phy"; reset-names = "phy";
status = "okay"; status = "okay";
}; };
usb3_phy: phy@78080 {
compatible = "amlogic,meson-gxl-usb3-phy";
#phy-cells = <0>;
reg = <0x0 0x78080 0x0 0x20>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
clock-names = "phy", "peripheral";
resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
reset-names = "phy", "peripheral";
status = "okay";
};
}; };
&efuse { &efuse {

View File

@@ -12,10 +12,6 @@
}; };
}; };
&dwc2 {
status = "okay";
};
&sd_emmc_c { &sd_emmc_c {
status = "okay"; status = "okay";
pinctrl-0 = <&emmc_pins>; pinctrl-0 = <&emmc_pins>;

View File

@@ -380,6 +380,7 @@
vref-supply = <&vddio_ao18>; vref-supply = <&vddio_ao18>;
}; };
&usb0 { &usb {
status = "okay"; status = "okay";
dr_mode = "peripheral";
}; };

View File

@@ -5,7 +5,3 @@
*/ */
#include "meson-gxl-u-boot.dtsi" #include "meson-gxl-u-boot.dtsi"
&dwc2 {
status = "okay";
};

View File

@@ -169,8 +169,11 @@
compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
}; };
&dwc3 { &usb {
phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; compatible = "amlogic,meson-gxm-usb-ctrl";
phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2";
phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
}; };
&vdec { &vdec {

View File

@@ -183,6 +183,23 @@
hdmi-phandle = <&hdmi_tx>; hdmi-phandle = <&hdmi_tx>;
}; };
&cpu_thermal {
trips {
cpu_active: cpu-active {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "active";
};
};
cooling-maps {
map {
trip = <&cpu_active>;
cooling-device = <&khadas_mcu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&ext_mdio { &ext_mdio {
external_phy: ethernet-phy@0 { external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */ /* Realtek RTL8211F (0x001cc916) */
@@ -222,6 +239,12 @@
pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
khadas_mcu: system-controller@18 {
compatible = "khadas,mcu";
reg = <0x18>;
#cooling-cells = <2>;
};
gpio_expander: gpio-controller@20 { gpio_expander: gpio-controller@20 {
compatible = "ti,tca6408"; compatible = "ti,tca6408";
reg = <0x20>; reg = <0x20>;
@@ -270,7 +293,6 @@
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed; cap-sd-highspeed;
sd-uhs-sdr50;
max-frequency = <100000000>; max-frequency = <100000000>;
non-removable; non-removable;
@@ -337,7 +359,7 @@
pinctrl-0 = <&nor_pins>; pinctrl-0 = <&nor_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
w25q32: spi-flash@0 { w25q128: spi-flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "winbond,w25q128fw", "jedec,spi-nor"; compatible = "winbond,w25q128fw", "jedec,spi-nor";

View File

@@ -8,6 +8,7 @@
#include "meson-sm1.dtsi" #include "meson-sm1.dtsi"
#include "meson-khadas-vim3.dtsi" #include "meson-khadas-vim3.dtsi"
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ { / {
compatible = "khadas,vim3l", "amlogic,sm1"; compatible = "khadas,vim3l", "amlogic,sm1";
@@ -31,6 +32,69 @@
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
sound {
compatible = "amlogic,axg-sound-card";
model = "SM1-KHADAS-VIM3L";
audio-aux-devs = <&tdmout_a>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
"TDM_A Playback", "TDMOUT_A OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
/* 8ch hdmi interface */
dai-link-3 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
};
};
/* hdmi glue */
dai-link-4 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
};
};
&arb {
status = "okay";
};
&clkc_audio {
status = "okay";
}; };
&cpu0 { &cpu0 {
@@ -61,6 +125,18 @@
clock-latency = <50000>; clock-latency = <50000>;
}; };
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&pwm_AO_cd { &pwm_AO_cd {
pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-0 = <&pwm_ao_d_e_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
@@ -88,8 +164,24 @@
status = "okay"; status = "okay";
}; };
&sd_emmc_a {
sd-uhs-sdr50;
};
&usb { &usb {
phys = <&usb2_phy0>, <&usb2_phy1>; phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1"; phy-names = "usb2-phy0", "usb2-phy1";
}; };
*/ */
&tdmif_a {
status = "okay";
};
&tdmout_a {
status = "okay";
};
&tohdmitx {
status = "okay";
};

View File

@@ -8,6 +8,7 @@
#include "meson-sm1.dtsi" #include "meson-sm1.dtsi"
#include <dt-bindings/gpio/meson-g12a-gpio.h> #include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/leds/common.h> #include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ { / {
compatible = "hardkernel,odroid-c4", "amlogic,sm1"; compatible = "hardkernel,odroid-c4", "amlogic,sm1";
@@ -186,6 +187,69 @@
}; };
}; };
}; };
sound {
compatible = "amlogic,axg-sound-card";
model = "SM1-ODROID-C4";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
"TDM_B Playback", "TDMOUT_B OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
/* 8ch hdmi interface */
dai-link-3 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
/* hdmi glue */
dai-link-4 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
};
};
&arb {
status = "okay";
};
&clkc_audio {
status = "okay";
}; };
&cpu0 { &cpu0 {
@@ -237,6 +301,18 @@
amlogic,tx-delay-ns = <2>; amlogic,tx-delay-ns = <2>;
}; };
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&gpio { &gpio {
gpio-line-names = gpio-line-names =
/* GPIOZ */ /* GPIOZ */
@@ -381,6 +457,18 @@
vqmmc-supply = <&flash_1v8>; vqmmc-supply = <&flash_1v8>;
}; };
&tdmif_b {
status = "okay";
};
&tdmout_b {
status = "okay";
};
&tohdmitx {
status = "okay";
};
&uart_AO { &uart_AO {
status = "okay"; status = "okay";
pinctrl-0 = <&uart_ao_a_pins>; pinctrl-0 = <&uart_ao_a_pins>;

View File

@@ -0,0 +1,254 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7622.dtsi"
#include "mt7622-u-boot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "mt7622-bpi-r64";
compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
chosen {
stdout-path = &uart0;
tick-timer = &timer0;
};
aliases {
spi0 = &snfi;
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
status = "okay";
pcie@0,0 {
status = "okay";
};
pcie@1,0 {
status = "okay";
};
};
&pinctrl {
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pcie1_pins: pcie1-pins {
mux {
function = "pcie";
groups = "pcie1_pad_perst",
"pcie1_0_waken",
"pcie1_0_clkreq";
};
};
snfi_pins: snfi-pins {
mux {
function = "flash";
groups = "snfi";
};
};
snor_pins: snor-pins {
mux {
function = "flash";
groups = "spi_nor";
};
};
uart0_pins: uart0 {
mux {
function = "uart";
groups = "uart0_0_tx_rx" ;
};
};
pwm_pins: pwm1 {
mux {
function = "pwm";
groups = "pwm_ch1_0" ;
};
};
watchdog_pins: watchdog-default {
mux {
function = "watchdog";
groups = "watchdog";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "emmc";
groups = "emmc";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
*/
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
bias-pull-down;
};
};
mmc1_pins_default: mmc1default {
mux {
function = "sd";
groups = "sd_0";
};
/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
* DAT2, DAT3, CMD, CLK for SD respectively.
*/
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
drive-strength = <8>;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
drive-strength = <12>;
bias-pull-down;
};
conf-cd {
pins = "TXD3";
bias-pull-up;
};
};
};
&snfi {
pinctrl-names = "default", "snfi";
pinctrl-0 = <&snor_pins>;
pinctrl-1 = <&snfi_pins>;
status = "okay";
spi-flash@0{
compatible = "jedec,spi-nor";
reg = <0>;
u-boot,dm-pre-reloc;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
status = "okay";
bus-width = <8>;
max-frequency = <50000000>;
cap-sd-highspeed;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
non-removable;
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <1>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gpio {
/*gpio 90 for setting mode to sata*/
asm_sel {
gpio-hog;
gpios = <90 GPIO_ACTIVE_HIGH>;
output-low;
};
};
&ssusb {
status = "okay";
};
&u3phy {
status = "okay";
};

View File

@@ -46,8 +46,39 @@
}; };
}; };
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
status = "okay";
pcie@0,0 {
status = "okay";
};
pcie@1,0 {
status = "okay";
};
};
&pinctrl { &pinctrl {
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pcie1_pins: pcie1-pins {
mux {
function = "pcie";
groups = "pcie1_pad_perst",
"pcie1_0_waken",
"pcie1_0_clkreq";
};
};
snfi_pins: snfi-pins { snfi_pins: snfi-pins {
mux { mux {
function = "flash"; function = "flash";
@@ -191,3 +222,11 @@
full-duplex; full-duplex;
}; };
}; };
&ssusb {
status = "okay";
};
&u3phy {
status = "okay";
};

View File

@@ -10,6 +10,7 @@
#include <dt-bindings/power/mt7629-power.h> #include <dt-bindings/power/mt7629-power.h>
#include <dt-bindings/reset/mt7629-reset.h> #include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
/ { / {
compatible = "mediatek,mt7622"; compatible = "mediatek,mt7622";
@@ -142,6 +143,11 @@
reg = <0x10212000 0x800>; reg = <0x10212000 0x800>;
}; };
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&watchdog>;
};
gic: interrupt-controller@10300000 { gic: interrupt-controller@10300000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
interrupt-controller; interrupt-controller;
@@ -186,6 +192,172 @@
status = "disabled"; status = "disabled";
}; };
ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys",
"syscon";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pcie: pcie@1a140000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
reg = <0x1a140000 0x1000>,
<0x1a143000 0x1000>,
<0x1a145000 0x1000>;
reg-names = "subsys", "port0", "port1";
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
<&pciesys CLK_PCIE_P1_MAC_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P0_AUX_EN>,
<&pciesys CLK_PCIE_P1_AUX_EN>,
<&pciesys CLK_PCIE_P0_AXI_EN>,
<&pciesys CLK_PCIE_P1_AXI_EN>,
<&pciesys CLK_PCIE_P0_OBFF_EN>,
<&pciesys CLK_PCIE_P1_OBFF_EN>,
<&pciesys CLK_PCIE_P0_PIPE_EN>,
<&pciesys CLK_PCIE_P1_PIPE_EN>;
clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
status = "disabled";
pcie0: pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
status = "disabled";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
status = "disabled";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
sata: sata@1a200000 {
compatible = "mediatek,mtk-ahci";
reg = <0x1a200000 0x1100>;
resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
<&pciesys MT7622_SATA_PHY_SW_RST>,
<&pciesys MT7622_SATA_PHY_REG_RST>;
reset-names = "axi", "sw", "reg";
mediatek,phy-mode = <&pciesys>;
ports-implemented = <0x1>;
phys = <&sata_port PHY_TYPE_SATA>;
phy-names = "sata-phy";
status = "okay";
};
sata_phy: sata-phy@1a243000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0x1a243000 0x0100>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "okay";
sata_port: sata-phy@1a243000 {
reg = <0x1a243000 0x0100>;
clocks = <&topckgen CLK_TOP_ETH_500M>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
ssusb: usb@1a0c0000 {
compatible = "mediatek,mt7622-xhci",
"mediatek,mtk-xhci";
reg = <0x1a0c0000 0x01000>,
<0x1a0c4700 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
<&ssusbsys CLK_SSUSB_REF_EN>,
<&ssusbsys CLK_SSUSB_MCU_EN>,
<&ssusbsys CLK_SSUSB_DMA_EN>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
status = "disabled";
};
u3phy: usb-phy@1a0c4000 {
compatible = "mediatek,mt7622-u3phy",
"mediatek,generic-tphy-v1";
reg = <0x1a0c4000 0x700>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
u2port0: usb-phy@1a0c4800 {
reg = <0x1a0c4800 0x0100>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
clock-names = "ref";
};
u3port0: usb-phy@1a0c4900 {
reg = <0x1a0c4900 0x0700>;
#phy-cells = <1>;
};
u2port1: usb-phy@1a0c5000 {
reg = <0x1a0c5000 0x0100>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
clock-names = "ref";
};
};
ethsys: syscon@1b000000 { ethsys: syscon@1b000000 {
compatible = "mediatek,mt7622-ethsys", "syscon"; compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b000000 0x1000>; reg = <0x1b000000 0x1000>;

View File

@@ -352,6 +352,52 @@
}; };
}; };
usb1: usb@1a1c0000 {
compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
reg = <0x1a1c0000 0x1000>, <0x1a1c4700 0x0100>;
reg-names = "mac", "ippc";
power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
clock-names = "sys_ck", "ref_ck";
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
status = "disabled";
};
u3phy1: usb-phy@1a1c4000 {
compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
reg = <0x1a1c4000 0x0700>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
u2port0: usb-phy@1a1c4800 {
reg = <0x1a1c4800 0x0100>;
#phy-cells = <1>;
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
clock-names = "ref";
};
u3port0: usb-phy@1a1c4900 {
reg = <0x1a1c4900 0x0700>;
#phy-cells = <1>;
clocks = <&clk26m>;
clock-names = "ref";
};
};
usb2: usb@1a240000 {
compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
reg = <0x1a240000 0x1000>, <0x1a244700 0x0100>;
reg-names = "mac", "ippc";
power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
clock-names = "sys_ck", "ref_ck";
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
status = "disabled";
};
u3phy2: usb-phy@1a244000 { u3phy2: usb-phy@1a244000 {
compatible = "mediatek,generic-tphy-v1"; compatible = "mediatek,generic-tphy-v1";
reg = <0x1a244000 0x0700>; reg = <0x1a244000 0x0700>;

View File

@@ -248,3 +248,19 @@
pinctrl-0 = <&uart2_pins_a>; pinctrl-0 = <&uart2_pins_a>;
status = "okay"; status = "okay";
}; };
&usb1 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&usb2 {
status = "okay";
};
&u3phy2 {
status = "okay";
};

View File

@@ -43,6 +43,25 @@
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
usb_p0_vbus: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "p0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_p1_vbus: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "p1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 32 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
}; };
&mmc0 { &mmc0 {
@@ -95,6 +114,21 @@
}; };
}; };
&ssusb {
dr_mode = "peripheral";
maximum-speed = "high-speed";
status = "okay";
};
&usb3 {
vbus-supply = <&usb_p0_vbus>;
status = "okay";
};
&u3phy {
status = "okay";
};
&uart0 { &uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>; pinctrl-0 = <&uart0_pins>;

View File

@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
/ { / {
compatible = "mediatek,mt8512"; compatible = "mediatek,mt8512";
@@ -100,6 +101,52 @@
status = "disabled"; status = "disabled";
}; };
usb3: usb@11213e00 {
compatible = "mediatek,mt8512-mtu3", "mediatek,mtu3";
reg = <0x11213e00 0x0100>;
reg-names = "ippc";
phys = <&u2port0 PHY_TYPE_USB2>, <&u2port1 PHY_TYPE_USB2>;
clocks = <&infracfg CLK_INFRA_USB_SYS>,
<&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
<&infracfg CLK_INFRA_ICUSB>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
ssusb: usb@11210000 {
compatible = "mediatek,ssusb";
reg = <0x11210000 0x3e00>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
reg-names = "mac";
status = "disabled";
};
};
u3phy: usb-phy@11cc0000 {
compatible = "mediatek,mt8512-tphy",
"mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
u2port0: usb-phy@11cc0000 {
reg = <0x11cc0000 0x400>;
clocks = <&topckgen CLK_TOP_USB20_48M_EN>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u2port1: usb-phy@11c40000 {
reg = <0x11c40000 0x400>;
#phy-cells = <1>;
status = "okay";
};
};
mmc0: mmc@11230000 { mmc0: mmc@11230000 {
compatible = "mediatek,mt8512-mmc"; compatible = "mediatek,mt8512-mmc";
reg = <0x11230000 0x1000>, reg = <0x11230000 0x1000>,
@@ -112,4 +159,4 @@
status = "disabled"; status = "disabled";
}; };
}; };

View File

@@ -11,4 +11,14 @@
chosen { chosen {
stdout-path = &uart1; stdout-path = &uart1;
}; };
ethernet@2c000000 {
compatible = "smsc,lan9221","smsc,lan9115";
reg = <0x2c000000 0xff>;
bank-width = <2>;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
};
}; };

View File

@@ -11,4 +11,14 @@
chosen { chosen {
stdout-path = &uart1; stdout-path = &uart1;
}; };
ethernet@2c000000 {
compatible = "smsc,lan9221","smsc,lan9115";
reg = <0x2c000000 0xff>;
bank-width = <2>;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
};
}; };

View File

@@ -10,6 +10,8 @@
#include "skeleton.dtsi" #include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h> #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
#include <dt-bindings/reset/qcom,ipq4019-reset.h>
/ { / {
#address-cells = <1>; #address-cells = <1>;
@@ -20,6 +22,7 @@
aliases { aliases {
serial0 = &blsp1_uart1; serial0 = &blsp1_uart1;
spi0 = &blsp1_spi1;
}; };
reserved-memory { reserved-memory {
@@ -38,6 +41,11 @@
}; };
}; };
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
};
soc: soc { soc: soc {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@@ -52,6 +60,21 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
rng: rng@22000 {
compatible = "qcom,prng";
reg = <0x22000 0x140>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
status = "disabled";
};
reset: gcc-reset@1800000 {
compatible = "qcom,gcc-reset-ipq4019";
reg = <0x1800000 0x60000>;
#clock-cells = <1>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
pinctrl: qcom,tlmm@1000000 { pinctrl: qcom,tlmm@1000000 {
compatible = "qcom,tlmm-ipq4019"; compatible = "qcom,tlmm-ipq4019";
reg = <0x1000000 0x300000>; reg = <0x1000000 0x300000>;
@@ -61,7 +84,7 @@
blsp1_uart1: serial@78af000 { blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>; reg = <0x78af000 0x200>;
clock = <&gcc 26>; clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
bit-rate = <0xFF>; bit-rate = <0xFF>;
status = "disabled"; status = "disabled";
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
@@ -74,6 +97,121 @@
gpio-count = <100>; gpio-count = <100>;
gpio-bank-name="soc"; gpio-bank-name="soc";
#gpio-cells = <2>; #gpio-cells = <2>;
u-boot,dm-pre-reloc;
};
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
u-boot,dm-pre-reloc;
};
mdio: mdio@90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,ipq4019-mdio";
reg = <0x90000 0x64>;
status = "disabled";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
};
ethphy4: ethernet-phy@4 {
reg = <4>;
};
};
usb3_ss_phy: ssphy@9a000 {
compatible = "qcom,usb-ss-ipq4019-phy";
#phy-cells = <0>;
reg = <0x9a000 0x800>;
reg-names = "phy_base";
resets = <&reset USB3_UNIPHY_PHY_ARES>;
reset-names = "por_rst";
status = "disabled";
};
usb3_hs_phy: hsphy@a6000 {
compatible = "qcom,usb-hs-ipq4019-phy";
#phy-cells = <0>;
reg = <0xa6000 0x40>;
reg-names = "phy_base";
resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
reset-names = "por_rst", "srif_rst";
status = "disabled";
};
usb3: usb3@8af8800 {
compatible = "qcom,dwc3";
reg = <0x8af8800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gcc GCC_USB3_MASTER_CLK>,
<&gcc GCC_USB3_SLEEP_CLK>,
<&gcc GCC_USB3_MOCK_UTMI_CLK>;
clock-names = "master", "sleep", "mock_utmi";
ranges;
status = "disabled";
dwc3@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xf8000>;
phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
maximum-speed = "super-speed";
snps,dis_u2_susphy_quirk;
};
};
usb2_hs_phy: hsphy@a8000 {
compatible = "qcom,usb-hs-ipq4019-phy";
#phy-cells = <0>;
reg = <0xa8000 0x40>;
reg-names = "phy_base";
resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
reset-names = "por_rst", "srif_rst";
status = "disabled";
};
usb2: usb2@60f8800 {
compatible = "qcom,dwc3";
reg = <0x60f8800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gcc GCC_USB2_MASTER_CLK>,
<&gcc GCC_USB2_SLEEP_CLK>,
<&gcc GCC_USB2_MOCK_UTMI_CLK>;
clock-names = "master", "sleep", "mock_utmi";
ranges;
status = "disabled";
dwc3@6000000 {
compatible = "snps,dwc3";
reg = <0x6000000 0xf8000>;
phys = <&usb2_hs_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
};
}; };
}; };
}; };

View File

@@ -10,6 +10,8 @@
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
#include <dt-bindings/power/r8a774a1-sysc.h> #include <dt-bindings/power/r8a774a1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
/ { / {
compatible = "renesas,r8a774a1"; compatible = "renesas,r8a774a1";
#address-cells = <2>; #address-cells = <2>;
@@ -2250,7 +2252,7 @@
status = "disabled"; status = "disabled";
}; };
sdhi0: sd@ee100000 { sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774a1", compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>; reg = <0 0xee100000 0 0x2000>;
@@ -2262,7 +2264,7 @@
status = "disabled"; status = "disabled";
}; };
sdhi1: sd@ee120000 { sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774a1", compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>; reg = <0 0xee120000 0 0x2000>;
@@ -2274,7 +2276,7 @@
status = "disabled"; status = "disabled";
}; };
sdhi2: sd@ee140000 { sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774a1", compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>; reg = <0 0xee140000 0 0x2000>;
@@ -2286,7 +2288,7 @@
status = "disabled"; status = "disabled";
}; };
sdhi3: sd@ee160000 { sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774a1", compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>; reg = <0 0xee160000 0 0x2000>;

2630
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arch/arm/dts/r8a774c0.dtsi Normal file

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1664
arch/arm/dts/r8a774e1.dtsi Normal file

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