ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Aaron Williams
Daniel Schwierzeck
parent
61674a17bc
commit
15afe725f3
@ -76,3 +76,4 @@ config IMXRT_SDRAM
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source "drivers/ram/rockchip/Kconfig"
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source "drivers/ram/sifive/Kconfig"
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source "drivers/ram/stm32mp1/Kconfig"
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source "drivers/ram/octeon/Kconfig"
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@ -19,3 +19,5 @@ obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
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obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
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obj-$(CONFIG_RAM_SIFIVE) += sifive/
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obj-$(CONFIG_ARCH_OCTEON) += octeon/
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17
drivers/ram/octeon/Kconfig
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17
drivers/ram/octeon/Kconfig
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@ -0,0 +1,17 @@
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config RAM_OCTEON
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bool "Ram drivers for Octeon SoCs"
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depends on RAM && ARCH_OCTEON
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default n
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help
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This enables support for RAM drivers for Octeon SoCs.
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if RAM_OCTEON
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config RAM_OCTEON_DDR4
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bool "Octeon III DDR4 RAM support"
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default n
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help
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This enables support for DDR4 RAM suppoort for Octeon III. This does
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not include support for Octeon CN70XX.
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endif # RAM_OCTEON
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8
drivers/ram/octeon/Makefile
Normal file
8
drivers/ram/octeon/Makefile
Normal file
@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright (c) 2020 Marvell, Inc.
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#
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obj-$(CONFIG_RAM_OCTEON_DDR4) += octeon_ddr.o
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obj-$(CONFIG_RAM_OCTEON_DDR4) += octeon3_lmc.o
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obj-y += dimm_spd_eeprom.o
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407
drivers/ram/octeon/dimm_spd_eeprom.c
Normal file
407
drivers/ram/octeon/dimm_spd_eeprom.c
Normal file
@ -0,0 +1,407 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include <i2c.h>
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#include <ram.h>
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#include <mach/octeon_ddr.h>
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#define DEVICE_TYPE DDR4_SPD_KEY_BYTE_DEVICE_TYPE // same for DDR3 and DDR4
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#define MODULE_TYPE DDR4_SPD_KEY_BYTE_MODULE_TYPE // same for DDR3 and DDR4
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#define BUS_WIDTH(t) (((t) == DDR4_DRAM) ? \
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DDR4_SPD_MODULE_MEMORY_BUS_WIDTH : \
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DDR3_SPD_MEMORY_BUS_WIDTH)
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/*
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* Allow legacy code to encode bus number in the upper bits of the address
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* These are only supported in read_spd()
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*/
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#define OCTEON_TWSI_BUS_IN_ADDR_BIT 12
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#define OCTEON_TWSI_BUS_IN_ADDR_MASK (15 << OCTEON_TWSI_BUS_IN_ADDR_BIT)
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#define OCTEON_TWSI_GET_BUS(addr) \
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(((addr) >> OCTEON_TWSI_BUS_IN_ADDR_BIT) & 0xf)
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const char *ddr3_dimm_types[] = {
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/* 0000 */ "Undefined",
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/* 0001 */ "RDIMM",
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/* 0010 */ "UDIMM",
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/* 0011 */ "SO-DIMM",
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/* 0100 */ "Micro-DIMM",
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/* 0101 */ "Mini-RDIMM",
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/* 0110 */ "Mini-UDIMM",
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/* 0111 */ "Mini-CDIMM",
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/* 1000 */ "72b-SO-UDIMM",
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/* 1001 */ "72b-SO-RDIMM",
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/* 1010 */ "72b-SO-CDIMM"
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/* 1011 */ "LRDIMM",
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/* 1100 */ "16b-SO-DIMM",
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/* 1101 */ "32b-SO-DIMM",
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/* 1110 */ "Reserved",
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/* 1111 */ "Reserved"
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};
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const char *ddr4_dimm_types[] = {
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/* 0000 */ "Extended",
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/* 0001 */ "RDIMM",
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/* 0010 */ "UDIMM",
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/* 0011 */ "SO-DIMM",
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/* 0100 */ "LRDIMM",
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/* 0101 */ "Mini-RDIMM",
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/* 0110 */ "Mini-UDIMM",
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/* 0111 */ "Reserved",
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/* 1000 */ "72b-SO-RDIMM",
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/* 1001 */ "72b-SO-UDIMM",
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/* 1010 */ "Reserved",
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/* 1011 */ "Reserved",
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/* 1100 */ "16b-SO-DIMM",
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/* 1101 */ "32b-SO-DIMM",
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/* 1110 */ "Reserved",
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/* 1111 */ "Reserved"
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};
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static u16 ddr3_crc16(u8 *ptr, int count)
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{
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/* From DDR3 SPD specification */
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int crc, i;
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crc = 0;
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while (--count >= 0) {
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crc = crc ^ (int)*ptr++ << 8;
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for (i = 0; i < 8; ++i) {
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if (crc & 0x8000)
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crc = crc << 1 ^ 0x1021;
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else
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crc = crc << 1;
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}
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}
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return (crc & 0xFFFF);
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}
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static int validate_spd_checksum_ddr4(struct dimm_config *dimm_config,
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int dimm_index, int twsi_addr, int silent)
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{
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u8 *spd_data = dimm_config->spd_data[dimm_index];
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int crc_bytes = 126;
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u16 crc_comp;
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/* Check byte 0 to see how many bytes checksum is over */
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if (spd_data[0] & 0x80)
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crc_bytes = 117;
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crc_comp = ddr3_crc16(spd_data, crc_bytes);
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if (spd_data[126] == (crc_comp & 0xff) &&
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spd_data[127] == (crc_comp >> 8))
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return 1;
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if (!silent) {
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printf("DDR4 SPD CRC error, spd addr: 0x%x, calculated crc: 0x%04x, read crc: 0x%02x%02x\n",
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twsi_addr, crc_comp, spd_data[127], spd_data[126]);
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}
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return 0;
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}
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static int validate_spd_checksum(struct ddr_priv *priv,
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struct dimm_config *dimm_config,
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int dimm_index, int twsi_addr,
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int silent, u8 rv)
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{
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if (ddr_verbose(priv))
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debug("Validating DIMM at address 0x%x\n", twsi_addr);
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if (rv >= 0x8 && rv <= 0xA)
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printf("%s: Error: DDR2 support disabled\n", __func__);
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if (rv == 0xB)
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printf("%s: Error: DDR3 support disabled\n", __func__);
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if (rv == 0xC) {
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return validate_spd_checksum_ddr4(dimm_config, dimm_index,
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twsi_addr, silent);
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}
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if (!silent) {
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printf("Unrecognized DIMM type: 0x%x at spd address: 0x%x\n",
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rv, twsi_addr);
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}
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return 0;
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}
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/*
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* Read an DIMM SPD value, either using TWSI to read it from the DIMM, or
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* from a provided array.
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*/
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int read_spd(struct dimm_config *dimm_config, int dimm_index, int spd_field)
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{
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dimm_index = !!dimm_index;
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if (spd_field >= SPD_EEPROM_SIZE) {
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printf("ERROR: Trying to read unsupported SPD EEPROM value %d\n",
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spd_field);
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}
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/*
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* If pointer to data is provided, use it, otherwise read from SPD
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* over twsi
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*/
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if (dimm_config->spd_ptrs[dimm_index])
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return dimm_config->spd_ptrs[dimm_index][spd_field];
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else if (dimm_config->spd_addrs[dimm_index])
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return dimm_config->spd_data[dimm_index][spd_field];
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return -1;
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}
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int read_spd_init(struct dimm_config *dimm_config, int dimm_index)
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{
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u8 busno = OCTEON_TWSI_GET_BUS(dimm_config->spd_addrs[dimm_index]);
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u8 cmdno = dimm_config->spd_addrs[dimm_index];
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struct udevice *dev_i2c;
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u8 *spd_data;
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int ret;
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if (dimm_config->spd_cached[dimm_index])
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return 0;
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dimm_config->spd_cached[dimm_index] = 1;
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spd_data = dimm_config->spd_data[dimm_index];
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ret = i2c_get_chip_for_busnum(busno, cmdno, 2, &dev_i2c);
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if (ret) {
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debug("Cannot find SPL EEPROM: %d\n", ret);
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return -ENODEV;
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}
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ret = dm_i2c_read(dev_i2c, 0, spd_data, SPD_EEPROM_SIZE);
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return ret;
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}
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int validate_dimm(struct ddr_priv *priv, struct dimm_config *dimm_config,
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int dimm_index)
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{
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int spd_addr;
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dimm_index = !!dimm_index; /* Normalize to 0/1 */
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spd_addr = dimm_config->spd_addrs[dimm_index];
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debug("Validating dimm %d, spd addr: 0x%02x spd ptr: %p\n",
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dimm_index,
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dimm_config->spd_addrs[dimm_index],
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dimm_config->spd_ptrs[dimm_index]);
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/* Only validate 'real' dimms, assume compiled in values are OK */
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if (!dimm_config->spd_ptrs[dimm_index]) {
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int val0, val1;
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int dimm_type;
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int ret;
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ret = read_spd_init(dimm_config, dimm_index);
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if (ret)
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return 0;
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dimm_type = read_spd(dimm_config, dimm_index,
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DDR2_SPD_MEM_TYPE) & 0xff;
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switch (dimm_type) {
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case 0x0B: /* DDR3 */
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if (ddr_verbose(priv))
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printf("Validating DDR3 DIMM %d\n", dimm_index);
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val0 = read_spd(dimm_config, dimm_index,
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DDR3_SPD_DENSITY_BANKS);
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val1 = read_spd(dimm_config, dimm_index,
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DDR3_SPD_ADDRESSING_ROW_COL_BITS);
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if (val0 < 0 && val1 < 0) {
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if (ddr_verbose(priv))
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printf("Error reading SPD for DIMM %d\n",
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dimm_index);
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return 0; /* Failed to read dimm */
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}
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if (val0 == 0xff && val1 == 0xff) {
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if (ddr_verbose(priv))
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printf("Blank or unreadable SPD for DIMM %d\n",
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dimm_index);
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/* Blank SPD or otherwise unreadable device */
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return 0;
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}
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/* Don't treat bad checksums as fatal */
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validate_spd_checksum(priv, dimm_config, dimm_index,
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spd_addr, 0, dimm_type);
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break;
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case 0x0C: /* DDR4 */
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if (ddr_verbose(priv))
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printf("Validating DDR4 DIMM %d\n", dimm_index);
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val0 = read_spd(dimm_config, dimm_index,
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DDR4_SPD_DENSITY_BANKS);
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val1 = read_spd(dimm_config, dimm_index,
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DDR4_SPD_ADDRESSING_ROW_COL_BITS);
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if (val0 < 0 && val1 < 0) {
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if (ddr_verbose(priv))
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printf("Error reading SPD for DIMM %d\n",
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dimm_index);
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return 0; /* Failed to read dimm */
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}
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if (val0 == 0xff && val1 == 0xff) {
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if (ddr_verbose(priv)) {
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printf("Blank or unreadable SPD for DIMM %d\n",
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dimm_index);
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}
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/* Blank SPD or otherwise unreadable device */
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return 0;
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}
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/* Don't treat bad checksums as fatal */
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validate_spd_checksum(priv, dimm_config, dimm_index,
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spd_addr, 0, dimm_type);
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break;
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case 0x00:
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/* Terminator detected. Fail silently. */
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return 0;
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default:
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debug("Unknown DIMM type 0x%x for DIMM %d @ 0x%x\n",
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dimm_type, dimm_index,
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dimm_config->spd_addrs[dimm_index]);
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return 0; /* Failed to read dimm */
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}
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}
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return 1;
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}
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int get_ddr_type(struct dimm_config *dimm_config, int upper_dimm)
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{
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int spd_ddr_type;
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spd_ddr_type = read_spd(dimm_config, upper_dimm, DEVICE_TYPE);
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debug("%s:%d spd_ddr_type=0x%02x\n", __func__, __LINE__,
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spd_ddr_type);
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/* we return only DDR4 or DDR3 */
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return (spd_ddr_type == 0x0C) ? DDR4_DRAM : DDR3_DRAM;
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}
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static int get_dimm_ecc(struct dimm_config *dimm_config, int upper_dimm,
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int ddr_type)
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{
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return !!(read_spd(dimm_config, upper_dimm, BUS_WIDTH(ddr_type)) & 8);
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}
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int get_dimm_module_type(struct dimm_config *dimm_config, int upper_dimm,
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int ddr_type)
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{
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return read_spd(dimm_config, upper_dimm, MODULE_TYPE) & 0x0f;
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}
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char *printable_rank_spec(char *buffer, int num_ranks, int dram_width,
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int spd_package)
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{
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int die_count = ((spd_package >> 4) & 7) + 1;
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if (spd_package & 0x80) { // non-monolithic
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if ((spd_package & 3) == 2) { // 3DS
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sprintf(buffer, "%dS%dRx%d", num_ranks, die_count,
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dram_width);
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} else { // MLS
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char hchar = (die_count == 2) ? 'D' : 'Q';
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sprintf(buffer, "%d%cRx%d", num_ranks, hchar,
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dram_width);
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}
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} else {
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sprintf(buffer, "%dRx%d", num_ranks, dram_width);
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}
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return buffer;
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}
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static void report_common_dimm(struct dimm_config *dimm_config, int upper_dimm,
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int dimm, const char **dimm_types, int ddr_type,
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char *volt_str, int if_num,
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int num_ranks, int dram_width, int spd_package)
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{
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unsigned int spd_module_type;
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char rank_spec[8];
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int spd_ecc;
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spd_module_type = get_dimm_module_type(dimm_config, upper_dimm,
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ddr_type);
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spd_ecc = get_dimm_ecc(dimm_config, upper_dimm, ddr_type);
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printable_rank_spec(rank_spec, num_ranks, dram_width, spd_package);
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printf("LMC%d.DIMM%d: DDR%d %s %s %s, %s\n",
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if_num, dimm, ddr_type, dimm_types[spd_module_type],
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rank_spec, spd_ecc ? "ECC" : "non-ECC", volt_str);
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}
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static void report_ddr3_dimm(struct dimm_config *dimm_config, int upper_dimm,
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int dimm, int if_num)
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{
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int spd_voltage;
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char *volt_str;
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int spd_org = read_spd(dimm_config, upper_dimm,
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DDR3_SPD_MODULE_ORGANIZATION);
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int num_ranks = 1 + ((spd_org >> 3) & 0x7);
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int dram_width = 4 << ((spd_org >> 0) & 0x7);
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spd_voltage = read_spd(dimm_config, upper_dimm,
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DDR3_SPD_NOMINAL_VOLTAGE);
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if (spd_voltage == 0 || spd_voltage & 3)
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volt_str = "1.5V";
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if (spd_voltage & 2)
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volt_str = "1.35V";
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if (spd_voltage & 4)
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volt_str = "1.2xV";
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report_common_dimm(dimm_config, upper_dimm, dimm, ddr3_dimm_types,
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DDR3_DRAM, volt_str, if_num,
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num_ranks, dram_width, /*spd_package*/0);
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}
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static void report_ddr4_dimm(struct dimm_config *dimm_config, int upper_dimm,
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int dimm, int if_num)
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{
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int spd_voltage;
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char *volt_str;
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int spd_package = 0xff & read_spd(dimm_config, upper_dimm,
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DDR4_SPD_PACKAGE_TYPE);
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int spd_org = 0xff & read_spd(dimm_config, upper_dimm,
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DDR4_SPD_MODULE_ORGANIZATION);
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int num_ranks = 1 + ((spd_org >> 3) & 0x7);
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int dram_width = 4 << ((spd_org >> 0) & 0x7);
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spd_voltage = read_spd(dimm_config, upper_dimm,
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DDR4_SPD_MODULE_NOMINAL_VOLTAGE);
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if (spd_voltage == 0x01 || spd_voltage & 0x02)
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volt_str = "1.2V";
|
||||
if (spd_voltage == 0x04 || spd_voltage & 0x08)
|
||||
volt_str = "TBD1 V";
|
||||
if (spd_voltage == 0x10 || spd_voltage & 0x20)
|
||||
volt_str = "TBD2 V";
|
||||
|
||||
report_common_dimm(dimm_config, upper_dimm, dimm, ddr4_dimm_types,
|
||||
DDR4_DRAM, volt_str, if_num,
|
||||
num_ranks, dram_width, spd_package);
|
||||
}
|
||||
|
||||
void report_dimm(struct dimm_config *dimm_config, int upper_dimm,
|
||||
int dimm, int if_num)
|
||||
{
|
||||
int ddr_type;
|
||||
|
||||
/* ddr_type only indicates DDR4 or DDR3 */
|
||||
ddr_type = get_ddr_type(dimm_config, upper_dimm);
|
||||
|
||||
if (ddr_type == DDR4_DRAM)
|
||||
report_ddr4_dimm(dimm_config, 0, dimm, if_num);
|
||||
else
|
||||
report_ddr3_dimm(dimm_config, 0, dimm, if_num);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user