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video: dw-mipi-dsi: permit configuring the escape clock rate

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The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong 2020-10-02 11:16:09 +02:00 committed by Anatolij Gustschin
parent b53c122631
commit 01c9857fa8
2 changed files with 19 additions and 6 deletions
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24
drivers/video/dw_mipi_dsi.c
View File

@ -485,15 +485,27 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
{
const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
unsigned int esc_rate;
u32 esc_clk_division;
/*
* The maximum permitted escape clock is 20MHz and it is derived from
* lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
*
* (lane_mbps >> 3) / esc_clk_division < 20
* which is:
* (lane_mbps >> 3) / 20 > esc_clk_division
* lanebyteclk, which is running at "lane_mbps / 8".
*/
u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
if (phy_ops->get_esc_clk_rate)
phy_ops->get_esc_clk_rate(dsi->device, &esc_rate);
else
esc_rate = 20; /* Default to 20MHz */
/*
* We want:
*
* (lane_mbps >> 3) / esc_clk_division < X
* which is:
* (lane_mbps >> 3) / X > esc_clk_division
*/
esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
dsi_write(dsi, DSI_PWR_UP, RESET);

1
include/mipi_dsi.h
View File

@ -123,6 +123,7 @@ struct mipi_dsi_phy_ops {
void (*post_set_mode)(void *priv_data, unsigned long mode_flags);
int (*get_timing)(void *priv_data, unsigned int lane_mbps,
struct mipi_dsi_phy_timing *timing);
void (*get_esc_clk_rate)(void *priv_data, unsigned int *esc_clk_rate);
};
/**