x86: acpi: Add common Intel ACPI tables
Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Bin Meng
parent
350c7f52b9
commit
9b3e6d4c1f
@ -2,6 +2,8 @@
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#
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# Copyright (c) 2016 Google, Inc
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obj-$(CONFIG_INTEL_ACPIGEN) += acpi.o
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ifdef CONFIG_HAVE_MRC
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obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
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377
arch/x86/cpu/intel_common/acpi.c
Normal file
377
arch/x86/cpu/intel_common/acpi.c
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@ -0,0 +1,377 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Generic Intel ACPI table generation
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*
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* Copyright (C) 2017 Intel Corp.
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot src/soc/intel/common/block/acpi.c
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*/
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#include <common.h>
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#include <bloblist.h>
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#include <cpu.h>
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#include <dm.h>
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#include <acpi/acpigen.h>
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#include <asm/acpigen.h>
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#include <asm/acpi_table.h>
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#include <asm/cpu.h>
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#include <asm/cpu_common.h>
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#include <asm/intel_acpi.h>
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#include <asm/ioapic.h>
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#include <asm/mpspec.h>
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#include <asm/smm.h>
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#include <asm/turbo.h>
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#include <asm/intel_gnvs.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/systemagent.h>
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#include <dm/acpi.h>
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#include <linux/err.h>
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#include <power/acpi_pmc.h>
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u32 acpi_fill_mcfg(u32 current)
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{
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/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
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current += acpi_create_mcfg_mmconfig((void *)current,
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CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
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(CONFIG_SA_PCIEX_LENGTH >> 20)
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- 1);
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return current;
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}
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static int acpi_sci_irq(void)
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{
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int sci_irq = 9;
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uint scis;
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int ret;
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ret = arch_read_sci_irq_select();
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if (IS_ERR_VALUE(ret))
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return log_msg_ret("sci_irq", ret);
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scis = ret;
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scis &= SCI_IRQ_MASK;
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scis >>= SCI_IRQ_SHIFT;
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/* Determine how SCI is routed. */
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switch (scis) {
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case SCIS_IRQ9:
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case SCIS_IRQ10:
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case SCIS_IRQ11:
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sci_irq = scis - SCIS_IRQ9 + 9;
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break;
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case SCIS_IRQ20:
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case SCIS_IRQ21:
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case SCIS_IRQ22:
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case SCIS_IRQ23:
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sci_irq = scis - SCIS_IRQ20 + 20;
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break;
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default:
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log_warning("Invalid SCI route! Defaulting to IRQ9\n");
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sci_irq = 9;
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break;
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}
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log_debug("SCI is IRQ%d\n", sci_irq);
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return sci_irq;
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}
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static unsigned long acpi_madt_irq_overrides(unsigned long current)
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{
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int sci = acpi_sci_irq();
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u16 flags = MP_IRQ_TRIGGER_LEVEL;
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if (sci < 0)
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return log_msg_ret("sci irq", sci);
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/* INT_SRC_OVR */
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current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
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flags |= arch_madt_sci_irq_polarity(sci);
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/* SCI */
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current +=
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acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
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return current;
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}
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u32 acpi_fill_madt(u32 current)
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{
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/* Local APICs */
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current += acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
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return acpi_madt_irq_overrides(current);
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}
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void intel_acpi_fill_fadt(struct acpi_fadt *fadt)
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{
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const u16 pmbase = IOMAP_ACPI_BASE;
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/* Use ACPI 3.0 revision. */
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fadt->header.revision = acpi_get_table_revision(ACPITAB_FADT);
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fadt->sci_int = acpi_sci_irq();
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0;
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fadt->pm1a_evt_blk = pmbase + PM1_STS;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->gpe0_blk = pmbase + GPE0_STS;
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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/* GPE0 STS/EN pairs each 32 bits wide. */
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fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
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fadt->flush_size = 0x400; /* twice of cache size */
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fadt->flush_stride = 0x10; /* Cache line width */
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fadt->duty_offset = 1;
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fadt->day_alrm = 0xd;
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fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
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ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
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fadt->reset_reg.space_id = 1;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.addrl = IO_PORT_RESET;
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fadt->reset_value = RST_CPU | SYS_RST;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
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fadt->x_pm1b_evt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
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fadt->x_pm1b_cnt_blk.space_id = 1;
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fadt->x_gpe1_blk.space_id = 1;
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}
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int intel_southbridge_write_acpi_tables(const struct udevice *dev,
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struct acpi_ctx *ctx)
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{
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int ret;
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ret = acpi_write_dbg2_pci_uart(ctx, gd->cur_serial_dev,
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ACPI_ACCESS_SIZE_DWORD_ACCESS);
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if (ret)
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return log_msg_ret("dbg2", ret);
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ret = acpi_write_hpet(ctx);
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if (ret)
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return log_msg_ret("hpet", ret);
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return 0;
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}
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__weak u32 acpi_fill_soc_wake(u32 generic_pm1_en,
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const struct chipset_power_state *ps)
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{
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return generic_pm1_en;
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}
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__weak int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
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{
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return 0;
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}
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int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx)
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{
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struct acpi_global_nvs *gnvs;
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int ret;
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ret = bloblist_ensure_size(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs),
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(void **)&gnvs);
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if (ret)
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return log_msg_ret("bloblist", ret);
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memset(gnvs, '\0', sizeof(*gnvs));
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ret = acpi_create_gnvs(gnvs);
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if (ret)
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return log_msg_ret("gnvs", ret);
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/*
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* TODO(sjg@chromum.org): tell SMI about it
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* smm_setup_structures(gnvs, NULL, NULL);
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*/
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/* Add it to DSDT */
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acpigen_write_scope(ctx, "\\");
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acpigen_write_name_dword(ctx, "NVSA", (uintptr_t)gnvs);
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acpigen_pop_len(ctx);
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return 0;
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}
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static int calculate_power(int tdp, int p1_ratio, int ratio)
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{
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u32 m;
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u32 power;
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/*
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* M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
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*
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* Power = (ratio / p1_ratio) * m * tdp
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*/
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m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
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m = (m * m) / 1000;
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power = ((ratio * 100000 / p1_ratio) / 100);
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power *= (m / 100) * (tdp / 1000);
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power /= 1000;
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return power;
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}
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void generate_p_state_entries(struct acpi_ctx *ctx, int core,
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int cores_per_package)
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{
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int ratio_min, ratio_max, ratio_turbo, ratio_step;
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int coord_type, power_max, num_entries;
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int ratio, power, clock, clock_max;
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bool turbo;
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coord_type = cpu_get_coord_type();
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ratio_min = cpu_get_min_ratio();
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ratio_max = cpu_get_max_ratio();
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clock_max = (ratio_max * cpu_get_bus_clock_khz()) / 1000;
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turbo = (turbo_get_state() == TURBO_ENABLED);
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/* Calculate CPU TDP in mW */
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power_max = cpu_get_power_max();
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/* Write _PCT indicating use of FFixedHW */
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acpigen_write_empty_pct(ctx);
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/* Write _PPC with no limit on supported P-state */
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acpigen_write_ppc_nvs(ctx);
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/* Write PSD indicating configured coordination type */
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acpigen_write_psd_package(ctx, core, 1, coord_type);
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/* Add P-state entries in _PSS table */
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acpigen_write_name(ctx, "_PSS");
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/* Determine ratio points */
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ratio_step = PSS_RATIO_STEP;
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do {
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num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
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if (((ratio_max - ratio_min) % ratio_step) > 0)
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num_entries += 1;
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if (turbo)
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num_entries += 1;
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if (num_entries > PSS_MAX_ENTRIES)
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ratio_step += 1;
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} while (num_entries > PSS_MAX_ENTRIES);
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/* _PSS package count depends on Turbo */
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acpigen_write_package(ctx, num_entries);
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/* P[T] is Turbo state if enabled */
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if (turbo) {
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ratio_turbo = cpu_get_max_turbo_ratio();
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/* Add entry for Turbo ratio */
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acpigen_write_pss_package(ctx, clock_max + 1, /* MHz */
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power_max, /* mW */
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PSS_LATENCY_TRANSITION,/* lat1 */
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PSS_LATENCY_BUSMASTER,/* lat2 */
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ratio_turbo << 8, /* control */
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ratio_turbo << 8); /* status */
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num_entries -= 1;
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}
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/* First regular entry is max non-turbo ratio */
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acpigen_write_pss_package(ctx, clock_max, /* MHz */
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power_max, /* mW */
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PSS_LATENCY_TRANSITION,/* lat1 */
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PSS_LATENCY_BUSMASTER,/* lat2 */
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ratio_max << 8, /* control */
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ratio_max << 8); /* status */
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num_entries -= 1;
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/* Generate the remaining entries */
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for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
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ratio >= ratio_min; ratio -= ratio_step) {
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/* Calculate power at this ratio */
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power = calculate_power(power_max, ratio_max, ratio);
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clock = (ratio * cpu_get_bus_clock_khz()) / 1000;
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acpigen_write_pss_package(ctx, clock, /* MHz */
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power, /* mW */
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PSS_LATENCY_TRANSITION,/* lat1 */
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PSS_LATENCY_BUSMASTER,/* lat2 */
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ratio << 8, /* control */
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ratio << 8); /* status */
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}
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/* Fix package length */
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acpigen_pop_len(ctx);
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}
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void generate_t_state_entries(struct acpi_ctx *ctx, int core,
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int cores_per_package, struct acpi_tstate *entry,
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int nentries)
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{
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if (!nentries)
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return;
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/* Indicate SW_ALL coordination for T-states */
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acpigen_write_tsd_package(ctx, core, cores_per_package, SW_ALL);
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/* Indicate FixedHW so OS will use MSR */
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acpigen_write_empty_ptc(ctx);
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/* Set NVS controlled T-state limit */
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acpigen_write_tpc(ctx, "\\TLVL");
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/* Write TSS table for MSR access */
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acpigen_write_tss_package(ctx, entry, nentries);
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}
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int acpi_generate_cpu_header(struct acpi_ctx *ctx, int core_id,
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const struct acpi_cstate *c_state_map,
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int num_cstates)
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{
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bool is_first = !core_id;
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/* Generate processor \_PR.CPUx */
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acpigen_write_processor(ctx, core_id, is_first ? ACPI_BASE_ADDRESS : 0,
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is_first ? 6 : 0);
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/* Generate C-state tables */
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acpigen_write_cst_package(ctx, c_state_map, num_cstates);
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return 0;
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}
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int acpi_generate_cpu_package_final(struct acpi_ctx *ctx, int cores_per_package)
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{
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/*
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* PPKG is usually used for thermal management of the first and only
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* package
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*/
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acpigen_write_processor_package(ctx, "PPKG", 0, cores_per_package);
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/* Add a method to notify processor nodes */
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acpigen_write_processor_cnot(ctx, cores_per_package);
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return 0;
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}
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@ -291,3 +291,17 @@ int cpu_get_max_turbo_ratio(void)
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return msr.lo & 0xff;
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}
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int cpu_get_cores_per_package(void)
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{
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struct cpuid_result result;
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int cores = 1;
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if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
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return 1;
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result = cpuid_ext(0xb, 1);
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cores = result.ebx & 0xff;
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return cores;
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}
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@ -76,4 +76,26 @@ ulong write_acpi_tables(ulong start);
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*/
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ulong acpi_get_rsdp_addr(void);
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/**
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* arch_read_sci_irq_select() - Read the system-control interrupt number
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*
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* @returns value of IRQ register in the PMC
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*/
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int arch_read_sci_irq_select(void);
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/**
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* arch_write_sci_irq_select() - Set the system-control interrupt number
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*
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* @scis: New value for IRQ register in the PMC
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*/
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int arch_write_sci_irq_select(uint scis);
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/**
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* arch_madt_sci_irq_polarity() - Return the priority to use for the MADT
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*
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* @sci: System-control interrupt number
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* @return priority to use (MP_IRQ_POLARITY_...)
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*/
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int arch_madt_sci_irq_polarity(int sci);
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#endif /* __ASM_ACPI_TABLE_H__ */
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@ -177,4 +177,11 @@ int cpu_get_power_max(void);
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*/
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int cpu_get_max_turbo_ratio(void);
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/**
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* cpu_get_cores_per_package() - Get the number of CPU cores in each package
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*
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* @return number of cores
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*/
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int cpu_get_cores_per_package(void);
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#endif
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52
arch/x86/include/asm/intel_acpi.h
Normal file
52
arch/x86/include/asm/intel_acpi.h
Normal file
@ -0,0 +1,52 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#ifndef __ASM_INTEL_ACPI_H__
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#define __ASM_INTEL_ACPI_H__
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struct acpi_cstate;
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struct acpi_ctx;
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struct acpi_tstate;
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struct udevice;
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/**
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||||
* acpi_generate_cpu_header() - Start generating an ACPI CPU entry
|
||||
*
|
||||
* Generates the ACPI information for a CPU. After this, the caller should
|
||||
* generate_p_state_entries(), generate_t_state_entries and then
|
||||
* acpigen_pop_len() to close off this package.
|
||||
*
|
||||
* @ctx: ACPI context pointer
|
||||
* @core_id: CPU core number, as numbered by the SoC
|
||||
* @c_state_map: Information about each C state
|
||||
* @num_cstates: Number of entries in @c_state_map
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int acpi_generate_cpu_header(struct acpi_ctx *ctx, int core_id,
|
||||
const struct acpi_cstate *c_state_map,
|
||||
int num_cstates);
|
||||
|
||||
/**
|
||||
* acpi_generate_cpu_package_final() - Write out the CPU PPKG entry
|
||||
*
|
||||
* This writes information about the CPUs in the package
|
||||
*
|
||||
* @ctx: ACPI context pointer
|
||||
* @cores_per_package: Number of CPU cores in each package in the SoC
|
||||
*/
|
||||
int acpi_generate_cpu_package_final(struct acpi_ctx *ctx,
|
||||
int cores_per_package);
|
||||
|
||||
void generate_p_state_entries(struct acpi_ctx *ctx, int core,
|
||||
int cores_per_package);
|
||||
void generate_t_state_entries(struct acpi_ctx *ctx, int core,
|
||||
int cores_per_package, struct acpi_tstate *entry,
|
||||
int nentries);
|
||||
int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx);
|
||||
|
||||
int intel_southbridge_write_acpi_tables(const struct udevice *dev,
|
||||
struct acpi_ctx *ctx);
|
||||
|
||||
#endif /* __ASM_INTEL_ACPI_H__ */
|
||||
@ -277,4 +277,13 @@ config ACPIGEN
|
||||
things like generating device-specific tables and returning the ACPI
|
||||
name of a device.
|
||||
|
||||
config INTEL_ACPIGEN
|
||||
bool "Support ACPI table generation for Intel SoCs"
|
||||
depends on ACPIGEN
|
||||
help
|
||||
This option adds some functions used for programatic generation of
|
||||
ACPI tables on Intel SoCs. This provides features for writing CPU
|
||||
information such as P states and T stages. Also included is a way
|
||||
to create a GNVS table and set it up.
|
||||
|
||||
endmenu
|
||||
|
||||
Loading…
Reference in New Issue
Block a user