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IPQ40xx: Add SPI support

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Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Robert Marko 2020-10-08 22:05:10 +02:00 committed by Tom Rini
parent 367ea426a5
commit 96d6036671
3 changed files with 30 additions and 2 deletions
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12
arch/arm/dts/qcom-ipq4019.dtsi
View File

@ -22,6 +22,7 @@
aliases {
serial0 = &blsp1_uart1;
spi0 = &blsp1_spi1;
};
reserved-memory {
@ -89,6 +90,17 @@
gpio-count = <100>;
gpio-bank-name="soc";
#gpio-cells = <2>;
u-boot,dm-pre-reloc;
};
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
u-boot,dm-pre-reloc;
};
usb3_ss_phy: ssphy@9a000 {

17
arch/arm/mach-ipq40xx/clock-ipq4019.c
View File

@ -2,7 +2,7 @@
/*
* Clock drivers for Qualcomm IPQ40xx
*
* Copyright (c) 2019 Sartura Ltd.
* Copyright (c) 2020 Sartura Ltd.
*
* Author: Robert Marko <robert.marko@sartura.hr>
*
@ -24,7 +24,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
switch (clk->id) {
case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
/* This clock is already initialized by SBL1 */
return 0;
return 0;
break;
default:
return 0;
@ -47,8 +47,21 @@ static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
return msm_set_rate(clk, rate);
}
static int msm_enable(struct clk *clk)
{
switch (clk->id) {
case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
/* This clock is already initialized by SBL1 */
return 0;
break;
default:
return 0;
}
}
static struct clk_ops msm_clk_ops = {
.set_rate = msm_clk_set_rate,
.enable = msm_enable,
};
static const struct udevice_id msm_clk_ids[] = {

3
arch/arm/mach-ipq40xx/pinctrl-ipq4019.c
View File

@ -18,6 +18,9 @@ static const struct pinctrl_function msm_pinctrl_functions[] = {
{"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
{"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */
{"blsp_uart1", 1},
{"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */
{"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */
{"blsp_spi1", 2},
};
static const char *ipq4019_get_function_name(struct udevice *dev,