Release v1.3.3

Update CHANGELOG for release.

Signed-off-by: Wolfgang Denk <wd@denx.de>

.gitignore

@@ -11,6 +11,7 @@
 *.a
 *.o
 *~
+*.patch
 
 #
 # Top-level generic files
@@ -37,6 +38,7 @@
 
 # stgit generated dirs
 patches-*
+.stgit-edit.txt
 
 # quilt's files
 patches

CREDITS

@@ -236,6 +236,10 @@ E: mark.jonas@freescale.com
 D: Support for Freescale Total5200 platform
 W: http://www.mobilegt.com/
 
+N: Mark Jonas
+E: mark.jonas@de.bosch.com
+D: Support for MPR2 board
+
 N: Sam Song
 E: samsongshu@yahoo.com.cn
 D: Port to the RPXlite_DW board
@@ -431,6 +435,7 @@ D: Support for EP82xxM
 N: Art Shipkowski
 E: art@videon-central.com
 D: Support for NetSilicon NS7520
+D: Support for ColdFire MCF5275
 
 N: Michal Simek
 E: monstr@monstr.eu

MAINTAINERS

@@ -172,6 +172,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Niklaus Giger <niklaus.giger@netstal.com>
 
 	HCU4			PPC405GPr
+	MCU25			PPC405GPr
 	HCU5			PPC440EPx
 
 Frank Gottschling <fgottschling@eltec.de>
@@ -319,7 +320,9 @@ Stefan Roese <sr@denx.de>
 	alpr			PPC440GX
 	bamboo			PPC440EP
 	bunbinga		PPC405EP
+	canyonlands		PPC460EX
 	ebony			PPC440GP
+	glacier			PPC460GT
 	haleakala		PPC405EXr
 	katmai			PPC440SPe
 	kilauea			PPC405EX
@@ -405,6 +408,10 @@ John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx		MPC8xx
 
+Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+	linkstation		MPC8241
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -527,6 +534,11 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
 
 	omap730p2		ARM926EJS
 
+Stelian Pop <stelian.pop@leadtechdesign.com>
+
+	at91cap9adk		ARM926EJS (AT91CAP9 SoC)
+	at91sam9260ek		ARM926EJS (AT91SAM9260 SoC)
+
 Stefan Roese <sr@denx.de>
 
 	ixdpg425		xscale
@@ -552,6 +564,10 @@ Richard Woodruff <r-woodruff2@ti.com>
 
 	omap2420h4		ARM1136EJS
 
+Kyungmin Park <kyungmin.park@samsung.com>
+
+	apollon			ARM1136EJS
+
 Alex Z<>pke <azu@sysgo.de>
 
 	lart			SA1100
@@ -591,7 +607,7 @@ Thomas Lange <thomas@corelatus.se>
 	dbau1x00		MIPS32 Au1000
 	gth2			MIPS32 Au1000
 
-Vlad Lungu <vlad@comsys.ro>
+Vlad Lungu <vlad.lungu@windriver.com>
 	qemu_mips		MIPS32
 
 #########################################################################
@@ -652,10 +668,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 
 	TASREG			MCF5249
 
-Zachary P. Landau <zachary.landau@labxtechnologies.com>
-
-	r5200			mcf52x2
-
 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 
 	M52277EVB		mcf5227x
@@ -692,15 +704,40 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
 #	Board			CPU					#
 #########################################################################
 
-Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
+Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 
 	MS7750SE		SH7750
 	MS7722SE		SH7722
+	R7780MP			SH7780
+	R2DPlus			SH7751R
+
+Mark Jonas <mark.jonas@de.bosch.com>
+
+	mpr2			SH7720
 
 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 
 	MS7720SE		SH7720
 
+Yusuke Goda <goda.yusuke@renesas.com>
+
+	MIGO-R			SH7722
+
+#########################################################################
+# Blackfin Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Mike Frysinger <vapier@gentoo.org>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+
+	BF533-EZKIT		BF533
+	BF533-STAMP		BF533
+	BF537-STAMP		BF537
+	BF561-EZKIT		BF561
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################

MAKEALL

@@ -42,6 +42,7 @@ LIST_5xxx="		\
 	fo300		\
 	icecube_5100	\
 	icecube_5200	\
+	inka4x0		\
 	lite5200b	\
 	mcc200		\
 	mecp5200	\
@@ -165,6 +166,8 @@ LIST_4xx="		\
 	bamboo_nand	\
 	bubinga		\
 	CANBT		\
+	canyonlands	\
+	canyonlands_nand \
 	CMS700		\
 	CPCI2DP		\
 	CPCI405		\
@@ -183,6 +186,7 @@ LIST_4xx="		\
 	ERIC		\
 	EXBITGEN	\
 	G2000		\
+	glacier		\
 	haleakala	\
 	haleakala_nand	\
 	hcu4		\
@@ -198,6 +202,7 @@ LIST_4xx="		\
 	luan		\
 	lwmon5		\
 	makalu		\
+	mcu25		\
 	METROBOX	\
 	MIP405		\
 	MIP405T		\
@@ -256,6 +261,7 @@ LIST_824x="		\
 	debris		\
 	eXalion		\
 	HIDDEN_DRAGON	\
+	linkstation_HGLAN	\
 	MOUSSE		\
 	MUSENKI		\
 	MVBLUE		\
@@ -300,6 +306,7 @@ LIST_8260="		\
 	TQM8260_AC	\
 	TQM8260_AD	\
 	TQM8260_AE	\
+	TQM8272		\
 	ZPC1900		\
 "
 
@@ -381,12 +388,6 @@ LIST_74xx="		\
 	ZUMA		\
 "
 
-LIST_TSEC="		\
-	${LIST_85xx}	\
-	${LIST_86xx}	\
-	${LIST_83xx}	\
-"
-
 LIST_7xx="		\
 	BAB7xx		\
 	CPCI750		\
@@ -395,6 +396,16 @@ LIST_7xx="		\
 	ppmc7xx		\
 "
 
+#########################################################################
+## PowerPC groups
+#########################################################################
+
+LIST_TSEC="		\
+	${LIST_83xx}	\
+	${LIST_85xx}	\
+	${LIST_86xx}	\
+"
+
 LIST_ppc="		\
 	${LIST_5xx}	\
 	${LIST_512x}	\
@@ -448,6 +459,7 @@ LIST_ARM7="		\
 LIST_ARM9="			\
 	at91cap9adk		\
 	at91rm9200dk		\
+	at91sam9260ek		\
 	cmc_pu2			\
 	ap920t			\
 	ap922_XA10		\
@@ -459,6 +471,8 @@ LIST_ARM9="			\
 	cp926ejs		\
 	cp946es			\
 	cp966			\
+	csb637			\
+	kb9202			\
 	lpd7a400		\
 	m501sk			\
 	mp2usb			\
@@ -468,6 +482,7 @@ LIST_ARM9="			\
 	omap1510inn		\
 	omap1610h2		\
 	omap1610inn		\
+	omap5912osk		\
 	omap730p2		\
 	sbc2410x		\
 	scb9328			\
@@ -499,6 +514,9 @@ LIST_ARM11="		\
 	cp1136		\
 	omap2420h4	\
 	apollon		\
+	imx31_litekit	\
+	imx31_phycore	\
+	mx31ads		\
 "
 
 #########################################################################
@@ -533,6 +551,9 @@ LIST_ixp="		\
 	scpu		\
 "
 
+#########################################################################
+## ARM groups
+#########################################################################
 
 LIST_arm="		\
 	${LIST_SA}	\
@@ -637,8 +658,8 @@ LIST_nios2="		\
 #########################################################################
 
 LIST_microblaze="	\
-	suzaku		\
 	ml401		\
+	suzaku		\
 	xupv2p		\
 "
 
@@ -657,13 +678,13 @@ LIST_coldfire="			\
 	M5253EVB		\
 	M5271EVB		\
 	M5272C3			\
+	M5275EVB		\
 	M5282EVB		\
 	M5329AFEE		\
 	M5373EVB		\
 	M54455EVB		\
 	M5475AFE		\
 	M5485AFE		\
-	r5200			\
 	TASREG			\
 "
 
@@ -693,13 +714,17 @@ LIST_blackfin="		\
 ## SH Systems
 #########################################################################
 
+LIST_sh3="		\
+	mpr2		\
+	ms7720se	\
+"
+
 LIST_sh4="		\
 	ms7750se	\
 	ms7722se	\
-"
+	Migo-R		\
-
+	r7780mp		\
-LIST_sh3="		\
+	r2dplus		\
-	ms7720se	\
 "
 
 LIST_sh="		\
@@ -707,6 +732,12 @@ LIST_sh="		\
 	${LIST_sh4}	\
 "
 
+#########################################################################
+## SPARC Systems
+#########################################################################
+
+LIST_sparc="gr_xc3s_1500	gr_cpci_ax2000	gr_ep2s60	grsim	grsim_leon2"
+
 #-----------------------------------------------------------------------
 
 #----- for now, just run PPC by default -----
@@ -733,16 +764,17 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa| \
+	arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa \
-	avr32| \
+	|avr32 \
-	blackfin| \
+	|blackfin \
-	coldfire| \
+	|coldfire \
-	microblaze| \
+	|microblaze \
-	mips|mips_el| \
+	|mips|mips_el \
-	nios|nios2| \
+	|nios|nios2 \
-	ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
+	|ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
-	x86|I486|TSEC| \
+	|sh|sh3|sh4 \
-	sh|sh4|sh3 \
+	|sparc \
+	|x86|I486 \
 	)
 			for target in `eval echo '$LIST_'${arg}`
 			do

Makefile

@@ -23,7 +23,7 @@
 
 VERSION = 1
 PATCHLEVEL = 3
-SUBLEVEL = 2
+SUBLEVEL = 3
 EXTRAVERSION =
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
@@ -123,6 +123,10 @@ unexport CDPATH
 
 #########################################################################
 
+ifeq ($(ARCH),powerpc)
+ARCH = ppc
+endif
+
 ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
 
 # load ARCH, BOARD, and CPU configuration
@@ -165,7 +169,10 @@ CROSS_COMPILE = avr32-linux-
 endif
 ifeq ($(ARCH),sh)
 CROSS_COMPILE = sh4-linux-
-endif	# sh
+endif
+ifeq ($(ARCH),sparc)
+CROSS_COMPILE = sparc-elf-
+endif	# sparc
 endif	# HOSTARCH,ARCH
 endif	# CROSS_COMPILE
 
@@ -194,7 +201,6 @@ OBJS := $(addprefix $(obj),$(OBJS))
 LIBS  = lib_generic/libgeneric.a
 LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
 	"board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
-LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 ifdef SOC
 LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
@@ -233,22 +239,17 @@ LIBS += drivers/rtc/librtc.a
 LIBS += drivers/serial/libserial.a
 LIBS += drivers/usb/libusb.a
 LIBS += drivers/video/libvideo.a
-LIBS += post/libpost.a post/drivers/libpostdrivers.a
-LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
-	"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
-LIBS += $(shell if [ -d post/lib_$(ARCH)/fpu ]; then echo \
-	"post/lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
-LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
-	"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
-LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
-	"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
 LIBS += common/libcommon.a
 LIBS += libfdt/libfdt.a
 LIBS += api/libapi.a
+LIBS += post/libpost.a
 
 LIBS := $(addprefix $(obj),$(LIBS))
 .PHONY : $(LIBS) $(VERSION_FILE)
 
+LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
+LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
+
 # Add GCC lib
 PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
 
@@ -271,7 +272,7 @@ U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
 endif
 
 __OBJS := $(subst $(obj),,$(OBJS))
-__LIBS := $(subst $(obj),,$(LIBS))
+__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
 
 #########################################################################
 #########################################################################
@@ -314,8 +315,9 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
-$(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
+$(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
-		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
+		UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+		sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
 			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
@@ -326,6 +328,9 @@ $(OBJS):	depend $(obj)include/autoconf.mk
 $(LIBS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $(dir $(subst $(obj),,$@))
 
+$(LIBBOARD):	depend $(LIBS) $(obj)include/autoconf.mk
+		$(MAKE) -C $(dir $(subst $(obj),,$@))
+
 $(SUBDIRS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $@ all
 
@@ -339,17 +344,17 @@ $(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
 $(ONENAND_IPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
-		$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
+		$(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all
 
 $(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
+		$(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all
 		cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
+		cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin
 
 $(VERSION_FILE):
-		@( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \
+		@( printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' "$(U_BOOT_VERSION)" \
-		echo -n "$(U_BOOT_VERSION)" ; \
+		 '$(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion $(TOPDIR))' \
-		echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
+		 ) > $@.tmp
-			 $(TOPDIR)) ; \
-		echo "\"" ) > $@.tmp
 		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
 
 gdbtools:
@@ -419,13 +424,19 @@ $(obj)System.map:	$(obj)u-boot
 # This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
 # the dep file is only include in this top level makefile to determine when
 # to regenerate the autoconf.mk file.
-$(obj)include/autoconf.mk: $(obj)include/config.h $(VERSION_FILE)
+$(obj)include/autoconf.mk.dep: $(obj)include/config.h include/common.h
-	@$(XECHO) Generating include/autoconf.mk ; \
+	@$(XECHO) Generating $@ ; \
 	set -e ; \
 	: Generate the dependancies ; \
-	$(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -MQ $@ include/common.h > $@.dep ; \
+	$(CC) -x c -DDO_DEPS_ONLY -M $(HOST_CFLAGS) $(CPPFLAGS) \
+		-MQ $(obj)include/autoconf.mk include/common.h > $@
+
+$(obj)include/autoconf.mk: $(obj)include/config.h
+	@$(XECHO) Generating $@ ; \
+	set -e ; \
 	: Extract the config macros ; \
-	$(CPP) $(CFLAGS) -dM include/common.h | sed -n -f tools/scripts/define2mk.sed > $@
+	$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
+		sed -n -f tools/scripts/define2mk.sed > $@
 
 sinclude $(obj)include/autoconf.mk.dep
 
@@ -1170,6 +1181,25 @@ bubinga_config:	unconfig
 CANBT_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
 
+# Canyonlands & Glacier use different U-Boot images
+canyonlands_config \
+glacier_config:	unconfig
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
+		tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
+	@$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc
+
+canyonlands_nand_config \
+glacier_nand_config:	unconfig
+	@mkdir -p $(obj)include $(obj)board/amcc/canyonlands
+	@mkdir -p $(obj)nand_spl/board/amcc/canyonlands
+	@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+	@echo "#define CONFIG_$$(echo $(subst ,,$(@:_nand_config=)) | \
+		tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
+	@$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc
+	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/canyonlands/config.tmp
+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
 CATcenter_config	\
 CATcenter_25_config	\
 CATcenter_33_config:	unconfig
@@ -1281,6 +1311,10 @@ lwmon5_config:	unconfig
 makalu_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx makalu amcc
 
+mcu25_config:  unconfig
+	@mkdir -p $(obj)board/netstal/common
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx mcu25 netstal
+
 METROBOX_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
 
@@ -1477,6 +1511,18 @@ HIDDEN_DRAGON_config: unconfig
 kvme080_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc824x kvme080 etin
 
+# HDLAN is broken ATM. Should be fixed as soon as hardware is available and as
+# time permits.
+#linkstation_HDLAN_config \
+# Remove this line when HDLAN is fixed
+linkstation_HGLAN_config: unconfig
+	@mkdir -p $(obj)include
+	@case $@ in \
+		*HGLAN*) echo "#define CONFIG_HGLAN 1" >$(obj)include/config.h; ;; \
+		*HDLAN*) echo "#define CONFIG_HLAN 1" >$(obj)include/config.h; ;; \
+	esac
+	@$(MKCONFIG) -n $@ -a linkstation ppc mpc824x linkstation
+
 MOUSSE_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc824x mousse
 
@@ -1594,7 +1640,7 @@ PQ2FADS-ZU_66MHz_config	\
 PQ2FADS-ZU_66MHz_lowboot_config	\
 	:		unconfig
 	@mkdir -p $(obj)include
-	@mkdir -p $(obj)board/mpc8260ads
+	@mkdir -p $(obj)board/freescale/mpc8260ads
 	$(if $(findstring PQ2FADS,$@), \
 	@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \
 	@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
@@ -1603,13 +1649,13 @@ PQ2FADS-ZU_66MHz_lowboot_config	\
 	$(if $(findstring VR,$@), \
 	@echo "#define CONFIG_8260_CLKIN 66000000" >> $(obj)include/config.h))
 	@[ -z "$(findstring lowboot_,$@)" ] || \
-		{ echo "TEXT_BASE = 0xFF800000" >$(obj)board/mpc8260ads/config.tmp ; \
+		{ echo "TEXT_BASE = 0xFF800000" >$(obj)board/freescale/mpc8260ads/config.tmp ; \
 		  $(XECHO) "... with lowboot configuration" ; \
 		}
-	@$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads
+	@$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads freescale
 
 MPC8266ADS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads
+	@$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads freescale
 
 # PM825/PM826 default configuration:  small (= 8 MB) Flash / boot from 64-bit flash
 PM825_config	\
@@ -1802,15 +1848,15 @@ M5271EVB_config :		unconfig
 M5272C3_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3
 
+M5275EVB_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5275evb freescale
+
 M5282EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb
 
 TASREG_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd
 
-r5200_config :		unconfig
-	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
-
 M5329AFEE_config \
 M5329BFEE_config :	unconfig
 	@case "$@" in \
@@ -2228,7 +2274,7 @@ EVB64260_750CX_config:	unconfig
 	@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
 
 mpc7448hpc2_config:  unconfig
-	@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
+	@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2 freescale
 
 P3G4_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
@@ -2279,14 +2325,9 @@ shannon_config	:	unconfig
 ## ARM92xT Systems
 #########################################################################
 
-xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
+#########################################################################
-
+## Atmel AT91RM9200 Systems
-xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))
+#########################################################################
-
-xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
-
-at91cap9adk_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91cap9
 
 at91rm9200dk_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
@@ -2297,12 +2338,25 @@ cmc_pu2_config	:	unconfig
 csb637_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200
 
+kb9202_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200
+
 mp2usb_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
 
 m501sk_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t m501sk NULL at91rm9200
 
+#########################################################################
+## Atmel ARM926EJ-S Systems
+#########################################################################
+
+at91cap9adk_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91sam9
+
+at91sam9260ek_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
+
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
 integratorap_config	\
@@ -2329,9 +2383,6 @@ cp922_XA10_config	\
 cp1026_config: unconfig
 	@board/integratorcp/split_by_variant.sh $@
 
-kb9202_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200
-
 lpd7a400_config \
 lpd7a404_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
@@ -2360,6 +2411,8 @@ davinci_schmoogie_config :	unconfig
 davinci_sonata_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
 
+xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))
+
 omap1610inn_config \
 omap1610inn_cs0boot_config \
 omap1610inn_cs3boot_config \
@@ -2381,6 +2434,8 @@ omap1610h2_cs_autoboot_config:	unconfig
 	fi;
 	@$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap
 
+xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
+
 omap730p2_config \
 omap730p2_cs0boot_config \
 omap730p2_cs3boot_config :	unconfig
@@ -2410,6 +2465,8 @@ SX1_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm925t sx1
 
 # TRAB default configuration:	8 MB Flash, 32 MB RAM
+xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
+
 trab_config \
 trab_bigram_config \
 trab_bigflash_config \
@@ -2455,11 +2512,6 @@ cm4008_config	:	unconfig
 cm41xx_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695
 
-gth2_config		:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_GTH2 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a gth2 mips mips gth2
-
 #########################################################################
 ## S3C44B0 Systems
 #########################################################################
@@ -2575,14 +2627,23 @@ zylonite_config :
 ## ARM1136 Systems
 #########################################################################
 omap2420h4_config	: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
+	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
 
 apollon_config		: unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
-	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
+	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
 	@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
 
+imx31_litekit_config	: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
+
+imx31_phycore_config	: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+
+mx31ads_config		: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
+
 #========================================================================
 # i386
 #========================================================================
@@ -2662,6 +2723,11 @@ pb1000_config		:	unconfig
 	@echo "#define CONFIG_PB1000 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a pb1x00 mips mips pb1x00
 
+gth2_config:	unconfig
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_GTH2 1" >$(obj)include/config.h
+	@$(MKCONFIG) -a gth2 mips mips gth2
+
 qemu_mips_config: unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h
@@ -2788,7 +2854,7 @@ xupv2p_config:	unconfig
 BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit
 
 $(BFIN_BOARDS:%=%_config)	: unconfig
-	@$(MKCONFIG) $(@:_config=) blackfin $(firstword $(subst -, ,$@)) $(@:_config=)
+	@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
 
 $(BFIN_BOARDS):
 	$(MAKE) $@_config
@@ -2798,7 +2864,7 @@ $(BFIN_BOARDS):
 # AVR32
 #========================================================================
 #########################################################################
-## AT32AP7xxx
+## AT32AP70xx
 #########################################################################
 
 atstk1002_config	:	unconfig
@@ -2820,6 +2886,11 @@ atngw100_config	:	unconfig
 #########################################################################
 ## sh3 (Renesas SuperH)
 #########################################################################
+mpr2_config: unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_MPR2 1" >> include/config.h
+	@$(MKCONFIG) -a $(@:_config=) sh sh3 mpr2
+
 ms7720se_config: unconfig
 	@echo "#define CONFIG_MS7720SE 1" > include/config.h
 	@$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se
@@ -2835,6 +2906,53 @@ ms7722se_config :	unconfig
 	@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) sh sh4 ms7722se
 
+MigoR_config :       unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_MIGO_R 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 MigoR
+
+r7780mp_config: unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_R7780MP 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 r7780mp
+
+r2dplus_config  :   unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_R2DPLUS 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 r2dplus
+
+#========================================================================
+# SPARC
+#========================================================================
+#########################################################################
+## LEON3
+#########################################################################
+
+# Gaisler GR-XC3S-1500 board
+gr_xc3s_1500_config : unconfig
+	@$(MKCONFIG) $(@:_config=) sparc leon3 gr_xc3s_1500 gaisler
+
+# Gaisler GR-CPCI-AX2000 board, a General purpose FPGA-AX system
+gr_cpci_ax2000_config : unconfig
+	@$(MKCONFIG) $(@:_config=) sparc leon3 gr_cpci_ax2000 gaisler
+
+# Gaisler GRLIB template design (GPL SPARC/LEON3) for Altera NIOS
+# Development board Stratix II edition, FPGA Device EP2S60.
+gr_ep2s60_config: unconfig
+	@$(MKCONFIG) $(@:_config=) sparc leon3 gr_ep2s60 gaisler
+
+# Gaisler LEON3 GRSIM simulator
+grsim_config : unconfig
+	@$(MKCONFIG) $(@:_config=) sparc leon3 grsim gaisler
+
+#########################################################################
+## LEON2
+#########################################################################
+
+# Gaisler LEON2 GRSIM simulator
+grsim_leon2_config : unconfig
+	@$(MKCONFIG) $(@:_config=) sparc leon2 grsim_leon2 gaisler
+
 #########################################################################
 #########################################################################
 #########################################################################
@@ -2856,9 +2974,11 @@ clean:
 	       $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin}	  \
 	       $(obj)board/trab/trab_fkt   $(obj)board/voiceblue/eeprom   \
 	       $(obj)board/{integratorap,integratorcp}/u-boot.lds	  \
-	       $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds
+	       $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds \
-	@rm -f $(obj)include/bmp_logo.h $(obj)nand_spl/{u-boot-spl,u-boot-spl.map}
+	       $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
-	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl.map}
+	@rm -f $(obj)include/bmp_logo.h
+	@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
+	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
 	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \
@@ -2873,7 +2993,9 @@ clobber:	clean
 	@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
 		$(obj)cscope.* $(obj)*.*~
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
-	@rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,sha1.c,inca-swap-bytes}
+	@rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,md5.c,sha1.c,inca-swap-bytes}
+	@rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c,zlib.h}
+	@rm -f $(obj)tools/{fdt_wip.c,libfdt_internal.h}
 	@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f

README

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000 - 2005
+# (C) Copyright 2000 - 2008
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -51,7 +51,8 @@ Makefile have been tested to some extent and can be considered
 "working". In fact, many of them are used in production systems.
 
 In case of problems see the CHANGELOG and CREDITS files to find out
-who contributed the specific port.
+who contributed the specific port. The MAINTAINERS file lists board
+maintainers.
 
 
 Where to get help:
@@ -65,6 +66,22 @@ before asking FAQ's. Please see
 http://lists.sourceforge.net/lists/listinfo/u-boot-users/
 
 
+Where to get source code:
+=========================
+
+The U-Boot source code is maintained in the git repository at
+git://www.denx.de/git/u-boot.git ; you can browse it online at
+http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
+
+The "snapshot" links on this page allow you to download tarballs of
+any version you might be interested in. Ofifcial releases are also
+available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
+directory.
+
+Pre-built (and tested) images are available from
+ftp://ftp.denx.de/pub/u-boot/images/
+
+
 Where we come from:
 ===================
 
@@ -81,6 +98,7 @@ Where we come from:
 - create ARMBoot project (http://sourceforge.net/projects/armboot)
 - add other CPU families (starting with ARM)
 - create U-Boot project (http://sourceforge.net/projects/u-boot)
+- current project page: see http://www.denx.de/wiki/UBoot
 
 
 Names and Spelling:
@@ -135,6 +153,8 @@ Directory Hierarchy:
   - at32ap	Files specific to Atmel AVR32 AP CPUs
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
+  - leon2	Files specific to Gaisler LEON2 SPARC CPU
+  - leon3	Files specific to Gaisler LEON3 SPARC CPU
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
   - mcf5227x	Files specific to Freescale ColdFire MCF5227x CPUs
   - mcf532x	Files specific to Freescale ColdFire MCF5329 CPUs
@@ -168,7 +188,8 @@ Directory Hierarchy:
 - lib_mips	Files generic to MIPS	 architecture
 - lib_nios	Files generic to NIOS	 architecture
 - lib_ppc	Files generic to PowerPC architecture
-- libfdt 	Library files to support flattened device trees
+- lib_sparc	Files generic to SPARC	 architecture
+- libfdt	Library files to support flattened device trees
 - net		Networking code
 - post		Power On Self Test
 - rtc		Real Time Clock drivers
@@ -320,7 +341,7 @@ The following options need to be configured:
 		converts clock data to MHZ before passing it to the
 		Linux kernel.
 		When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
-		"clocks_in_mhz=1" is  automatically  included  in  the
+		"clocks_in_mhz=1" is automatically included in the
 		default environment.
 
 		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
@@ -354,19 +375,6 @@ The following options need to be configured:
 
 		boards with QUICC Engines require OF_QE to set UCC mac addresses
 
-		CONFIG_OF_HAS_BD_T
-
-		 * CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
-		 * CONFIG_OF_FLAT_TREE - The resulting flat device tree
-		     will have a copy of the bd_t.  Space should be
-		     pre-allocated in the dts for the bd_t.
-
-		CONFIG_OF_HAS_UBOOT_ENV
-
-		 * CONFIG_OF_LIBFDT - enables the "fdt env" command
-		 * CONFIG_OF_FLAT_TREE - The resulting flat device tree
-		     will have a copy of u-boot's environment variables
-
 		CONFIG_OF_BOARD_SETUP
 
 		Board code has addition modification that it wants to make
@@ -615,7 +623,6 @@ The following options need to be configured:
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_USB		* USB support
 		CONFIG_CMD_VFD		* VFD support (TRAB)
-		CONFIG_CMD_BSP		* Board SPecific functions
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_FSL		* Microblaze FSL support
 
@@ -664,12 +671,15 @@ The following options need to be configured:
 
 		CONFIG_RTC_MPC8xx	- use internal RTC of MPC8xx
 		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
+		CONFIG_RTC_MC13783	- use MC13783 RTC
 		CONFIG_RTC_MC146818	- use MC146818 RTC
 		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
+		CONFIG_RTC_ISL1208	- use Intersil ISL1208 RTC
 		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
+		CFG_RTC_DS1337_NOOSC	- Turn off the OSC output for DS1337
 
 		Note that if the RTC uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
@@ -685,9 +695,9 @@ The following options need to be configured:
 		CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION
 		and/or CONFIG_ISO_PARTITION
 
-		If IDE or SCSI support	is  enabled  (CONFIG_CMD_IDE or
+		If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
-		CONFIG_CMD_SCSI) you must configure support for at least
+		CONFIG_CMD_SCSI) you must configure support for at
-		one partition type as well.
+		least one partition type as well.
 
 - IDE Reset method:
 		CONFIG_IDE_RESET_ROUTINE - this is defined in several
@@ -731,6 +741,9 @@ The following options need to be configured:
 		CONFIG_E1000
 		Support for Intel 8254x gigabit chips.
 
+		CONFIG_E1000_FALLBACK_MAC
+		default MAC for empty eeprom after production.
+
 		CONFIG_EEPRO100
 		Support for Intel 82557/82559/82559ER chips.
 		Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
@@ -1131,6 +1144,20 @@ The following options need to be configured:
 		of the "hostname" environment variable is passed as
 		option 12 to the DHCP server.
 
+		CONFIG_BOOTP_DHCP_REQUEST_DELAY
+
+		A 32bit value in microseconds for a delay between
+		receiving a "DHCP Offer" and sending the "DHCP Request".
+		This fixes a problem with certain DHCP servers that don't
+		respond 100% of the time to a "DHCP request". E.g. On an
+		AT91RM9200 processor running at 180MHz, this delay needed
+		to be *at least* 15,000 usec before a Windows Server 2003
+		DHCP server would reply 100% of the time. I recommend at
+		least 50,000 usec to be safe. The alternative is to hope
+		that one of the retries will be successful but note that
+		the DHCP timeout and retry process takes a longer than
+		this delay.
+
  - CDP Options:
 		CONFIG_CDP_DEVICE_ID
 
@@ -1324,7 +1351,7 @@ The following options need to be configured:
 		This option specifies a list of I2C devices that will be skipped
 		when the 'i2c probe' command is issued (or 'iprobe' using the legacy
 		command).  If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device
-		pairs.  Otherwise, specify a 1D array of device addresses
+		pairs.	Otherwise, specify a 1D array of device addresses
 
 		e.g.
 			#undef	CONFIG_I2C_MULTI_BUS
@@ -1387,6 +1414,11 @@ The following options need to be configured:
 		Currently supported on some MPC8xxx processors.  For an
 		example, see include/configs/mpc8349emds.h.
 
+		CONFIG_MXC_SPI
+
+		Enables the driver for the SPI controllers on i.MX and MXC
+		SoCs. Currently only i.MX31 is supported.
+
 - FPGA Support: CONFIG_FPGA
 
 		Enables FPGA subsystem.
@@ -1528,6 +1560,10 @@ The following options need to be configured:
 		before giving up the operation. If not defined, a
 		default value of 5 is used.
 
+		CONFIG_ARP_TIMEOUT
+
+		Timeout waiting for an ARP reply in milliseconds.
+
 - Command Interpreter:
 		CONFIG_AUTO_COMPLETE
 
@@ -1659,6 +1695,8 @@ The following options need to be configured:
 		example, some LED's) on your board. At the moment,
 		the following checkpoints are implemented:
 
+Legacy uImage format:
+
   Arg	Where			When
     1	common/cmd_bootm.c	before attempting to boot an image
    -1	common/cmd_bootm.c	Image header has bad	 magic number
@@ -1669,25 +1707,26 @@ The following options need to be configured:
     4	common/cmd_bootm.c	Image data   has correct checksum
    -4	common/cmd_bootm.c	Image is for unsupported architecture
     5	common/cmd_bootm.c	Architecture check OK
-   -5	common/cmd_bootm.c	Wrong Image Type (not kernel, multi, standalone)
+   -5	common/cmd_bootm.c	Wrong Image Type (not kernel, multi)
     6	common/cmd_bootm.c	Image Type check OK
    -6	common/cmd_bootm.c	gunzip uncompression error
    -7	common/cmd_bootm.c	Unimplemented compression type
     7	common/cmd_bootm.c	Uncompression OK
-   -8	common/cmd_bootm.c	Wrong Image Type (not kernel, multi, standalone)
+    8	common/cmd_bootm.c	No uncompress/copy overwrite error
-    8	common/cmd_bootm.c	Image Type check OK
    -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
-    9	common/cmd_bootm.c	Start initial ramdisk verification
+
-  -10	common/cmd_bootm.c	Ramdisk header has bad	   magic number
+    9	common/image.c		Start initial ramdisk verification
-  -11	common/cmd_bootm.c	Ramdisk header has bad	   checksum
+  -10	common/image.c		Ramdisk header has bad	   magic number
-   10	common/cmd_bootm.c	Ramdisk header is OK
+  -11	common/image.c		Ramdisk header has bad	   checksum
-  -12	common/cmd_bootm.c	Ramdisk data   has bad	   checksum
+   10	common/image.c		Ramdisk header is OK
-   11	common/cmd_bootm.c	Ramdisk data   has correct checksum
+  -12	common/image.c		Ramdisk data   has bad	   checksum
-   12	common/cmd_bootm.c	Ramdisk verification complete, start loading
+   11	common/image.c		Ramdisk data   has correct checksum
-  -13	common/cmd_bootm.c	Wrong Image Type (not PPC Linux Ramdisk)
+   12	common/image.c		Ramdisk verification complete, start loading
-   13	common/cmd_bootm.c	Start multifile image verification
+  -13	common/image.c		Wrong Image Type (not PPC Linux Ramdisk)
-   14	common/cmd_bootm.c	No initial ramdisk, no multifile, continue.
+   13	common/image.c		Start multifile image verification
-   15	common/cmd_bootm.c	All preparation done, transferring control to OS
+   14	common/image.c		No initial ramdisk, no multifile, continue.
+
+   15	lib_<arch>/bootm.c	All preparation done, transferring control to OS
 
   -30	lib_ppc/board.c		Fatal error, hang the system
   -31	post/post.c		POST test failed, detected by post_output_backlog()
@@ -1757,6 +1796,59 @@ The following options need to be configured:
   -83	common/cmd_net.c	some error in automatic boot or autoscript
    84	common/cmd_net.c	end without errors
 
+FIT uImage format:
+
+  Arg	Where			When
+  100	common/cmd_bootm.c	Kernel FIT Image has correct format
+ -100	common/cmd_bootm.c	Kernel FIT Image has incorrect format
+  101	common/cmd_bootm.c	No Kernel subimage unit name, using configuration
+ -101	common/cmd_bootm.c	Can't get configuration for kernel subimage
+  102	common/cmd_bootm.c	Kernel unit name specified
+ -103	common/cmd_bootm.c	Can't get kernel subimage node offset
+  103	common/cmd_bootm.c	Found configuration node
+  104	common/cmd_bootm.c	Got kernel subimage node offset
+ -104	common/cmd_bootm.c	Kernel subimage hash verification failed
+  105	common/cmd_bootm.c	Kernel subimage hash verification OK
+ -105	common/cmd_bootm.c	Kernel subimage is for unsupported architecture
+  106	common/cmd_bootm.c	Architecture check OK
+ -106	common/cmd_bootm.c	Kernel subimage has wrong typea
+  107	common/cmd_bootm.c	Kernel subimge type OK
+ -107	common/cmd_bootm.c	Can't get kernel subimage data/size
+  108	common/cmd_bootm.c	Got kernel subimage data/size
+ -108	common/cmd_bootm.c	Wrong image type (not legacy, FIT)
+ -109	common/cmd_bootm.c	Can't get kernel subimage type
+ -110	common/cmd_bootm.c	Can't get kernel subimage comp
+ -111	common/cmd_bootm.c	Can't get kernel subimage os
+ -112	common/cmd_bootm.c	Can't get kernel subimage load address
+ -113	common/cmd_bootm.c	Image uncompress/copy overwrite error
+
+  120	common/image.c		Start initial ramdisk verification
+ -120	common/image.c		Ramdisk FIT image has incorrect format
+  121	common/image.c		Ramdisk FIT image has correct format
+  122	common/image.c		No Ramdisk subimage unit name, using configuration
+ -122	common/image.c		Can't get configuration for ramdisk subimage
+  123	common/image.c		Ramdisk unit name specified
+ -124	common/image.c		Can't get ramdisk subimage node offset
+  125	common/image.c		Got ramdisk subimage node offset
+ -125	common/image.c		Ramdisk subimage hash verification failed
+  126	common/image.c		Ramdisk subimage hash verification OK
+ -126	common/image.c		Ramdisk subimage for unsupported architecture
+  127	common/image.c		Architecture check OK
+ -127	common/image.c		Can't get ramdisk subimage data/size
+  128	common/image.c		Got ramdisk subimage data/size
+  129	common/image.c		Can't get ramdisk load address
+ -129	common/image.c		Got ramdisk load address
+
+ -130	common/cmd_doc.c	Icorrect FIT image format
+  131	common/cmd_doc.c	FIT image format OK
+
+ -140	common/cmd_ide.c	Icorrect FIT image format
+  141	common/cmd_ide.c	FIT image format OK
+
+ -150	common/cmd_nand.c	Icorrect FIT image format
+  151	common/cmd_nand.c	FIT image format OK
+
+
 Modem Support:
 --------------
 
@@ -1853,6 +1945,27 @@ Configuration Settings:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 
+- CFG_MEM_TOP_HIDE (PPC only):
+		If CFG_MEM_TOP_HIDE is defined in the board config header,
+		this specified memory area will get subtracted from the top
+		(end) of ram and won't get "touched" at all by U-Boot. By
+		fixing up gd->ram_size the Linux kernel should gets passed
+		the now "corrected" memory size and won't touch it either.
+		This should work for arch/ppc and arch/powerpc. Only Linux
+		board ports in arch/powerpc with bootwrapper support that
+		recalculate the memory size from the SDRAM controller setup
+		will have to get fixed in Linux additionally.
+
+		This option can be used as a workaround for the 440EPx/GRx
+		CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
+		be touched.
+
+		WARNING: Please make sure that this value is a multiple of
+		the Linux page size (normally 4k). If this is not the case,
+		then the end address of the Linux memory will be located at a
+		non page size aligned address and this could cause major
+		problems.
+
 - CFG_TFTP_LOADADDR:
 		Default load address for network file downloads
 
@@ -1893,8 +2006,11 @@ Configuration Settings:
 - CFG_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
-		the Linux kernel (bd_info, boot arguments, eventually
+		the Linux kernel (bd_info, boot arguments, FDT blob if
-		initrd image) must be put below this limit.
+		used) must be put below this limit, unless "bootm_low"
+		enviroment variable is defined and non-zero. In such case
+		all data for the Linux kernel must be between "bootm_low"
+		and "bootm_low" + CFG_BOOTMAPSZ.
 
 - CFG_MAX_FLASH_BANKS:
 		Max number of Flash memory banks
@@ -1939,12 +2055,24 @@ Configuration Settings:
 		This option also enables the building of the cfi_flash driver
 		in the drivers directory
 
+- CFG_FLASH_USE_BUFFER_WRITE
+		Use buffered writes to flash.
+
+- CONFIG_FLASH_SPANSION_S29WS_N
+		s29ws-n MirrorBit flash has non-standard addresses for buffered
+		write commands.
+
 - CFG_FLASH_QUIET_TEST
 		If this option is defined, the common CFI flash doesn't
 		print it's warning upon not recognized FLASH banks. This
 		is useful, if some of the configured banks are only
 		optionally available.
 
+- CONFIG_FLASH_SHOW_PROGRESS
+		If defined (must be an integer), print out countdown
+		digits and dots.  Recommended value: 45 (9..1) for 80
+		column displays, 15 (3..1) for 40 column displays.
+
 - CFG_RX_ETH_BUFFER:
 		Defines the number of ethernet receive buffers. On some
 		ethernet controllers it is recommended to set this value
@@ -2318,22 +2446,24 @@ Low Level (hardware related) configuration options:
 		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
 
 - CONFIG_SPD_EEPROM
-		Get DDR timing information from an I2C EEPROM.  Common with pluggable
+		Get DDR timing information from an I2C EEPROM. Common
-		memory modules such as SODIMMs
+		with pluggable memory modules such as SODIMMs
+
   SPD_EEPROM_ADDRESS
 		I2C address of the SPD EEPROM
 
 - CFG_SPD_BUS_NUM
-		If SPD EEPROM is on an I2C bus other than the first one, specify here.
+		If SPD EEPROM is on an I2C bus other than the first
-		Note that the value must resolve to something your driver can deal with.
+		one, specify here. Note that the value must resolve
+		to something your driver can deal with.
 
 - CFG_83XX_DDR_USES_CS0
-		Only for 83xx systems. If specified, then DDR should be configured
+		Only for 83xx systems. If specified, then DDR should
-		using CS0 and CS1 instead of CS2 and CS3.
+		be configured using CS0 and CS1 instead of CS2 and CS3.
 
 - CFG_83XX_DDR_USES_CS0
-		Only for 83xx systems. If specified, then DDR should be configured
+		Only for 83xx systems. If specified, then DDR should
-		using CS0 and CS1 instead of CS2 and CS3.
+		be configured using CS0 and CS1 instead of CS2 and CS3.
 
 - CONFIG_ETHER_ON_FEC[12]
 		Define to enable FEC[12] on a 8xx series processor.
@@ -2399,29 +2529,30 @@ Low Level (hardware related) configuration options:
 Building the Software:
 ======================
 
-Building U-Boot has been tested in native PPC environments (on a
+Building U-Boot has been tested in several native build environments
-PowerBook G3 running LinuxPPC 2000) and in cross environments
+and in many different cross environments. Of course we cannot support
-(running RedHat 6.x and 7.x Linux on x86, Solaris 2.6 on a SPARC, and
+all possibly existing versions of cross development tools in all
-NetBSD 1.5 on x86).
+(potentially obsolete) versions. In case of tool chain problems we
+recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK)
+which is extensively used to build and test U-Boot.
 
-If you are not using a native PPC environment, it is assumed that you
+If you are not using a native environment, it is assumed that you
-have the GNU cross compiling tools available in your path and named
+have GNU cross compiling tools available in your path. In this case,
-with a prefix of "powerpc-linux-". If this is not the case, (e.g. if
+you must set the environment variable CROSS_COMPILE in your shell.
-you are using Monta Vista's Hard Hat Linux CDK 1.2) you must change
+Note that no changes to the Makefile or any other source files are
-the definition of CROSS_COMPILE in Makefile. For HHL on a 4xx CPU,
+necessary. For example using the ELDK on a 4xx CPU, please enter:
-change it to:
 
-	CROSS_COMPILE = ppc_4xx-
+	$ CROSS_COMPILE=ppc_4xx-
+	$ export CROSS_COMPILE
 
-
+U-Boot is intended to be simple to build. After installing the
-U-Boot is intended to be  simple  to  build.  After  installing	 the
+sources you must configure U-Boot for one specific board type. This
-sources	 you must configure U-Boot for one specific board type. This
 is done by typing:
 
 	make NAME_config
 
-where "NAME_config" is the name of one of the existing
+where "NAME_config" is the name of one of the existing configu-
-configurations; see the main Makefile for supported names.
+rations; see the main Makefile for supported names.
 
 Note: for some board special configuration names may exist; check if
       additional information is available from the board vendor; for
@@ -2497,20 +2628,20 @@ steps:
 Testing of U-Boot Modifications, Ports to New Hardware, etc.:
 ==============================================================
 
-If you have modified U-Boot sources (for instance added a new	board
+If you have modified U-Boot sources (for instance added a new board
-or  support  for  new  devices,	 a new CPU, etc.) you are expected to
+or support for new devices, a new CPU, etc.) you are expected to
 provide feedback to the other developers. The feedback normally takes
 the form of a "patch", i. e. a context diff against a certain (latest
-official or latest in CVS) version of U-Boot sources.
+official or latest in the git repository) version of U-Boot sources.
 
-But before you submit such a patch, please verify that	your  modifi-
+But before you submit such a patch, please verify that your modifi-
-cation	did not break existing code. At least make sure that *ALL* of
+cation did not break existing code. At least make sure that *ALL* of
 the supported boards compile WITHOUT ANY compiler warnings. To do so,
 just run the "MAKEALL" script, which will configure and build U-Boot
-for ALL supported system. Be warned, this will take a while. You  can
+for ALL supported system. Be warned, this will take a while. You can
-select	which  (cross)	compiler  to use by passing a `CROSS_COMPILE'
+select which (cross) compiler to use by passing a `CROSS_COMPILE'
-environment variable to the script, i. e. to use the cross tools from
+environment variable to the script, i. e. to use the ELDK cross tools
-MontaVista's Hard Hat Linux you can type
+you can type
 
 	CROSS_COMPILE=ppc_8xx- MAKEALL
 
@@ -2518,20 +2649,21 @@ or to build on a native PowerPC system you can type
 
 	CROSS_COMPILE=' ' MAKEALL
 
-When using the MAKEALL script, the default behaviour is to build U-Boot
+When using the MAKEALL script, the default behaviour is to build
-in the source directory. This location can be changed by setting the
+U-Boot in the source directory. This location can be changed by
-BUILD_DIR environment variable. Also, for each target built, the MAKEALL
+setting the BUILD_DIR environment variable. Also, for each target
-script saves two log files (<target>.ERR and <target>.MAKEALL) in the
+built, the MAKEALL script saves two log files (<target>.ERR and
-<source dir>/LOG directory. This default location can be changed by
+<target>.MAKEALL) in the <source dir>/LOG directory. This default
-setting the MAKEALL_LOGDIR environment variable. For example:
+location can be changed by setting the MAKEALL_LOGDIR environment
+variable. For example:
 
 	export BUILD_DIR=/tmp/build
 	export MAKEALL_LOGDIR=/tmp/log
 	CROSS_COMPILE=ppc_8xx- MAKEALL
 
-With the above settings build objects are saved in the /tmp/build, log
+With the above settings build objects are saved in the /tmp/build,
-files are saved in the /tmp/log and the source tree remains clean during
+log files are saved in the /tmp/log and the source tree remains clean
-the whole build process.
+during the whole build process.
 
 
 See also "U-Boot Porting Guide" below.
@@ -2623,11 +2755,33 @@ Some configuration options can be set using Environment Variables:
 
   bootfile	- Name of the image to load with TFTP
 
+  bootm_low	- Memory range available for image processing in the bootm
+		  command can be restricted. This variable is given as
+		  a hexadecimal number and defines lowest address allowed
+		  for use by the bootm command. See also "bootm_size"
+		  environment variable. Address defined by "bootm_low" is
+		  also the base of the initial memory mapping for the Linux
+		  kernel -- see the descripton of CFG_BOOTMAPSZ.
+
+  bootm_size	- Memory range available for image processing in the bootm
+		  command can be restricted. This variable is given as
+		  a hexadecimal number and defines the size of the region
+		  allowed for use by the bootm command. See also "bootm_low"
+		  environment variable.
+
   autoload	- if set to "no" (any string beginning with 'n'),
 		  "bootp" will just load perform a lookup of the
 		  configuration from the BOOTP server, but not try to
 		  load any image using TFTP
 
+  autoscript	- if set to "yes" commands like "loadb", "loady",
+		  "bootp", "tftpb", "rarpboot" and "nfs" will attempt
+		  to automatically run script images (by internally
+		  calling "autoscript").
+
+  autoscript_uname - if script image is in a format (FIT) this
+		     variable is used to get script subimage unit name.
+
   autostart	- if set to "yes", an image loaded using the "bootp",
 		  "rarpboot", "tftpboot" or "diskboot" commands will
 		  be automatically started (by internally calling
@@ -2842,10 +2996,24 @@ o If neither SROM nor the environment contain a MAC address, an error
 Image Formats:
 ==============
 
-The "boot" commands of this monitor operate on "image" files which
+U-Boot is capable of booting (and performing other auxiliary operations on)
-can be basicly anything, preceeded by a special header; see the
+images in two formats:
-definitions in include/image.h for details; basicly, the header
+
-defines the following image properties:
+New uImage format (FIT)
+-----------------------
+
+Flexible and powerful format based on Flattened Image Tree -- FIT (similar
+to Flattened Device Tree). It allows the use of images with multiple
+components (several kernels, ramdisks, etc.), with contents protected by
+SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
+
+
+Old uImage format
+-----------------
+
+Old image format is based on binary files which can be basically anything,
+preceded by a special header; see the definitions in include/image.h for
+details; basically, the header defines the following image properties:
 
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
@@ -3087,7 +3255,7 @@ TQM8xxL is in the first Flash bank):
 
 
 You can check the success of the download using the 'iminfo' command;
-this includes a checksum verification so you  can  be  sure  no	 data
+this includes a checksum verification so you can be sure no data
 corruption happened:
 
 	=> imi 40100000
@@ -3432,7 +3600,7 @@ models provide on-chip memory (like the IMMR area on MPC8xx and
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 
-	Chris Hallinan posted a good summary of	 these	issues	to  the
+	Chris Hallinan posted a good summary of these issues to the
 	u-boot-users mailing list:
 
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
@@ -3722,6 +3890,8 @@ may be rejected, even when they contain important and valuable stuff.
 
 Patches shall be sent to the u-boot-users mailing list.
 
+Please see http://www.denx.de/wiki/UBoot/Patches for details.
+
 When you send a patch, please include the following information with
 it:
 
@@ -3742,18 +3912,23 @@ it:
 * If your patch adds new configuration options, don't forget to
   document these in the README file.
 
-* The patch itself. If you are accessing the CVS repository use "cvs
+* The patch itself. If you are using git (which is *strongly*
-  update; cvs diff -puRN"; else, use "diff -purN OLD NEW". If your
+  recommended) you can easily generate the patch using the
-  version of diff does not support these options, then get the latest
+  "git-format-patch". If you then use "git-send-email" to send it to
-  version of GNU diff.
+  the U-Boot mailing list, you will avoid most of the common problems
+  with some other mail clients.
 
-  The current directory when running this command shall be the top
+  If you cannot use git, use "diff -purN OLD NEW". If your version of
-  level directory of the U-Boot source tree, or it's parent directory
+  diff does not support these options, then get the latest version of
-  (i. e. please make sure that your patch includes sufficient
+  GNU diff.
-  directory information for the affected files).
 
-  We accept patches as plain text, MIME attachments or as uuencoded
+  The current directory when running this command shall be the parent
-  gzipped text.
+  directory of the U-Boot source tree (i. e. please make sure that
+  your patch includes sufficient directory information for the
+  affected files).
+
+  We prefer patches as plain text. MIME attachments are discouraged,
+  and compressed attachments must not be used.
 
 * If one logical set of modifications affects or creates several
   files, all these changes shall be submitted in a SINGLE patch file.
@@ -3780,4 +3955,6 @@ Notes:
   modification.
 
 * Remember that there is a size limit of 40 kB per message on the
-  u-boot-users mailing list. Compression may help.
+  u-boot-users mailing list. Bigger patches will be moderated. If
+  they are reasonable and not bigger than 100 kB, they will be
+  acknowledged. Even bigger patches should be avoided.

api/api.c

@@ -30,6 +30,7 @@
 #include <command.h>
 #include <common.h>
 #include <malloc.h>
+#include <environment.h>
 #include <linux/types.h>
 #include <api_public.h>
 
@@ -40,8 +41,6 @@
 
 /* U-Boot routines needed */
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
-extern uchar (*env_get_char)(int);
-extern uchar *env_get_addr(int);
 
 /*****************************************************************************
  *
@@ -583,7 +582,7 @@ int syscall(int call, int *retval, ...)
 	va_list	ap;
 	int rv;
 
-	if (call < 0 || call >= calls_no || calls_table[call] == NULL) {
+	if (call < 0 || call >= calls_no) {
 		debugf("invalid call #%d\n", call);
 		return 0;
 	}

blackfin_config.mk

@@ -21,12 +21,19 @@
 # MA 02111-1307 USA
 #
 
+CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
+CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
+
 PLATFORM_RELFLAGS += -ffixed-P5
 PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
 
+ifneq (,$(CONFIG_BFIN_CPU))
+PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
+endif
+
 SYM_PREFIX = _
 
 LDR_FLAGS += --use-vmas
-ifeq (,$(findstring s,$(MAKEFLAGS)))
+ifneq (,$(findstring s,$(MAKEFLAGS)))
 LDR_FLAGS += --quiet
 endif

board/BuS/EB+MCF-EV123/config.mk

@@ -22,7 +22,7 @@
 # MA 02111-1307 USA
 #
 
-sinclude $(TOPDIR)/board/$(BOARDDIR)/textbase.mk
+sinclude $(OBJTREE)/board/$(BOARDDIR)/textbase.mk
 ifndef TEXT_BASE
 TEXT_BASE = 0xFE000000
 endif

board/BuS/EB+MCF-EV123/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(m68k)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/LEOX/elpt860/u-boot.lds

@@ -31,7 +31,6 @@
 */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/LEOX/elpt860/u-boot.lds.debug

@@ -31,7 +31,6 @@
 */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/MAI/AmigaOneG3SE/u-boot.lds

@@ -29,7 +29,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/Marvell/db64360/u-boot.lds

@@ -26,7 +26,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/Marvell/db64460/u-boot.lds

@@ -26,7 +26,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/MigoR/Makefile

@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= migo_r.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/MigoR/config.mk

@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000

board/MigoR/lowlevel_init.S

@@ -0,0 +1,264 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+/*
+ *  Board specific low level init code, called _very_ early in the
+ *  startup sequence. Relocation to SDRAM has not happened yet, no
+ *  stack is available, bss section has not been initialised, etc.
+ *
+ *  (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	mov.l	CCR_A, r1	! Address of Cache Control Register
+	mov.l	CCR_D, r0	! Instruction Cache Invalidate
+	mov.l	r0, @r1
+
+	mov.l	MMUCR_A, r1	! Address of MMU Control Register
+	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
+	mov.l	r0, @r1
+
+	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
+	mov.l	MSTPCR0_D, r0	!
+	mov.l	r0, @r1
+
+	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
+	mov.l	MSTPCR2_D, r0	!
+	mov.l	r0, @r1
+
+	mov.l	PFC_PULCR_A, r1
+	mov.w	PFC_PULCR_D, r0
+	mov.w	r0,@r1
+
+	mov.l	PFC_DRVCR_A, r1
+	mov.w	PFC_DRVCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	SBSCR_A, r1	!
+	mov.w	SBSCR_D, r0	!
+	mov.w	r0, @r1
+
+	mov.l	PSCR_A, r1	!
+	mov.w	PSCR_D, r0	!
+	mov.w	r0, @r1
+
+	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
+	mov.w	r0, @r1
+
+	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
+	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
+	mov.w	r0, @r1
+
+	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
+	mov.w	r0, @r1
+
+	mov.l	DLLFRQ_A, r1	! 20080115
+	mov.l	DLLFRQ_D, r0 	! 20080115
+	mov.l	r0, @r1
+
+	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
+	mov.l	FRQCR_D, r0	! 20080115
+	mov.l	r0, @r1
+
+	mov.l	CCR_A, r1		! Address of Cache Control Register
+	mov.l	CCR_D_2, r0	! ??
+	mov.l	r0, @r1
+
+bsc_init:
+	mov.l	CMNCR_A, r1	! CMNCR address -> R1
+	mov.l 	CMNCR_D, r0	! CMNCR data    -> R0
+	mov.l	r0, @r1		! CMNCR set
+
+	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
+	mov.l 	CS0BCR_D, r0	! CS0BCR data    -> R0
+	mov.l	r0, @r1		! CS0BCR set
+
+	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
+	mov.l	CS4BCR_D, r0	! CS4BCR data    -> R0
+	mov.l	r0, @r1		! CS4BCR set
+
+	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
+	mov.l 	CS5ABCR_D, r0	! CS5ABCR data    -> R0
+	mov.l	r0, @r1		! CS5ABCR set
+
+	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
+	mov.l 	CS5BBCR_D, r0	! CS5BBCR data    -> R0
+	mov.l	r0, @r1		! CS5BBCR set
+
+	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
+	mov.l 	CS6ABCR_D, r0	! CS6ABCR data    -> R0
+	mov.l	r0, @r1		! CS6ABCR set
+
+	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
+	mov.l 	CS0WCR_D, r0	! CS0WCR data    -> R0
+	mov.l	r0, @r1		! CS0WCR set
+
+	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
+	mov.l 	CS4WCR_D, r0	! CS4WCR data    -> R0
+	mov.l	r0, @r1		! CS4WCR set
+
+	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
+	mov.l 	CS5AWCR_D, r0	! CS5AWCR data    -> R0
+	mov.l	r0, @r1		! CS5AWCR set
+
+	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
+	mov.l 	CS5BWCR_D, r0	! CS5BWCR data    -> R0
+	mov.l	r0, @r1		! CS5BWCR set
+
+	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
+	mov.l 	CS6AWCR_D, r0	! CS6AWCR data    -> R0
+	mov.l	r0, @r1		! CS6AWCR set
+
+	! SDRAM initialization
+	mov.l	SDCR_A, r1	! SB_SDCR address -> R1
+	mov.l	SDCR_D, r0	! SB_SDCR data    -> R0
+	mov.l	r0, @r1		! SB_SDCR set
+
+	mov.l	SDWCR_A, r1	! SB_SDWCR address -> R1
+	mov.l	SDWCR_D, r0	! SB_SDWCR data    -> R0
+	mov.l	r0, @r1		! SB_SDWCR set
+
+	mov.l	SDPCR_A, r1	! SB_SDPCR address -> R1
+	mov.l	SDPCR_D, r0	! SB_SDPCR data    -> R0
+	mov.l	r0, @r1		! SB_SDPCR set
+
+	mov.l	RTCOR_A, r1	! SB_RTCOR address -> R1
+	mov.l	RTCOR_D, r0	! SB_RTCOR data    -> R0
+	mov.l	r0, @r1		! SB_RTCOR set
+
+	mov.l	RTCNT_A, r1	! SB_RTCNT address -> R1
+	mov.l	RTCNT_D, r0	! SB_RTCNT data    -> R0
+	mov.l	r0, @r1
+
+	mov.l	RTCSR_A, r1	! SB_RTCSR address -> R1
+	mov.l	RTCSR_D, r0	! SB_RTCSR data    -> R0
+	mov.l	r0, @r1		! SB_RTCSR set
+
+	mov.l	RFCR_A, r1	! SB_RFCR address -> R1
+	mov.l	RFCR_D, r0	! SB_RFCR data    -> R0
+	mov.l	r0, @r1
+
+	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
+	mov 	#0x00, r0	! SDMR3 data    -> R0
+	mov.b	r0, @r1		! SDMR3 set
+
+	! BL bit off (init = ON)  (?!?)
+
+	stc	sr, r0				! BL bit off(init=ON)
+	mov.l	SR_MASK_D, r1
+	and	r1, r0
+	ldc	r0, sr
+
+	rts
+	mov	#0, r0
+
+	.align	4
+
+CCR_A:		.long	CCR
+MMUCR_A:	.long	MMUCR
+MSTPCR0_A:	.long	MSTPCR0
+MSTPCR2_A:	.long	MSTPCR2
+PFC_PULCR_A:	.long	PULCR
+PFC_DRVCR_A:	.long	DRVCR
+SBSCR_A:	.long	SBSCR
+PSCR_A:		.long	PSCR
+RWTCSR_A:	.long	RWTCSR
+RWTCNT_A:	.long	RWTCNT
+FRQCR_A:	.long	FRQCR
+PLLCR_A:	.long	PLLCR
+DLLFRQ_A:	.long	DLLFRQ
+
+CCR_D:		.long	0x00000800
+CCR_D_2:	.long	0x00000103
+MMUCR_D:	.long	0x00000004
+MSTPCR0_D:	.long	0x00001001
+MSTPCR2_D:	.long	0xffffffff
+PFC_PULCR_D:	.long	0x6000
+PFC_DRVCR_D:	.long	0x0464
+FRQCR_D:	.long	0x07033639
+PLLCR_D:	.long	0x00005000
+DLLFRQ_D:	.long	0x000004F6	! 20080115
+
+CMNCR_A:	.long	CMNCR
+CMNCR_D:	.long	0x0000001B	! 20080115
+CS0BCR_A:	.long	CS0BCR		! Flash bank 1
+CS0BCR_D:	.long	0x24920400
+CS4BCR_A:	.long	CS4BCR		!
+CS4BCR_D:	.long	0x10003400	! 20080115
+CS5ABCR_A:	.long	CS5ABCR		!
+CS5ABCR_D:	.long	0x24920400
+CS5BBCR_A:	.long	CS5BBCR		!
+CS5BBCR_D:	.long	0x24920400
+CS6ABCR_A:	.long	CS6ABCR		!
+CS6ABCR_D:	.long	0x24920400
+
+CS0WCR_A:	.long	CS0WCR
+CS0WCR_D:	.long	0x00000380
+CS4WCR_A:	.long	CS4WCR
+CS4WCR_D:	.long	0x00100A81	! 20080115
+CS5AWCR_A:	.long	CS5AWCR
+CS5AWCR_D:	.long	0x00000300
+CS5BWCR_A:	.long	CS5BWCR
+CS5BWCR_D:	.long	0x00000300
+CS6AWCR_A:	.long	CS6AWCR
+CS6AWCR_D:	.long	0x00000300
+
+SDCR_A:		.long	SBSC_SDCR
+SDCR_D:		.long	0x80160809	! 20080115
+SDWCR_A:	.long	SBSC_SDWCR
+SDWCR_D:	.long	0x0014450C	! 20080115
+SDPCR_A:	.long	SBSC_SDPCR
+SDPCR_D:	.long	0x00000087
+RTCOR_A:	.long	SBSC_RTCOR
+RTCNT_A:	.long	SBSC_RTCNT
+RTCNT_D:	.long	0xA55A0012
+RTCOR_D:	.long	0xA55A001C	! 20080115
+RTCSR_A:	.long	SBSC_RTCSR
+RFCR_A:		.long	SBSC_RFCR
+RFCR_D:		.long	0xA55A0221
+RTCSR_D:	.long	0xA55A009a	! 20080115
+SDMR3_A:	.long	0xFE581180	! 20080115
+
+SR_MASK_D:	.long	0xEFFFFF0F
+
+	.align	2
+
+SBSCR_D:	.word	0x0044
+PSCR_D:		.word	0x0000
+RWTCSR_D_1:	.word	0xA507
+RWTCSR_D_2:	.word	0xA504		! 20080115
+RWTCNT_D:	.word	0x5A00

board/MigoR/migo_r.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/migo_r.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas MigoR\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+}

board/MigoR/u-boot.lds

@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+
+	*/
+	. = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}

board/RPXClassic/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/RPXClassic/u-boot.lds.debug

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/RPXlite/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/RPXlite/u-boot.lds.debug

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/RPXlite_dw/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/RPXlite_dw/u-boot.lds.debug

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/RRvision/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/adder/adder.c

@@ -26,6 +26,9 @@
 
 #include <common.h>
 #include <mpc8xx.h>
+#if defined(CONFIG_OF_LIBFDT)
+	#include <libfdt.h>
+#endif
 
 /*
  * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
@@ -111,3 +114,11 @@ int checkboard( void )
 
 	return 0;
 }
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+}
+#endif

board/amcc/acadia/config.mk

@@ -28,7 +28,7 @@
 sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
 
 ifndef TEXT_BASE
-TEXT_BASE = 0xFFFC0000
+TEXT_BASE = 0xFFF80000
 endif
 
 ifeq ($(debug),1)

board/amcc/acadia/u-boot-nand.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */

board/amcc/acadia/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/bamboo/u-boot-nand.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */

board/amcc/bamboo/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/bubinga/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/canyonlands/Makefile

@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+COBJS	+= bootstrap.o
+SOBJS	:= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/amcc/canyonlands/bootstrap.c

@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+/*
+ * NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The
+ * values are independent of the rest of the clock settings.
+ */
+
+#define NAND_COMPATIBLE	0x01
+#define NOR_COMPATIBLE  0x02
+
+#define I2C_EEPROM_ADDR 0x52
+
+static char *config_labels[] = {
+	"CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+	"CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+	NULL
+};
+
+static u8 boot_configs[][17] = {
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08,
+		0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08,
+		0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+	}
+};
+
+/*
+ * Bytes 5,6,8,9,11 change for NAND boot
+ */
+#if 0
+/*
+ * Values for 512 page size NAND chips, not used anymore, just
+ * keep them here for reference
+ */
+static u8 nand_boot[] = {
+	0x90, 0x01,  0xa0, 0x68, 0x58
+};
+#else
+/*
+ * Values for 2k page size NAND chips
+ */
+static u8 nand_boot[] = {
+	0x90, 0x01,  0xa0, 0xe8, 0x58
+};
+#endif
+
+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u8 *buf, b_nand;
+	int x, y, nbytes, selcfg;
+	extern char console_buffer[];
+
+	if (argc < 2) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if ((strcmp(argv[1], "nor") != 0) &&
+	    (strcmp(argv[1], "nand") != 0)) {
+		printf("Unsupported boot-device - only nor|nand support\n");
+		return 1;
+	}
+
+	/* set the nand flag based on provided input */
+	if ((strcmp(argv[1], "nand") == 0))
+		b_nand = 1;
+	else
+		b_nand = 0;
+
+	printf("Available configurations: \n\n");
+
+	if (b_nand) {
+		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+			/* filter on nand compatible */
+			if (boot_configs[x][0] & NAND_COMPATIBLE) {
+				printf(" %d - %s\n", (y+1), config_labels[x]);
+				y++;
+			}
+		}
+	} else {
+		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+			/* filter on nor compatible */
+			if (boot_configs[x][0] & NOR_COMPATIBLE) {
+				printf(" %d - %s\n", (y+1), config_labels[x]);
+				y++;
+			}
+		}
+	}
+
+	do {
+		nbytes = readline(" Selection [1-x / quit]: ");
+
+		if (nbytes) {
+			if (strcmp(console_buffer, "quit") == 0)
+				return 0;
+			selcfg = simple_strtol(console_buffer, NULL, 10);
+			if ((selcfg < 1) || (selcfg > y))
+				nbytes = 0;
+		}
+	} while (nbytes == 0);
+
+
+	y = (selcfg - 1);
+
+	for (x = 0; boot_configs[x][0] != 0; x++) {
+		if (b_nand) {
+			if (boot_configs[x][0] & NAND_COMPATIBLE) {
+				if (y > 0)
+					y--;
+				else if (y < 1)
+					break;
+			}
+		} else {
+			if (boot_configs[x][0] & NOR_COMPATIBLE) {
+				if (y > 0)
+					y--;
+				else if (y < 1)
+					break;
+			}
+		}
+	}
+
+	buf = &boot_configs[x][1];
+
+	if (b_nand) {
+		buf[5] = nand_boot[0];
+		buf[6] = nand_boot[1];
+		buf[8] = nand_boot[2];
+		buf[9] = nand_boot[3];
+		buf[11] = nand_boot[4];
+	}
+
+	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
+		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
+	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+
+	printf("Done\n");
+	printf("Please power-cycle the board for the changes to take effect\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bootstrap,	2,	0,	do_bootstrap,
+	"bootstrap - program the I2C bootstrap EEPROM\n",
+	"<nand|nor> - strap to boot from NAND or NOR flash\n"
+	);

board/amcc/canyonlands/canyonlands.c

@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/gpio.h>
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CFG_BCSR3_PCIE		0x10
+
+#define BOARD_CANYONLANDS_PCIE	1
+#define BOARD_CANYONLANDS_SATA	2
+#define BOARD_GLACIER		3
+
+int board_early_init_f(void)
+{
+	u32 sdr0_cust0;
+	u32 pvr = get_pvr();
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(uic2er, 0x00000000);	/* disable all */
+	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic3sr, 0xffffffff);	/* clear all */
+	mtdcr(uic3er, 0x00000000);	/* disable all */
+	mtdcr(uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic3pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic3tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic3sr, 0xffffffff);	/* clear all */
+
+	/* SDR Setting - enable NDFC */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
+		(0x80000000 >> (28 + CFG_NAND_CS));
+	mtsdr(SDR0_CUST0, sdr0_cust0);
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * UART0: 4 pins
+	 */
+	mtsdr(SDR0_PFC1, 0x00040000);
+
+	/* Enable PCI host functionality in SDR0_PCI0 */
+	mtsdr(SDR0_PCI0, 0xe0000000);
+
+	/* Enable ethernet and take out of reset */
+	out_8((void *)CFG_BCSR_BASE + 6, 0);
+
+	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
+	out_8((void *)CFG_BCSR_BASE + 5, 0);
+
+	/* Enable USB host & USB-OTG */
+	out_8((void *)CFG_BCSR_BASE + 7, 0);
+
+	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
+
+	/* Setup PLB4-AHB bridge based on the system address map */
+	mtdcr(AHB_TOP, 0x8000004B);
+	mtdcr(AHB_BOT, 0x8000004B);
+
+	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
+		/*
+		 * Configure USB-STP pins as alternate and not GPIO
+		 * It seems to be neccessary to configure the STP pins as GPIO
+		 * input at powerup (perhaps while USB reset is asserted). So
+		 * we configure those pins to their "real" function now.
+		 */
+		gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+		gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	}
+
+	return 0;
+}
+
+static void canyonlands_sata_init(int board_type)
+{
+	u32 reg;
+
+	if (board_type == BOARD_CANYONLANDS_SATA) {
+		/* Put SATA in reset */
+		SDR_WRITE(SDR0_SRST1, 0x00020001);
+
+		/* Set the phy for SATA, not PCI-E port 0 */
+		reg = SDR_READ(PESDR0_PHY_CTL_RST);
+		SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
+		reg = SDR_READ(PESDR0_L0CLK);
+		SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
+		SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
+		SDR_WRITE(PESDR0_L0DRV, 0x00000104);
+
+		/* Bring SATA out of reset */
+		SDR_WRITE(SDR0_SRST1, 0x00000000);
+	}
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u32 pvr = get_pvr();
+
+	if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
+		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
+		gd->board_type = BOARD_GLACIER;
+	} else {
+		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
+		if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
+			gd->board_type = BOARD_CANYONLANDS_PCIE;
+		else
+			gd->board_type = BOARD_CANYONLANDS_SATA;
+	}
+
+	switch (gd->board_type) {
+	case BOARD_CANYONLANDS_PCIE:
+	case BOARD_GLACIER:
+		puts(", 2*PCIe");
+		break;
+
+	case BOARD_CANYONLANDS_SATA:
+		puts(", 1*PCIe/1*SATA");
+		break;
+	}
+
+	printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	canyonlands_sata_init(gd->board_type);
+
+	return (0);
+}
+
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+
+#if defined(CONFIG_NAND_U_BOOT)
+/*
+ * NAND booting U-Boot version uses a fixed initialization, since the whole
+ * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
+ * code.
+ */
+long int initdram(int board_type)
+{
+	return CFG_MBYTES_SDRAM << 20;
+}
+#endif
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_KBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	/*
+	 * Disable everything
+	 */
+	out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
+	out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
+	out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
+	out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+
+	/*
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+	 * strapping options to not support sizes such as 128/256 MB.
+	 */
+	out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+	out_le32((void *)PCIX0_PIM0LAH, 0);
+	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out_le32((void *)PCIX0_BAR0, 0);
+
+	/*
+	 * Program the board's subsystem id/vendor id
+	 */
+	out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
+	out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+
+	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI)
+/*
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+	/* Board is always configured as host. */
+	return (1);
+}
+
+static struct pci_controller pcie_hose[2] = {{0},{0}};
+
+void pcie_setup_hoses(int busno)
+{
+	struct pci_controller *hose;
+	int i, bus;
+	int ret = 0;
+	char *env;
+	unsigned int delay;
+	int start;
+
+	/*
+	 * assume we're called after the PCIX hose is initialized, which takes
+	 * bus ID 0 and therefore start numbering PCIe's from 1.
+	 */
+	bus = busno;
+
+	/*
+	 * Canyonlands with SATA enabled has only one PCIe slot
+	 * (2nd one).
+	 */
+	if (gd->board_type == BOARD_CANYONLANDS_SATA)
+		start = 1;
+	else
+		start = 0;
+
+	for (i = start; i <= 1; i++) {
+
+		if (is_end_point(i))
+			ret = ppc4xx_init_pcie_endport(i);
+		else
+			ret = ppc4xx_init_pcie_rootport(i);
+		if (ret) {
+			printf("PCIE%d: initialization as %s failed\n", i,
+			       is_end_point(i) ? "endpoint" : "root-complex");
+			continue;
+		}
+
+		hose = &pcie_hose[i];
+		hose->first_busno = bus;
+		hose->last_busno = bus;
+		hose->current_busno = bus;
+
+		/* setup mem resource */
+		pci_set_region(hose->regions + 0,
+			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+			       CFG_PCIE_MEMSIZE,
+			       PCI_REGION_MEM);
+		hose->region_count = 1;
+		pci_register_hose(hose);
+
+		if (is_end_point(i)) {
+			ppc4xx_setup_pcie_endpoint(hose, i);
+			/*
+			 * Reson for no scanning is endpoint can not generate
+			 * upstream configuration accesses.
+			 */
+		} else {
+			ppc4xx_setup_pcie_rootpoint(hose, i);
+			env = getenv ("pciscandelay");
+			if (env != NULL) {
+				delay = simple_strtoul(env, NULL, 10);
+				if (delay > 5)
+					printf("Warning, expect noticable delay before "
+					       "PCIe scan due to 'pciscandelay' value!\n");
+				mdelay(delay * 1000);
+			}
+
+			/*
+			 * Config access can only go down stream
+			 */
+			hose->last_busno = pci_hose_scan(hose);
+			bus = hose->last_busno + 1;
+		}
+	}
+}
+#endif /* CONFIG_PCI */
+
+int board_early_init_r (void)
+{
+	/*
+	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+	 * boot EBC mapping only supports a maximum of 16MBytes
+	 * (4.ff00.0000 - 4.ffff.ffff).
+	 * To solve this problem, the FLASH has to get remapped to another
+	 * EBC address which accepts bigger regions:
+	 *
+	 * 0xfc00.0000 -> 4.cc00.0000
+	 */
+
+	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
+#else
+	mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
+#endif
+
+	/* Remove TLB entry of boot EBC mapping */
+	remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
+
+	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
+	program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
+		    TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+	 * 0xfc00.0000 is possible
+	 */
+
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 sdr0_srst1 = 0;
+	u32 eth_cfg;
+	u32 pvr = get_pvr();
+
+	/*
+	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+	 * This is board specific, so let's do it here.
+	 */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	/* disable SGMII mode */
+	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+		     SDR0_ETH_CFG_SGMII1_ENABLE |
+		     SDR0_ETH_CFG_SGMII0_ENABLE);
+	/* Set the for 2 RGMII mode */
+	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
+		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	else
+		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	/*
+	 * The AHB Bridge core is held in reset after power-on or reset
+	 * so enable it now
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_AHB;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 val[4];
+	int rc;
+
+	ft_cpu_setup(blob, bd);
+
+	/* Fixup NOR mapping */
+	val[0] = 0;				/* chip select number */
+	val[1] = 0;				/* always 0 */
+	val[2] = CFG_FLASH_BASE_PHYS_L;		/* we fixed up this address */
+	val[3] = gd->bd->bi_flashsize;
+	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+				  val, sizeof(val), 1);
+	if (rc) {
+		printf("Unable to update property NOR mapping, err=%s\n",
+		       fdt_strerror(rc));
+	}
+
+	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
+		/*
+		 * When SATA is selected we need to disable the first PCIe
+		 * node in the device tree, so that Linux doesn't initialize
+		 * it.
+		 */
+		rc = fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCIe node, err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+
+	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
+		/*
+		 * When PCIe is selected we need to disable the SATA
+		 * node in the device tree, so that Linux doesn't initialize
+		 * it.
+		 */
+		rc = fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCIe node, err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

board/amcc/canyonlands/config.mk

@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 460EX/460GT Evaluation Board (Canyonlands) board
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif

board/amcc/canyonlands/init.S

@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+	 * use the speed up boot process. It is patched after relocation to
+	 * enable SA_I
+	 */
+#ifndef CONFIG_NAND_SPL
+	tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+#else
+	tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+#endif
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+#ifdef CFG_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+#endif
+
+	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+
+	/* PCIe UTL register */
+	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+
+	/* TLB-entry for NAND */
+	tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	/* TLB-entry for CPLD */
+	tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+
+	/* TLB-entry for OCM */
+	tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+
+	/* TLB-entry for Local Configuration registers => peripherals */
+	tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	/* AHB: Internal USB Peripherals (USB, SATA) */
+	tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * For NAND booting the first TLB has to be reconfigured to full size
+	 * and with caching disabled after running from RAM!
+	 */
+#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	.globl	reconfig_tlb0
+reconfig_tlb0:
+	sync
+	isync
+	addi	r4,r0,0x0000		/* TLB entry #0 */
+	lis	r5,TLB00@h
+	ori	r5,r5,TLB00@l
+	tlbwe	r5,r4,0x0000		/* Save it out */
+	lis	r5,TLB01@h
+	ori	r5,r5,TLB01@l
+	tlbwe	r5,r4,0x0001		/* Save it out */
+	lis	r5,TLB02@h
+	ori	r5,r5,TLB02@l
+	tlbwe	r5,r4,0x0002		/* Save it out */
+	sync
+	isync
+	blr
+#endif

board/amcc/canyonlands/u-boot-nand.lds

@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    /* Align to next NAND block */
+    . = ALIGN(0x20000);
+    common/environment.o  (.ppcenv)
+    /* Keep some space here for redundant env and potential bad env blocks */
+    . = ALIGN(0x80000);
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}

board/amcc/canyonlands/u-boot.lds

@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amcc/canyonlands/init.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}

board/amcc/ebony/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/katmai/config.mk

@@ -25,7 +25,7 @@
 # AMCC 440SPe Evaluation (Katmai) board
 #
 
-TEXT_BASE = 0xfffc0000
+TEXT_BASE = 0xFFFA0000
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
 

board/amcc/katmai/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/kilauea/init.S

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * Based on code provided from UDTech and AMCC
@@ -64,7 +64,7 @@ ext_bus_cntlr_init:
 	/* SET SDRAM_MB3CF  - Not enabled */
 	mtsdram_as(SDRAM_MB3CF, 0x00000000);
 
-	/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
+	/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
 	mtsdram_as(SDRAM_CLKTR, 0x80000000);
 
 	/* Refresh Time register (0x30) Refresh every 7.8125uS */

board/amcc/kilauea/kilauea.c

@@ -230,14 +230,22 @@ int misc_init_r(void)
 	return 0;
 }
 
-int board_emac_count(void)
+static int is_405exr(void)
 {
 	u32 pvr = get_pvr();
 
+	if (pvr & 0x00000004)
+		return 0;		/* bit 2 set -> 405EX */
+
+	return 1;			/* bit 2 cleared -> 405EXr */
+}
+
+int board_emac_count(void)
+{
 	/*
 	 * 405EXr only has one EMAC interface, 405EX has two
 	 */
-	if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+	if (is_405exr())
 		return 1;
 	else
 		return 2;
@@ -245,12 +253,10 @@ int board_emac_count(void)
 
 static int board_pcie_count(void)
 {
-	u32 pvr = get_pvr();
-
 	/*
 	 * 405EXr only has one EMAC interface, 405EX has two
 	 */
-	if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+	if (is_405exr())
 		return 1;
 	else
 		return 2;
@@ -259,9 +265,8 @@ static int board_pcie_count(void)
 int checkboard (void)
 {
 	char *s = getenv("serial#");
-	u32 pvr = get_pvr();
 
-	if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+	if (is_405exr())
 		printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
 	else
 		printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");

board/amcc/kilauea/u-boot-nand.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */

board/amcc/kilauea/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/luan/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/makalu/init.S

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * Based on code provided from Senao and AMCC
@@ -57,7 +57,7 @@ ext_bus_cntlr_init:
 	/* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
 	mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
 
-	/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
+	/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
 	mtsdram_as(SDRAM_CLKTR,0x80000000);
 
 	/* Refresh Time register (0x30) Refresh every 7.8125uS */

board/amcc/makalu/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/ocotea/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/sequoia/u-boot-nand.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */

board/amcc/sequoia/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/taihu/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/taishan/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/walnut/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/yosemite/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amcc/yosemite/yosemite.c

@@ -26,6 +26,8 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -554,3 +556,24 @@ void board_reset(void)
 	/* give reset to BCSR */
 	*(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
 }
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 val[4];
+	int rc;
+
+	ft_cpu_setup(blob, bd);
+
+	/* Fixup NOR mapping */
+	val[0] = 0;				/* chip select number */
+	val[1] = 0;				/* always 0 */
+	val[2] = gd->bd->bi_flashstart;
+	val[3] = gd->bd->bi_flashsize;
+	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+				  val, sizeof(val), 1);
+	if (rc)
+		printf("Unable to update property NOR mapping, err=%s\n",
+		       fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

board/amcc/yucca/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/amirix/ap1000/u-boot.lds

@@ -22,7 +22,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/atmel/at91cap9adk/Makefile

@@ -1,6 +1,6 @@
 #
 # (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= at91cap9adk.o led.o nand.o
+COBJS-y	+= at91cap9adk.o
+COBJS-y	+= led.o
+COBJS-y	+= partition.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+OBJS    := $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)

board/atmel/at91cap9adk/at91cap9adk.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -23,7 +23,13 @@
  */
 
 #include <common.h>
-#include <asm/arch/AT91CAP9.h>
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/at91cap9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
@@ -40,126 +46,106 @@ DECLARE_GLOBAL_DATA_PTR;
 static void at91cap9_serial_hw_init(void)
 {
 #ifdef CONFIG_USART0
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
+	at91_set_A_periph(AT91_PIN_PA22, 1);		/* TXD0 */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
+	at91_set_A_periph(AT91_PIN_PA23, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
 #endif
 
 #ifdef CONFIG_USART1
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
+	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
+	at91_set_A_periph(AT91_PIN_PD1, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
 #endif
 
 #ifdef CONFIG_USART2
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
+	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
+	at91_set_A_periph(AT91_PIN_PD3, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
 #endif
 
 #ifdef CONFIG_USART3	/* DBGU */
-	AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
+	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
 #endif
-
-
 }
 
 static void at91cap9_nor_hw_init(void)
 {
+	unsigned long csa;
+
 	/* Ensure EBI supply is 3.3V */
-	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 	/* Configure SMC CS0 for parallel flash */
-	AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
+	at91_sys_write(AT91_SMC_SETUP(0),
-				     AT91C_FLASH_NCS_WR_SETUP |
+		       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
-				     AT91C_FLASH_NRD_SETUP |
+		       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
-				     AT91C_FLASH_NCS_RD_SETUP;
+	at91_sys_write(AT91_SMC_PULSE(0),
-
+		       AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
-	AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
+		       AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
-				     AT91C_FLASH_NCS_WR_PULSE |
+	at91_sys_write(AT91_SMC_CYCLE(0),
-				     AT91C_FLASH_NRD_PULSE |
+		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
-				     AT91C_FLASH_NCS_RD_PULSE;
+	at91_sys_write(AT91_SMC_MODE(0),
-
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-	AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
+		       AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
-				     AT91C_FLASH_NRD_CYCLE;
+		       AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
-
-	AT91C_BASE_SMC->SMC_CTRL0 =  AT91C_SMC_READMODE |
-				     AT91C_SMC_WRITEMODE |
-				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
-				     AT91C_SMC_BAT_BYTE_WRITE |
-				     AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
-				     (AT91C_SMC_TDF & (1 << 16));
 }
 
 #ifdef CONFIG_CMD_NAND
 static void at91cap9_nand_hw_init(void)
 {
+	unsigned long csa;
+
 	/* Enable CS3 */
-	AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
+		       AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
+	at91_sys_write(AT91_SMC_SETUP(3),
-				     AT91C_SM_NCS_WR_SETUP |
+		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
-				     AT91C_SM_NRD_SETUP |
+		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
-				     AT91C_SM_NCS_RD_SETUP;
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
+		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
 
-	AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
-				     AT91C_SM_NCS_WR_PULSE |
-				     AT91C_SM_NRD_PULSE |
-				     AT91C_SM_NCS_RD_PULSE;
-
-	AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
-				     AT91C_SM_NRD_CYCLE;
-
-	AT91C_BASE_SMC->SMC_CTRL3 =  AT91C_SMC_READMODE |
-				     AT91C_SMC_WRITEMODE |
-				     AT91C_SMC_NWAITM_NWAIT_DISABLE |
-				     AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
-				     AT91C_SM_TDF;
-
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
 
 	/* RDY/BSY is not connected */
 
 	/* Enable NandFlash */
-	AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
+	at91_set_gpio_output(AT91_PIN_PD15, 1);
-	AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
 }
 #endif
 
 #ifdef CONFIG_HAS_DATAFLASH
 static void at91cap9_spi_hw_init(void)
 {
-	AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
+	at91_set_B_periph(AT91_PIN_PA5, 0);	/* SPI0_NPCS0 */
-				   AT91C_PD1_SPI0_NPCS3D;
-	AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
-				   AT91C_PD1_SPI0_NPCS3D;
 
-	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
+	at91_set_B_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
-	AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
+	at91_set_B_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
-				   AT91C_PA1_SPI0_MOSI |
+	at91_set_B_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
-				   AT91C_PA0_SPI0_MISO |
-				   AT91C_PA3_SPI0_NPCS1 |
-				   AT91C_PA5_SPI0_NPCS0 |
-				   AT91C_PA2_SPI0_SPCK;
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
-				   AT91C_PA4_SPI0_NPCS2A |
-				   AT91C_PA1_SPI0_MOSI |
-				   AT91C_PA0_SPI0_MISO |
-				   AT91C_PA3_SPI0_NPCS1 |
-				   AT91C_PA5_SPI0_NPCS0 |
-				   AT91C_PA2_SPI0_SPCK;
 
-	/* Enable Clock */
+	/* Enable clock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void at91cap9_macb_hw_init(void)
 {
-	unsigned int gpio;
-
 	/* Enable clock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
 
 	/*
 	 * Disable pull-up on:
@@ -169,54 +155,59 @@ static void at91cap9_macb_hw_init(void)
 	 *
 	 * PHY has internal pull-down
 	 */
-	AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
+	writel(pin_to_mask(AT91_PIN_PB22) |
-				     AT91C_PB25_E_RX0 |
+	       pin_to_mask(AT91_PIN_PB25) |
-				     AT91C_PB26_E_RX1;
+	       pin_to_mask(AT91_PIN_PB26),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 
 	/* Need to reset PHY -> 500ms reset */
-	AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				    (AT91C_RSTC_ERSTL & (0x0D << 8)) |
+				     AT91_RSTC_ERSTL | (0x0D << 8) |
-				    AT91C_RSTC_URSTEN;
+				     AT91_RSTC_URSTEN);
-	AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
+
-				    AT91C_RSTC_EXTRST;
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 
 	/* Wait for end hardware reset */
-	while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 
 	/* Re-enable pull-up */
-	AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
+	writel(pin_to_mask(AT91_PIN_PB22) |
-				     AT91C_PB25_E_RX0 |
+	       pin_to_mask(AT91_PIN_PB25) |
-				     AT91C_PB26_E_RX1;
+	       pin_to_mask(AT91_PIN_PB26),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 
-#ifdef CONFIG_RMII
+	at91_set_A_periph(AT91_PIN_PB21, 0);	/* ETXCK_EREFCK */
-	gpio =	AT91C_PB30_E_MDIO |
+	at91_set_A_periph(AT91_PIN_PB22, 0);	/* ERXDV */
-		AT91C_PB29_E_MDC  |
+	at91_set_A_periph(AT91_PIN_PB25, 0);	/* ERX0 */
-		AT91C_PB21_E_TXCK |
+	at91_set_A_periph(AT91_PIN_PB26, 0);	/* ERX1 */
-		AT91C_PB27_E_RXER |
+	at91_set_A_periph(AT91_PIN_PB27, 0);	/* ERXER */
-		AT91C_PB25_E_RX0  |
+	at91_set_A_periph(AT91_PIN_PB28, 0);	/* ETXEN */
-		AT91C_PB22_E_RXDV |
+	at91_set_A_periph(AT91_PIN_PB23, 0);	/* ETX0 */
-		AT91C_PB26_E_RX1  |
+	at91_set_A_periph(AT91_PIN_PB24, 0);	/* ETX1 */
-		AT91C_PB28_E_TXEN |
+	at91_set_A_periph(AT91_PIN_PB30, 0);	/* EMDIO */
-		AT91C_PB23_E_TX0  |
+	at91_set_A_periph(AT91_PIN_PB29, 0);	/* EMDC */
-		AT91C_PB24_E_TX1;
+
-	AT91C_BASE_PIOB->PIO_ASR = gpio;
+#ifndef CONFIG_RMII
-	AT91C_BASE_PIOB->PIO_BSR = 0;
+	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ECRS */
-	AT91C_BASE_PIOB->PIO_PDR = gpio;
+	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
-#else
+	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
-#error AT91CAP9A-DK works only in RMII mode
+	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
 #endif
-
 	/* Unlock EMAC, 3 0 2 1 sequence */
 #define MP_MAC_KEY0	0x5969cb2a
 #define MP_MAC_KEY1	0xb4a1872e
 #define MP_MAC_KEY2	0x05683fbc
 #define MP_MAC_KEY3	0x3634fba4
 #define UNLOCK_MAC	0x00000008
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
+	writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
+	writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
+	writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
+	writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
+	writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
 }
 #endif
 
@@ -229,11 +220,11 @@ static void at91cap9_uhp_hw_init(void)
 #define MP_OHCI_KEY2	0x4823efbc
 #define MP_OHCI_KEY3	0x8651aae4
 #define UNLOCK_OHCI	0x00000010
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
+	writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
+	writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
+	writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
+	writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
-	*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
+	writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
 }
 #endif
 

board/atmel/at91cap9adk/led.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -23,58 +23,55 @@
  */
 
 #include <common.h>
-#include <asm/arch/AT91CAP9.h>
+#include <asm/arch/at91cap9.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
 
-#define	RED_LED		AT91C_PIO_PC29	/* this is the power led */
+#define	RED_LED		AT91_PIN_PC29	/* this is the power led */
-#define	GREEN_LED	AT91C_PIO_PA10	/* this is the user1 led */
+#define	GREEN_LED	AT91_PIN_PA10	/* this is the user1 led */
-#define	YELLOW_LED	AT91C_PIO_PA11	/* this is the user1 led */
+#define	YELLOW_LED	AT91_PIN_PA11	/* this is the user1 led */
 
 void red_LED_on(void)
 {
-	AT91C_BASE_PIOC->PIO_SODR = RED_LED;
+	at91_set_gpio_value(RED_LED, 1);
 }
 
 void red_LED_off(void)
 {
-	AT91C_BASE_PIOC->PIO_CODR = RED_LED;
+	at91_set_gpio_value(RED_LED, 0);
 }
 
 void green_LED_on(void)
 {
-	AT91C_BASE_PIOA->PIO_CODR = GREEN_LED;
+	at91_set_gpio_value(GREEN_LED, 0);
 }
 
 void green_LED_off(void)
 {
-	AT91C_BASE_PIOA->PIO_SODR = GREEN_LED;
+	at91_set_gpio_value(GREEN_LED, 1);
 }
 
 void yellow_LED_on(void)
 {
-	AT91C_BASE_PIOA->PIO_CODR = YELLOW_LED;
+	at91_set_gpio_value(YELLOW_LED, 0);
 }
 
 void yellow_LED_off(void)
 {
-	AT91C_BASE_PIOA->PIO_SODR = YELLOW_LED;
+	at91_set_gpio_value(YELLOW_LED, 1);
 }
 
 void coloured_LED_init(void)
 {
 	/* Enable clock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
 
-	/* Disable peripherals on LEDs */
+	at91_set_gpio_output(RED_LED, 1);
-	AT91C_BASE_PIOA->PIO_PER = GREEN_LED | YELLOW_LED;
+	at91_set_gpio_output(GREEN_LED, 1);
-	/* Enable pins as outputs */
+	at91_set_gpio_output(YELLOW_LED, 1);
-	AT91C_BASE_PIOA->PIO_OER = GREEN_LED | YELLOW_LED;
-	/* Turn all LEDs OFF */
-	AT91C_BASE_PIOA->PIO_SODR = GREEN_LED | YELLOW_LED;
 
-	/* Disable peripherals on LEDs */
+	at91_set_gpio_output(RED_LED, 0);
-	AT91C_BASE_PIOC->PIO_PER = RED_LED;
+	at91_set_gpio_output(GREEN_LED, 1);
-	/* Enable pins as outputs */
+	at91_set_gpio_output(YELLOW_LED, 1);
-	AT91C_BASE_PIOC->PIO_OER = RED_LED;
-	/* Turn all LEDs OFF */
-	AT91C_BASE_PIOC->PIO_CODR = RED_LED;
 }

board/atmel/at91cap9adk/nand.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
@@ -25,9 +25,9 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/at91cap9.h>
-
+#include <asm/arch/gpio.h>
-#ifdef CONFIG_CMD_NAND
+#include <asm/arch/at91_pio.h>
 
 #include <nand.h>
 
@@ -51,10 +51,10 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 		IO_ADDR_W |= MASK_ALE;
 		break;
 	case NAND_CTL_CLRNCE:
-		AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15;
+		at91_set_gpio_value(AT91_PIN_PD15, 1);
 		break;
 	case NAND_CTL_SETNCE:
-		AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15;
+		at91_set_gpio_value(AT91_PIN_PD15, 0);
 		break;
 	}
 	this->IO_ADDR_W = (void *) IO_ADDR_W;
@@ -68,4 +68,3 @@ int board_nand_init(struct nand_chip *nand)
 
 	return 0;
 }
-#endif

board/atmel/at91cap9adk/partition.c

@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
+	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

board/atmel/at91cap9adk/u-boot.lds

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.

board/atmel/at91rm9200dk/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= at91rm9200dk.o flash.o led.o mux.o
+COBJS	:= at91rm9200dk.o flash.o led.o mux.o partition.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/atmel/at91rm9200dk/partition.c

@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
+	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

board/atmel/at91sam9260ek/Makefile

@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= at91sam9260ek.o
+COBJS-y	+= led.o
+COBJS-y	+= partition.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/atmel/at91sam9260ek/at91sam9260ek.c

@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void at91sam9260ek_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+#endif
+
+#ifdef CONFIG_USART1
+	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PB7, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+#endif
+
+#ifdef CONFIG_USART2
+	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_set_A_periph(AT91_PIN_PB14, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PB15, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9260ek_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(AT91_PIN_PC13, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(AT91_PIN_PC14, 1);
+}
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+static void at91sam9260ek_spi_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA3, 0);	/* SPI0_NPCS0 */
+	at91_set_B_periph(AT91_PIN_PC11, 0);	/* SPI0_NPCS1 */
+
+	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
+	at91_set_A_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
+	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9260ek_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 * 	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0 << 8) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PA23, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PA24, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
+#endif
+
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91SAM9260EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91sam9260ek_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	at91sam9260ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91sam9260ek_spi_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	at91sam9260ek_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif

board/atmel/at91sam9260ek/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000

board/atmel/at91sam9260ek/led.c

@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+#define	RED_LED		AT91_PIN_PA9	/* this is the power led */
+#define	GREEN_LED	AT91_PIN_PA6	/* this is the user led */
+
+void red_LED_on(void)
+{
+	at91_set_gpio_value(RED_LED, 1);
+}
+
+void red_LED_off(void)
+{
+	at91_set_gpio_value(RED_LED, 0);
+}
+
+void green_LED_on(void)
+{
+	at91_set_gpio_value(GREEN_LED, 0);
+}
+
+void green_LED_off(void)
+{
+	at91_set_gpio_value(GREEN_LED, 1);
+}
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
+
+	at91_set_gpio_output(RED_LED, 1);
+	at91_set_gpio_output(GREEN_LED, 1);
+
+	at91_set_gpio_value(RED_LED, 0);
+	at91_set_gpio_value(GREEN_LED, 1);
+}

board/atmel/at91sam9260ek/nand.c

@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+
+#include <nand.h>
+
+/*
+ *	hardware specific access to control-lines
+ */
+#define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
+#define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
+
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		IO_ADDR_W |= MASK_CLE;
+		break;
+	case NAND_CTL_SETALE:
+		IO_ADDR_W |= MASK_ALE;
+		break;
+	case NAND_CTL_CLRNCE:
+		at91_set_gpio_value(AT91_PIN_PC14, 1);
+		break;
+	case NAND_CTL_SETNCE:
+		at91_set_gpio_value(AT91_PIN_PC14, 0);
+		break;
+	}
+	this->IO_ADDR_W = (void *) IO_ADDR_W;
+}
+
+static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
+{
+	return at91_get_gpio_value(AT91_PIN_PC13);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
+	nand->dev_ready = at91sam9260ek_nand_ready;
+	nand->chip_delay = 20;
+
+	return 0;
+}

board/atmel/at91sam9260ek/partition.c

@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
+	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

board/atmel/at91sam9260ek/u-boot.lds

@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/atum8548/tlb.c

@@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * 0xe210_0000	1M	PCI2 IO
 	 * 0xe300_0000	1M	PCIe IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 };

board/atum8548/u-boot.lds

@@ -21,7 +21,6 @@
  */
 
 OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS

board/bf533-ezkit/Makefile

@@ -39,7 +39,7 @@ $(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 u-boot.lds: u-boot.lds.S
-	$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
 	mv -f $@.tmp $@
 
 clean:

board/bf533-ezkit/bf533-ezkit.c

@@ -34,13 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
-#if (BFIN_CPU == ADSP_BF531)
-	printf("CPU:   ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
-#elif (BFIN_CPU == ADSP_BF532)
-	printf("CPU:   ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
-#else
-	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
-#endif
 	printf("Board: ADI BF533 EZ-Kit Lite board\n");
 	printf("       Support: http://blackfin.uclinux.org/\n");
 	return 0;

board/bf533-ezkit/config.mk

@@ -20,6 +20,6 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+
-#  256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+# This is not actually used for Blackfin boards so do not change it
-TEXT_BASE = 0x01FC0000
+#TEXT_BASE = do-not-use-me

board/bf533-ezkit/u-boot.lds.S

@@ -1,7 +1,7 @@
 /*
  * U-boot - u-boot.lds.S
  *
- * Copyright (c) 2005-2007 Analog Device Inc.
+ * Copyright (c) 2005-2008 Analog Device Inc.
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -26,127 +26,113 @@
  */
 
 #include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error.  If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM      CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
 
 OUTPUT_ARCH(bfin)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+
-/* Do we need any of these for elf?
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
-   __DYNAMIC = 0;    */
+MEMORY
+{
+	ram     : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+	l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
+	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
 SECTIONS
 {
-  /* Read-only sections, merged into text segment: */
+	.text :
-  . = + SIZEOF_HEADERS;
+	{
-  .interp : { *(.interp) }
+#ifdef ENV_IS_EMBEDDED
-  .hash          : { *(.hash)		}
+		/* WARNING - the following is hand-optimized to fit within
-  .dynsym        : { *(.dynsym)		}
+		 * the sector before the environment sector. If it throws
-  .dynstr        : { *(.dynstr)		}
+		 * an error during compilation remove an object here to get
-  .rel.text      : { *(.rel.text)	}
+		 * it linked after the configuration sector.
-  .rela.text     : { *(.rela.text) 	}
+		 */
-  .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
-  .rel.got       : { *(.rel.got)	}
-  .rela.got      : { *(.rela.got)	}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)	}
-  .rela.bss      : { *(.rela.bss)	}
-  .rel.plt       : { *(.rel.plt)	}
-  .rela.plt      : { *(.rela.plt)	}
-  .init          : { *(.init)		}
-  .plt : { *(.plt) }
-  . = CFG_MONITOR_BASE;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector before the environment sector. If it throws 	*/
-    /* an error during compilation remove an object here to get	*/
-    /* it linked after the configuration sector.		*/
 
-    cpu/bf533/start.o		(.text)
+		cpu/blackfin/start.o		(.text)
-    cpu/bf533/start1.o		(.text)
+		cpu/blackfin/traps.o		(.text)
-    cpu/bf533/traps.o		(.text)
+		cpu/blackfin/interrupt.o	(.text)
-    cpu/bf533/interrupt.o	(.text)
+		cpu/blackfin/serial.o		(.text)
-    cpu/bf533/serial.o		(.text)
+		common/dlmalloc.o		(.text)
-    common/dlmalloc.o		(.text)
+		lib_generic/crc32.o		(.text)
-/*  lib_blackfin/bf533_string.o	(.text) */
+		lib_generic/zlib.o		(.text)
-/*  lib_generic/vsprintf.o	(.text) */
+		board/bf533-ezkit/bf533-ezkit.o		(.text)
-    lib_generic/crc32.o		(.text)
-    lib_generic/zlib.o		(.text)
-    board/bf533-ezkit/bf533-ezkit.o		(.text)
 
-    . = DEFINED(env_offset) ? env_offset : .;
+		. = DEFINED(env_offset) ? env_offset : .;
-    common/environment.o	(.text)
+		common/environment.o	(.text)
+#endif
 
-    *(.text)
+		*(.text .text.*)
-    *(.fixup)
+	} >ram
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
 
-  /* Read-write section, merged into data segment: */
+	.rodata :
-  . = (. + 0x00FF) & 0xFFFFFF00;
+	{
-  _erotext = .;
+		. = ALIGN(4);
-  PROVIDE (erotext = .);
+		*(.rodata .rodata.*)
-  .reloc   :
+		*(.rodata1)
-  {
+		*(.eh_frame)
-    *(.got)
+		. = ALIGN(4);
-    _GOT2_TABLE_ = .;
+	} >ram
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
 
-  .data    :
+	.data :
-  {
+	{
-    *(.data)
+		. = ALIGN(256);
-    *(.data1)
+		*(.data .data.*)
-    *(.sdata)
+		*(.data1)
-    *(.sdata2)
+		*(.sdata)
-    *(.dynamic)
+		*(.sdata2)
-    CONSTRUCTORS
+		*(.dynamic)
-  }
+		CONSTRUCTORS
-  _edata  =  .;
+	} >ram
-  PROVIDE (edata = .);
 
-  ___u_boot_cmd_start = .;
+	.u_boot_cmd :
-  .u_boot_cmd : { *(.u_boot_cmd) }
+	{
-  ___u_boot_cmd_end = .;
+		___u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		___u_boot_cmd_end = .;
+	} >ram
 
+	.text_l1 :
+	{
+		. = ALIGN(4);
+		__stext_l1 = .;
+		*(.l1.text)
+		. = ALIGN(4);
+		__etext_l1 = .;
+	} >l1_code AT>ram
+	__stext_l1_lma = LOADADDR(.text_l1);
 
-  __start___ex_table = .;
+	.data_l1 :
-  __ex_table : { *(__ex_table) }
+	{
-  __stop___ex_table = .;
+		. = ALIGN(4);
+		__sdata_l1 = .;
+		*(.l1.data)
+		*(.l1.bss)
+		. = ALIGN(4);
+		__edata_l1 = .;
+	} >l1_data AT>ram
+	__sdata_l1_lma = LOADADDR(.data_l1);
 
-  . = ALIGN(256);
+	.bss :
-  __init_begin = .;
+	{
-  .text.init : { *(.text.init) }
+		. = ALIGN(4);
-  .data.init : { *(.data.init) }
+		__bss_start = .;
-  . = ALIGN(256);
+		*(.sbss) *(.scommon)
-  __init_end = .;
+		*(.dynbss)
-
+		*(.bss .bss.*)
-  __bss_start = .;
+		*(COMMON)
-  .bss       :
+		__bss_end = .;
-  {
+	} >ram
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  _end = . ;
-  PROVIDE (end = .);
 }

board/bf533-stamp/Makefile

@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o spi.o
+COBJS	:= $(BOARD).o spi_flash.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
@@ -39,7 +39,7 @@ $(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 u-boot.lds: u-boot.lds.S
-	$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
 	mv -f $@.tmp $@
 
 clean:

board/bf533-stamp/bf533-stamp.c

@@ -43,13 +43,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
-#if (BFIN_CPU == ADSP_BF531)
-	printf("CPU:   ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
-#elif (BFIN_CPU == ADSP_BF532)
-	printf("CPU:   ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
-#else
-	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
-#endif
 	printf("Board: ADI BF533 Stamp board\n");
 	printf("       Support: http://blackfin.uclinux.org/\n");
 	return 0;

board/bf533-stamp/config.mk

@@ -20,6 +20,6 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+
-#  256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+# This is not actually used for Blackfin boards so do not change it
-TEXT_BASE = 0x07FC0000
+#TEXT_BASE = do-not-use-me

board/bf533-stamp/spi.c

@@ -1,474 +0,0 @@
-/****************************************************************************
- *  SPI flash driver for M25P64
- ****************************************************************************/
-#include <common.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/spi.h>
-
-#if defined(CONFIG_SPI)
-
- /*Application definitions */
-
-#define	NUM_SECTORS 	128	/* number of sectors */
-#define SECTOR_SIZE		0x10000
-#define NOP_NUM		1000
-
-#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL)	/*Settings to the SPI_CTL */
-#define TIMOD01 (0x01)		/*stes the SPI to work with core instructions */
-
- /*Flash commands */
-#define SPI_WREN	(0x06)	/*Set Write Enable Latch */
-#define SPI_WRDI	(0x04)	/*Reset Write Enable Latch */
-#define SPI_RDSR	(0x05)	/*Read Status Register */
-#define SPI_WRSR	(0x01)	/*Write Status Register */
-#define SPI_READ	(0x03)	/*Read data from memory */
-#define SPI_PP  	(0x02)	/*Program Data into memory */
-#define SPI_SE  	(0xD8)	/*Erase one sector in memory */
-#define SPI_BE		(0xC7)	/*Erase all memory */
-#define WIP		(0x1)	/*Check the write in progress bit of the SPI status register */
-#define WEL		(0x2)	/*Check the write enable bit of the SPI status register */
-
-#define TIMEOUT 350000000
-
-typedef enum {
-	NO_ERR,
-	POLL_TIMEOUT,
-	INVALID_SECTOR,
-	INVALID_BLOCK,
-} ERROR_CODE;
-
-void spi_init_f(void);
-void spi_init_r(void);
-ssize_t spi_read(uchar *, int, uchar *, int);
-ssize_t spi_write(uchar *, int, uchar *, int);
-
-char ReadStatusRegister(void);
-void Wait_For_SPIF(void);
-void SetupSPI(const int spi_setting);
-void SPI_OFF(void);
-void SendSingleCommand(const int iCommand);
-
-ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
-ERROR_CODE EraseBlock(int nBlock);
-ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
-ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
-ERROR_CODE Wait_For_Status(char Statusbit);
-ERROR_CODE Wait_For_WEL(void);
-
-/* -------------------
- * Variables
- * ------------------- */
-
-/* **************************************************************************
- *
- *  Function:    spi_init_f
- *
- *  Description: Init SPI-Controller (ROM part)
- *
- *  return:      ---
- *
- * *********************************************************************** */
-void spi_init_f(void)
-{
-}
-
-/* **************************************************************************
- *
- *  Function:    spi_init_r
- *
- *  Description: Init SPI-Controller (RAM part) -
- *		 The malloc engine is ready and we can move our buffers to
- *		 normal RAM
- *
- *  return:      ---
- *
- * *********************************************************************** */
-void spi_init_r(void)
-{
-	return;
-}
-
-/****************************************************************************
- *  Function:    spi_write
- **************************************************************************** */
-ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
-{
-	unsigned long offset;
-	int start_block, end_block;
-	int start_byte, end_byte;
-	ERROR_CODE result = NO_ERR;
-	uchar temp[SECTOR_SIZE];
-	int i, num;
-
-	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
-	/* Get the start block number */
-	result = GetSectorNumber(offset, &start_block);
-	if (result == INVALID_SECTOR) {
-		printf("Invalid sector! ");
-		return 0;
-	}
-	/* Get the end block number */
-	result = GetSectorNumber(offset + len - 1, &end_block);
-	if (result == INVALID_SECTOR) {
-		printf("Invalid sector! ");
-		return 0;
-	}
-
-	for (num = start_block; num <= end_block; num++) {
-		ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
-		start_byte = num * SECTOR_SIZE;
-		end_byte = (num + 1) * SECTOR_SIZE - 1;
-		if (start_byte < offset)
-			start_byte = offset;
-		if (end_byte > (offset + len))
-			end_byte = (offset + len - 1);
-		for (i = start_byte; i <= end_byte; i++)
-			temp[i - num * SECTOR_SIZE] = buffer[i - offset];
-		EraseBlock(num);
-		result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
-		if (result != NO_ERR)
-			return 0;
-		printf(".");
-	}
-	return len;
-}
-
-/****************************************************************************
- *  Function:    spi_read
- **************************************************************************** */
-ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
-{
-	unsigned long offset;
-	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
-	ReadData(offset, len, (int *)buffer);
-	return len;
-}
-
-void SendSingleCommand(const int iCommand)
-{
-	unsigned short dummy;
-
-	/*turns on the SPI in single write mode */
-	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
-	/*sends the actual command to the SPI TX register */
-	*pSPI_TDBR = iCommand;
-	SSYNC();
-
-	/*The SPI status register will be polled to check the SPIF bit */
-	Wait_For_SPIF();
-
-	dummy = *pSPI_RDBR;
-
-	/*The SPI will be turned off */
-	SPI_OFF();
-
-}
-
-void SetupSPI(const int spi_setting)
-{
-
-	if (icache_status() || dcache_status())
-		udelay(CONFIG_CCLK_HZ / 50000000);
-	/*sets up the PF2 to be the slave select of the SPI */
-	*pSPI_FLG = 0xFB04;
-	*pSPI_BAUD = CONFIG_SPI_BAUD;
-	*pSPI_CTL = spi_setting;
-	SSYNC();
-}
-
-void SPI_OFF(void)
-{
-
-	*pSPI_CTL = 0x0400;	/* disable SPI */
-	*pSPI_FLG = 0;
-	*pSPI_BAUD = 0;
-	SSYNC();
-	udelay(CONFIG_CCLK_HZ / 50000000);
-
-}
-
-void Wait_For_SPIF(void)
-{
-	unsigned short dummyread;
-	while ((*pSPI_STAT & TXS)) ;
-	while (!(*pSPI_STAT & SPIF)) ;
-	while (!(*pSPI_STAT & RXS)) ;
-	dummyread = *pSPI_RDBR;	/* Read dummy to empty the receive register      */
-
-}
-
-ERROR_CODE Wait_For_WEL(void)
-{
-	int i;
-	char status_register = 0;
-	ERROR_CODE ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
-
-	for (i = 0; i < TIMEOUT; i++) {
-		status_register = ReadStatusRegister();
-		if ((status_register & WEL)) {
-			ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
-			break;
-		}
-		ErrorCode = POLL_TIMEOUT;	/* Time out error */
-	};
-
-	return ErrorCode;
-}
-
-ERROR_CODE Wait_For_Status(char Statusbit)
-{
-	int i;
-	char status_register = 0xFF;
-	ERROR_CODE ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
-
-	for (i = 0; i < TIMEOUT; i++) {
-		status_register = ReadStatusRegister();
-		if (!(status_register & Statusbit)) {
-			ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
-			break;
-		}
-		ErrorCode = POLL_TIMEOUT;	/* Time out error */
-	};
-
-	return ErrorCode;
-}
-
-char ReadStatusRegister(void)
-{
-	char status_register = 0;
-
-	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
-
-	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
-	SSYNC();
-	Wait_For_SPIF();	/*wait until the instruction has been sent */
-	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
-	SSYNC();
-	Wait_For_SPIF();	/*wait until the data has been sent */
-	status_register = *pSPI_RDBR;	/*read the status register */
-
-	SPI_OFF();		/* Turn off the SPI */
-
-	return status_register;
-}
-
-ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
-{
-	int nSector = 0;
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
-		ErrorCode = INVALID_SECTOR;
-		return ErrorCode;
-	}
-
-	nSector = (int)ulOffset / 0x10000;
-	*pnSector = nSector;
-
-	/* ok */
-	return ErrorCode;
-}
-
-ERROR_CODE EraseBlock(int nBlock)
-{
-	unsigned long ulSectorOff = 0x0, ShiftValue;
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	/* if the block is invalid just return */
-	if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
-		ErrorCode = INVALID_BLOCK;	/* tells us if there was an error erasing flash */
-		return ErrorCode;
-	}
-	/* figure out the offset of the block in flash */
-	if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
-		ulSectorOff = (nBlock * SECTOR_SIZE);
-
-	} else {
-		ErrorCode = INVALID_BLOCK;	/* tells us if there was an error erasing flash */
-		return ErrorCode;
-	}
-
-	/* A write enable instruction must previously have been executed */
-	SendSingleCommand(SPI_WREN);
-
-	/*The status register will be polled to check the write enable latch "WREN" */
-	ErrorCode = Wait_For_WEL();
-
-	if (POLL_TIMEOUT == ErrorCode) {
-		printf("SPI Erase block error\n");
-		return ErrorCode;
-	} else
-		/*Turn on the SPI to send single commands */
-		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
-	/* Send the erase block command to the flash followed by the 24 address  */
-	/* to point to the start of a sector. */
-	*pSPI_TDBR = SPI_SE;
-	SSYNC();
-	Wait_For_SPIF();
-	ShiftValue = (ulSectorOff >> 16);	/* Send the highest byte of the 24 bit address at first */
-	*pSPI_TDBR = ShiftValue;
-	SSYNC();
-	Wait_For_SPIF();	/* Wait until the instruction has been sent */
-	ShiftValue = (ulSectorOff >> 8);	/* Send the middle byte of the 24 bit address  at second */
-	*pSPI_TDBR = ShiftValue;
-	SSYNC();
-	Wait_For_SPIF();	/* Wait until the instruction has been sent */
-	*pSPI_TDBR = ulSectorOff;	/* Send the lowest byte of the 24 bit address finally */
-	SSYNC();
-	Wait_For_SPIF();	/* Wait until the instruction has been sent */
-
-	/*Turns off the SPI */
-	SPI_OFF();
-
-	/* Poll the status register to check the Write in Progress bit */
-	/* Sector erase takes time */
-	ErrorCode = Wait_For_Status(WIP);
-
-	/* block erase should be complete */
-	return ErrorCode;
-}
-
-/*****************************************************************************
-* ERROR_CODE ReadData()
-*
-* Read a value from flash for verify purpose
-*
-* Inputs:	unsigned long ulStart - holds the SPI start address
-*			int pnData - pointer to store value read from flash
-*			long lCount - number of elements to read
-***************************************************************************** */
-ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
-{
-	unsigned long ShiftValue;
-	char *cnData;
-	int i;
-
-	cnData = (char *)pnData;	/* Pointer cast to be able to increment byte wise */
-
-	/* Start SPI interface   */
-	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
-	*pSPI_TDBR = SPI_READ;	/* Send the read command to SPI device */
-	SSYNC();
-	Wait_For_SPIF();	/* Wait until the instruction has been sent */
-	ShiftValue = (ulStart >> 16);	/* Send the highest byte of the 24 bit address at first */
-	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
-	SSYNC();
-	Wait_For_SPIF();	/* Wait until the instruction has been sent */
-	ShiftValue = (ulStart >> 8);	/* Send the middle byte of the 24 bit address  at second */
-	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
-	SSYNC();
-	Wait_For_SPIF();	/* Wait until the instruction has been sent */
-	*pSPI_TDBR = ulStart;	/* Send the lowest byte of the 24 bit address finally */
-	SSYNC();
-	Wait_For_SPIF();	/* Wait until the instruction has been sent */
-
-	/* After the SPI device address has been placed on the MOSI pin the data can be */
-	/* received on the MISO pin. */
-	for (i = 0; i < lCount; i++) {
-		*pSPI_TDBR = 0;	/*send dummy */
-		SSYNC();
-		while (!(*pSPI_STAT & RXS)) ;
-		*cnData++ = *pSPI_RDBR;	/*read  */
-
-		if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
-			printf(".");
-	}
-
-	SPI_OFF();		/* Turn off the SPI */
-
-	return NO_ERR;
-}
-
-ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
-		      int *iDataSource, long *lWriteCount)
-{
-
-	unsigned long ulWAddr;
-	long lWTransferCount = 0;
-	int i;
-	char iData;
-	char *temp = (char *)iDataSource;
-	ERROR_CODE ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
-
-	/* First, a Write Enable Command must be sent to the SPI. */
-	SendSingleCommand(SPI_WREN);
-
-	/* Second, the SPI Status Register will be tested whether the  */
-	/*         Write Enable Bit has been set.  */
-	ErrorCode = Wait_For_WEL();
-	if (POLL_TIMEOUT == ErrorCode) {
-		printf("SPI Write Time Out\n");
-		return ErrorCode;
-	} else
-		/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
-		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turns the SPI on */
-	*pSPI_TDBR = SPI_PP;
-	SSYNC();
-	Wait_For_SPIF();	/*wait until the instruction has been sent */
-	ulWAddr = (ulStartAddr >> 16);
-	*pSPI_TDBR = ulWAddr;
-	SSYNC();
-	Wait_For_SPIF();	/*wait until the instruction has been sent */
-	ulWAddr = (ulStartAddr >> 8);
-	*pSPI_TDBR = ulWAddr;
-	SSYNC();
-	Wait_For_SPIF();	/*wait until the instruction has been sent */
-	ulWAddr = ulStartAddr;
-	*pSPI_TDBR = ulWAddr;
-	SSYNC();
-	Wait_For_SPIF();	/*wait until the instruction has been sent */
-	/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
-	/* and sent to the SPI device. */
-	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
-		iData = *temp;
-		*pSPI_TDBR = iData;
-		SSYNC();
-		Wait_For_SPIF();	/*wait until the instruction has been sent */
-		temp++;
-	}
-
-	SPI_OFF();		/* Turns the SPI off */
-
-	/* Sixth, the SPI Write in Progress Bit must be toggled to ensure the  */
-	/* programming is done before start of next transfer. */
-	ErrorCode = Wait_For_Status(WIP);
-
-	if (POLL_TIMEOUT == ErrorCode) {
-		printf("SPI Program Time out!\n");
-		return ErrorCode;
-	} else
-
-		*lWriteCount = lWTransferCount;
-
-	return ErrorCode;
-}
-
-ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
-{
-
-	unsigned long ulWStart = ulStart;
-	long lWCount = lCount, lWriteCount;
-	long *pnWriteCount = &lWriteCount;
-
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	while (lWCount != 0) {
-		ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
-
-		/* After each function call of WriteFlash the counter must be adjusted */
-		lWCount -= *pnWriteCount;
-
-		/* Also, both address pointers must be recalculated. */
-		ulWStart += *pnWriteCount;
-		pnData += *pnWriteCount / 4;
-	}
-
-	/* return the appropriate error code */
-	return ErrorCode;
-}
-
-#endif				/* CONFIG_SPI */

board/bf533-stamp/spi_flash.c

@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"

board/bf533-stamp/u-boot.lds.S

@@ -1,7 +1,7 @@
 /*
  * U-boot - u-boot.lds.S
  *
- * Copyright (c) 2005-2007 Analog Device Inc.
+ * Copyright (c) 2005-2008 Analog Device Inc.
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -26,127 +26,111 @@
  */
 
 #include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error.  If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM      CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
 
 OUTPUT_ARCH(bfin)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+
-/* Do we need any of these for elf?
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
-   __DYNAMIC = 0;    */
+MEMORY
+{
+	ram     : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+	l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
+	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
 SECTIONS
 {
-  /* Read-only sections, merged into text segment: */
+	.text :
-  . = + SIZEOF_HEADERS;
+	{
-  .interp : { *(.interp) }
+#ifdef ENV_IS_EMBEDDED
-  .hash          : { *(.hash)		}
+		/* WARNING - the following is hand-optimized to fit within
-  .dynsym        : { *(.dynsym)		}
+		 * the sector before the environment sector. If it throws
-  .dynstr        : { *(.dynstr)		}
+		 * an error during compilation remove an object here to get
-  .rel.text      : { *(.rel.text)	}
+		 * it linked after the configuration sector.
-  .rela.text     : { *(.rela.text) 	}
+		 */
-  .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
-  .rel.got       : { *(.rel.got)	}
-  .rela.got      : { *(.rela.got)	}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)	}
-  .rela.bss      : { *(.rela.bss)	}
-  .rel.plt       : { *(.rel.plt)	}
-  .rela.plt      : { *(.rela.plt)	}
-  .init          : { *(.init)		}
-  .plt : { *(.plt) }
-  . = CFG_MONITOR_BASE;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector before the environment sector. If it throws 	*/
-    /* an error during compilation remove an object here to get	*/
-    /* it linked after the configuration sector.		*/
 
-    cpu/bf533/start.o		(.text)
+		cpu/blackfin/start.o		(.text)
-    cpu/bf533/start1.o		(.text)
+		cpu/blackfin/traps.o		(.text)
-    cpu/bf533/traps.o		(.text)
+		cpu/blackfin/interrupt.o	(.text)
-    cpu/bf533/interrupt.o	(.text)
+		cpu/blackfin/serial.o		(.text)
-    cpu/bf533/serial.o		(.text)
+		common/dlmalloc.o		(.text)
-    common/dlmalloc.o		(.text)
+		lib_generic/crc32.o		(.text)
-/*  lib_blackfin/bf533_string.o	(.text)	*/
-/*  lib_generic/vsprintf.o	(.text) */
-    lib_generic/crc32.o		(.text)
-/*  lib_generic/zlib.o		(.text) */
-/*  board/stamp/stamp.o		(.text) */
 
-    . = DEFINED(env_offset) ? env_offset : .;
+		. = DEFINED(env_offset) ? env_offset : .;
-    common/environment.o	(.text)
+		common/environment.o	(.text)
+#endif
 
-    *(.text)
+		*(.text .text.*)
-    *(.fixup)
+	} >ram
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
 
-  /* Read-write section, merged into data segment: */
+	.rodata :
-  . = (. + 0x00FF) & 0xFFFFFF00;
+	{
-  _erotext = .;
+		. = ALIGN(4);
-  PROVIDE (erotext = .);
+		*(.rodata .rodata.*)
-  .reloc   :
+		*(.rodata1)
-  {
+		*(.eh_frame)
-    *(.got)
+		. = ALIGN(4);
-    _GOT2_TABLE_ = .;
+	} >ram
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
 
-  .data    :
+	.data :
-  {
+	{
-    *(.data)
+		. = ALIGN(256);
-    *(.data1)
+		*(.data .data.*)
-    *(.sdata)
+		*(.data1)
-    *(.sdata2)
+		*(.sdata)
-    *(.dynamic)
+		*(.sdata2)
-    CONSTRUCTORS
+		*(.dynamic)
-  }
+		CONSTRUCTORS
-  _edata  =  .;
+	} >ram
-  PROVIDE (edata = .);
 
-  ___u_boot_cmd_start = .;
+	.u_boot_cmd :
-  .u_boot_cmd : { *(.u_boot_cmd) }
+	{
-  ___u_boot_cmd_end = .;
+		___u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		___u_boot_cmd_end = .;
+	} >ram
 
+	.text_l1 :
+	{
+		. = ALIGN(4);
+		__stext_l1 = .;
+		*(.l1.text)
+		. = ALIGN(4);
+		__etext_l1 = .;
+	} >l1_code AT>ram
+	__stext_l1_lma = LOADADDR(.text_l1);
 
-  __start___ex_table = .;
+	.data_l1 :
-  __ex_table : { *(__ex_table) }
+	{
-  __stop___ex_table = .;
+		. = ALIGN(4);
+		__sdata_l1 = .;
+		*(.l1.data)
+		*(.l1.bss)
+		. = ALIGN(4);
+		__edata_l1 = .;
+	} >l1_data AT>ram
+	__sdata_l1_lma = LOADADDR(.data_l1);
 
-  . = ALIGN(256);
+	.bss :
-  __init_begin = .;
+	{
-  .text.init : { *(.text.init) }
+		. = ALIGN(4);
-  .data.init : { *(.data.init) }
+		__bss_start = .;
-  . = ALIGN(256);
+		*(.sbss) *(.scommon)
-  __init_end = .;
+		*(.dynbss)
-
+		*(.bss .bss.*)
-  __bss_start = .;
+		*(COMMON)
-  .bss       :
+		__bss_end = .;
-  {
+	} >ram
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  _end = . ;
-  PROVIDE (end = .);
 }

board/bf537-stamp/Makefile

@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o flash.o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
+COBJS	:= $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
@@ -39,7 +39,7 @@ $(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 u-boot.lds: u-boot.lds.S
-	$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
 	mv -f $@.tmp $@
 
 clean:

board/bf537-stamp/bf537-stamp.c

@@ -31,7 +31,6 @@
 #include <asm/blackfin.h>
 #include <asm/io.h>
 #include <net.h>
-#include "ether_bf537.h"
 #include <asm/mach-common/bits/bootrom.h>
 
 /**
@@ -54,60 +53,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define POST_WORD_ADDR 0xFF903FFC
 
-/*
- * the bootldr command loads an address, checks to see if there
- *   is a Boot stream that the on-chip BOOTROM can understand,
- *   and loads it via the BOOTROM Callback. It is possible
- *   to also add booting from SPI, or TWI, but this function does
- *   not currently support that.
- */
-int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
-	ulong addr, entry;
-	ulong *data;
-
-	/* Get the address */
-	if (argc < 2) {
-		addr = load_addr;
-	} else {
-		addr = simple_strtoul(argv[1], NULL, 16);
-	}
-
-	/* Check if it is a LDR file */
-	data = (ulong *) addr;
-	if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) {
-		/* We want to boot from FLASH or SDRAM */
-		entry = _BOOTROM_BOOT_DXE_FLASH;
-		printf("## Booting ldr image at 0x%08lx ...\n", addr);
-		if (icache_status())
-			icache_disable();
-		if (dcache_status())
-			dcache_disable();
-
-	      __asm__("R7=%[a];\n" "P0=%[b];\n" "JUMP (P0);\n":
-	      :[a] "d"(addr),[b] "a"(entry)
-	      :"R7", "P0");
-
-	} else {
-		printf("## No ldr image at address 0x%08lx\n", addr);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(bootldr, 2, 0, do_bootldr,
-	   "bootldr - boot ldr image from memory\n",
-	   "[addr]\n         - boot ldr image stored in memory\n");
-
 int checkboard(void)
 {
-#if (BFIN_CPU == ADSP_BF534)
-	printf("CPU:   ADSP BF534 Rev.: 0.%d\n", *pCHIPID >> 28);
-#elif (BFIN_CPU == ADSP_BF536)
-	printf("CPU:   ADSP BF536 Rev.: 0.%d\n", *pCHIPID >> 28);
-#else
-	printf("CPU:   ADSP BF537 Rev.: 0.%d\n", *pCHIPID >> 28);
-#endif
 	printf("Board: ADI BF537 stamp board\n");
 	printf("       Support: http://blackfin.uclinux.org/\n");
 	return 0;
@@ -173,12 +120,10 @@ long int initdram(int board_type)
 /* miscellaneous platform dependent initialisations */
 int misc_init_r(void)
 {
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+#if defined(CONFIG_CMD_NET)
 	char nid[32];
 	unsigned char *pMACaddr = (unsigned char *)0x203F0000;
-	u8 SrcAddr[6] = { 0x02, 0x80, 0xAD, 0x20, 0x31, 0xB8 };
 
-#if defined(CONFIG_CMD_NET)
 	/* The 0xFF check here is to make sure we don't use the address
 	 * in flash if it's simply been erased (aka all 0xFF values) */
 	if (getenv("ethaddr") == NULL && is_valid_ether_addr(pMACaddr)) {
@@ -187,11 +132,7 @@ int misc_init_r(void)
 			pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]);
 		setenv("ethaddr", nid);
 	}
-	if (getenv("ethaddr")) {
-		SetupMacAddr(SrcAddr);
-	}
 #endif
-#endif				/* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */
 
 #if defined(CONFIG_BFIN_IDE)
 #if defined(CONFIG_BFIN_TRUE_IDE)
@@ -214,13 +155,6 @@ int misc_init_r(void)
 #endif				/* CONFIG_MISC_INIT_R */
 
 #ifdef CONFIG_POST
-#if (BFIN_BOOT_MODE != BF537_BYPASS_BOOT)
-/* Using sw10-PF5 as the hotkey */
-int post_hotkeys_pressed(void)
-{
-	return 0;
-}
-#else
 /* Using sw10-PF5 as the hotkey */
 int post_hotkeys_pressed(void)
 {
@@ -253,7 +187,6 @@ int post_hotkeys_pressed(void)
 	}
 }
 #endif
-#endif
 
 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 void post_word_store(ulong a)

board/bf537-stamp/config.mk

@@ -20,6 +20,10 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+
-#  256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+# This is not actually used for Blackfin boards so do not change it
-TEXT_BASE = 0x03FC0000
+#TEXT_BASE = do-not-use-me
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_UART       := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

board/bf537-stamp/flash-defines.h

@@ -1,123 +0,0 @@
-/*
- * U-boot - flash-defines.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __FLASHDEFINES_H__
-#define __FLASHDEFINES_H__
-
-#include <common.h>
-
-#define V_ULONG(a)		(*(volatile unsigned long *)( a ))
-#define V_BYTE(a)		(*(volatile unsigned char *)( a ))
-#define TRUE			0x1
-#define FALSE			0x0
-#define BUFFER_SIZE		0x80000
-#define NO_COMMAND		0
-#define GET_CODES		1
-#define RESET			2
-#define WRITE			3
-#define FILL			4
-#define ERASE_ALL		5
-#define ERASE_SECT		6
-#define READ			7
-#define GET_SECTNUM		8
-#define FLASH_START_L		0x0000
-#define FLASH_START_H		0x2000
-#define FLASH_MAN_ST		2
-#define RESET_VAL		0xF0
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-
-int get_codes(void);
-int poll_toggle_bit(long lOffset);
-void reset_flash(void);
-int erase_flash(void);
-int erase_block_flash(int);
-void unlock_flash(long lOffset);
-int write_data(long lStart, long lCount, uchar * pnData);
-int read_flash(long nOffset, int *pnValue);
-int write_flash(long nOffset, int nValue);
-void get_sector_number(long lOffset, int *pnSector);
-int GetSectorProtectionStatus(flash_info_t * info, int nSector);
-int GetOffset(int nBlock);
-int AFP_NumSectors = 71;
-long AFP_SectorSize2 = 0x10000;
-int AFP_SectorSize1 = 0x2000;
-
-#define NUM_SECTORS		71
-
-#define WRITESEQ1		0x0AAA
-#define WRITESEQ2		0x0554
-#define WRITESEQ3		0x0AAA
-#define WRITESEQ4		0x0AAA
-#define WRITESEQ5		0x0554
-#define WRITESEQ6		0x0AAA
-#define WRITEDATA1		0xaa
-#define WRITEDATA2		0x55
-#define WRITEDATA3		0x80
-#define WRITEDATA4		0xaa
-#define WRITEDATA5		0x55
-#define WRITEDATA6		0x10
-#define PriFlashABegin		0
-#define SecFlashABegin		8
-#define SecFlashBBegin		36
-#define PriFlashAOff		0x0
-#define PriFlashBOff		0x100000
-#define SecFlashAOff		0x10000
-#define SecFlashBOff		0x280000
-#define INVALIDLOCNSTART	0x20270000
-#define INVALIDLOCNEND		0x20280000
-#define BlockEraseVal		0x30
-#define UNLOCKDATA1		0xaa
-#define UNLOCKDATA2		0x55
-#define UNLOCKDATA3		0xa0
-#define GETCODEDATA1		0xaa
-#define GETCODEDATA2		0x55
-#define GETCODEDATA3		0x90
-#define SecFlashASec1Off	0x200000
-#define SecFlashASec2Off	0x204000
-#define SecFlashASec3Off	0x206000
-#define SecFlashASec4Off	0x208000
-#define SecFlashAEndOff		0x210000
-#define SecFlashBSec1Off	0x280000
-#define SecFlashBSec2Off	0x284000
-#define SecFlashBSec3Off	0x286000
-#define SecFlashBSec4Off	0x288000
-#define SecFlashBEndOff		0x290000
-
-#define SECT32			32
-#define SECT33			33
-#define SECT34			34
-#define SECT35			35
-#define SECT36			36
-#define SECT37			37
-#define SECT38			38
-#define SECT39			39
-
-#define FLASH_SUCCESS	0
-#define FLASH_FAIL	-1
-
-#endif

board/bf537-stamp/flash.c

@@ -1,403 +0,0 @@
-/*
- * U-boot - flash.c Flash driver for PSD4256GV
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <malloc.h>
-#include <config.h>
-#include <asm/io.h>
-#include "flash-defines.h"
-
-void flash_reset(void)
-{
-	reset_flash();
-}
-
-unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
-{
-	int id = 0, i = 0;
-	static int FlagDev = 1;
-
-	id = get_codes();
-	if (FlagDev) {
-		FlagDev = 0;
-	}
-	info->flash_id = id;
-	switch (bank_flag) {
-	case 0:
-		for (i = PriFlashABegin; i < SecFlashABegin; i++)
-			info->start[i] = (baseaddr + (i * AFP_SectorSize1));
-		for (i = SecFlashABegin; i < NUM_SECTORS; i++)
-			info->start[i] =
-			    (baseaddr + SecFlashAOff +
-			     ((i - SecFlashABegin) * AFP_SectorSize2));
-		info->size = 0x400000;
-		info->sector_count = NUM_SECTORS;
-		break;
-	case 1:
-		info->start[0] = baseaddr + SecFlashASec1Off;
-		info->start[1] = baseaddr + SecFlashASec2Off;
-		info->start[2] = baseaddr + SecFlashASec3Off;
-		info->start[3] = baseaddr + SecFlashASec4Off;
-		info->size = 0x10000;
-		info->sector_count = 4;
-		break;
-	case 2:
-		info->start[0] = baseaddr + SecFlashBSec1Off;
-		info->start[1] = baseaddr + SecFlashBSec2Off;
-		info->start[2] = baseaddr + SecFlashBSec3Off;
-		info->start[3] = baseaddr + SecFlashBSec4Off;
-		info->size = 0x10000;
-		info->sector_count = 4;
-		break;
-	}
-	return (info->size);
-}
-
-unsigned long flash_init(void)
-{
-	unsigned long size_b;
-	int i;
-
-	size_b = 0;
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	size_b = flash_get_size(CFG_FLASH_BASE, &flash_info[0], 0);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b == 0) {
-		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-		       size_b, size_b >> 20);
-	}
-
-	/* flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */
-	(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
-			    (flash_info[0].start[2] - 1), &flash_info[0]);
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-	(void)flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF,
-			    &flash_info[0]);
-#endif
-
-	return (size_b);
-}
-
-void flash_print_info(flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id) {
-	case (STM_ID_29W320EB & 0xFFFF):
-	case (STM_ID_29W320DB & 0xFFFF):
-		printf("ST Microelectronics ");
-		break;
-	default:
-		printf("Unknown Vendor: (0x%08X) ", info->flash_id);
-		break;
-	}
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-		       info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf("\n");
-	return;
-}
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	int cnt = 0, i;
-	int prot, sect;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!\n",
-		       prot);
-	else
-		printf("\n");
-
-	cnt = s_last - s_first + 1;
-
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-	printf("Erasing Flash locations, Please Wait\n");
-	for (i = s_first; i <= s_last; i++) {
-		if (info->protect[i] == 0) {	/* not protected */
-			if (erase_block_flash(i) < 0) {
-				printf("Error Sector erasing \n");
-				return FLASH_FAIL;
-			}
-		}
-	}
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-	if (cnt == FLASH_TOT_SECT) {
-		printf("Erasing flash, Please Wait \n");
-		if (erase_flash() < 0) {
-			printf("Erasing flash failed \n");
-			return FLASH_FAIL;
-		}
-	} else {
-		printf("Erasing Flash locations, Please Wait\n");
-		for (i = s_first; i <= s_last; i++) {
-			if (info->protect[i] == 0) {	/* not protected */
-				if (erase_block_flash(i) < 0) {
-					printf("Error Sector erasing \n");
-					return FLASH_FAIL;
-				}
-			}
-		}
-	}
-#endif
-	printf("\n");
-	return FLASH_SUCCESS;
-}
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	int d;
-	if (addr % 2) {
-		read_flash(addr - 1 - CFG_FLASH_BASE, &d);
-		d = (int)((d & 0x00FF) | (*src++ << 8));
-		write_data(addr - 1, 2, (uchar *) & d);
-		write_data(addr + 1, cnt - 1, src);
-	} else
-		write_data(addr, cnt, src);
-	return FLASH_SUCCESS;
-}
-
-int write_data(long lStart, long lCount, uchar * pnData)
-{
-	long i = 0;
-	unsigned long ulOffset = lStart - CFG_FLASH_BASE;
-	int d;
-	int nSector = 0;
-	int flag = 0;
-
-	if (lCount % 2) {
-		flag = 1;
-		lCount = lCount - 1;
-	}
-
-	for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
-		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset, &d);
-		if (d != 0xffff) {
-			printf
-			    ("Flash not erased at offset 0x%x Please erase to reprogram \n",
-			     ulOffset);
-			return FLASH_FAIL;
-		}
-		unlock_flash(ulOffset);
-		d = (int)(pnData[i] | pnData[i + 1] << 8);
-		write_flash(ulOffset, d);
-		if (poll_toggle_bit(ulOffset) < 0) {
-			printf("Error programming the flash \n");
-			return FLASH_FAIL;
-		}
-		if ((i > 0) && (!(i % AFP_SectorSize2)))
-			printf(".");
-	}
-	if (flag) {
-		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset, &d);
-		if (d != 0xffff) {
-			printf
-			    ("Flash not erased at offset 0x%x Please erase to reprogram \n",
-			     ulOffset);
-			return FLASH_FAIL;
-		}
-		unlock_flash(ulOffset);
-		d = (int)(pnData[i] | (d & 0xFF00));
-		write_flash(ulOffset, d);
-		if (poll_toggle_bit(ulOffset) < 0) {
-			printf("Error programming the flash \n");
-			return FLASH_FAIL;
-		}
-	}
-	return FLASH_SUCCESS;
-}
-
-int write_flash(long nOffset, int nValue)
-{
-	long addr;
-
-	addr = (CFG_FLASH_BASE + nOffset);
-	*(unsigned volatile short *)addr = nValue;
-	SSYNC();
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-	if (icache_status())
-		udelay(CONFIG_CCLK_HZ / 1000000);
-#endif
-	return FLASH_SUCCESS;
-}
-
-int read_flash(long nOffset, int *pnValue)
-{
-	unsigned short *pFlashAddr =
-	    (unsigned short *)(CFG_FLASH_BASE + nOffset);
-
-	*pnValue = *pFlashAddr;
-
-	return TRUE;
-}
-
-int poll_toggle_bit(long lOffset)
-{
-	unsigned int u1, u2;
-	volatile unsigned long *FB =
-	    (volatile unsigned long *)(CFG_FLASH_BASE + lOffset);
-	while (1) {
-		u1 = *(volatile unsigned short *)FB;
-		u2 = *(volatile unsigned short *)FB;
-		u1 ^= u2;
-		if (!(u1 & 0x0040))
-			break;
-		if (!(u2 & 0x0020))
-			continue;
-		else {
-			u1 = *(volatile unsigned short *)FB;
-			u2 = *(volatile unsigned short *)FB;
-			u1 ^= u2;
-			if (!(u1 & 0x0040))
-				break;
-			else {
-				reset_flash();
-				return FLASH_FAIL;
-			}
-		}
-	}
-	return FLASH_SUCCESS;
-}
-
-void reset_flash(void)
-{
-	write_flash(WRITESEQ1, RESET_VAL);
-	/* Wait for 10 micro seconds */
-	udelay(10);
-}
-
-int erase_flash(void)
-{
-	write_flash(WRITESEQ1, WRITEDATA1);
-	write_flash(WRITESEQ2, WRITEDATA2);
-	write_flash(WRITESEQ3, WRITEDATA3);
-	write_flash(WRITESEQ4, WRITEDATA4);
-	write_flash(WRITESEQ5, WRITEDATA5);
-	write_flash(WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(0x0000) < 0)
-		return FLASH_FAIL;
-
-	return FLASH_SUCCESS;
-}
-
-int erase_block_flash(int nBlock)
-{
-	long ulSectorOff = 0x0;
-
-	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
-		return FALSE;
-
-	/* figure out the offset of the block in flash */
-	if ((nBlock >= 0) && (nBlock < SecFlashABegin))
-		ulSectorOff = nBlock * AFP_SectorSize1;
-
-	else if ((nBlock >= SecFlashABegin) && (nBlock < NUM_SECTORS))
-		ulSectorOff =
-		    SecFlashAOff + (nBlock - SecFlashABegin) * AFP_SectorSize2;
-	/* no such sector */
-	else
-		return FLASH_FAIL;
-
-	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
-	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
-	write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
-	write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
-	write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
-
-	write_flash(ulSectorOff, BlockEraseVal);
-
-	if (poll_toggle_bit(ulSectorOff) < 0)
-		return FLASH_FAIL;
-	printf(".");
-
-	return FLASH_SUCCESS;
-}
-
-void unlock_flash(long ulOffset)
-{
-	unsigned long ulOffsetAddr = ulOffset;
-	ulOffsetAddr &= 0xFFFF0000;
-
-	write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
-	write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
-	write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
-}
-
-int get_codes()
-{
-	int dev_id = 0;
-
-	write_flash(WRITESEQ1, GETCODEDATA1);
-	write_flash(WRITESEQ2, GETCODEDATA2);
-	write_flash(WRITESEQ3, GETCODEDATA3);
-
-	read_flash(0x0402, &dev_id);
-	dev_id &= 0x0000FFFF;
-
-	reset_flash();
-
-	return dev_id;
-}
-
-void get_sector_number(long ulOffset, int *pnSector)
-{
-	int nSector = 0;
-	long lMainEnd = 0x400000;
-	long lBootEnd = 0x10000;
-
-	/* sector numbers for the FLASH A boot sectors */
-	if (ulOffset < lBootEnd) {
-		nSector = (int)ulOffset / AFP_SectorSize1;
-	}
-	/* sector numbers for the FLASH B boot sectors */
-	else if ((ulOffset >= lBootEnd) && (ulOffset < lMainEnd)) {
-		nSector = ((ulOffset / (AFP_SectorSize2)) + 7);
-	}
-	/* if it is a valid sector, set it */
-	if ((nSector >= 0) && (nSector < AFP_NumSectors))
-		*pnSector = nSector;
-
-}

board/bf537-stamp/spi_flash.c

@@ -0,0 +1,815 @@
+/*
+ * SPI flash driver
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* Configuration options:
+ * CONFIG_SPI_BAUD - value to load into SPI_BAUD (divisor of SCLK to get SPI CLK)
+ * CONFIG_SPI_FLASH_SLOW_READ - force usage of the slower read
+ *		WARNING: make sure your SCLK + SPI_BAUD is slow enough
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/mach-common/bits/spi.h>
+
+/* Forcibly phase out these */
+#ifdef CONFIG_SPI_FLASH_NUM_SECTORS
+# error do not set CONFIG_SPI_FLASH_NUM_SECTORS
+#endif
+#ifdef CONFIG_SPI_FLASH_SECTOR_SIZE
+# error do not set CONFIG_SPI_FLASH_SECTOR_SIZE
+#endif
+
+#if defined(CONFIG_SPI)
+
+struct flash_info {
+	char     *name;
+	uint16_t id;
+	unsigned sector_size;
+	unsigned num_sectors;
+};
+
+/* SPI Speeds: 50 MHz / 33 MHz */
+static struct flash_info flash_spansion_serial_flash[] = {
+	{ "S25FL016", 0x0215, 64 * 1024, 32 },
+	{ "S25FL032", 0x0216, 64 * 1024, 64 },
+	{ "S25FL064", 0x0217, 64 * 1024, 128 },
+	{ "S25FL0128", 0x0218, 256 * 1024, 64 },
+	{ NULL, 0, 0, 0 }
+};
+
+/* SPI Speeds: 50 MHz / 20 MHz */
+static struct flash_info flash_st_serial_flash[] = {
+	{ "m25p05", 0x2010, 32 * 1024, 2 },
+	{ "m25p10", 0x2011, 32 * 1024, 4 },
+	{ "m25p20", 0x2012, 64 * 1024, 4 },
+	{ "m25p40", 0x2013, 64 * 1024, 8 },
+	{ "m25p16", 0x2015, 64 * 1024, 32 },
+	{ "m25p32", 0x2016, 64 * 1024, 64 },
+	{ "m25p64", 0x2017, 64 * 1024, 128 },
+	{ "m25p128", 0x2018, 256 * 1024, 64 },
+	{ NULL, 0, 0, 0 }
+};
+
+/* SPI Speeds: 66 MHz / 33 MHz */
+static struct flash_info flash_atmel_dataflash[] = {
+	{ "AT45DB011x", 0x0c, 264, 512 },
+	{ "AT45DB021x", 0x14, 264, 1025 },
+	{ "AT45DB041x", 0x1c, 264, 2048 },
+	{ "AT45DB081x", 0x24, 264, 4096 },
+	{ "AT45DB161x", 0x2c, 528, 4096 },
+	{ "AT45DB321x", 0x34, 528, 8192 },
+	{ "AT45DB642x", 0x3c, 1056, 8192 },
+	{ NULL, 0, 0, 0 }
+};
+
+/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */
+static struct flash_info flash_winbond_serial_flash[] = {
+	{ "W25X10", 0x3011, 16 * 256, 32 },
+	{ "W25X20", 0x3012, 16 * 256, 64 },
+	{ "W25X40", 0x3013, 16 * 256, 128 },
+	{ "W25X80", 0x3014, 16 * 256, 256 },
+	{ "W25P80", 0x2014, 256 * 256, 16 },
+	{ "W25P16", 0x2015, 256 * 256, 32 },
+	{ NULL, 0, 0, 0 }
+};
+
+struct flash_ops {
+	uint8_t read, write, erase, status;
+};
+
+#ifdef CONFIG_SPI_FLASH_SLOW_READ
+# define OP_READ 0x03
+#else
+# define OP_READ 0x0B
+#endif
+static struct flash_ops flash_st_ops = {
+	.read = OP_READ,
+	.write = 0x02,
+	.erase = 0xD8,
+	.status = 0x05,
+};
+
+static struct flash_ops flash_atmel_ops = {
+	.read = OP_READ,
+	.write = 0x82,
+	.erase = 0x81,
+	.status = 0xD7,
+};
+
+static struct flash_ops flash_winbond_ops = {
+	.read = OP_READ,
+	.write = 0x02,
+	.erase = 0x20,
+	.status = 0x05,
+};
+
+struct manufacturer_info {
+	const char *name;
+	uint8_t id;
+	struct flash_info *flashes;
+	struct flash_ops *ops;
+};
+
+static struct {
+	struct manufacturer_info *manufacturer;
+	struct flash_info *flash;
+	struct flash_ops *ops;
+	uint8_t manufacturer_id, device_id1, device_id2;
+	unsigned int write_length;
+	unsigned long sector_size, num_sectors;
+} flash;
+
+enum {
+	JED_MANU_SPANSION = 0x01,
+	JED_MANU_ST       = 0x20,
+	JED_MANU_ATMEL    = 0x1F,
+	JED_MANU_WINBOND  = 0xEF,
+};
+
+static struct manufacturer_info flash_manufacturers[] = {
+	{
+		.name = "Spansion",
+		.id = JED_MANU_SPANSION,
+		.flashes = flash_spansion_serial_flash,
+		.ops = &flash_st_ops,
+	},
+	{
+		.name = "ST",
+		.id = JED_MANU_ST,
+		.flashes = flash_st_serial_flash,
+		.ops = &flash_st_ops,
+	},
+	{
+		.name = "Atmel",
+		.id = JED_MANU_ATMEL,
+		.flashes = flash_atmel_dataflash,
+		.ops = &flash_atmel_ops,
+	},
+	{
+		.name = "Winbond",
+		.id = JED_MANU_WINBOND,
+		.flashes = flash_winbond_serial_flash,
+		.ops = &flash_winbond_ops,
+	},
+};
+
+#define	TIMEOUT	5000	/* timeout of 5 seconds */
+
+/* BF54x support */
+#ifndef pSPI_CTL
+# define pSPI_CTL  pSPI0_CTL
+# define pSPI_BAUD pSPI0_BAUD
+# define pSPI_FLG  pSPI0_FLG
+# define pSPI_RDBR pSPI0_RDBR
+# define pSPI_STAT pSPI0_STAT
+# define pSPI_TDBR pSPI0_TDBR
+# define SPI0_SCK	0x0001
+# define SPI0_MOSI	0x0004
+# define SPI0_MISO	0x0002
+# define SPI0_SEL1	0x0010
+#endif
+
+/* Default to the SPI SSEL that we boot off of:
+ *	BF54x, BF537, (everything new?): SSEL1
+ *	BF533, BF561: SSEL2
+ */
+#ifndef CONFIG_SPI_FLASH_SSEL
+# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
+     defined(__ADSPBF533__) || defined(__ADSPBF561__)
+#  define CONFIG_SPI_FLASH_SSEL 2
+# else
+#  define CONFIG_SPI_FLASH_SSEL 1
+# endif
+#endif
+#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL)
+
+static void SPI_INIT(void)
+{
+	/* [#3541] This delay appears to be necessary, but not sure
+	 * exactly why as the history behind it is non-existant.
+	 */
+	udelay(CONFIG_CCLK_HZ / 25000000);
+
+	/* enable SPI pins: SSEL, MOSI, MISO, SCK */
+#ifdef __ADSPBF54x__
+	*pPORTE_FER |= (SPI0_SCK | SPI0_MOSI | SPI0_MISO | SPI0_SEL1);
+#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
+	*pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
+#elif defined(__ADSPBF52x__)
+	bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3);
+	bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4);
+#endif
+
+	/* initate communication upon write of TDBR */
+	*pSPI_CTL = (SPE|MSTR|CPHA|CPOL|0x01);
+	*pSPI_BAUD = CONFIG_SPI_BAUD;
+}
+
+static void SPI_DEINIT(void)
+{
+	/* put SPI settings back to reset state */
+	*pSPI_CTL = 0x0400;
+	*pSPI_BAUD = 0;
+	SSYNC();
+}
+
+static void SPI_ON(void)
+{
+	/* toggle SSEL to reset the device so it'll take a new command */
+	*pSPI_FLG = 0xFF00 | SSEL_MASK;
+	SSYNC();
+
+	*pSPI_FLG = ((0xFF & ~SSEL_MASK) << 8) | SSEL_MASK;
+	SSYNC();
+}
+
+static void SPI_OFF(void)
+{
+	/* put SPI settings back to reset state */
+	*pSPI_FLG = 0xFF00;
+	SSYNC();
+}
+
+static uint8_t spi_write_read_byte(uint8_t transmit)
+{
+	*pSPI_TDBR = transmit;
+	SSYNC();
+
+	while ((*pSPI_STAT & TXS))
+		if (ctrlc())
+			break;
+	while (!(*pSPI_STAT & SPIF))
+		if (ctrlc())
+			break;
+	while (!(*pSPI_STAT & RXS))
+		if (ctrlc())
+			break;
+
+	/* Read dummy to empty the receive register */
+	return *pSPI_RDBR;
+}
+
+static uint8_t read_status_register(void)
+{
+	uint8_t status_register;
+
+	/* send instruction to read status register */
+	SPI_ON();
+	spi_write_read_byte(flash.ops->status);
+	/* send dummy to receive the status register */
+	status_register = spi_write_read_byte(0);
+	SPI_OFF();
+
+	return status_register;
+}
+
+static int wait_for_ready_status(void)
+{
+	ulong start = get_timer(0);
+
+	while (get_timer(0) - start < TIMEOUT) {
+		switch (flash.manufacturer_id) {
+		case JED_MANU_SPANSION:
+		case JED_MANU_ST:
+		case JED_MANU_WINBOND:
+			if (!(read_status_register() & 0x01))
+				return 0;
+			break;
+
+		case JED_MANU_ATMEL:
+			if (read_status_register() & 0x80)
+				return 0;
+			break;
+		}
+
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return -1;
+		}
+	}
+
+	puts("Timeout\n");
+	return -1;
+}
+
+/* Request and read the manufacturer and device id of parts which
+ * are compatible with the JEDEC standard (JEP106) and use that to
+ * setup other operating conditions.
+ */
+static int spi_detect_part(void)
+{
+	uint16_t dev_id;
+	size_t i;
+
+	static char called_init;
+	if (called_init)
+		return 0;
+
+	SPI_ON();
+
+	/* Send the request for the part identification */
+	spi_write_read_byte(0x9F);
+
+	/* Now read in the manufacturer id bytes */
+	do {
+		flash.manufacturer_id = spi_write_read_byte(0);
+		if (flash.manufacturer_id == 0x7F)
+			puts("Warning: unhandled manufacturer continuation byte!\n");
+	} while (flash.manufacturer_id == 0x7F);
+
+	/* Now read in the first device id byte */
+	flash.device_id1 = spi_write_read_byte(0);
+
+	/* Now read in the second device id byte */
+	flash.device_id2 = spi_write_read_byte(0);
+
+	SPI_OFF();
+
+	dev_id = (flash.device_id1 << 8) | flash.device_id2;
+
+	for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) {
+		if (flash.manufacturer_id == flash_manufacturers[i].id)
+			break;
+	}
+	if (i == ARRAY_SIZE(flash_manufacturers))
+		goto unknown;
+
+	flash.manufacturer = &flash_manufacturers[i];
+	flash.ops = flash_manufacturers[i].ops;
+
+	switch (flash.manufacturer_id) {
+	case JED_MANU_SPANSION:
+	case JED_MANU_ST:
+	case JED_MANU_WINBOND:
+		for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
+			if (dev_id == flash.manufacturer->flashes[i].id)
+				break;
+		}
+		if (!flash.manufacturer->flashes[i].name)
+			goto unknown;
+
+		flash.flash = &flash.manufacturer->flashes[i];
+		flash.sector_size = flash.flash->sector_size;
+		flash.num_sectors = flash.flash->num_sectors;
+		flash.write_length = 256;
+		break;
+
+	case JED_MANU_ATMEL: {
+		uint8_t status = read_status_register();
+
+		for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
+			if ((status & 0x3c) == flash.manufacturer->flashes[i].id)
+				break;
+		}
+		if (!flash.manufacturer->flashes[i].name)
+			goto unknown;
+
+		flash.flash = &flash.manufacturer->flashes[i];
+		flash.sector_size = flash.flash->sector_size;
+		flash.num_sectors = flash.flash->num_sectors;
+
+		/* see if flash is in "power of 2" mode */
+		if (status & 0x1)
+			flash.sector_size &= ~(1 << (ffs(flash.sector_size) - 1));
+
+		flash.write_length = flash.sector_size;
+		break;
+	}
+	}
+
+	called_init = 1;
+	return 0;
+
+ unknown:
+	printf("Unknown SPI device: 0x%02X 0x%02X 0x%02X\n",
+		flash.manufacturer_id, flash.device_id1, flash.device_id2);
+	return 1;
+}
+
+/*
+ * Function:    spi_init_f
+ * Description: Init SPI-Controller (ROM part)
+ * return:      ---
+ */
+void spi_init_f(void)
+{
+}
+
+/*
+ * Function:    spi_init_r
+ * Description: Init SPI-Controller (RAM part) -
+ *		 The malloc engine is ready and we can move our buffers to
+ *		 normal RAM
+ *  return:      ---
+ */
+void spi_init_r(void)
+{
+#if defined(CONFIG_POST) && (CONFIG_POST & CFG_POST_SPI)
+	/* Our testing strategy here is pretty basic:
+	 *  - fill src memory with an 8-bit pattern
+	 *  - write the src memory to the SPI flash
+	 *  - read the SPI flash into the dst memory
+	 *  - compare src and dst memory regions
+	 *  - repeat a few times
+	 * The variations we test for:
+	 *  - change the 8-bit pattern a bit
+	 *  - change the read/write block size so we know:
+	 *    - writes smaller/equal/larger than the buffer work
+	 *    - writes smaller/equal/larger than the sector work
+	 *  - change the SPI offsets so we know:
+	 *    - writing partial sectors works
+	 */
+	uint8_t *mem_src, *mem_dst;
+	size_t i, c, l, o;
+	size_t test_count, errors;
+	uint8_t pattern;
+
+	SPI_INIT();
+
+	if (spi_detect_part())
+		goto out;
+	eeprom_info();
+
+	ulong lengths[] = {
+		flash.write_length,
+		flash.write_length * 2,
+		flash.write_length / 2,
+		flash.sector_size,
+		flash.sector_size * 2,
+		flash.sector_size / 2
+	};
+	ulong offsets[] = {
+		0,
+		flash.write_length,
+		flash.write_length * 2,
+		flash.write_length / 2,
+		flash.write_length / 4,
+		flash.sector_size,
+		flash.sector_size * 2,
+		flash.sector_size / 2,
+		flash.sector_size / 4,
+	};
+
+	/* the exact addresses are arbitrary ... they just need to not overlap */
+	mem_src = (void *)(0);
+	mem_dst = (void *)(max(flash.write_length, flash.sector_size) * 2);
+
+	test_count = 0;
+	errors = 0;
+	pattern = 0x00;
+
+	for (i = 0; i < 16; ++i) {	/* 16 = 8 bits * 2 iterations */
+		for (l = 0; l < ARRAY_SIZE(lengths); ++l) {
+			for (o = 0; o < ARRAY_SIZE(offsets); ++o) {
+				ulong len = lengths[l];
+				ulong off = offsets[o];
+
+				printf("Testing pattern 0x%02X of length %5lu and offset %5lu: ", pattern, len, off);
+
+				/* setup the source memory region */
+				memset(mem_src, pattern, len);
+
+				test_count += 4;
+				for (c = 0; c < 4; ++c) {	/* 4 is just a random repeat count */
+					if (ctrlc()) {
+						puts("\nAbort\n");
+						goto out;
+					}
+
+					/* make sure background fill pattern != pattern */
+					memset(mem_dst, pattern ^ 0xFF, len);
+
+					/* write out the source memory and then read it back and compare */
+					eeprom_write(0, off, mem_src, len);
+					eeprom_read(0, off, mem_dst, len);
+
+					if (memcmp(mem_src, mem_dst, len)) {
+						for (c = 0; c < len; ++c)
+							if (mem_src[c] != mem_dst[c])
+								break;
+						printf(" FAIL @ offset %u, skipping repeats ", c);
+						++errors;
+						break;
+					}
+
+					/* XXX: should shrink write region here to test with
+					 * leading/trailing canaries so we know surrounding
+					 * bytes don't get screwed.
+					 */
+				}
+				puts("\n");
+			}
+		}
+
+		/* invert the pattern every other run and shift out bits slowly */
+		pattern ^= 0xFF;
+		if (i % 2)
+			pattern = (pattern | 0x01) << 1;
+	}
+
+	if (errors)
+		printf("SPI FAIL: Out of %i tests, there were %i errors ;(\n", test_count, errors);
+	else
+		printf("SPI PASS: %i tests worked!\n", test_count);
+
+ out:
+	SPI_DEINIT();
+
+#endif
+}
+
+static void transmit_address(uint32_t addr)
+{
+	/* Send the highest byte of the 24 bit address at first */
+	spi_write_read_byte(addr >> 16);
+	/* Send the middle byte of the 24 bit address  at second */
+	spi_write_read_byte(addr >> 8);
+	/* Send the lowest byte of the 24 bit address finally */
+	spi_write_read_byte(addr);
+}
+
+/*
+ * Read a value from flash for verify purpose
+ * Inputs:	unsigned long ulStart - holds the SPI start address
+ *			int pnData - pointer to store value read from flash
+ *			long lCount - number of elements to read
+ */
+static int read_flash(unsigned long address, long count, uchar *buffer)
+{
+	size_t i;
+
+	/* Send the read command to SPI device */
+	SPI_ON();
+	spi_write_read_byte(flash.ops->read);
+	transmit_address(address);
+
+#ifndef CONFIG_SPI_FLASH_SLOW_READ
+	/* Send dummy byte when doing SPI fast reads */
+	spi_write_read_byte(0);
+#endif
+
+	/* After the SPI device address has been placed on the MOSI pin the data can be */
+	/* received on the MISO pin. */
+	for (i = 1; i <= count; ++i) {
+		*buffer++ = spi_write_read_byte(0);
+		if (i % flash.sector_size == 0)
+			puts(".");
+	}
+
+	SPI_OFF();
+
+	return 0;
+}
+
+static int enable_writing(void)
+{
+	ulong start;
+
+	if (flash.manufacturer_id == JED_MANU_ATMEL)
+		return 0;
+
+	/* A write enable instruction must previously have been executed */
+	SPI_ON();
+	spi_write_read_byte(0x06);
+	SPI_OFF();
+
+	/* The status register will be polled to check the write enable latch "WREN" */
+	start = get_timer(0);
+	while (get_timer(0) - start < TIMEOUT) {
+		if (read_status_register() & 0x02)
+			return 0;
+
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return -1;
+		}
+	}
+
+	puts("Timeout\n");
+	return -1;
+}
+
+static long address_to_sector(unsigned long address)
+{
+	if (address > (flash.num_sectors * flash.sector_size) - 1)
+		return -1;
+	return address / flash.sector_size;
+}
+
+static int erase_sector(int address)
+{
+	/* sector gets checked in higher function, so assume it's valid
+	 * here and figure out the offset of the sector in flash
+	 */
+	if (enable_writing())
+		return -1;
+
+	/*
+	 * Send the erase block command to the flash followed by the 24 address
+	 * to point to the start of a sector
+	 */
+	SPI_ON();
+	spi_write_read_byte(flash.ops->erase);
+	transmit_address(address);
+	SPI_OFF();
+
+	return wait_for_ready_status();
+}
+
+/* Write [count] bytes out of [buffer] into the given SPI [address] */
+static long write_flash(unsigned long address, long count, uchar *buffer)
+{
+	long i, write_buffer_size;
+
+	if (enable_writing())
+		return -1;
+
+	/* Send write command followed by the 24 bit address */
+	SPI_ON();
+	spi_write_read_byte(flash.ops->write);
+	transmit_address(address);
+
+	/* Shoot out a single write buffer */
+	write_buffer_size = min(count, flash.write_length);
+	for (i = 0; i < write_buffer_size; ++i)
+		spi_write_read_byte(buffer[i]);
+
+	SPI_OFF();
+
+	/* Wait for the flash to do its thing */
+	if (wait_for_ready_status()) {
+		puts("SPI Program Time out! ");
+		return -1;
+	}
+
+	return i;
+}
+
+/* Write [count] bytes out of [buffer] into the given SPI [address] */
+static int write_sector(unsigned long address, long count, uchar *buffer)
+{
+	long write_cnt;
+
+	while (count != 0) {
+		write_cnt = write_flash(address, count, buffer);
+		if (write_cnt == -1)
+			return -1;
+
+		/* Now that we've sent some bytes out to the flash, update
+		 * our counters a bit
+		 */
+		count -= write_cnt;
+		address += write_cnt;
+		buffer += write_cnt;
+	}
+
+	/* return the appropriate error code */
+	return 0;
+}
+
+/*
+ * Function:    spi_write
+ */
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
+{
+	unsigned long offset;
+	int start_sector, end_sector;
+	int start_byte, end_byte;
+	uchar *temp = NULL;
+	int num, ret = 0;
+
+	SPI_INIT();
+
+	if (spi_detect_part())
+		goto out;
+
+	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+
+	/* Get the start block number */
+	start_sector = address_to_sector(offset);
+	if (start_sector == -1) {
+		puts("Invalid sector! ");
+		goto out;
+	}
+	end_sector = address_to_sector(offset + len - 1);
+	if (end_sector == -1) {
+		puts("Invalid sector! ");
+		goto out;
+	}
+
+	/* Since flashes operate in sector units but the eeprom command
+	 * operates as a continuous stream of bytes, we need to emulate
+	 * the eeprom behavior.  So here we read in the sector, overlay
+	 * any bytes we're actually modifying, erase the sector, and
+	 * then write back out the new sector.
+	 */
+	temp = malloc(flash.sector_size);
+	if (!temp) {
+		puts("Malloc for sector failed! ");
+		goto out;
+	}
+
+	for (num = start_sector; num <= end_sector; num++) {
+		unsigned long address = num * flash.sector_size;
+
+		/* XXX: should add an optimization when spanning sectors:
+		 * No point in reading in a sector if we're going to be
+		 * clobbering the whole thing.  Need to also add a test
+		 * case to make sure the optimization is correct.
+		 */
+		if (read_flash(address, flash.sector_size, temp)) {
+			puts("Read sector failed! ");
+			len = 0;
+			break;
+		}
+
+		start_byte = max(address, offset);
+		end_byte = address + flash.sector_size - 1;
+		if (end_byte > (offset + len))
+			end_byte = (offset + len - 1);
+
+		memcpy(temp + start_byte - address,
+			buffer + start_byte - offset,
+			end_byte - start_byte + 1);
+
+		if (erase_sector(address)) {
+			puts("Erase sector failed! ");
+			goto out;
+		}
+
+		if (write_sector(address, flash.sector_size, temp)) {
+			puts("Write sector failed! ");
+			goto out;
+		}
+
+		puts(".");
+	}
+
+	ret = len;
+
+ out:
+	free(temp);
+
+	SPI_DEINIT();
+
+	return ret;
+}
+
+/*
+ * Function: spi_read
+ */
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
+{
+	unsigned long offset;
+
+	SPI_INIT();
+
+	if (spi_detect_part())
+		len = 0;
+	else {
+		offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+		read_flash(offset, len, buffer);
+	}
+
+	SPI_DEINIT();
+
+	return len;
+}
+
+/*
+ *	Spit out some useful information about the SPI eeprom
+ */
+int eeprom_info(void)
+{
+	int ret = 0;
+
+	SPI_INIT();
+
+	if (spi_detect_part())
+		ret = 1;
+	else
+		printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n"
+			"Parameters: num sectors = %i, sector size = %i, write size = %i\n"
+			"Flash Size: %i mbit (%i mbyte)\n"
+			"Status: 0x%02X\n",
+			flash.flash->name, flash.manufacturer_id, flash.manufacturer->name,
+			flash.device_id1, flash.device_id2, flash.num_sectors,
+			flash.sector_size, flash.write_length,
+			(flash.num_sectors * flash.sector_size) >> 17,
+			(flash.num_sectors * flash.sector_size) >> 20,
+			read_status_register());
+
+	SPI_DEINIT();
+
+	return ret;
+}
+
+#endif

board/bf537-stamp/stm_m25p64.c

@@ -1,516 +0,0 @@
-/****************************************************************************
- *  SPI flash driver for M25P64
- ****************************************************************************/
-#include <common.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/spi.h>
-
-#if defined(CONFIG_SPI)
-
-/* Application definitions */
-
-#define	NUM_SECTORS	128	/* number of sectors */
-#define SECTOR_SIZE	0x10000
-#define NOP_NUM		1000
-
-#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /* Settings to the SPI_CTL */
-#define TIMOD01 (0x01)	/* stes the SPI to work with core instructions */
-
-/* Flash commands */
-#define	SPI_WREN	(0x06)	/*Set Write Enable Latch */
-#define	SPI_WRDI	(0x04)	/*Reset Write Enable Latch */
-#define	SPI_RDSR	(0x05)	/*Read Status Register */
-#define	SPI_WRSR	(0x01)	/*Write Status Register */
-#define	SPI_READ	(0x03)	/*Read data from memory */
-#define	SPI_FAST_READ	(0x0B)	/*Read data from memory */
-#define	SPI_PP		(0x02)	/*Program Data into memory */
-#define	SPI_SE		(0xD8)	/*Erase one sector in memory */
-#define	SPI_BE		(0xC7)	/*Erase all memory */
-#define	WIP		(0x1)	/*Check the write in progress bit of the SPI status register */
-#define	WEL		(0x2)	/*Check the write enable bit of the SPI status register */
-
-#define	TIMEOUT		350000000
-
-typedef enum {
-	NO_ERR,
-	POLL_TIMEOUT,
-	INVALID_SECTOR,
-	INVALID_BLOCK,
-} ERROR_CODE;
-
-void spi_init_f(void);
-void spi_init_r(void);
-ssize_t spi_read(uchar *, int, uchar *, int);
-ssize_t spi_write(uchar *, int, uchar *, int);
-
-char ReadStatusRegister(void);
-void Wait_For_SPIF(void);
-void SetupSPI(const int spi_setting);
-void SPI_OFF(void);
-void SendSingleCommand(const int iCommand);
-
-ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
-ERROR_CODE EraseBlock(int nBlock);
-ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
-ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
-ERROR_CODE Wait_For_Status(char Statusbit);
-ERROR_CODE Wait_For_WEL(void);
-
-/*
- * Function:    spi_init_f
- * Description: Init SPI-Controller (ROM part)
- * return:      ---
- */
-void spi_init_f(void)
-{
-}
-
-/*
- * Function:    spi_init_r
- * Description: Init SPI-Controller (RAM part) -
- *		 The malloc engine is ready and we can move our buffers to
- *		 normal RAM
- *  return:      ---
- */
-void spi_init_r(void)
-{
-	return;
-}
-
-/*
- * Function:    spi_write
- */
-ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
-{
-	unsigned long offset;
-	int start_block, end_block;
-	int start_byte, end_byte;
-	ERROR_CODE result = NO_ERR;
-	uchar temp[SECTOR_SIZE];
-	int i, num;
-
-	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
-	/* Get the start block number */
-	result = GetSectorNumber(offset, &start_block);
-	if (result == INVALID_SECTOR) {
-		printf("Invalid sector! ");
-		return 0;
-	}
-	/* Get the end block number */
-	result = GetSectorNumber(offset + len - 1, &end_block);
-	if (result == INVALID_SECTOR) {
-		printf("Invalid sector! ");
-		return 0;
-	}
-
-	for (num = start_block; num <= end_block; num++) {
-		ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
-		start_byte = num * SECTOR_SIZE;
-		end_byte = (num + 1) * SECTOR_SIZE - 1;
-		if (start_byte < offset)
-			start_byte = offset;
-		if (end_byte > (offset + len))
-			end_byte = (offset + len - 1);
-		for (i = start_byte; i <= end_byte; i++)
-			temp[i - num * SECTOR_SIZE] = buffer[i - offset];
-		EraseBlock(num);
-		result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
-		if (result != NO_ERR)
-			return 0;
-		printf(".");
-	}
-	return len;
-}
-
-/*
- * Function: spi_read
- */
-ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
-{
-	unsigned long offset;
-	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
-	ReadData(offset, len, (int *)buffer);
-	return len;
-}
-
-void SendSingleCommand(const int iCommand)
-{
-	unsigned short dummy;
-
-	/* turns on the SPI in single write mode */
-	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
-	/* sends the actual command to the SPI TX register */
-	*pSPI_TDBR = iCommand;
-	SSYNC();
-
-	/* The SPI status register will be polled to check the SPIF bit */
-	Wait_For_SPIF();
-
-	dummy = *pSPI_RDBR;
-
-	/* The SPI will be turned off */
-	SPI_OFF();
-
-}
-
-void SetupSPI(const int spi_setting)
-{
-
-	if (icache_status() || dcache_status())
-		udelay(CONFIG_CCLK_HZ / 50000000);
-	/*sets up the PF10 to be the slave select of the SPI */
-	*pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
-	*pSPI_FLG = 0xFF02;
-	*pSPI_BAUD = CONFIG_SPI_BAUD;
-	*pSPI_CTL = spi_setting;
-	SSYNC();
-
-	*pSPI_FLG = 0xFD02;
-	SSYNC();
-}
-
-void SPI_OFF(void)
-{
-
-	*pSPI_CTL = 0x0400;	/* disable SPI */
-	*pSPI_FLG = 0;
-	*pSPI_BAUD = 0;
-	SSYNC();
-	udelay(CONFIG_CCLK_HZ / 50000000);
-
-}
-
-void Wait_For_SPIF(void)
-{
-	unsigned short dummyread;
-	while ((*pSPI_STAT & TXS)) ;
-	while (!(*pSPI_STAT & SPIF)) ;
-	while (!(*pSPI_STAT & RXS)) ;
-	/* Read dummy to empty the receive register */
-	dummyread = *pSPI_RDBR;
-}
-
-ERROR_CODE Wait_For_WEL(void)
-{
-	int i;
-	char status_register = 0;
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	for (i = 0; i < TIMEOUT; i++) {
-		status_register = ReadStatusRegister();
-		if ((status_register & WEL)) {
-			ErrorCode = NO_ERR;
-			break;
-		}
-		ErrorCode = POLL_TIMEOUT;	/* Time out error */
-	};
-
-	return ErrorCode;
-}
-
-ERROR_CODE Wait_For_Status(char Statusbit)
-{
-	int i;
-	char status_register = 0xFF;
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	for (i = 0; i < TIMEOUT; i++) {
-		status_register = ReadStatusRegister();
-		if (!(status_register & Statusbit)) {
-			ErrorCode = NO_ERR;
-			break;
-		}
-		ErrorCode = POLL_TIMEOUT;	/* Time out error */
-	};
-
-	return ErrorCode;
-}
-
-char ReadStatusRegister(void)
-{
-	char status_register = 0;
-
-	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
-
-	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
-	SSYNC();
-	Wait_For_SPIF();	/*wait until the instruction has been sent */
-	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
-	SSYNC();
-	Wait_For_SPIF();	/*wait until the data has been sent */
-	status_register = *pSPI_RDBR;	/*read the status register */
-
-	SPI_OFF();		/* Turn off the SPI */
-
-	return status_register;
-}
-
-ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
-{
-	int nSector = 0;
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
-		ErrorCode = INVALID_SECTOR;
-		return ErrorCode;
-	}
-
-	nSector = (int)ulOffset / 0x10000;
-	*pnSector = nSector;
-
-	return ErrorCode;
-}
-
-ERROR_CODE EraseBlock(int nBlock)
-{
-	unsigned long ulSectorOff = 0x0, ShiftValue;
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	/* if the block is invalid just return */
-	if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
-		ErrorCode = INVALID_BLOCK;
-		return ErrorCode;
-	}
-	/* figure out the offset of the block in flash */
-	if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
-		ulSectorOff = (nBlock * SECTOR_SIZE);
-
-	} else {
-		ErrorCode = INVALID_BLOCK;
-		return ErrorCode;
-	}
-
-	/* A write enable instruction must previously have been executed */
-	SendSingleCommand(SPI_WREN);
-
-	/* The status register will be polled to check the write enable latch "WREN" */
-	ErrorCode = Wait_For_WEL();
-
-	if (POLL_TIMEOUT == ErrorCode) {
-		printf("SPI Erase block error\n");
-		return ErrorCode;
-	} else
-
-	/* Turn on the SPI to send single commands */
-	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
-	/*
-	 * Send the erase block command to the flash followed by the 24 address
-	 * to point to the start of a sector
-	 */
-	*pSPI_TDBR = SPI_SE;
-	SSYNC();
-	Wait_For_SPIF();
-	/* Send the highest byte of the 24 bit address at first */
-	ShiftValue = (ulSectorOff >> 16);
-	*pSPI_TDBR = ShiftValue;
-	SSYNC();
-	/* Wait until the instruction has been sent */
-	Wait_For_SPIF();
-	/* Send the middle byte of the 24 bit address  at second */
-	ShiftValue = (ulSectorOff >> 8);
-	*pSPI_TDBR = ShiftValue;
-	SSYNC();
-	/* Wait until the instruction has been sent */
-	Wait_For_SPIF();
-	/* Send the lowest byte of the 24 bit address finally */
-	*pSPI_TDBR = ulSectorOff;
-	SSYNC();
-	/* Wait until the instruction has been sent */
-	Wait_For_SPIF();
-
-	/* Turns off the SPI */
-	SPI_OFF();
-
-	/* Poll the status register to check the Write in Progress bit */
-	/* Sector erase takes time */
-	ErrorCode = Wait_For_Status(WIP);
-
-	/* block erase should be complete */
-	return ErrorCode;
-}
-
-/*
- * ERROR_CODE ReadData()
- * Read a value from flash for verify purpose
- * Inputs:	unsigned long ulStart - holds the SPI start address
- *			int pnData - pointer to store value read from flash
- *			long lCount - number of elements to read
- */
-ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
-{
-	unsigned long ShiftValue;
-	char *cnData;
-	int i;
-
-	/* Pointer cast to be able to increment byte wise */
-
-	cnData = (char *)pnData;
-	/* Start SPI interface */
-	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
-#ifdef CONFIG_SPI_FLASH_FAST_READ
-	/* Send the read command to SPI device */
-	*pSPI_TDBR = SPI_FAST_READ;
-#else
-	/* Send the read command to SPI device */
-	*pSPI_TDBR = SPI_READ;
-#endif
-	SSYNC();
-	/* Wait until the instruction has been sent */
-	Wait_For_SPIF();
-	/* Send the highest byte of the 24 bit address at first */
-	ShiftValue = (ulStart >> 16);
-	/* Send the byte to the SPI device */
-	*pSPI_TDBR = ShiftValue;
-	SSYNC();
-	/* Wait until the instruction has been sent */
-	Wait_For_SPIF();
-	/* Send the middle byte of the 24 bit address  at second */
-	ShiftValue = (ulStart >> 8);
-	/* Send the byte to the SPI device */
-	*pSPI_TDBR = ShiftValue;
-	SSYNC();
-	/* Wait until the instruction has been sent */
-	Wait_For_SPIF();
-	/* Send the lowest byte of the 24 bit address finally */
-	*pSPI_TDBR = ulStart;
-	SSYNC();
-	/* Wait until the instruction has been sent */
-	Wait_For_SPIF();
-
-#ifdef CONFIG_SPI_FLASH_FAST_READ
-	/* Send dummy for FAST_READ */
-	*pSPI_TDBR = 0;
-	SSYNC();
-	/* Wait until the instruction has been sent */
-	Wait_For_SPIF();
-#endif
-
-	/* After the SPI device address has been placed on the MOSI pin the data can be */
-	/* received on the MISO pin. */
-	for (i = 0; i < lCount; i++) {
-		*pSPI_TDBR = 0;
-		SSYNC();
-		while (!(*pSPI_STAT & RXS)) ;
-		*cnData++ = *pSPI_RDBR;
-
-		if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
-			printf(".");
-	}
-
-	/* Turn off the SPI */
-	SPI_OFF();
-
-	return NO_ERR;
-}
-
-ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
-		      int *iDataSource, long *lWriteCount)
-{
-
-	unsigned long ulWAddr;
-	long lWTransferCount = 0;
-	int i;
-	char iData;
-	char *temp = (char *)iDataSource;
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	/* First, a Write Enable Command must be sent to the SPI. */
-	SendSingleCommand(SPI_WREN);
-
-	/*
-	 * Second, the SPI Status Register will be tested whether the
-	 * Write Enable Bit has been set
-	 */
-	ErrorCode = Wait_For_WEL();
-	if (POLL_TIMEOUT == ErrorCode) {
-		printf("SPI Write Time Out\n");
-		return ErrorCode;
-	} else
-		/* Third, the 24 bit address will be shifted out
-		 * the SPI MOSI bytewise.
-		 * Turns the SPI on
-		 */
-		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-	*pSPI_TDBR = SPI_PP;
-	SSYNC();
-	/*wait until the instruction has been sent */
-	Wait_For_SPIF();
-	ulWAddr = (ulStartAddr >> 16);
-	*pSPI_TDBR = ulWAddr;
-	SSYNC();
-	/*wait until the instruction has been sent */
-	Wait_For_SPIF();
-	ulWAddr = (ulStartAddr >> 8);
-	*pSPI_TDBR = ulWAddr;
-	SSYNC();
-	/*wait until the instruction has been sent */
-	Wait_For_SPIF();
-	ulWAddr = ulStartAddr;
-	*pSPI_TDBR = ulWAddr;
-	SSYNC();
-	/*wait until the instruction has been sent */
-	Wait_For_SPIF();
-	/*
-	 * Fourth, maximum number of 256 bytes will be taken from the Buffer
-	 * and sent to the SPI device.
-	 */
-	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
-		iData = *temp;
-		*pSPI_TDBR = iData;
-		SSYNC();
-		/*wait until the instruction has been sent */
-		Wait_For_SPIF();
-		temp++;
-	}
-
-	/* Turns the SPI off */
-	SPI_OFF();
-
-	/*
-	 * Sixth, the SPI Write in Progress Bit must be toggled to ensure the
-	 * programming is done before start of next transfer
-	 */
-	ErrorCode = Wait_For_Status(WIP);
-
-	if (POLL_TIMEOUT == ErrorCode) {
-		printf("SPI Program Time out!\n");
-		return ErrorCode;
-	} else
-
-		*lWriteCount = lWTransferCount;
-
-	return ErrorCode;
-}
-
-ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
-{
-
-	unsigned long ulWStart = ulStart;
-	long lWCount = lCount, lWriteCount;
-	long *pnWriteCount = &lWriteCount;
-
-	ERROR_CODE ErrorCode = NO_ERR;
-
-	while (lWCount != 0) {
-		ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
-
-		/*
-		 * After each function call of WriteFlash the counter
-		 * must be adjusted
-		 */
-		lWCount -= *pnWriteCount;
-
-		/* Also, both address pointers must be recalculated. */
-		ulWStart += *pnWriteCount;
-		pnData += *pnWriteCount / 4;
-	}
-
-	/* return the appropriate error code */
-	return ErrorCode;
-}
-
-#endif				/* CONFIG_SPI */

board/bf537-stamp/u-boot.lds.S

@@ -1,7 +1,7 @@
 /*
  * U-boot - u-boot.lds.S
  *
- * Copyright (c) 2005-2007 Analog Device Inc.
+ * Copyright (c) 2005-2008 Analog Device Inc.
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -26,165 +26,111 @@
  */
 
 #include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error.  If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM      CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
 
 OUTPUT_ARCH(bfin)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+
-/* Do we need any of these for elf?
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
-   __DYNAMIC = 0;    */
 MEMORY
- {
+{
- ram :	   ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
+	ram     : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
- l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
+	l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
+	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
- }
+}
 
 SECTIONS
 {
-  /* Read-only sections, merged into text segment: */
+	.text :
-  . = + SIZEOF_HEADERS; /*0x1000;*/
+	{
-  .interp : { *(.interp) }
+#ifdef ENV_IS_EMBEDDED
-  .hash          : { *(.hash)		}
+		/* WARNING - the following is hand-optimized to fit within
-  .dynsym        : { *(.dynsym)		}
+		 * the sector before the environment sector. If it throws
-  .dynstr        : { *(.dynstr)		}
+		 * an error during compilation remove an object here to get
-  .rel.text      : { *(.rel.text)	}
+		 * it linked after the configuration sector.
-  .rela.text     : { *(.rela.text)	}
+		 */
-  .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)	}
-  .rela.got      : { *(.rela.got)	}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)	}
-  .rela.bss      : { *(.rela.bss)	}
-  .rel.plt       : { *(.rel.plt)	}
-  .rela.plt      : { *(.rela.plt)	}
-  .init          : { *(.init)		}
-  .plt : { *(.plt) }
-  . = CFG_MONITOR_BASE;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector before the environment sector. If it throws	*/
-    /* an error during compilation remove an object here to get	*/
-    /* it linked after the configuration sector.		*/
 
-    cpu/bf537/start.o		(.text)
+		cpu/blackfin/start.o		(.text)
-    cpu/bf537/start1.o		(.text)
+		cpu/blackfin/traps.o		(.text)
-    cpu/bf537/traps.o		(.text)
+		cpu/blackfin/interrupt.o	(.text)
-    cpu/bf537/interrupt.o	(.text)
+		cpu/blackfin/serial.o		(.text)
-    cpu/bf537/serial.o		(.text)
+		common/dlmalloc.o		(.text)
-    common/dlmalloc.o		(.text)
+		lib_generic/crc32.o		(.text)
-/*  lib_blackfin/bf533_string.o	(.text) */
-/*  lib_generic/vsprintf.o	(.text) */
-    lib_generic/crc32.o		(.text)
-/*  lib_generic/zlib.o		(.text) */
-/*  board/bf537-stamp/bf537-stamp.o		(.text) */
 
-    . = DEFINED(env_offset) ? env_offset : .;
+		. = DEFINED(env_offset) ? env_offset : .;
-    common/environment.o	(.text)
+		common/environment.o	(.text)
+#endif
 
-    *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .text)
+		*(.text .text.*)
-    *(.fixup)
+	} >ram
-    *(.got1)
-  }  > ram
-  _etext = .;
-  PROVIDE (etext = .);
-  .text_l1	:
-  {
-  . = ALIGN(4) ;
-  _text_l1 = .;
-  PROVIDE (text_l1 = .);
-  board/bf537-stamp/post-memory.o   (.text)
-  . = ALIGN(4) ;
-  _etext_l1 = .;
-  PROVIDE (etext_l1 = .);
-  } > l1_code AT > ram
 
-  .rodata :
+	.rodata :
-  {
+	{
-    . = ALIGN(4);
+		. = ALIGN(4);
-    *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata)
+		*(.rodata .rodata.*)
-    *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata1)
+		*(.rodata1)
-    *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata.str1.4)
+		*(.eh_frame)
-    *(.eh_frame)
+		. = ALIGN(4);
-    . = ALIGN(4);
+	} >ram
-  } > ram
 
-  . = ALIGN(4);
+	.data :
-  _erodata = .;
+	{
-  PROVIDE (erodata = .);
+		. = ALIGN(256);
-  .rodata_l1 :
+		*(.data .data.*)
- {
+		*(.data1)
-   . = ALIGN(4) ;
+		*(.sdata)
-   _rodata_l1 = .;
+		*(.sdata2)
-   PROVIDE (rodata_l1 = .);
+		*(.dynamic)
-   board/bf537-stamp/post-memory.o (.rodata)
+		CONSTRUCTORS
-   board/bf537-stamp/post-memory.o (.rodata1)
+	} >ram
-   board/bf537-stamp/post-memory.o (.rodata.str1.4)
-   . = ALIGN(4) ;
-   _erodata_l1 = .;
-   PROVIDE(erodata_l1 = .);
- } > l1_data AT > ram
 
-  .fini      : { *(.fini)    } =0
+	.u_boot_cmd :
-  .ctors     : { *(.ctors)   }
+	{
-  .dtors     : { *(.dtors)   }
+		___u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		___u_boot_cmd_end = .;
+	} >ram
 
-  /* Read-write section, merged into data segment: */
+	.text_l1 :
-  . = (. + 0x00FF) & 0xFFFFFF00;
+	{
-  _erotext = .;
+		. = ALIGN(4);
-  PROVIDE (erotext = .);
+		__stext_l1 = .;
-  .reloc   :
+		*(.l1.text)
-  {
+		. = ALIGN(4);
-    *(.got)
+		__etext_l1 = .;
-    _GOT2_TABLE_ = .;
+	} >l1_code AT>ram
-    *(.got2)
+	__stext_l1_lma = LOADADDR(.text_l1);
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
 
-  .data    :
+	.data_l1 :
-  {
+	{
-    *(.data)
+		. = ALIGN(4);
-    *(.data1)
+		__sdata_l1 = .;
-    *(.sdata)
+		*(.l1.data)
-    *(.sdata2)
+		*(.l1.bss)
-    *(.dynamic)
+		. = ALIGN(4);
-    CONSTRUCTORS
+		__edata_l1 = .;
-  } > ram
+	} >l1_data AT>ram
-  _edata  =  .;
+	__sdata_l1_lma = LOADADDR(.data_l1);
-  PROVIDE (edata = .);
 
-  ___u_boot_cmd_start = .;
+	.bss :
-  .u_boot_cmd : { *(.u_boot_cmd) } > ram
+	{
-  ___u_boot_cmd_end = .;
+		. = ALIGN(4);
-
+		__bss_start = .;
-
+		*(.sbss) *(.scommon)
-  __start___ex_table = .;
+		*(.dynbss)
-  __ex_table : { *(__ex_table) }
+		*(.bss .bss.*)
-  __stop___ex_table = .;
+		*(COMMON)
-
+		__bss_end = .;
-  . = ALIGN(256);
+	} >ram
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  .bss       :
-  {
-  __bss_start = .;
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  } > ram
-  _end = . ;
-  PROVIDE (end = .);
 }

board/bf561-ezkit/Makefile

@@ -39,7 +39,7 @@ $(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 u-boot.lds: u-boot.lds.S
-	$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
 	mv -f $@.tmp $@
 
 clean:

board/bf561-ezkit/config.mk

@@ -20,6 +20,6 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+
-#  256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+# This is not actually used for Blackfin boards so do not change it
-TEXT_BASE = 0x03FC0000
+#TEXT_BASE = do-not-use-me

board/bf561-ezkit/u-boot.lds.S

@@ -1,7 +1,7 @@
 /*
  * U-boot - u-boot.lds.S
  *
- * Copyright (c) 2005-2007 Analog Device Inc.
+ * Copyright (c) 2005-2008 Analog Device Inc.
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -26,128 +26,113 @@
  */
 
 #include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error.  If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM      CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
 
 OUTPUT_ARCH(bfin)
-OUTPUT_ARCH(bfin)
+
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
-/* Do we need any of these for elf?
+MEMORY
-   __DYNAMIC = 0;    */
+{
+	ram     : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+	l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
+	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
 SECTIONS
 {
-  /* Read-only sections, merged into text segment: */
+	.text :
-  . = + SIZEOF_HEADERS;
+	{
-  .interp : { *(.interp) }
+#ifdef ENV_IS_EMBEDDED
-  .hash		: { *(.hash)		}
+		/* WARNING - the following is hand-optimized to fit within
-  .dynsym	: { *(.dynsym)		}
+		 * the sector before the environment sector. If it throws
-  .dynstr	: { *(.dynstr)		}
+		 * an error during compilation remove an object here to get
-  .rel.text	: { *(.rel.text)	}
+		 * it linked after the configuration sector.
-  .rela.text	: { *(.rela.text) 	}
+		 */
-  .rel.data	: { *(.rel.data)	}
-  .rela.data	: { *(.rela.data) 	}
-  .rel.rodata	: { *(.rel.rodata) 	}
-  .rela.rodata	: { *(.rela.rodata) 	}
-  .rel.got	: { *(.rel.got)		}
-  .rela.got	: { *(.rela.got)	}
-  .rel.ctors	: { *(.rel.ctors)	}
-  .rela.ctors	: { *(.rela.ctors)	}
-  .rel.dtors	: { *(.rel.dtors)	}
-  .rela.dtors	: { *(.rela.dtors)	}
-  .rel.bss	: { *(.rel.bss)	}
-  .rela.bss	: { *(.rela.bss)	}
-  .rel.plt	: { *(.rel.plt)	}
-  .rela.plt	: { *(.rela.plt)	}
-  .init		: { *(.init)		}
-  .plt : { *(.plt) }
-  . = CFG_MONITOR_BASE;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector before the environment sector. If it throws 	*/
-    /* an error during compilation remove an object here to get	*/
-    /* it linked after the configuration sector.		*/
 
-    cpu/bf561/start.o		(.text)
+		cpu/blackfin/start.o		(.text)
-    cpu/bf561/start1.o		(.text)
+		cpu/blackfin/traps.o		(.text)
-    cpu/bf561/traps.o		(.text)
+		cpu/blackfin/interrupt.o	(.text)
-    cpu/bf561/interrupt.o	(.text)
+		cpu/blackfin/serial.o		(.text)
-    cpu/bf561/serial.o		(.text)
+		common/dlmalloc.o		(.text)
-    common/dlmalloc.o		(.text)
+		lib_generic/crc32.o		(.text)
-/*  lib_blackfin/bf533_string.o	(.text) */
+		lib_generic/zlib.o		(.text)
-/*  lib_generic/vsprintf.o	(.text) */
+		board/bf561-ezkit/bf561-ezkit.o		(.text)
-    lib_generic/crc32.o		(.text)
-    lib_generic/zlib.o		(.text)
-    board/bf561-ezkit/bf561-ezkit.o		(.text)
 
-    . = DEFINED(env_offset) ? env_offset : .;
+		. = DEFINED(env_offset) ? env_offset : .;
-    common/environment.o	(.text)
+		common/environment.o	(.text)
+#endif
 
-    *(.text)
+		*(.text .text.*)
-    *(.fixup)
+	} >ram
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
 
-  /* Read-write section, merged into data segment: */
+	.rodata :
-  . = (. + 0x00FF) & 0xFFFFFF00;
+	{
-  _erotext = .;
+		. = ALIGN(4);
-  PROVIDE (erotext = .);
+		*(.rodata .rodata.*)
-  .reloc   :
+		*(.rodata1)
-  {
+		*(.eh_frame)
-    *(.got)
+		. = ALIGN(4);
-    _GOT2_TABLE_ = .;
+	} >ram
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
 
-  .data    :
+	.data :
-  {
+	{
-    *(.data)
+		. = ALIGN(256);
-    *(.data1)
+		*(.data .data.*)
-    *(.sdata)
+		*(.data1)
-    *(.sdata2)
+		*(.sdata)
-    *(.dynamic)
+		*(.sdata2)
-    CONSTRUCTORS
+		*(.dynamic)
-  }
+		CONSTRUCTORS
-  _edata  =  .;
+	} >ram
-  PROVIDE (edata = .);
 
-  ___u_boot_cmd_start = .;
+	.u_boot_cmd :
-  .u_boot_cmd : { *(.u_boot_cmd) }
+	{
-  ___u_boot_cmd_end = .;
+		___u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		___u_boot_cmd_end = .;
+	} >ram
 
+	.text_l1 :
+	{
+		. = ALIGN(4);
+		__stext_l1 = .;
+		*(.l1.text)
+		. = ALIGN(4);
+		__etext_l1 = .;
+	} >l1_code AT>ram
+	__stext_l1_lma = LOADADDR(.text_l1);
 
-  __start___ex_table = .;
+	.data_l1 :
-  __ex_table : { *(__ex_table) }
+	{
-  __stop___ex_table = .;
+		. = ALIGN(4);
+		__sdata_l1 = .;
+		*(.l1.data)
+		*(.l1.bss)
+		. = ALIGN(4);
+		__edata_l1 = .;
+	} >l1_data AT>ram
+	__sdata_l1_lma = LOADADDR(.data_l1);
 
-  . = ALIGN(256);
+	.bss :
-  __init_begin = .;
+	{
-  .text.init : { *(.text.init) }
+		. = ALIGN(4);
-  .data.init : { *(.data.init) }
+		__bss_start = .;
-  . = ALIGN(256);
+		*(.sbss) *(.scommon)
-  __init_end = .;
+		*(.dynbss)
-
+		*(.bss .bss.*)
-  __bss_start = .;
+		*(COMMON)
-  .bss       :
+		__bss_end = .;
-  {
+	} >ram
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  _end = . ;
-  PROVIDE (end = .);
 }