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ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)

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This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-03-11 15:05:50 +01:00
parent 8ac41e3e37
commit 2801b2d2a9
5 changed files with 178 additions and 7 deletions
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45
cpu/ppc4xx/cpu.c
View File

@ -54,7 +54,8 @@ static int pci_async_enabled(void)
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
unsigned long val;
mfsdr(sdr_sdstp1, val);
@ -86,7 +87,8 @@ static int pci_arbiter_enabled(void)
return (val & 0x80000000);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
unsigned long val;
mfsdr(sdr_pci0, val);
@ -167,6 +169,21 @@ static char *bootstrap_str[] = {
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_PINSTP_SHIFT 29
static char *bootstrap_str[] = {
"EBC (8 bits)",
"EBC (16 bits)",
"PCI",
"PCI",
"EBC (16 bits)",
"NAND (8 bits)",
"I2C (Addr 0x54)", /* A8 */
"I2C (Addr 0x52)", /* A4 */
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
#if defined(CONFIG_405EZ)
#define SDR0_PINSTP_SHIFT 28
static char *bootstrap_str[] = {
@ -257,7 +274,11 @@ int checkcpu (void)
puts("05");
#endif
#if defined(CONFIG_440)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
puts("60");
#else
puts("40");
#endif
#endif
switch (pvr) {
@ -448,6 +469,26 @@ int checkcpu (void)
strcpy(addstr, "No RAID 6 support");
break;
case PVR_460EX_RA:
puts("EX Rev. A");
strcpy(addstr, "No Security/Kasumi support");
break;
case PVR_460EX_SE_RA:
puts("EX Rev. A");
strcpy(addstr, "Security/Kasumi support");
break;
case PVR_460GT_RA:
puts("GT Rev. A");
strcpy(addstr, "No Security/Kasumi support");
break;
case PVR_460GT_SE_RA:
puts("GT Rev. A");
strcpy(addstr, "Security/Kasumi support");
break;
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;

1
cpu/ppc4xx/cpu_init.c
View File

@ -302,5 +302,6 @@ int cpu_init_r (void)
}
#endif /* defined(CONFIG_405GP) */
#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
return (0);
}

3
cpu/ppc4xx/ndfc.c
View File

@ -34,7 +34,8 @@
#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
(defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EZ) || defined(CONFIG_405EX))
defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT))
#include <nand.h>
#include <linux/mtd/ndfc.h>

125
cpu/ppc4xx/speed.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2007
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -35,6 +35,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define DEBUGF(fmt,args...)
#endif
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
@ -201,7 +203,126 @@ ulong get_PCI_freq (void)
#elif defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
static u8 pll_fwdv_multi_bits[] = {
/* values for: 1 - 16 */
0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
0x05, 0x08, 0x07, 0x02, 0x0b, 0x06
};
u32 get_cpr0_fwdv(unsigned long cpr_reg_fwdv)
{
u32 index;
for (index = 0; index < ARRAY_SIZE(pll_fwdv_multi_bits); index++)
if (cpr_reg_fwdv == (u32)pll_fwdv_multi_bits[index])
return index + 1;
return 0;
}
static u8 pll_fbdv_multi_bits[] = {
/* values for: 1 - 100 */
0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
/* values for: 101 - 200 */
0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
0x20, 0xc0, 0x01, 0x83, 0x77, 0xff, 0x1f, 0xbf, 0x7f, 0xfe,
0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
/* values for: 201 - 255 */
0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
};
u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
{
u32 index;
for (index = 0; index < ARRAY_SIZE(pll_fbdv_multi_bits); index++)
if (cpr_reg_fbdv == (u32)pll_fbdv_multi_bits[index])
return index + 1;
return 0;
}
/*
* AMCC_TODO: verify this routine against latest EAS, cause stuff changed
* with latest EAS
*/
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
unsigned long strp1;
unsigned long temp;
unsigned long m;
unsigned long plbedv0;
/* Extract configured divisors */
mfsdr(sdr_sdstp0, strp0);
mfsdr(sdr_sdstp1, strp1);
temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4);
sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
temp = (strp0 & PLLSYS0_FWD_DIV_B_MASK);
sysInfo->pllFwdDivB = get_cpr0_fwdv(temp);
temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 8;
sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
temp = (strp1 & PLLSYS0_OPB_DIV_MASK) >> 26;
sysInfo->pllOpbDiv = temp ? temp : 4;
/* AMCC_TODO: verify the SDR0_SDSTP1.PERDV0 value sysInfo->pllExtBusDiv */
temp = (strp1 & PLLSYS0_PERCLK_DIV_MASK) >> 24;
sysInfo->pllExtBusDiv = temp ? temp : 4;
temp = (strp1 & PLLSYS0_PLBEDV0_DIV_MASK) >> 29;
plbedv0 = temp ? temp: 8;
/* Calculate 'M' based on feedback source */
temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
if (temp == 0) {
/* PLL internal feedback */
m = sysInfo->pllFbkDiv;
} else {
/* PLL PerClk feedback */
m = sysInfo->pllFwdDivA * plbedv0 * sysInfo->pllOpbDiv *
sysInfo->pllExtBusDiv;
}
/* Now calculate the individual clocks */
sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1);
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz / sysInfo->pllFwdDivA / plbedv0;
sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
sysInfo->freqDDR = sysInfo->freqPLB;
sysInfo->freqUART = sysInfo->freqPLB;
return;
}
#elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
void get_sys_info (sys_info_t *sysInfo)
{

11
cpu/ppc4xx/start.S
View File

@ -672,7 +672,9 @@ _start:
/* 440EP & 440GR are only 440er PPC's without internal SRAM */
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
/* not all PPC's have internal SRAM usable as L2-cache */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
@ -711,6 +713,10 @@ _start:
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr isram0_sb3cr,r1
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
lis r1,0x4000 /* BAS = 8000_0000 */
ori r1,r1,0x4580 /* 16k */
mtdcr isram0_sb0cr,r1
#elif defined(CONFIG_440GP)
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
@ -1370,7 +1376,8 @@ relocate_code:
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
/*
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
* to speed up the boot process. Now this cache needs to be disabled.