mpc83xx: unreinvent mem_clk
delete ddr_clk and use mem_clk instead. Rename other ddr_*_clk to mem_*_clk for consistency's sake. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
parent
730e792926
commit
35cf155c5e
@ -78,12 +78,12 @@ extern int dma_xfer(void *dest, uint count, void *src);
|
||||
int
|
||||
picos_to_clk(int picos)
|
||||
{
|
||||
unsigned int ddr_bus_clk;
|
||||
unsigned int mem_bus_clk;
|
||||
int clks;
|
||||
|
||||
ddr_bus_clk = gd->ddr_clk >> 1;
|
||||
clks = picos / (1000000000 / (ddr_bus_clk / 1000));
|
||||
if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
|
||||
mem_bus_clk = gd->mem_clk >> 1;
|
||||
clks = picos / (1000000000 / (mem_bus_clk / 1000));
|
||||
if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
|
||||
clks++;
|
||||
|
||||
return clks;
|
||||
@ -313,7 +313,7 @@ long int spd_sdram()
|
||||
|
||||
debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
|
||||
|
||||
ddrc_clk = gd->ddr_clk / 1000000;
|
||||
ddrc_clk = gd->mem_clk / 1000000;
|
||||
effective_data_rate = 0;
|
||||
|
||||
if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
|
||||
|
@ -122,9 +122,9 @@ int get_clocks(void)
|
||||
u32 enc_clk;
|
||||
u32 lbiu_clk;
|
||||
u32 lclk_clk;
|
||||
u32 ddr_clk;
|
||||
u32 mem_clk;
|
||||
#if defined(CONFIG_MPC8360)
|
||||
u32 ddr_sec_clk;
|
||||
u32 mem_sec_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
|
||||
u32 qepmf;
|
||||
@ -400,11 +400,11 @@ int get_clocks(void)
|
||||
return -12;
|
||||
}
|
||||
|
||||
ddr_clk = csb_clk *
|
||||
mem_clk = csb_clk *
|
||||
(1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
|
||||
corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
|
||||
#if defined(CONFIG_MPC8360)
|
||||
ddr_sec_clk = csb_clk * (1 +
|
||||
mem_sec_clk = csb_clk * (1 +
|
||||
((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
|
||||
#endif
|
||||
|
||||
@ -466,9 +466,9 @@ int get_clocks(void)
|
||||
gd->enc_clk = enc_clk;
|
||||
gd->lbiu_clk = lbiu_clk;
|
||||
gd->lclk_clk = lclk_clk;
|
||||
gd->ddr_clk = ddr_clk;
|
||||
gd->mem_clk = mem_clk;
|
||||
#if defined(CONFIG_MPC8360)
|
||||
gd->ddr_sec_clk = ddr_sec_clk;
|
||||
gd->mem_sec_clk = mem_sec_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
|
||||
gd->qe_clk = qe_clk;
|
||||
@ -508,9 +508,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
#endif
|
||||
printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
|
||||
printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
|
||||
printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
|
||||
printf(" DDR: %4d MHz\n", gd->mem_clk / 1000000);
|
||||
#if defined(CONFIG_MPC8360)
|
||||
printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
|
||||
printf(" DDR Secondary: %4d MHz\n", gd->mem_sec_clk / 1000000);
|
||||
#endif
|
||||
printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
|
||||
printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
|
||||
|
@ -74,7 +74,6 @@ typedef struct global_data {
|
||||
u32 enc_clk;
|
||||
u32 lbiu_clk;
|
||||
u32 lclk_clk;
|
||||
u32 ddr_clk;
|
||||
u32 pci_clk;
|
||||
#if defined(CONFIG_MPC837X)
|
||||
u32 pciexp1_clk;
|
||||
@ -84,7 +83,7 @@ typedef struct global_data {
|
||||
u32 sata_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8360)
|
||||
u32 ddr_sec_clk;
|
||||
u32 mem_sec_clk;
|
||||
#endif /* CONFIG_MPC8360 */
|
||||
#endif
|
||||
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
|
||||
|
Loading…
Reference in New Issue
Block a user