ppc4xx: Update APC405 board support
- enable esd's auto_update mechanism - fix LCD support on latest hardware revision (uses other LCD controller) - support alternative flash layout on rev. 1.8 boards - coding style cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
83975d02e2
commit
0b9872515a
@ -28,7 +28,9 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o strataflash.o ../common/misc.o
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COBJS = $(BOARD).o \
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../common/misc.o \
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../common/auto_update.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -1,4 +1,7 @@
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/*
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* (C) Copyright 2005-2008
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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@ -23,17 +26,22 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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#include <flash.h>
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#include <asm/4xx_pci.h>
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if 0
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#define FPGA_DEBUG
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#endif
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#undef FPGA_DEBUG
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void lxt971_no_sleep(void);
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extern ulong flash_get_size (ulong base, int banknum);
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int flash_banks = CFG_MAX_FLASH_BANKS_DETECT;
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/* fpga configuration data - gzip compressed and generated by bin2c */
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const unsigned char fpgadata[] =
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@ -46,82 +54,94 @@ const unsigned char fpgadata[] =
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*/
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#include "../common/fpga.c"
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/* Prototypes */
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int gunzip(void *, int, unsigned char *, unsigned long *);
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#ifdef CONFIG_LCD_USED
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/* logo bitmap data - gzip compressed and generated by bin2c */
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unsigned char logo_bmp[] =
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{
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#include CFG_LCD_LOGO_NAME
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#include "logo_640_480_24bpp.c"
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};
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/*
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* include common lcd code (for esd boards)
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*/
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#include "../common/lcd.c"
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#include CFG_LCD_HEADER_NAME
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#include "../common/s1d13505_640_480_16bpp.h"
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#include "../common/s1d13806_640_480_16bpp.h"
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#endif /* CONFIG_LCD_USED */
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/*
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* include common auto-update code (for esd boards)
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*/
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#include "../common/auto_update.h"
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au_image_t au_image[] = {
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{"preinst.img", 0, -1, AU_SCRIPT},
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{"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
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{"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
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{"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
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{"work.img", 0xfe500000, 0x01400000, AU_NOR},
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{"data.img", 0xff900000, 0x00580000, AU_NOR},
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{"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
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{"postinst.img", 0, 0, AU_SCRIPT},
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};
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int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
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int board_revision(void)
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{
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unsigned long cntrl0Reg;
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unsigned long value;
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volatile unsigned long value;
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/*
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* Get version of APC405 board from GPIO's
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*/
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/*
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* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
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*/
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/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x03000000);
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
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udelay(1000); /* wait some time before reading input */
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value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
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mtdcr(cntrl0, cntrl0Reg | 0x03800000);
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out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
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/* wait some time before reading input */
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udelay(1000);
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/* get config bits */
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value = in_be32((void*)GPIO0_IR) & 0x001c0000;
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/*
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* Restore GPIO settings
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*/
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mtdcr(cntrl0, cntrl0Reg);
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switch (value) {
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case 0x00180000:
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/* CS2==1 && CS3==1 -> version <= 1.2 */
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case 0x001c0000:
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/* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
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return 2;
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case 0x00080000:
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/* CS2==0 && CS3==1 -> version 1.3 */
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case 0x000c0000:
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/* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
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return 3;
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#if 0 /* not yet manufactured ! */
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case 0x00100000:
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/* CS2==1 && CS3==0 -> version 1.4 */
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return 4;
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case 0x00000000:
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/* CS2==0 && CS3==0 -> version 1.5 */
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return 5;
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#endif
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case 0x00180000:
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/* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
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return 6;
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case 0x00140000:
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/* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
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return 8;
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default:
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/* should not be reached! */
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return 0;
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}
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}
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int board_early_init_f (void)
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{
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/*
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* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
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* First pull fpga-prg pin low, to disable fpga logic
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*/
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out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
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out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
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out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
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out32(GPIO0_OR, 0); /* pull prg low */
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out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
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out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
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out_be32((void*)GPIO0_OR, 0); /* pull prg low */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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@ -140,48 +160,61 @@ int board_early_init_f (void)
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicvcr, 0x00000001); /* set vect base=0 */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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* EBC Configuration Register: set ready timeout to 512 ebc-clks
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*/
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#if 1 /* test-only */
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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#else
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mtebc (epcr, 0x28400000); /* ebc in high-z */
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#endif
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mtebc(epcr, 0xa8400000); /* ebc always driven */
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/*
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* New boards have a single 32MB flash connected to CS0
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* instead of two 16MB flashes on CS0+1.
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*/
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if (board_revision() >= 8) {
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/* disable CS1 */
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mtebc(pb1ap, 0);
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mtebc(pb1cr, 0);
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/* resize CS0 to 32MB */
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mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8);
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mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8);
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}
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_f (void)
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int board_early_init_r(void)
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{
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return 0; /* dummy implementation */
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if (gd->board_type >= 8)
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flash_banks = 1;
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return 0;
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}
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#define FUJI_BASE 0xf0100200
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#define LCDBL_PWM 0xa0
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#define LCDBL_PWMMIN 0xa4
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#define LCDBL_PWMMAX 0xa8
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int misc_init_r (void)
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int misc_init_r(void)
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{
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volatile unsigned short *fpga_mode =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
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volatile unsigned short *fpga_ctrl2 =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
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volatile unsigned char *duart0_mcr =
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(unsigned char *)((ulong)DUART0_BA + 4);
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volatile unsigned char *duart1_mcr =
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(unsigned char *)((ulong)DUART1_BA + 4);
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volatile unsigned short *fuji_lcdbl_pwm =
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(unsigned short *)((ulong)0xf0100200 + 0xa0);
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u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
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u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
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u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
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u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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unsigned long cntrl0Reg;
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char *str;
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uchar *logo_addr;
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ulong logo_size;
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ushort minb, maxb;
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int result;
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/*
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* Setup GPIO pins (CS6+CS7 as GPIO)
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@ -190,9 +223,9 @@ int misc_init_r (void)
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mtdcr(cntrl0, cntrl0Reg | 0x00300000);
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dst = malloc(CFG_FPGA_MAX_SIZE);
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if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf ("GUNZIP ERROR - must RESET board to recover\n");
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do_reset (NULL, 0, 0, NULL);
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if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf("GUNZIP ERROR - must RESET board to recover\n");
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do_reset(NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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@ -200,31 +233,34 @@ int misc_init_r (void)
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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printf("(Timeout: "
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"INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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printf("(Timeout: "
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"INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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printf("(Timeout: "
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"DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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for (i = 0; i < 4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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index += len + 3;
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}
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putc ('\n');
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putc('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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for (i = 20; i > 0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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for (index = 0; index < 1000; index++)
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udelay(1000);
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}
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putc ('\n');
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putc('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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@ -235,12 +271,12 @@ int misc_init_r (void)
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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for (i = 0; i < 4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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printf("%s ", &(dst[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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putc('\n');
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free(dst);
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@ -255,51 +291,117 @@ int misc_init_r (void)
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/*
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* Write board revision in FPGA
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*/
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*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
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out_be16(fpga_ctrl2,
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(in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
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/*
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* Enable power on PS/2 interface (with reset)
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*/
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*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
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out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET);
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for (i=0;i<100;i++)
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udelay(1000);
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udelay(1000);
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*fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;
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out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET);
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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*duart0_mcr = 0x08;
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*duart1_mcr = 0x08;
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out_8(duart0_mcr, 0x08);
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out_8(duart1_mcr, 0x08);
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/*
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* Init lcd interface and display logo
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*/
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lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
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regs_13806_640_480_16bpp,
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sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
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logo_bmp, sizeof(logo_bmp));
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str = getenv("splashimage");
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if (str) {
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logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
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logo_size = CFG_VIDEO_LOGO_MAX_SIZE;
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} else {
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logo_addr = logo_bmp;
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logo_size = sizeof(logo_bmp);
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}
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if (gd->board_type >= 6) {
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result = lcd_init((uchar *)CFG_LCD_BIG_REG,
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(uchar *)CFG_LCD_BIG_MEM,
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regs_13505_640_480_16bpp,
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sizeof(regs_13505_640_480_16bpp) /
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sizeof(regs_13505_640_480_16bpp[0]),
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logo_addr, logo_size);
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if (result && str) {
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/* retry with internal image */
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logo_addr = logo_bmp;
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logo_size = sizeof(logo_bmp);
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lcd_init((uchar *)CFG_LCD_BIG_REG,
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(uchar *)CFG_LCD_BIG_MEM,
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regs_13505_640_480_16bpp,
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sizeof(regs_13505_640_480_16bpp) /
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sizeof(regs_13505_640_480_16bpp[0]),
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logo_addr, logo_size);
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}
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} else {
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result = lcd_init((uchar *)CFG_LCD_BIG_REG,
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(uchar *)CFG_LCD_BIG_MEM,
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regs_13806_640_480_16bpp,
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sizeof(regs_13806_640_480_16bpp) /
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sizeof(regs_13806_640_480_16bpp[0]),
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logo_addr, logo_size);
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if (result && str) {
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/* retry with internal image */
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logo_addr = logo_bmp;
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logo_size = sizeof(logo_bmp);
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lcd_init((uchar *)CFG_LCD_BIG_REG,
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(uchar *)CFG_LCD_BIG_MEM,
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regs_13806_640_480_16bpp,
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sizeof(regs_13806_640_480_16bpp) /
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sizeof(regs_13806_640_480_16bpp[0]),
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logo_addr, logo_size);
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}
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}
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/*
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* Reset microcontroller and setup backlight PWM controller
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*/
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*fpga_mode |= 0x0014;
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out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
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for (i=0;i<10;i++)
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udelay(1000);
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*fpga_mode |= 0x001c;
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*fuji_lcdbl_pwm = 0x00ff;
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out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
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minb = 0;
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maxb = 0xff;
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str = getenv("lcdbl");
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if (str) {
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minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
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if (str && (*str=',')) {
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str++;
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maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
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} else
|
||||
minb = 0;
|
||||
|
||||
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
|
||||
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
|
||||
|
||||
printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
|
||||
}
|
||||
out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
|
||||
|
||||
if (getenv("usb_self") == NULL) {
|
||||
setenv("usb_load", CFG_USB_LOAD_COMMAND);
|
||||
setenv("usbargs", CFG_USB_ARGS);
|
||||
setenv("bootcmd", CONFIG_BOOTCOMMAND);
|
||||
setenv("usb_self", CFG_USB_SELF_COMMAND);
|
||||
saveenv();
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
unsigned char str[64];
|
||||
char str[64];
|
||||
int i = getenv_r ("serial#", str, sizeof(str));
|
||||
|
||||
puts ("Board: ");
|
||||
@ -311,18 +413,11 @@ int checkboard (void)
|
||||
}
|
||||
|
||||
gd->board_type = board_revision();
|
||||
printf(", Rev 1.%ld\n", gd->board_type);
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
printf(", Rev. 1.%ld\n", gd->board_type);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
unsigned long val;
|
||||
@ -330,43 +425,64 @@ long int initdram (int board_type)
|
||||
mtdcr(memcfga, mem_mb0cf);
|
||||
val = mfdcr(memcfgd);
|
||||
|
||||
#if 0
|
||||
printf("\nmb0cf=%x\n", val); /* test-only */
|
||||
printf("strap=%x\n", mfdcr(strap)); /* test-only */
|
||||
#endif
|
||||
|
||||
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int testdram (void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("test: 16 MB - ok\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_IDE_RESET
|
||||
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
volatile unsigned short *fpga_mode =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
|
||||
u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
|
||||
|
||||
/*
|
||||
* Assert or deassert CompactFlash Reset Pin
|
||||
*/
|
||||
if (on) { /* assert RESET */
|
||||
*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
|
||||
} else { /* release RESET */
|
||||
*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
|
||||
if (on) {
|
||||
out_be16(fpga_mode,
|
||||
in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET);
|
||||
} else {
|
||||
out_be16(fpga_mode,
|
||||
in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
void reset_phy(void)
|
||||
{
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
|
||||
int usb_board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_board_stop(void)
|
||||
{
|
||||
unsigned short tmp;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* reset PCI bus
|
||||
* This is required to make some very old Linux OHCI driver
|
||||
* work after U-Boot has used the OHCI controller.
|
||||
*/
|
||||
pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
|
||||
pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
|
||||
|
||||
for (i = 0; i < 100; i++)
|
||||
udelay(1000);
|
||||
|
||||
pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_board_init_fail(void)
|
||||
{
|
||||
usb_board_stop();
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user