85xx: Update multicore boot mechanism to ePAPR v0.81 spec
The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Andrew Fleming-AFLEMING
parent
25eedb2c19
commit
79679d8002
@ -26,7 +26,7 @@
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int
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cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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unsigned long cpuid, val = 0;
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unsigned long cpuid;
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if (argc < 3) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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@ -59,9 +59,7 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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return 1;
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}
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val = simple_strtoul(argv[3], NULL, 16);
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if (cpu_release(cpuid, val, argc - 4, argv + 4)) {
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if (cpu_release(cpuid, argc - 3, argv + 3)) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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@ -71,17 +69,16 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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#ifdef CONFIG_PPC
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#define CPU_ARCH_HELP \
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" [args] : <pir> <r3> <r4> <r6> <r7>\n" \
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" [args] : <pir> <r3> <r6>\n" \
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" pir - processor id (if writeable)\n" \
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" r3 - value for gpr 3\n" \
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" r4 - value for gpr 4\n" \
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" r6 - value for gpr 6\n" \
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" r7 - value for gpr 7\n" \
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"\n" \
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" Use '-' for any arg if you want the default value.\n" \
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" Default for r3, r4, r7 is 0, r6 is 0x65504150\n" \
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" Default for r3 is <num> and r6 is 0\n" \
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"\n" \
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" When cpu <num> is released r5 = 0 per the ePAPR spec.\n"
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" When cpu <num> is released r4 and r5 = 0.\n" \
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" r7 will contain the size of the initial mapped area\n"
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#endif
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U_BOOT_CMD(
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@ -52,7 +52,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
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if (*reg == id) {
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fdt_setprop_string(blob, off, "status", "okay");
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} else {
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u32 val = *reg * 24 + spin_tbl_addr;
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u32 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
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val = cpu_to_fdt32(val);
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fdt_setprop_string(blob, off, "status",
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"disabled");
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@ -28,14 +28,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define BOOT_ENTRY_ADDR 0
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#define BOOT_ENTRY_PIR 1
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#define BOOT_ENTRY_R3 2
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#define BOOT_ENTRY_R4 3
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#define BOOT_ENTRY_R6 4
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#define BOOT_ENTRY_R7 5
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#define NUM_BOOT_ENTRY 6
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u32 get_my_id()
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{
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return mfspr(SPRN_PIR);
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@ -63,40 +55,54 @@ int cpu_status(int nr)
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printf("Running on cpu %d\n", id);
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printf("\n");
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printf("table @ 0x%08x:\n", table);
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printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR]);
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printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
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printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
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printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3]);
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printf(" r4 - 0x%08x\n", table[BOOT_ENTRY_R4]);
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printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6]);
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printf(" r7 - 0x%08x\n", table[BOOT_ENTRY_R7]);
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printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
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printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
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}
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return 0;
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}
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int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[])
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static u8 boot_entry_map[4] = {
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0,
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BOOT_ENTRY_PIR,
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BOOT_ENTRY_R3_LOWER,
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BOOT_ENTRY_R6_LOWER,
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};
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int cpu_release(int nr, int argc, char *argv[])
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{
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u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
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u64 boot_addr;
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if (nr == get_my_id()) {
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printf("Invalid to release the boot core.\n\n");
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return 1;
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}
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if (argc != 5) {
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if (argc != 4) {
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printf("Invalid number of arguments to release.\n\n");
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return 1;
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}
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/* handle pir, r3, r4, r6, r7 */
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for (i = 0; i < 5; i++) {
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#ifdef CFG_64BIT_STRTOUL
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boot_addr = simple_strtoull(argv[0], NULL, 16);
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#else
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boot_addr = simple_strtoul(argv[0], NULL, 16);
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#endif
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/* handle pir, r3, r6 */
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for (i = 1; i < 4; i++) {
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if (argv[i][0] != '-') {
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u8 entry = boot_entry_map[i];
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val = simple_strtoul(argv[i], NULL, 16);
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table[i+BOOT_ENTRY_PIR] = val;
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table[entry] = val;
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}
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}
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table[BOOT_ENTRY_ADDR] = boot_addr;
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table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
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table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
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return 0;
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}
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@ -5,4 +5,15 @@ ulong get_spin_addr(void);
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void setup_mp(void);
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u32 get_my_id(void);
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#define BOOT_ENTRY_ADDR_UPPER 0
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#define BOOT_ENTRY_ADDR_LOWER 1
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#define BOOT_ENTRY_R3_UPPER 2
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#define BOOT_ENTRY_R3_LOWER 3
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#define BOOT_ENTRY_RESV 4
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#define BOOT_ENTRY_PIR 5
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#define BOOT_ENTRY_R6_UPPER 6
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#define BOOT_ENTRY_R6_LOWER 7
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#define NUM_BOOT_ENTRY 8
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#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
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#endif
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@ -57,61 +57,91 @@ __secondary_start_page:
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lis r3,toreset(__spin_table)@h
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ori r3,r3,toreset(__spin_table)@l
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/* r9 has the base address for the entry */
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/* r10 has the base address for the entry */
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mfspr r0,SPRN_PIR
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mr r4,r0
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slwi r8,r4,4
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slwi r9,r4,3
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add r8,r8,r9
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add r9,r3,r8
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slwi r8,r4,5
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add r10,r3,r8
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#define EPAPR_MAGIC (0x65504150)
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#define ENTRY_ADDR 0
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#define ENTRY_PIR 4
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#define ENTRY_R3 8
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#define ENTRY_R4 12
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#define ENTRY_R6 16
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#define ENTRY_R7 20
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#define EPAPR_MAGIC (0x45504150)
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#define ENTRY_ADDR_UPPER 0
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#define ENTRY_ADDR_LOWER 4
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#define ENTRY_R3_UPPER 8
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#define ENTRY_R3_LOWER 12
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#define ENTRY_RESV 16
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#define ENTRY_PIR 20
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#define ENTRY_R6_UPPER 24
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#define ENTRY_R6_LOWER 28
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#define ENTRY_SIZE 32
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/* setup the entry */
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li r4,0
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li r3,0
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li r8,1
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lis r6,EPAPR_MAGIC@h
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ori r6,r6,EPAPR_MAGIC@l
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stw r0,ENTRY_PIR(r9)
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stw r8,ENTRY_ADDR(r9)
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stw r4,ENTRY_R3(r9)
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stw r4,ENTRY_R4(r9)
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stw r6,ENTRY_R6(r9)
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stw r4,ENTRY_R7(r9)
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stw r0,ENTRY_PIR(r10)
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stw r3,ENTRY_ADDR_UPPER(r10)
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stw r8,ENTRY_ADDR_LOWER(r10)
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stw r3,ENTRY_R3_UPPER(r10)
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stw r4,ENTRY_R3_LOWER(r10)
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stw r3,ENTRY_R6_UPPER(r10)
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stw r3,ENTRY_R6_LOWER(r10)
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/* setup mapping for AS = 1, and jump there */
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lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
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mtspr SPRN_MAS0,r11
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lis r11,(MAS1_VALID|MAS1_IPROT)@h
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ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
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mtspr SPRN_MAS1,r11
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lis r11,(0xfffff000|MAS2_I)@h
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ori r11,r11,(0xfffff000|MAS2_I)@l
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mtspr SPRN_MAS2,r11
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lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
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ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
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mtspr SPRN_MAS3,r11
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tlbwe
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bl 1f
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1: mflr r11
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addi r11,r11,28
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mfmsr r13
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ori r12,r13,MSR_IS|MSR_DS@l
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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rfi
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/* spin waiting for addr */
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1: lwz r4,ENTRY_ADDR(r9)
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2:
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lwz r4,ENTRY_ADDR_LOWER(r10)
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andi. r11,r4,1
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bne 1b
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bne 2b
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/* get the upper bits of the addr */
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lwz r11,ENTRY_ADDR_UPPER(r10)
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/* setup branch addr */
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mtctr r4
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mtspr SPRN_SRR0,r4
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/* mark the entry as released */
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li r8,3
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stw r8,ENTRY_ADDR(r9)
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stw r8,ENTRY_ADDR_LOWER(r10)
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/* mask by ~64M to setup our tlb we will jump to */
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rlwinm r8,r4,0,0,5
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rlwinm r12,r4,0,0,5
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/* setup r3, r5, r6, r7 */
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lwz r3,ENTRY_R3(r9)
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lwz r4,ENTRY_R4(r9)
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/* setup r3, r4, r5, r6, r7, r8, r9 */
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lwz r3,ENTRY_R3_LOWER(r10)
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li r4,0
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li r5,0
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lwz r6,ENTRY_R6(r9)
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lwz r7,ENTRY_R7(r9)
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lwz r6,ENTRY_R6_LOWER(r10)
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lis r7,(64*1024*1024)@h
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li r8,0
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li r9,0
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/* load up the pir */
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lwz r0,ENTRY_PIR(r9)
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lwz r0,ENTRY_PIR(r10)
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mtspr SPRN_PIR,r0
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mfspr r0,SPRN_PIR
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stw r0,ENTRY_PIR(r9)
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stw r0,ENTRY_PIR(r10)
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/*
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* Coming here, we know the cpu has one TLB mapping in TLB1[0]
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@ -119,26 +149,30 @@ __secondary_start_page:
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* second mapping that maps addr 1:1 for 64M, and then we jump to
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* addr
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*/
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lis r9,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
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mtspr SPRN_MAS0,r9
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lis r9,(MAS1_VALID|MAS1_IPROT)@h
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ori r9,r9,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
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mtspr SPRN_MAS1,r9
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lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
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mtspr SPRN_MAS0,r10
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lis r10,(MAS1_VALID|MAS1_IPROT)@h
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ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
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mtspr SPRN_MAS1,r10
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/* WIMGE = 0b00000 for now */
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mtspr SPRN_MAS2,r8
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ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR)
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mtspr SPRN_MAS3,r8
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mtspr SPRN_MAS2,r12
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ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
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mtspr SPRN_MAS3,r12
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr SPRN_MAS7,r11
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#endif
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tlbwe
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/* Now we have another mapping for this page, so we jump to that
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* mapping
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*/
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bctr
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mtspr SPRN_SRR1,r13
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rfi
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.align 3
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.globl __spin_table
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__spin_table:
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.space CONFIG_NR_CPUS*24
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.space CONFIG_NR_CPUS*ENTRY_SIZE
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/* Fill in the empty space. The actual reset vector is
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* the last word of the page */
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@ -673,7 +673,7 @@ void inline show_boot_progress (int val);
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#ifdef CONFIG_MP
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int cpu_status(int nr);
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int cpu_reset(int nr);
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int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[]);
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int cpu_release(int nr, int argc, char *argv[]);
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#endif
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#endif /* __COMMON_H_ */
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