Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -192,7 +192,7 @@ long int fixed_sdram(void)
 	ddr->cs0_bnds = 0x0000001f;
 	ddr->cs0_config = 0x80010202;
 
-	ddr->ext_refrec = 0x00000000;
+	ddr->timing_cfg_3 = 0x00000000;
 	ddr->timing_cfg_0 = 0x00260802;
 	ddr->timing_cfg_1 = 0x3935d322;
 	ddr->timing_cfg_2 = 0x14904cc8;

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -130,7 +130,7 @@ fixed_sdram(void)
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
 	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
 	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;

board/sbc8548/sbc8548.c

@@ -299,7 +299,7 @@ long int fixed_sdram (void)
 	ddr->cs1_config		= 0x80010101;
 	ddr->cs2_config		= 0x00000000;
 	ddr->cs3_config		= 0x00000000;
-	ddr->ext_refrec		= 0x00000000;
+	ddr->timing_cfg_3		= 0x00000000;
 	ddr->timing_cfg_0	= 0x00220802;
 	ddr->timing_cfg_1	= 0x38377322;
 	ddr->timing_cfg_2	= 0x0fa044C7;

board/sbc8641d/sbc8641d.c

@@ -135,7 +135,7 @@ long int fixed_sdram (void)
 	ddr->cs1_config = CFG_DDR_CS1_CONFIG;
 	ddr->cs2_config = CFG_DDR_CS2_CONFIG;
 	ddr->cs3_config = CFG_DDR_CS3_CONFIG;
-	ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
 	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
 	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
@@ -166,7 +166,7 @@ long int fixed_sdram (void)
 	ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
 	ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
 	ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
-	ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
+	ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH;
 	ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
 	ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
 	ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;

cpu/mpc85xx/spd_sdram.c

@@ -610,8 +610,8 @@ spd_sdram(void)
 	/*
 	 * Sneak in some Extended Refresh Recovery.
 	 */
-	ddr->ext_refrec = (trfc_high << 16);
-	debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+	ddr->timing_cfg_3 = (trfc_high << 16);
+	debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 
 	ddr->timing_cfg_1 =
 	    (0

cpu/mpc86xx/spd_sdram.c

@@ -644,8 +644,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 	/*
 	 * Sneak in some Extended Refresh Recovery.
 	 */
-	ddr->ext_refrec = (trfc_high << 16);
-	debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+	ddr->timing_cfg_3 = (trfc_high << 16);
+	debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 
 	ddr->timing_cfg_1 =
 	    (0

include/asm-ppc/immap_85xx.h

@@ -92,7 +92,7 @@ typedef struct ccsr_ddr {
 	uint	cs2_config_2;		/* 0x20c8 - DDR Chip Select Configuration 2 */
 	uint	cs3_config_2;		/* 0x20cc - DDR Chip Select Configuration 2 */
 	char	res5[48];
-	uint	ext_refrec;		/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+	uint	timing_cfg_3;		/* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
 	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
 	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
@@ -106,8 +106,8 @@ typedef struct ccsr_ddr {
 	char	res6[4];
 	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
 	char	res7[20];
-	uint	init_address;		/* 0x2148 - DDR training initialization address */
-	uint	init_ext_address;	/* 0x214C - DDR training initialization extended address */
+	uint	init_addr;		/* 0x2148 - DDR training initialization address */
+	uint	init_ext_addr;		/* 0x214C - DDR training initialization extended address */
 	char	res8_1[16];
 	uint	timing_cfg_4;		/* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
 	uint	timing_cfg_5;		/* 0x2164 - DDR SDRAM Timing Configuration Register 5 */

include/asm-ppc/immap_86xx.h

@@ -109,7 +109,7 @@ typedef struct ccsr_ddr {
 	uint	cs4_config;		/* 0x2090 - DDR Chip Select Configuration */
 	uint	cs5_config;		/* 0x2094 - DDR Chip Select Configuration */
 	char	res7[104];
-	uint    ext_refrec;             /* 0x2100 - DDR SDRAM extended refresh recovery */
+	uint	timing_cfg_3;		/* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
 	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
 	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
@@ -126,7 +126,7 @@ typedef struct ccsr_ddr {
 	uint    sdram_ocd_cntl;		/* 0x2140 - DDR SDRAM OCD Control */
 	uint    sdram_ocd_status;	/* 0x2144 - DDR SDRAM OCD Status */
 	uint    init_addr;		/* 0x2148 - DDR training initialzation address */
-	uint    init_addr_ext;		/* 0x214C - DDR training initialzation extended address */
+	uint    init_ext_addr;		/* 0x214C - DDR training initialzation extended address */
 	char    res10[2728];
 	uint    ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
 	uint    ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */

include/configs/MPC8610HPCD.h

@@ -114,7 +114,7 @@
 #if 0 /* TODO */
 #define CFG_DDR_CS0_BNDS	0x0000000F
 #define CFG_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
-#define CFG_DDR_EXT_REFRESH	0x00000000
+#define CFG_DDR_TIMING_3	0x00000000
 #define CFG_DDR_TIMING_0	0x00260802
 #define CFG_DDR_TIMING_1	0x3935d322
 #define CFG_DDR_TIMING_2	0x14904cc8

include/configs/sbc8641d.h

@@ -136,7 +136,7 @@
     #define CFG_DDR_CS1_CONFIG	0x00000000
     #define CFG_DDR_CS2_CONFIG	0x00000000
     #define CFG_DDR_CS3_CONFIG	0x00000000
-    #define CFG_DDR_EXT_REFRESH 0x00000000
+    #define CFG_DDR_TIMING_3 0x00000000
     #define CFG_DDR_TIMING_0	0x00220802
     #define CFG_DDR_TIMING_1	0x38377322
     #define CFG_DDR_TIMING_2	0x002040c7