new PHY @ e1000 - 2nd try
Add 82541ER device with latest integrated IGP2 PHY. Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Andre Schwarz
Ben Warren
parent
c2b7da5522
commit
ac3315c26e
3
README
3
README
@ -751,6 +751,9 @@ The following options need to be configured:
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CONFIG_E1000
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Support for Intel 8254x gigabit chips.
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CONFIG_E1000_FALLBACK_MAC
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default MAC for empty eeprom after production.
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CONFIG_EEPRO100
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Support for Intel 82557/82559/82559ER chips.
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Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
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@ -1,5 +1,5 @@
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/**************************************************************************
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Inter Pro 1000 for ppcboot/das-u-boot
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Intel Pro 1000 for ppcboot/das-u-boot
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Drivers are port from Intel's Linux driver e1000-4.3.15
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and from Etherboot pro 1000 driver by mrakes at vivato dot net
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tested on both gig copper and gig fiber boards
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@ -82,6 +82,7 @@ static struct pci_device_id supported[] = {
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
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};
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/* Function forward declarations */
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@ -512,6 +513,11 @@ e1000_read_mac_addr(struct eth_device *nic)
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/* Invert the last bit if this is the second device */
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nic->enetaddr[5] += 1;
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}
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#ifdef CONFIG_E1000_FALLBACK_MAC
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if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 )
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for ( i=0; i < NODE_ADDRESS_SIZE; i++ )
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nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff;
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#endif
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#else
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/*
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* The AP1000's e1000 has no eeprom; the MAC address is stored in the
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@ -639,6 +645,9 @@ e1000_set_mac_type(struct e1000_hw *hw)
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case E1000_DEV_ID_82546EB_FIBER:
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hw->mac_type = e1000_82546;
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break;
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case E1000_DEV_ID_82541ER:
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hw->mac_type = e1000_82541_rev_2;
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break;
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default:
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/* Should never have loaded on this device */
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return -E1000_ERR_MAC_TYPE;
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@ -2485,6 +2494,36 @@ e1000_phy_reset(struct e1000_hw *hw)
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return 0;
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}
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static int
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e1000_set_phy_type(struct e1000_hw *hw)
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{
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DEBUGFUNC();
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if(hw->mac_type == e1000_undefined)
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return -E1000_ERR_PHY_TYPE;
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switch(hw->phy_id) {
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case M88E1000_E_PHY_ID:
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case M88E1000_I_PHY_ID:
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case M88E1011_I_PHY_ID:
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hw->phy_type = e1000_phy_m88;
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break;
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case IGP01E1000_I_PHY_ID:
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if(hw->mac_type == e1000_82541 ||
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hw->mac_type == e1000_82541_rev_2) {
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hw->phy_type = e1000_phy_igp;
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break;
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}
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/* Fall Through */
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default:
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/* Should never have loaded on this device */
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hw->phy_type = e1000_phy_undefined;
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return -E1000_ERR_PHY_TYPE;
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}
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return E1000_SUCCESS;
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}
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/******************************************************************************
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* Probes the expected PHY address for known PHY IDs
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*
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@ -2493,6 +2532,7 @@ e1000_phy_reset(struct e1000_hw *hw)
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static int
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e1000_detect_gig_phy(struct e1000_hw *hw)
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{
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int32_t phy_init_status;
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uint16_t phy_id_high, phy_id_low;
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int match = FALSE;
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@ -2526,11 +2566,19 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
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if (hw->phy_id == M88E1011_I_PHY_ID)
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match = TRUE;
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break;
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case e1000_82541_rev_2:
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if(hw->phy_id == IGP01E1000_I_PHY_ID)
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match = TRUE;
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break;
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default:
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DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
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return -E1000_ERR_CONFIG;
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}
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if (match) {
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phy_init_status = e1000_set_phy_type(hw);
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if ((match) && (phy_init_status == E1000_SUCCESS)) {
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DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
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return 0;
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}
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@ -2985,7 +3033,7 @@ e1000_initialize(bd_t * bis)
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free(nic);
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return 0;
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}
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#ifndef CONFIG_AP1000
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#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
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if (e1000_validate_eeprom_checksum(nic) < 0) {
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printf("The EEPROM Checksum Is Not Valid\n");
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free(hw);
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@ -71,6 +71,8 @@ typedef enum {
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e1000_82540,
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e1000_82545,
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e1000_82546,
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e1000_82541,
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e1000_82541_rev_2,
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e1000_num_macs
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} e1000_mac_type;
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@ -168,6 +170,13 @@ typedef enum {
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e1000_1000t_rx_status_undefined = 0xFF
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} e1000_1000t_rx_status;
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typedef enum {
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e1000_phy_m88 = 0,
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e1000_phy_igp,
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e1000_phy_igp_2,
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e1000_phy_undefined = 0xFF
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} e1000_phy_type;
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struct e1000_phy_info {
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e1000_cable_length cable_length;
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e1000_10bt_ext_dist_enable extended_10bt_distance;
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@ -184,14 +193,19 @@ struct e1000_phy_stats {
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};
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/* Error Codes */
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#define E1000_SUCCESS 0
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#define E1000_ERR_EEPROM 1
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#define E1000_ERR_PHY 2
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#define E1000_ERR_CONFIG 3
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#define E1000_ERR_PARAM 4
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#define E1000_ERR_MAC_TYPE 5
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#define E1000_ERR_NOLINK 6
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#define E1000_ERR_TIMEOUT 7
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#define E1000_SUCCESS 0
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#define E1000_ERR_EEPROM 1
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#define E1000_ERR_PHY 2
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#define E1000_ERR_CONFIG 3
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#define E1000_ERR_PARAM 4
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#define E1000_ERR_MAC_TYPE 5
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#define E1000_ERR_PHY_TYPE 6
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#define E1000_ERR_NOLINK 7
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#define E1000_ERR_TIMEOUT 8
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#define E1000_ERR_RESET 9
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#define E1000_ERR_MASTER_REQUESTS_PENDING 10
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#define E1000_ERR_HOST_INTERFACE_COMMAND 11
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#define E1000_BLK_PHY_RESET 12
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/* PCI Device IDs */
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#define E1000_DEV_ID_82542 0x1000
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@ -207,7 +221,8 @@ struct e1000_phy_stats {
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#define E1000_DEV_ID_82545EM_FIBER 0x1011
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#define E1000_DEV_ID_82546EB_COPPER 0x1010
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#define E1000_DEV_ID_82546EB_FIBER 0x1012
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#define NUM_DEV_IDS 13
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#define E1000_DEV_ID_82541ER 0x1078
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#define NUM_DEV_IDS 14
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#define NODE_ADDRESS_SIZE 6
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#define ETH_LENGTH_OF_ADDRESS 6
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@ -799,6 +814,8 @@ struct e1000_hw {
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pci_dev_t pdev;
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uint8_t *hw_addr;
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e1000_mac_type mac_type;
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e1000_phy_type phy_type;
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uint32_t phy_init_script;
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e1000_media_type media_type;
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e1000_lan_loc lan_loc;
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e1000_fc_type fc;
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@ -1517,7 +1534,22 @@ struct e1000_hw {
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#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
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#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
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#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
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#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
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/* IGP01E1000 specifics */
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#define IGP01E1000_IEEE_REGS_PAGE 0x0000
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#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
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#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
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/* IGP01E1000 Specific Registers */
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#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
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#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
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#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
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#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
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#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
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#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
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#define IGP02E1000_PHY_POWER_MGMT 0x19
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#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
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/* PHY Control Register */
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#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
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@ -1729,6 +1761,7 @@ struct e1000_hw {
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#define M88E1011_I_PHY_ID 0x01410C20
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#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
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#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
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#define IGP01E1000_I_PHY_ID 0x02A80380
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/* Miscellaneous PHY bit definitions. */
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#define PHY_PREAMBLE 0xFFFFFFFF
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@ -1810,6 +1810,7 @@
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#define PCI_DEVICE_ID_INTEL_82434 0x04a3
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#define PCI_DEVICE_ID_INTEL_I960 0x0960
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#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
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#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
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#define PCI_DEVICE_ID_INTEL_82542 0x1000
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#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
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#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004
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