ppc4xx: Fix comment in 405EX DDR2 init code
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
parent
b8aa57b5d4
commit
e4170e5a50
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* (C) Copyright 2007
|
||||
* (C) Copyright 2007-2008
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Based on code provided from UDTech and AMCC
|
||||
@ -64,7 +64,7 @@ ext_bus_cntlr_init:
|
||||
/* SET SDRAM_MB3CF - Not enabled */
|
||||
mtsdram_as(SDRAM_MB3CF, 0x00000000);
|
||||
|
||||
/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
|
||||
/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
|
||||
mtsdram_as(SDRAM_CLKTR, 0x80000000);
|
||||
|
||||
/* Refresh Time register (0x30) Refresh every 7.8125uS */
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* (C) Copyright 2007
|
||||
* (C) Copyright 2007-2008
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Based on code provided from Senao and AMCC
|
||||
@ -57,7 +57,7 @@ ext_bus_cntlr_init:
|
||||
/* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
|
||||
mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
|
||||
|
||||
/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
|
||||
/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
|
||||
mtsdram_as(SDRAM_CLKTR,0x80000000);
|
||||
|
||||
/* Refresh Time register (0x30) Refresh every 7.8125uS */
|
||||
|
Loading…
Reference in New Issue
Block a user