mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) code
in the spirit of commit 1ced121600,
85xx's "Update SVR numbers to expand support", simplify SPRIDR processing
and processor ID display. Add REVID_{MAJ,MIN}OR macros to make
REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR
convenience macros.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Kim Phillips
parent
81fd52c6c8
commit
e5c4ade4db
@ -98,11 +98,8 @@ int board_early_init_f(void)
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/* Enable flash write */
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bcsr[0xa] &= ~0x04;
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/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
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if (immr->sysconf.spridr == SPR_8360_REV20 ||
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immr->sysconf.spridr == SPR_8360E_REV20 ||
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immr->sysconf.spridr == SPR_8360_REV21 ||
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immr->sysconf.spridr == SPR_8360E_REV21)
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/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
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if (REVID_MAJOR(immr->sysconf.spridr) == 2)
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bcsr[0xe] = 0x30;
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/* Enable second UART */
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@ -308,8 +305,8 @@ void ft_board_setup(void *blob, bd_t *bd)
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* if on mpc8360ea rev. 2.1,
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* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
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*/
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if (immr->sysconf.spridr == SPR_8360_REV21 ||
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immr->sysconf.spridr == SPR_8360E_REV21) {
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if ((REVID_MAJOR(immr->sysconf.spridr) == 2) &&
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(REVID_MINOR(immr->sysconf.spridr) == 1)) {
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int nodeoffset;
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const char *prop;
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int path;
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@ -36,26 +36,23 @@ int board_early_init_f(void)
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* we check only part num, and don't look for CPU revisions */
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switch (spridr >> 16) {
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case SPR_8379E_REV10 >> 16:
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case SPR_8379_REV10 >> 16:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378E_REV10 >> 16:
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case SPR_8378_REV10 >> 16:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8377E_REV10 >> 16:
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case SPR_8377_REV10 >> 16:
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switch (spridr) {
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case SPR_8377:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8379:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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default:
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printf("serdes not configured: unknown CPU part number: "
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"%04x\n", spridr >> 16);
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@ -140,26 +140,23 @@ int board_early_init_f(void)
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* we check only part num, and don't look for CPU revisions */
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switch (spridr >> 16) {
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case SPR_8379E_REV10 >> 16:
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case SPR_8379_REV10 >> 16:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378E_REV10 >> 16:
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case SPR_8378_REV10 >> 16:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8377E_REV10 >> 16:
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case SPR_8377_REV10 >> 16:
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switch (PARTID_NO_E(spridr)) {
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case SPR_8377:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8379:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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default:
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printf("serdes not configured: unknown CPU part number: "
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"%04x\n", spridr >> 16);
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@ -42,6 +42,30 @@ int checkcpu(void)
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u32 pvr = get_pvr();
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u32 spridr;
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char buf[32];
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int i;
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#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
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const struct cpu_type {
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char name[15];
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u32 partid;
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} cpu_type_list [] = {
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CPU_TYPE_ENTRY(8311),
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CPU_TYPE_ENTRY(8313),
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CPU_TYPE_ENTRY(8314),
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CPU_TYPE_ENTRY(8315),
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CPU_TYPE_ENTRY(8321),
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CPU_TYPE_ENTRY(8323),
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CPU_TYPE_ENTRY(8343),
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CPU_TYPE_ENTRY(8347_TBGA_),
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CPU_TYPE_ENTRY(8347_PBGA_),
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CPU_TYPE_ENTRY(8349),
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CPU_TYPE_ENTRY(8358_TBGA_),
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CPU_TYPE_ENTRY(8358_PBGA_),
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CPU_TYPE_ENTRY(8360),
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CPU_TYPE_ENTRY(8377),
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CPU_TYPE_ENTRY(8378),
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CPU_TYPE_ENTRY(8379),
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};
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immr = (immap_t *)CFG_IMMR;
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@ -69,130 +93,26 @@ int checkcpu(void)
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}
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spridr = immr->sysconf.spridr;
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switch(spridr) {
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case SPR_8349E_REV10:
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case SPR_8349E_REV11:
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case SPR_8349E_REV31:
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puts("MPC8349E, ");
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break;
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case SPR_8349_REV10:
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case SPR_8349_REV11:
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case SPR_8349_REV31:
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puts("MPC8349, ");
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break;
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case SPR_8347E_REV10_TBGA:
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case SPR_8347E_REV11_TBGA:
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case SPR_8347E_REV31_TBGA:
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case SPR_8347E_REV10_PBGA:
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case SPR_8347E_REV11_PBGA:
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case SPR_8347E_REV31_PBGA:
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puts("MPC8347E, ");
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break;
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case SPR_8347_REV10_TBGA:
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case SPR_8347_REV11_TBGA:
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case SPR_8347_REV31_TBGA:
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case SPR_8347_REV10_PBGA:
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case SPR_8347_REV11_PBGA:
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case SPR_8347_REV31_PBGA:
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puts("MPC8347, ");
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break;
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case SPR_8343E_REV10:
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case SPR_8343E_REV11:
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case SPR_8343E_REV31:
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puts("MPC8343E, ");
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break;
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case SPR_8343_REV10:
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case SPR_8343_REV11:
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case SPR_8343_REV31:
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puts("MPC8343, ");
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break;
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case SPR_8360E_REV10:
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case SPR_8360E_REV11:
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case SPR_8360E_REV12:
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case SPR_8360E_REV20:
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case SPR_8360E_REV21:
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puts("MPC8360E, ");
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break;
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case SPR_8360_REV10:
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case SPR_8360_REV11:
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case SPR_8360_REV12:
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case SPR_8360_REV20:
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case SPR_8360_REV21:
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puts("MPC8360, ");
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break;
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case SPR_8323E_REV10:
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case SPR_8323E_REV11:
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puts("MPC8323E, ");
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break;
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case SPR_8323_REV10:
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case SPR_8323_REV11:
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puts("MPC8323, ");
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break;
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case SPR_8321E_REV10:
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case SPR_8321E_REV11:
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puts("MPC8321E, ");
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break;
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case SPR_8321_REV10:
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case SPR_8321_REV11:
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puts("MPC8321, ");
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break;
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case SPR_8311_REV10:
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puts("MPC8311, ");
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break;
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case SPR_8311E_REV10:
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puts("MPC8311E, ");
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break;
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case SPR_8313_REV10:
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puts("MPC8313, ");
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break;
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case SPR_8313E_REV10:
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puts("MPC8313E, ");
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break;
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case SPR_8315E_REV10:
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puts("MPC8315E, ");
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break;
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case SPR_8315_REV10:
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puts("MPC8315, ");
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break;
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case SPR_8314E_REV10:
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puts("MPC8314E, ");
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break;
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case SPR_8314_REV10:
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puts("MPC8314, ");
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break;
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case SPR_8379E_REV10:
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puts("MPC8379E, ");
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break;
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case SPR_8379_REV10:
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puts("MPC8379, ");
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break;
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case SPR_8378E_REV10:
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puts("MPC8378E, ");
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break;
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case SPR_8378_REV10:
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puts("MPC8378, ");
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break;
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case SPR_8377E_REV10:
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puts("MPC8377E, ");
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break;
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case SPR_8377_REV10:
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puts("MPC8377, ");
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break;
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default:
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printf("Rev: Unknown revision number:%08x\n"
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"Warning: Unsupported cpu revision!\n",spridr);
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return 0;
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}
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#if defined(CONFIG_MPC834X)
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/* Multiple revisons of 834x processors may have the same SPRIDR value.
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* So use PVR to identify the revision number.
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*/
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printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
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#else
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printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
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#endif
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printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
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puts("MPC");
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puts(cpu_type_list[i].name);
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if (IS_E_PROCESSOR(spridr))
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puts("E");
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if (REVID_MAJOR(spridr) >= 2)
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puts("A");
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printf(", Rev: %d.%d", REVID_MAJOR(spridr),
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REVID_MINOR(spridr));
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break;
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}
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if (i == ARRAY_SIZE(cpu_type_list))
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printf("(SPRIDR %08x unknown), ", spridr);
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printf(" at %s MHz, ", strmhz(buf, clock));
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printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
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return 0;
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}
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@ -48,71 +48,36 @@
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/* SPRIDR - System Part and Revision ID Register
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*/
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#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
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#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
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#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
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#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
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#define SPR_8349E_REV10 0x80300100
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#define SPR_8349_REV10 0x80310100
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#define SPR_8347E_REV10_TBGA 0x80320100
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#define SPR_8347_REV10_TBGA 0x80330100
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#define SPR_8347E_REV10_PBGA 0x80340100
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#define SPR_8347_REV10_PBGA 0x80350100
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#define SPR_8343E_REV10 0x80360100
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#define SPR_8343_REV10 0x80370100
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#if defined(CONFIG_MPC834X)
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#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
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#define REVID_MINOR(spridr) (spridr & 0x000000FF)
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#else
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#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
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#define REVID_MINOR(spridr) (spridr & 0x0000000F)
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#endif
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#define SPR_8349E_REV11 0x80300101
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#define SPR_8349_REV11 0x80310101
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#define SPR_8347E_REV11_TBGA 0x80320101
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#define SPR_8347_REV11_TBGA 0x80330101
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#define SPR_8347E_REV11_PBGA 0x80340101
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#define SPR_8347_REV11_PBGA 0x80350101
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#define SPR_8343E_REV11 0x80360101
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#define SPR_8343_REV11 0x80370101
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#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
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#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) /* has SEC */
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#define SPR_8349E_REV31 0x80300300
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#define SPR_8349_REV31 0x80310300
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#define SPR_8347E_REV31_TBGA 0x80320300
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#define SPR_8347_REV31_TBGA 0x80330300
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#define SPR_8347E_REV31_PBGA 0x80340300
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#define SPR_8347_REV31_PBGA 0x80350300
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#define SPR_8343E_REV31 0x80360300
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#define SPR_8343_REV31 0x80370300
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#define SPR_8360E_REV10 0x80480010
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#define SPR_8360_REV10 0x80490010
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#define SPR_8360E_REV11 0x80480011
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#define SPR_8360_REV11 0x80490011
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#define SPR_8360E_REV12 0x80480012
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#define SPR_8360_REV12 0x80490012
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#define SPR_8360E_REV20 0x80480020
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#define SPR_8360_REV20 0x80490020
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#define SPR_8360E_REV21 0x80480021
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#define SPR_8360_REV21 0x80490021
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#define SPR_8323E_REV10 0x80620010
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#define SPR_8323_REV10 0x80630010
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#define SPR_8321E_REV10 0x80660010
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#define SPR_8321_REV10 0x80670010
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#define SPR_8323E_REV11 0x80620011
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#define SPR_8323_REV11 0x80630011
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#define SPR_8321E_REV11 0x80660011
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#define SPR_8321_REV11 0x80670011
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#define SPR_8313E_REV10 0x80B00010
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#define SPR_8313_REV10 0x80B10010
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#define SPR_8311E_REV10 0x80B20010
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#define SPR_8311_REV10 0x80B30010
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#define SPR_8315E_REV10 0x80B40010
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#define SPR_8315_REV10 0x80B50010
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#define SPR_8314E_REV10 0x80B60010
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#define SPR_8314_REV10 0x80B70010
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#define SPR_8379E_REV10 0x80C20010
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#define SPR_8379_REV10 0x80C30010
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#define SPR_8378E_REV10 0x80C40010
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#define SPR_8378_REV10 0x80C50010
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#define SPR_8377E_REV10 0x80C60010
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#define SPR_8377_REV10 0x80C70010
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#define SPR_8311 0x80B2
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#define SPR_8313 0x80B0
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#define SPR_8314 0x80B6
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#define SPR_8315 0x80B4
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#define SPR_8321 0x8066
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#define SPR_8323 0x8062
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#define SPR_8343 0x8036
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#define SPR_8347_TBGA_ 0x8032
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#define SPR_8347_PBGA_ 0x8034
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#define SPR_8349 0x8030
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#define SPR_8358_TBGA_ 0x804A
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#define SPR_8358_PBGA_ 0x804E
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#define SPR_8360 0x8048
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#define SPR_8377 0x80C6
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#define SPR_8378 0x80C4
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||||
#define SPR_8379 0x80C2
|
||||
|
||||
/* SPCR - System Priority Configuration Register
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user