TSEC: add config options for VSC8601 RGMII PHY
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx and Tx clock lines. They are configured using 2 bits in extended register 0x17. Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Ben Warren <biggerbadderben@gmail.com> -- drivers/net/tsec.c | 6 ++++++ drivers/net/tsec.h | 3 +++ 2 files changed, 9 insertions(+), 0 deletions(-)
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@ -1277,6 +1277,12 @@ struct phy_info phy_info_VSC8601 = {
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{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
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#ifdef CFG_VSC8601_SKEWFIX
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{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
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if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
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{MIIM_EXT_PAGE_ACCESS,1,NULL},
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#define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
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{MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
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{MIIM_EXT_PAGE_ACCESS,0,NULL},
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#endif
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#endif
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{miim_end,}
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},
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@ -112,6 +112,8 @@
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#define MIIM_GBIT_CONTROL 0x9
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#define MIIM_GBIT_CONTROL_INIT 0xe00
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#define MIIM_EXT_PAGE_ACCESS 0x1f
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/* Broadcom BCM54xx -- taken from linux sungem_phy */
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#define MIIM_BCM54xx_AUXSTATUS 0x19
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#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
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@ -161,8 +163,9 @@
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/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
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/* Vitesse VSC8601 Extended PHY Control Register 1 */
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#define MIIM_VSC8601_EPHY_CON 0x17
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#define MIIM_VSC8601_EPHY_CON 0x17
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#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
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#define MIIM_VSC8601_SKEW_CTRL 0x1c
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/* 88E1011 PHY Status Register */
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#define MIIM_88E1011_PHY_STATUS 0x11
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@ -177,9 +180,9 @@
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#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
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/* 88E1111 PHY LED Control Register */
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#define MIIM_88E1111_PHY_LED_CONTROL 24
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#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
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#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
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#define MIIM_88E1111_PHY_LED_CONTROL 24
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#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
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#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
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/* 88E1145 Extended PHY Specific Control Register */
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#define MIIM_88E1145_PHY_EXT_CR 20
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