The following commit introduced some warnings associated with using
pci_addr_t instead of a proper 32-bit data type.
commit af778c6d9e
Author: Andrew Sharp <andywyse6@gmail.com>
Date: Wed Aug 1 12:27:16 2012 +0000
pci: fix errant data types and corresponding access functions
On some platforms pci_addr_t is defined as a 64-bit data type so its not
proper to use with pci_{read,write}_config_dword.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This makes it easier to include this header from other headers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The new debugging shows the value of integers and addresses read
from the device tree and tidy up GPIO output.
Signed-off-by: Simon Glass <sjg@chromium.org>
After further investigation this change is not correct and results in
get_ram_size returning incorrectly large values. Reported first by
Gerlando Falauto.
This reverts commit b8496cced8.
Signed-off-by: Tom Rini <trini@ti.com>
usb_hub_descriptor has to be packed as it's used for
communication with the device. Member wHubCharacteristics
violates the natural alignment rules.
Use explicit unaligned access functions for this member.
Fixes ARMv7 traping while using USB.
v2: fix typo found by Thomas Langer
v3: rebased on top of u-boot-usb/master
Signed-off-by: Lucas Stach <dev@lynxeye.de>
DMA buffer cache invalidation requires that buffers have cache-aligned
buffer locations and sizes. Use memalign() and ALLOC_CACHE_ALIGN_BUFFER()
to ensure this.
On Tegra at least, without this fix, the following fail commands fail in
u-boot-master/ext4, but succeeded at the branch's branch point in
u-boot/master. With this fix, the commands work again:
ext2ls mmc 0:1 /
ext2load mmc 0:1 /boot/zImage
Cc: Uma Shankar <uma.shankar@samsung.com>
Cc: Manjunatha C Achar <a.manjunatha@samsung.com>
Cc: Iqbal Shareef <iqbal.ams@samsung.com>
Cc: Hakgoo Lee <goodguy.lee@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
originally work by Jate Sujjavanich <jsujjavanich@syntech-fuelmaster.com>
----
The defines in arch/m68k/include/coldfire/flexbus.h are not compatible with
the 5235 processor. The registers in struct fbcs are different sizes from
those in the 5235. Also, the defines are a little different.
This is what I have so far. Comments?
----
Reformat the patch manually by Jason Jin
Signed-off-by: Jate Sujjavanich <jsujjavanich@syntech-fuelmaster.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.
Tested with MCF5270 which have 4 chip selects.
Activate by #define CONFIG_CF_QSPI in board config.
Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
This patch uses the general ffs definition to replace the
platform ffs definition.
This patch also fixes the build error by adding hweightN
definition for m5329evb and m5373evb.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
This patch fixes the build error for MCF537x. As the NANDFLASH_SIZE is
redefined in boards.cfg, it is needed to rename NANDFLASH_SIZE into
CONFIG_NANDFLASH_SIZE in include/configs/M5373EVB.h.
Signed-off-by: Alison Wang <b18965@freescale.com>
Add support for the onboard eSDHC MMC controller. The hardware on the
MPC8308RDB has the following errata:
- ESDHC111: manual asynchronous CMD12 is broken
- DMA is broken (PIO works)
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
[added include fsl_esdhc header to prevent implicit declarations of
fsl_esdhc_mmc_init() and fdt_fixup_esdhc()]
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The SPI pins are routed to header J8 for testing SPI functionality. A
Spansion flash has been wired up and tested on this header.
This patch breaks support for the second TSEC interface, since the GPIO
pin used as a chip select is pinmuxed with some of the TSEC pins.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The MPC8308RDB Reference Manual states that no bits in the SPMODE
register are allowed to change while the enable (EN) bit is set.
This driver changes the character length bits (LEN) while the enable
(EN) bit is set. Clearing the EN bit while changing the LEN bits makes
the driver work correctly on MPC8308RDB.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
With:
fatls mmc 0 /dir/file
dir: regular directory
file: regular file
The previous code read the contents of file as if it were directory entries to
list. This patch refuses to list file contents as if it were a folder.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
When variables explicitly specified on the command line are not present
in the imported env, delete them from the running env.
If the variable is also missing from the running env, issue a warning.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Change the syntax (user API) for "env default":
-f: override write-once variables
var... : accept individual variable(s)
-a: all (resetting the whole env is NOT the default behavior)
Enable variable checking and make changes effective by
enabling do_apply argument to himport_r().
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Change hashtable so that a callback function will decide whether a
variable can be overwritten, and possibly apply the changes.
So add a new field to struct hsearch_data:
o "apply" callback function to check whether a variable can be
overwritten, and possibly immediately apply the changes;
when NULL, no check is performed.
And a new argument to himport_r():
o "do_apply": whether to call the apply callback function
NOTE: This patch does not change the current behavior.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add 2 new arguments to himport_r():
o "nvars", "vars": number and list of variables to take into account
(0 means ALL)
NOTE: This patch does not change the current behaviour.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The logic of checking special parameters (e.g. baudrate, stdin, stdout,
for a valid value and/or whether can be overwritten) and applying the
new value to the running system is now all within a single function
env_check_apply() which can be called whenever changes are made
to the environment, no matter if by set, default or import.
With this patch env_check_apply() is only called by "env set",
retaining previous behavior.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
iomux_doenv() can only return 0 or 1.
So there is no need to save its return value in variable i, as checking
its truth value within an if statement is enough.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The original memory sizing code in get_ram_size clobbers the word
at the base address, but forgets to restore it.
Signed-off-by: Iwo Mergler <Iwo.Mergler@netcommwireless.com>
The third parameter to ALLOC_CACHE_ALIGN_BUFFER is not size (as named),
but rather count (number of elements of the type to allocate). The
current code ends up allocating one copy of env_t for each byte in its
size, which quite possibly ends up overflowing RAM.
This fixes a bug in commit 3801a15 "env_nand: align NAND buffers".
Reported-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reported-by: Prabhakar Lad <prabhakar.lad@ti.com>
This board is the only board that still sticks to OneNAND IPL.
Remove this board, since we have SPL around for a while and
OneNAND is well supported in the SPL framework. The board can
be revived if necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Tom Rini <trini@ti.com>
Remove linker command line options from the SPL makefile
that force the inclusion of unreferenced command code from
linked object files. As commands are not used in the SPL,
these options resulted in an unnecessary increase in the
image size, in addition to introducing the possibility of
tricky link errors in the case where the command code
contained symbols that were not resolved by linking in the
limited objects compiled in the SPL build.
Signed-off-by: Tyler Olmstead <tyler.j.olmstead@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
cmd_bdinfo.c: In function ‘do_bdinfo’:
cmd_bdinfo.c:220:9: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘int’ [-Wformat]
cmd_bdinfo.c:222:9: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘int’ [-Wformat]
cmd_bdinfo.c:224:9: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘int’ [-Wformat]
cmd_bdinfo.c:226:9: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘int’ [-Wformat]
cmd_bdinfo.c:228:9: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘int’ [-Wformat]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: u-boot-dm@lists.denx.de
greth.c: In function ‘greth_recv’:
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘unsigned int’ [-Wformat]
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘unsigned int’ [-Wformat]
greth.c:541:6: warning: pointer targets in assignment differ in signedness [-Wpointer-sign]
greth.c: In function ‘greth_initialize’:
greth.c:623:2: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:655:3: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:684:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: u-boot-dm@lists.denx.de
There is no reason to have board configs to select the NFC IP revision. Just let
the driver detect it. BTW, remove broken NFC IP revision configs from board
config files.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Do not stop boot as soon as an ECC error is detected. Only stop boot for
uncorrectable ECC errors.
This fixes boards no longer booting after some time because a NAND Flash bit has
flipped.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
On the NFC IP 1.1, the 32-bit ecc_status_result value comes from 2
consecutive 16-bit registers. This patch reads all the fields of this value,
which makes a difference for 4-kiB NF pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Set the spl mxc nand driver for IP 1.1 in symmetric mode, like the mtd driver.
In this way, for both drivers, one input clock period of the NFC IP will produce
one R/W cycle.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This is based on Linux kernel -next:
commit 14f44abf1dafc20ba42ce8616a8fc8fbd1b3712b
Author: Brian Norris <computersforpeace@gmail.com>
Date: Fri Jul 13 09:28:24 2012 -0700
mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is not
the same as others. Instead of bit 1 being lock, it is #lock_tight.
To make the driver support either format, ignore bit 1 and use only
bit 0 and bit 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND unlock command allows an invert bit to be set to unlock all but
the selected page range.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[scottwood@freescale.com: updated docs and added comment about invert bit]
Signed-off-by: Scott Wood <scottwood@freescale.com>
With onfi a flash is organized into one or more logical units (LUNs).
A logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Artem: split long line on 2 shorter ones.
This is commit 637957551c0ac80de8dfc7650d320c5a98c2c0c0 from Linux
Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com>
Acked-by: Florian Fainelli <ffainelli@freebox.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
[scottwood@freescale.com: picked from Linux into U-Boot]
Reported-by: Rafael Beims <rafael.beims@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The environment has been based on mx53loco and m28evk but keeping the
possibility to easy change the default console device as Freescale and
mainline kernels differ on the device name.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Constants set with binary value (0b...) are not compiled
from old toolchain when used by the clrsetbits_le32 macro.
Replaces them with the corresponding hex value.
The error reported (for example with the mx6qsabrelite board)
is something like:
mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant
Signed-off-by: Stefano Babic <sbabic@denx.de>
Support for multiple soft I2C buses.
Multibus I2C support is achieved by defining get_multi_{sda|scl}_pin
functions to switch between multiple "soft" I2C buses.
Common definition of I2C_X I2C buses is provided at <i2c.h>.
TEST HW:
Samsung's Exynos4210 evt.0.1 - Trats development board
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Heiko Schocher <hs@denx.de>
In case the "fdt addr" command wasn't ran yet and any other "fdt"
subcommand was issued, the system crashed due to NULL pointer being
used.
This is caused by "fdt addr" command setting up a pointer to the
FDT memory location. Prior issuing "fdt addr", the pointer is NULL
so calling any other subcommands crashed the u-boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
This fixes the following warnings in dlmalloc seen with my gcc 4.6.
dlmalloc.c: In function 'malloc_bin_reloc':
dlmalloc.c:1493: warning: dereferencing pointer 'p' does break strict-aliasing rules
dlmalloc.c:1493: warning: dereferencing pointer 'p' does break strict-aliasing rules
dlmalloc.c:1490: note: initialized from here
dlmalloc.c:1493: note: initialized from here
This version is tested on avr32 arch boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Move board specific function to board_init function in board/ folder
Remove externs from generic board.c
Use board_init_f function in board.c file.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
Fix CONFIG_SYS_HZ usage in board config.
Do not use hardcoded value. Use CONFIG_SYS_HZ instead.
Separate static configuration to single block.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Variable is used when CONFIG_SYS_FLASH_CHECKSUM is used.
Warning log:
board.c: In function 'board_init':
board.c:101: warning: unused variable 's'
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
This is minimum code required to be able to use device-tree
for u-boot initialization.
Currently only for device driver initialization.
Linker script change ensures DTB to be aligned
for both options CONFIG_OF_EMBED and CONFIG_OF_SEPARATE.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
CC: Simon Glass <sjg@chromium.org>
Warning is:
xilinx_spi.c: In function 'spi_setup_slave':
xilinx_spi.c:81: warning: unused variable 'regs'
Signed-off-by: Stephan Linz <linz@li-pro.net>
CC: Michal Simek <monstr@monstr.eu>
Initialize all possible uartlites and return the first
initialized port. For static configuration is initialization
done in userial_ports array.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
Use CONFIG parameters only at one location to simplify
the code. Also create ace_readw/writew functions.
Signed-off-by: Michal Simek <monstr@monstr.eu>
With Simon Glass's include/nand.h alignment changes, some mxs builds
were generating errors. Fix is to ensure asm/cache.h is included before
linux/mtd/nand.h. Moving common.h to top of include list does that.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.
Upcoming Tegra30 port will use common code/defines/names where possible.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
This allows for two things:
- VBus GPIO may be used on other ports than the OTG one
- VBus GPIO may be low active if specified by DT
Signed-off-by: Lucas Stach <dev@lynxeye.de>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <TWarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Up now only MX5 and MX6 can share code, because they have
a common source directory in cpu/armv7. Other not armv7
i.MX can profit of the same shared code. Move these files
into a directory accessible for all, similar to plat-mxc
in linux.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Using ZLIB compression with UBIFS fails if last data node is not a size of
UBIFS_BLOCK_SIZE (4096 bytes).
Easiest way to test this is trying to read a file smaller than 4k:
=> ubifsload 41000000 /etc/fstab
Loading file '/etc/fstab' to addr 0x41000000 with size 704 (0x000002c0)...
UBIFS error (pid 0): read_block: bad data node (block 0, inode 2506)
UBIFS error (pid 0): do_readpage: cannot read page 0 of inode 2506, error -22
Error reading file '/etc/fstab'
/etc/fstab not found!
exit not allowed from main input shell.
=>
With this patch:
=> ubifsload 41000000 /etc/fstab
Loading file '/etc/fstab' to addr 0x41000000 with size 704 (0x000002c0)...
Done
=>
Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Cc: kmpark@infradead.org
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Ventana always pulls in files from the Seaboard directory, so needs to
mkdir $(obj)../seaboard unconditionally. This fixes:
git clean -f -d -x
./MAKEALL ventana
"MAKEALL -s tegra20" passes without this change, because Seaboard
happens to be built before Ventana, and hence the directory has already
been created.
I believe the mkdir is only needed for out-of-tree builds, since the
seaboard directory is part of the source tree. However, since we always
build an SPL for Tegra now, which I believe is effectively an out-of-tree
build, we will always need this at some time. The overhead of just
uncondtionally executing the mkdir is minimal, and simplifies the
Makefile, since we don't need to code up the exact minimal condition to
execute the mkdir.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
None of harmony, seaboard, ventana, whistler directly build files from
../common/, so there's no need to mkdir the obj directory for such files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When I set up Tegra's config files to put the environment into eMMC, I
assumed that CONFIG_ENV_OFFSET was a linearized address relative to the
start of the eMMC device, and spanning HW partitions boot0, boot1,
general* and the user area in order. However, it turns out that the
offset is actually relative to the beginning of the user area. Hence,
the environment block ended up in a different location to expected and
documented.
Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust
CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire
eMMC.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
eMMC devices may have hardware-level partitions: 2 boot partitions,
up to 4 general partitions, plus the user area. This change introduces
optional config variable CONFIG_SYS_MMC_ENV_PART to indicate which
partition the environment should be stored in: 0=user, 1=boot0, 2=boot1,
4..7=general0..3. This allows the environment to be kept out of the user
area, which simplifies the management of OS-/user-level (MBR/GPT)
partitions within the user area.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables access to boot partitions solely based
on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only
influences access to "general" partitions.
eMMC devices affected by this issue exist on various NVIDIA Tegra
platforms (and presumably many others too), such as Harmony (plug-in eMMC),
Seaboard, Springbank, and Whistler (plug-in eMMC).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit enables NAND support on the Tamonten Evaluation Carrier and
adds the corresponding device tree nodes. Furthermore, the U-Boot
environment can now be stored in NAND.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In order for cache invalidation and flushing to work properly, the data
and OOB buffers must be aligned to full cache lines.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A device tree is used to configure the NAND, including memory
timings and block/pages sizes.
If this node is not present or is disabled, then NAND will not
be initialized.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a flash node to handle the NAND, including memory timings and
page / block size information.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
There were a couple of drivers that were actually using the flags
field of the cmd structure, despite the fact that no one ever
*set* that field. When we removed the field, those drivers failed
to compile. Replaced the references with the correct usage of
resp_type.
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch prevents dcache-related problem. The problem manifested
itself on the SPI driver, this is just a port to the MMC driver.
The scenario is the same. In case an "mmc read" is issued to a
buffer which was written right before it and data cache is enabled,
the cache eviction might happen during the DMA transfer into the
buffer, therefore corrupting the buffer. Clear any cache lines that
might contain the buffer to prevent such issue.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
This patch fixes dcache-related problem. The problem manifested
when dcache was enabled and the following command issued twice:
mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000
The SHA1 checksum was correct during the first call. Yet with
every subsequent call of the above command, it differed and was
wrong.
It turns out this was because of a race condition. On the first
time the command was called, no cacheline contained any data from
the destination memory location. The DMA transfered data into the
location and the cache above the location was invalidated. Then the
checksum was computed, but that meant the data were loaded into data
cache.
On any subsequent call, the DMA again transfered data into the same
destination. Yet during the transfer, some of the DCache lines were
evicted and written back into the main memory. Once the DMA transfer
completed, the data cache was invalidated over the memory location as
usual. But the data that were to be loaded back into the data cache
by subsequent SHA1 checksuming were corrupted.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Switch the mx35 timer driver to the 32-kHz clock source to avoid calling
mxc_get_clock() again and again, and to be consistent with the timer drivers of
other i.MX SoCs.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Define default SoC input clock frequencies for i.MX35 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The clock dividers that were used do not match at all the reference manual. They
were either completely broken, or came from an early silicon revision
incompatible with the current one.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Useless code is removed, and get buswidth value.
buswidth value will be used to choice the 4bit or 8bit.
(Now used 4bit mode in sdhci.c by default)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Samsung SoC is broken busy waiting for R1b type.
And clk delay control value is modified the previosuly value.
(that value used at the s5p_mmc.c)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Some boards have no Card Detect wired. In that case, set the CD test
bits in the standard interface.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When setting up the clocks in the sdhci driver, the "spec version"
must be masked off. Otherwise any time the vendor version is not 0,
the check will allways assume the interface is version 3. This breaks
when the interface is actually version 1 or 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When I set up Tegra's config files to put the environment into eMMC, I
assumed that CONFIG_ENV_OFFSET was a linearized address relative to the
start of the eMMC device, and spanning HW partitions boot0, boot1,
general* and the user area in order. However, it turns out that the
offset is actually relative to the beginning of the user area. Hence,
the environment block ended up in a different location to expected and
documented.
Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust
CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire
eMMC.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
eMMC devices may have hardware-level partitions: 2 boot partitions,
up to 4 general partitions, plus the user area. This change introduces
optional config variable CONFIG_SYS_MMC_ENV_PART to indicate which
partition the environment should be stored in: 0=user, 1=boot0, 2=boot1,
4..7=general0..3. This allows the environment to be kept out of the user
area, which simplifies the management of OS-/user-level (MBR/GPT)
partitions within the user area.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables access to boot partitions solely based
on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only
influences access to "general" partitions.
eMMC devices affected by this issue exist on various NVIDIA Tegra
platforms (and presumably many others too), such as Harmony (plug-in eMMC),
Seaboard, Springbank, and Whistler (plug-in eMMC).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Since the type of "ext_csd" was array of char, the following
calculation might fail when the value of ext_csd[EXT_CSD_SEC_CNT]
was minus.
capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
| ext_csd[EXT_CSD_SEC_CNT + 1] << 8
| ext_csd[EXT_CSD_SEC_CNT + 2] << 16
| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
So, this patch changes the type of "ext_csd" to array of u8.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The controller can control high capacity cards. So, the patch adds
the flag. If the flag is not set, "mmcinfo" will fail when a high
capacity card is used.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
(!timeout) condition check in mmc_send_status() can never be met,
because do-while loop ends up with negative timeout value, -1.
Fix the check to handle TIMEOUT case correctly.
Signed-off-by: Jongman Heo <jongman.heo@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
We have the timer code in arch/arm/cpu/armv7/omap-common/timer.c that
has been configuring and enabling the timer, so remove our code that
does the same thing by different methods.
Tested on EVM GP, SK-EVM and Beaglebone.
Signed-off-by: Tom Rini <trini@ti.com>
The manufacturer delivers the TAM3517 SOM with 4 MAC address.
They are stored on the EEPROM of the SOM. The patch adds a
function to get their values and set the ethaddr variables.
Signed-off-by: Stefano Babic <sbabic@denx.de>
AM/DM37x SoCs add the CTRL_WKUP_CTRL register. It contains the
GPIO_IO_PWRDNZ bit, which is required to be set to enable the I/O pads
of gpio_126, gpio_127 and gpio_129.
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
Cc: Tom Rini <trini@ti.com>
In order to use the serial interface on the PortuxG20 we need to enable the
level converter first by setting the PC9 pin to high. The level converter needs
some time to settle so we have to use the mdelay() function to wait for some
time. Unfortunately we have no timers available at board_early_init_f() so we
enable the serial output early within board_postclk_init().
Now the U-Boot output looks fine:
| U-Boot 2012.07-00132-gaf1a3b0-dirty (Aug 16 2012 - 18:21:32)
|
| CPU: AT91SAM9G20
| Crystal frequency: 18.432 MHz
| CPU clock : 396.288 MHz
| Master clock : 132.096 MHz
| DRAM: 64 MiB
| WARNING: Caches not enabled
| NAND: 128 MiB
| In: serial
| Out: serial
| Err: serial
| Net: macb0
| Hit any key to stop autoboot: 0
Signed-off-by: Markus Hubig <mhubig@imko.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The board_postclk_init() function can be used to perform operations
that requires a working timer early within the U-Boot init_sequence.
Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The configuration that is common for all Integrator boards may
just as well be stored in a common include file as per pattern
from other boards. This eases maintenance quite a bit.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Because of the way USB pad settings are handled it doesn't make sense to
be able to build the Efika MX board support without CONFIG_CMD_USB turned
on. So, we change the build to always compile in USB support.
We do not need to check for CONFIG_CMD_USB like we do with CONFIG_MXC_SPI
since the USB subsystem will error out of the compile for us.
Additionally, the following behaviors have changed;
* Smartbook "preboot" should not set input and output to USB keyboard as
there is no display support
* board_eth_init is implemented such that it does not cause U-Boot to
report an explicit failure ("CPU Net Initialization Failed").
Since Ethernet is implemented via USB (fixed on Smarttop, pluggable on
Smartbook, and handled by "usb start") - the warning that is left
("No ethernet found") is perfectly reasonable at the point it is printed
since the USB system hasn't been started and nothing has been probed yet.
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
The mtd name of the NAND in Linux is "gpmi-nand", not "gpmi-nand.0" as
it would be expected, since the controller doesn't support multiple NANDs
attached to it as of now. Rectify this flub by adjusting default mtdparts.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Recent conversion from mx28_adjust_memory_params to mxs_adjust_memory_params
missed to update mx28evk, which caused the board not to boot.
Apply the conversion so that the board can boot again.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Align the SSP clock speed with oscilator to achieve higher transfer
stability.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
* 'master' of git://git.denx.de/u-boot-avr32:
net:macb: add line break
avr32:portmux: fix setup for macb1
avr32: Remove redundant LDSCRIPT definition
Signed-off-by: Wolfgang Denk <wd@denx.de>
Without this patch we see annoying output like this:
---8<---
U-Boot> dhcp
macb1: PHY not foundmacb0: PHY present at 1
macb0: Starting autonegotiation...
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
* fix chip select initialization for frame buffer, this will be
increase frame buffer access speed
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* 'master' of git://git.denx.de/u-boot-cfi-flash:
cfi: Make the flash erase and write operations abortable
cfi: Check for blank before erase
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-ppc4xx:
ppc4xx: Canyonlands/Glacier: Squeeze NAND image a bit to fit again
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch restores the Linkstation's original behaviour when powering off.
Once the (soft) power switch is turned off, linux will reboot and the
bootloader turns off HDD and USB power. Then it loops as long as the switch
is in the off position, before continuing the boot process again.
Additionally, this patch fixes the board function set_led(LED_OFF).
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Hi,
This adds to the documenation to explain how to use the
kwbimage.cfg file necessary to generate an image with
prefixed board setup values necessary for the kirkwood
boards.
Signed-off-by: Karl O. Pinc <kop@meme.com>
The fanless boards now have a 7-digit (XXXXX-F) board name. This
triggers a border condition when reading this string in the IVM although
this string is smaller than the currenly read string size, but only by 1
character.
This patch corrects this by changing the size check condition for string
length. It is the same change that was done in the platform for this
same bug.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Stefan Bigler <stefan.bigler@keymile.com>
The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.
This patch implements a correct computation method according to the
kirkwood functionnal spec. table 600 (Serial Memory Interface
Configuration Register).
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
These parameters are used by the the sf probe command that are used by
our update script and they therefore need to be set for all of our
boards.
The timing is the same as for the ENV SPI NOR Flash (since it's the
same physical device) and takes the boco2 delay on the bus into account.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
Orion5x did not actually write GPIO output values
or input polarities, and ED Mini V2 had bad or
missing values for GPIO settings.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Check for ctrlc() in operations that take time and loop over the flash
addresses.
In netconsole, tstc() is expensive. Only check once in a while to not
slow down the operation significantly.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added an optional check in the CFI driver to evaluate if the sector is
already blank before issuing an erase command. Improves erase time by
over a factor of 10 if already blank.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since commit 50a47d0523
(net: punt bd->bi_ip_addr) booting old 2.4.x ppc kernels
is broken due to changed offsets of the fields in struct bd_t.
Offsets of the fields after removed bi_ip_addr are wrong,
causing wrong bus clocks and console baudrate configurations
and various other issues. Re-add the bi_ip_addr field to preserve
backward compatibility with older ppc kernels. Setting bi_ip_addr
in board.c is not really needed, grepping in the 2.4 linux tree
shows that bi_ip_addr is not accessed there. Adding bi_ip_addr
to struct bd_t for other arches isn't needed it seems. bd_t is
not used by other arches in the 2.4 linux tree.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
When a variable which contains a user-supplied value is dereferenced
(e.g. to be echo'ed), make sure that the value is not further parsed
by hush.
Set the hush local variable "HUSH_NO_EVAL=1" to enable this behavior.
Without this patch, a sequence like this occurs:
Panda # env set my_user_string Bob\'s favorite device
Panda # print my_user_string
my_user_string=Bob's favorite device
Panda # echo $my_user_string
syntax error hush.c:3007
With this patch, it looks like this:
Panda # HUSH_NO_EVAL=1
Panda # env set my_user_string Bob\'s favorite device
Panda # print my_user_string
my_user_string=Bob's favorite device
Panda # echo $my_user_string
Bob's favorite device
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Use standard sh syntax:
${VAR:-default}
Use default value: if VAR is set and non-null, expands to $VAR.
Otherwise, expands to default.
${VAR:=default}
Set default value: if VAR is set and non-null, expands to $VAR.
Otherwise, sets hush VAR to default and expands to default.
${VAR:+default}
If VAR is set and non-null, expands to the empty string.
Otherwise, expands to default.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 155cb01 replaced the read-only property of the ver env var
with an auto-restoring behavior. Update the README file accordingly.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
This patch contains UDM-design.txt, which is document containing
general description of the driver model. The remaining files contains
descriptions of conversion process of particular subsystems.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
On Microblaze with device tree support enabled we run into
the error below.
I'm not sure, but I think that all source code should include
at least the common.h and just this fix the problem on
Microblaz architecture.
The error is:
In file included from key_matrix.c:29:
include/malloc.h:364: error: conflicting types for 'memset'
include/linux/string.h:71: error: previous declaration of 'memset' was here
include/malloc.h:365: error: conflicting types for 'memcpy'
include/linux/string.h:74: error: previous declaration of 'memcpy' was here
Signed-off-by: Stephan Linz <linz@li-pro.net>
CC: Bernie Thompson <bhthompson@chromium.org>
CC: Simon Glass <sjg@chromium.org>
CC: Tom Warren <twarren@nvidia.com>
CC: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <monstr@monstr.eu>
The call to SYSTEM_MAP assumes that the u-boot output is in $PWD when
it really should be in $(obj). This fixes building out of tree.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch adds support to include Load, Entry address and OS tag
of ramdisk on to FIT image through mkimage tool.
Signed-off-by: Jagannadha Sutradharudu Teki <402jagan@gmail.com>
This driver uses the century bit of this RTC in the opposite way Linux does.
From Linux's rtc-pcf8563.c:
/*
* The meaning of MO_C bit varies by the chip type.
* From PCF8563 datasheet: this bit is toggled when the years
* register overflows from 99 to 00
* 0 indicates the century is 20xx
* 1 indicates the century is 19xx
* From RTC8564 datasheet: this bit indicates change of
* century. When the year digit data overflows from 99 to 00,
* this bit is set. By presetting it to 0 while still in the
* 20th century, it will be set in year 2000, ...
* There seems no reliable way to know how the system use this
* bit. So let's do it heuristically, assuming we are live in
* 1970...2069.
*/
As U-Boot's PCF8563 driver does not say it is supposed to support the RTC8564,
make this driver compatible with Linux's by giving the opposite meaning to the
century bit.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
One call to get_cluster can be factorized with another, so avoid
duplicating code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
Add a buffer bouncing mechanism to get_cluster. This can be useful
for misaligned applicative buffers passed through get_contents.
This is required for the following patches in the case of data
aligned differently relatively to buffers and clusters.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
With the previous code, the remaining prefetched sectors were read
again after each sector. With this patch, each sector is read only
once, thus making the prefetch useful.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
fatlength is not used after this assignment, so it is useless and can
be removed.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
startblock must be taken into account in order not to read past the
end of the FAT.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
wait_ticks() calls get_ticks() without building a back chain which
makes gdb unhappy when doing back trace. This can also cause
improper memory accesses.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
This patch forces the correct alignment for DMA operations of buffers used by
part_mac.c.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-usb:
MUSB driver: Timeout is never detected as the while loop does not end
usb: fix ulpi_set_vbus prototype
pxa25x: Add UDC registers definitions
USB: Fix strict aliasing in ohci-hcd
usb: Optimize USB storage read/write
ehci: Optimize qTD allocations
usb_stor_BBB_transport: Do not delay when not required
usb_storage: Remove EHCI constraints
usb_storage: Restore non-EHCI support
ehci-hcd: Boost transfer speed
ehci: cosmetic: Define used constants
ehci: Fail for multi-transaction interrupt transfers
arm:trats: Enable g_dnl composite USB gadget with embedded DFU function on TRATS
arm:trats: Support for USB UDC driver at TRATS board.
dfu:cmd: Support for DFU u-boot command
dfu: MMC specific routines for DFU operation
dfu: DFU backend implementation
dfu:usb: DFU USB function (f_dfu) support for g_dnl composite gadget
dfu:usb: Support for g_dnl composite download gadget.
ehci: cosmetic: Define the number of qt_buffers
Signed-off-by: Wolfgang Denk <wd@denx.de>
In case an address is listed in the To list, those will be skipped on
Cc list or user might end with a duplicated message.
This fixes the case when a tag points to same address used as series
destination thus avoiding duplicated sending.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
When a patchset had a RFC series, a v1 might have a changelog of
changes done since the RFC. The patch changes the range checked for
changelog and allow it to start for version 1.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Simon Glass <sjg@chromium.org>
Currently patman assumes that there should be only one Signoff line
and this is obviously incorrect: we often have to work with patches
containing other people signoffs. Moreover, it's really desirable
to preserve the comments between signoffs.
So until some sophisticated signoff processing will be developed I
suggest just don't mess with signoffs at all and treat them like
plain text lines. The only drawback I've found so far is the case
where you have a patch with someones else signoff but not yours and
also have to patman tags under signoff line. In this case you will
get extra empty line between signoffs.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Don't try to sort and uniq changelog entries as this breaks
multiline entries. It will be better to add some real multi-line
support but for now just preserve the entries as is.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
We already got all changes from git log output and the comment
to the ProcessLine function clearly states that 'patch' mode
is not for scanning tags.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Changes may end in '---' line or Signoff line (generated by
git format-patch) in case of Series-changes: lines being
the last ones in commit message. So detect it properly.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a
quick enumberation of the PCI devices, but don't need any setup work done.
This is very beneficial on platforms that have u-boot loaded by another
boot loader which does a more sophisticated job of setup of PCI devices
than u-boot. That way, u-boot can just read what's there and get on
with life. This is what SeaBIOS does.
Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
Add some recent entries to pci_ids.h for Intel and AMD/ATI devices that
are somewhat relevant to u-boot.
Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
Refactor the common PCI code just a tiny bit surrounding the PCI_PNP
(pciauto) stuff. Makes the code a tiny bit easier to read, and also
makes it more obvious that almost no platform needs to setup or use the
pci_config_table stuff.
Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
I tried to clean up the white space and formatting offenses and
inconsistencies in the generic PCI code that obviously has been around for
some time. Emphasis on large increases in readability and maintainability
and consistency. I omitted the platform/processor specific files in
the drivers/pci directory because I wanted to leave those file to those
that care more about them.
Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
In a couple of places, unsigned int and pci_config_*_dword were being
used when u16 and _word should be used. Unsigned int was also being
used in a couple of places that should be pci_addr_t.
Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
* 'agust@denx.de' of git://git.denx.de/u-boot-staging:
tx25: Use generic gpio_* calls
config: Always use GNU ld
tools: add kwboot binary to .gitignore file
fdt: Include arch specific gpio.h instead of asm-generic/gpio.h
serial: CONSOLE macro is not used
Conflicts:
board/karo/tx25/tx25.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
AVR32's LD script uses a standard location that is now automatically detected by
the main Makefile, so its definition in AVR32's config.mk is now obsolete and
redundant.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The Programmable Multibit ECC (PMECC) controller is a programmable binary
BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
can be used to support both SLC and MLC NAND Flash devices. It supports to
generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data.
To use PMECC in this driver, the user needs to set the PMECC correction
capability, the sector size and ROM lookup table offsets in board config file.
This driver is ported from Linux kernel atmel_nand PMECC patch. The main difference
is in this version it uses registers structure access hardware instead of using macros.
It is tested in 9x5 serial boards.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[rebase]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This patch
1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support.
2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail().
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix empty newline at EOF error and move return value check into ifdef]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add at91sam9x5 series spi flash boot support
Using at91sam9x5ek_spiflash to configure, then it can boot from at25df321
serial flash
SPI mater work in 30Mhz speed, while not 1Mhz speed. This will base on
atmel_spi patch, or else, it will occur receive overrun
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
As the maintainer for at91sam9g10ek and at91sam9m10g45ek can not reach
any more.
So I wish to take over the maintainer for sam9g10 and sam9m10g45
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
fix a bug:
when not boot from NAND, the NAND flash can not be detected.
Using this to fix it
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Before reset dbgu transmitter, we just wait TXEMPTY to drain the
transmitter register(Just in case). If not doing this, we may sometimes
see several weird characters from DBGU.
A short delay is also added to make sure the new serial settings are
settled.
Signed-off-by: Hong Xu <hong.xu@atmel.com>
[cherry-picked from u-boot-atmel/old-next]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The old update script uses 'load_addr' which is never set. Use 'fileaddr'
instead which is automagically set by e.g. dhcp.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
cc: Stelian Pop <stelian@popies.net>
Timeout variable is decremented once more when while condition is not met.
Following "if" does not detect correctly that timeout has occurred.
Because of this bug the "usb start" command on AM335X-EVM board did not detect correctly that USB device was not attached.
timeout = musb_cfg.timeout;
while (timeout--)
if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
break;
/* if musb core is not in host mode, then return */
if (!timeout)
return -1;
Signed-off-by: Matej Franceskin <Matej.Franceskin@comtrade.com>
CC: Marek Vasut <matex@denx.de>?
commit 5f6aa03fda
USB: Fix complaints about strict aliasing in OHCI-HCD
tried to fix this, but gcc4.4 still complains. So, this
patch basically reverts the above and does a simpler fix.
also, the above commit incorrectly changed
/* corresponds to data_buf[4-7] */
datab [1] = 0;
to
/* corresponds to databuf.u8[4-7] */
databuf.u8[1] = 0;
This patch also fixes that.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
There is a 5-ms delay in usb_stor_BBB_transport, which occurs every 10 kiB of
data for fragmented fatload usb, i.e. roughly 500 ms of delay per MiB. This adds
up to quite a bit of delay if you're loading a large ramdisk.
The purpose of this delay should be to debounce the 5-V/100-mA USB power up.
This patch skips the delay if the device has already been queried as ready.
Signed-off-by: Jim Shimer <mgi2475@motorola.com>
Rework following the review:
- Rebase against the latest u-boot-usb master.
- Replace typedef with #define.
- Use the existing flags struct field instead of adding a new field.
- Remove the setter function.
- Remove the typecasts.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Cc: Jim Shimer <mgi2475@motorola.com>
The commit 5dd95cf made the MSC driver EHCI-specific. This patch restores a
basic support of non-EHCI HCDs, like before that commit.
The fallback transfer size is certainly not optimal, but at least it should work
like before.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
This patch takes advantage of the hardware EHCI qTD queuing mechanism to avoid
software and transfer splitting overhead so as to make transfers as fast as
possible.
The only drawback is a call to memalign. However, this is fast compared to the
transfer timings, and the heap size to allocate is small, e.g. 128 kiB in the
worst case for a transfer length of 65535 packets of 512 bytes.
Tested on i.MX25, i.MX35 and i.MX51. In my test conditions, the speed gain was
very significant (several times faster), which is really appreciable when
accessing large files.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Interrupt transfers requiring several transactions are not supported by
submit_int_msg() because bInterval is ignored. This patch returns a failure code
and prints an error message in this case.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Enable the g_dnl composite USB gadget driver with embedded DFU function on it.
It now uses the composite gadget framework to support download specific
USB functions (like enabled DFU or USB Mass Storage).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
New, separate driver at ./drivers/dfu has been added. It allows platform
and storage independent operation of DFU.
It has been extended to use new MMC level of command abstraction.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Composite USB download gadget support (g_dnl) for download functions.
This code works on top of composite gadget.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so
disable it globally for this architecture. This avoids setting no_snoop for all
i.MX boards, and it prevents setting a reserved bit of a reserved register if
fsl_esdhc_mmc_init() is used on i.MX, like in
arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init().
Since no_snoop was only used on i.MX, get rid of it BTW.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Define ARCH_MXC for i.MX devices. This is useful to identify features or
behaviors common to all i.MX SoCs.
The i.MX28 is omitted because its architecture is a bit different (like imx/mxc
vs. mxs in Linux).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
The macro to get the gpio number id was renamed to
IMX_GPIO_NR as in kernel. Fix the wrong name in efika.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matt Sealey <matt@genesi-usa.com>
Acked-by: Matt Sealey <matt@genesi-usa.com>
We have no idea where the DCD was derived from for Smartbook support, but they
differ from the Smarttop settings, MX51EVK settings and certainly don't
correspond to any shipped or development version of U-Boot that Genesi has ever
had on any Smartbook.
So, copy the calibrated, verified settings from the U-Boot as shipped with every
Smartbook since retail production. Remove those few settings that just set the
POR defaults which have already been confirmed for the previous Smarttop DCD
change.
One of the lines is specific to i.MX51 TO3 designs and therefore TO2 Smartbooks
will possibly not work so reliably with this new DCD; that said, TO2 Smartbooks
basically don't exist at retail and the number of units in the world is less
than 5 (3 of which are at the Genesi office or owned by Genesi employees).
Many hours of memory testing confirms the new settings are stable.
Patch v2:
* picked the correct commit from our development tree, correcting tuned DDR ODF setting
(which was correct anyway)
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
This is a rework of a previously submitted patchset and bundles the
main board support and USB support into a single commit.
It requires the patch "mx5: add iomux-mx51.h include"
* Use iomux-mx51.h include to simplify board configuration.
* Simplify LED support (remove efikamx_toggle_led, change lit LEDs).
* Simplify MMC support for CD and WP pin differences.
* Fix broken CPU voltage setting - comment said 1.1V but the code set to
1.2V. It should never have been set to 1.2V even on i.MX51 TO2 and
all available Linux kernels would drop the voltage to 1.1V anyway and
work reliably. This should lower power consumption during the boot
process.
* Function renames for readability.
* Some board identification string changes to match actual product names.
* Passes checkpatch (v2)
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Cc: Stefano Babic <sbabic@denx.de>
For representing a timeout value, it makes more sense to pass it as
'unsigned int'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
PCBID pads seem to need time to settle due to external pulldowns, otherwise
we are reading floating GPIO pins with implicit pad pullups and get the wrong
data. However we can't "wait" at the time we need them before relocation,
since timers are not available. The time taken to get from DCD to the code
requiring the pads set seems to be more than long enough (even with caches
enabled).
We have space in the DCD due to the DDR settings changes to configure all
the pad settings we need for this, plus the LED pad settings too which
reduces the amount of code required later on.
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Efika MX boards configure their DDR pad settings twice, one in the DCD generated
from imximage_*.cfg and again in init_drive_strength called before relocation.
Rather than doing this, roll the changes it makes into the DCD so DDR is set up
before a single line of code in U-Boot is run.
The settings are identical with this DCD block which is shorter (by 7 entries)
than the old one, and after the output of init_drive_strength since a lot of the
functionality in the existing DCD and init_drive_strength function was just
setting the POR defaults. This goes to explain some now-missing entries.
Several hundred rounds of mtest have been run to test the settings before and
after to confirm DDR is stable and no ill-effects have been found.
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
* Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory
* Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This change implements DMA chaining into SPI driver. This allows
the transfers to go much faster, while also fixing SF issues.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Load from SPI flash can create a long DMA chain, which can take long
time to transfer. Change the DMA timeout to roughly 10s to prevent
such long chains misreporting errors.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Allow usage of the imx-common/iomux-v3.h framework by including pad settings
for the i.MX51. The content of the file is taken from Linux kernel at
commit 5d23b39 plus the required changes to make it work in U-Boot.
The contained pad settings are the minimum required to make an Efika MX boot
and get all the currently-implemented peripherals working in U-Boot.
It is recommended that this file not be just a dumping ground for pins but
only contain the settings required for all the boards using it.
Changes for v2:
* reference commit id from Linux kernel
* additionally roll in the USB pads
* removed GPIO_NUMBER define
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The DRAM initialization, after SPL has complete, is exactly the same
for all mxs SoCs so we should name it accordinly.
The following boards has been changed:
* apx4devkit
* m28evk
* mx28evk
* sc_sps_1
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
The internal Ethernet controller is only available on i.MX28
processors so it needs to use CONFIG_MX28 guardian to avoid having
this code called in others.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
gpio_get_value() should use PSR like Linux, not DR, because DR does not always
reflect the pin state, while PSR does. This is especially useful to detect a
short circuit on a GPIO pin configured as output, or to read the level of a pin
controlled by a non-GPIO IOMUX function.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The imx_decode_pll() function does not exist for mx5, so remove its declaration.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Each i.MX has its own gpio.h, defining the same structure.
The internal GPIO controller has the same layout
(at least for the register used by u-boot) and can be shared.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Tested-by: Matt Sealey <matt@genesi-usa.com>
commit d92591a (mxs: Convert sys_proto.h prefixes to 'mxs') introduced
a mxs_dram_init() function, which is not used anywhere.
Fix it, so that the following warning goes away:
mx28evk.c: In function ‘dram_init’:
mx28evk.c:67:2: warning: implicit declaration of function ‘mx28_dram_init’ [-Wimplicit-function-declaration]
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
For i.MX233 addition the base registers need to be change so the SoC
definition needs to be known before the header include.
The following boards has been changed:
* apx4devkit
* m28evk
* mx28evk
* sc_sps_1
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
The elftosb call needs to use a target param specific for i.MX28. This
patch allow for later addition of i.MX233.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Do not pretend to have initialized mmc successfully if CONFIG_FSL_ESDHC is not
defined. Instead, only implement a custom cpu_mmc_init() when it does something.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Use calloc() instead of malloc() to allocate the mxs_spi_slave structure.
Clearing the memory is necessary since most of the time this gets done
super early in boot, but on warm reboots, and when SPI probing is done
long after the init stages it could actually pick up previously used memory,
and things like the chipselect polarity and other data end up being filled
with trash data if not explicitly set by the board files.
This solves a semi-random, almost unreproducable error whereby SPI devices
act very, very strangly on boot.
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Use calloc() instead of malloc() to allocate the mxc_spi_slave structure.
Clearing the memory is necessary since most of the time this gets done
super early in boot, but on warm reboots, and when SPI probing is done
long after the init stages it could actually pick up previously used memory,
and things like the chipselect polarity and other data end up being filled
with trash data if not explicitly set by the board files.
This solves a semi-random, almost unreproducable error whereby SPI devices
act very, very strangly on boot. Tested on Efika MX over several years..
Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This allows a watchdog reset to start the ROM's
usb/serial downloader, or boot from an sdcard.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
This is useful for forcing the ROM's
usb downloader to activate upon a watchdog reset.
Or, you can boot from either SD Card.
Currently, support added for MX53 and MX6Q
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Note: MX53 support untested.
Acked-by: Stefano Babic <sbabic@denx.de>
Round up tick_to_time() value instead of truncating it. This avoids stopping
waits instantly for low usec values, and this generally guarantees that the code
always waits for at least the requested duration.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Now that the main i.MX features work fine with dcache enabled, enabled it by
default if CONFIG_SYS_DCACHE_OFF is not defined.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Now that the main i.MX features work fine with dcache enabled, enabled it by
default if CONFIG_SYS_DCACHE_OFF is not defined.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Since the input frequency of the API is a maximum that should not be exceeded in
order for the devices to operate properly, the SPI clock divider should be
rounded up, not truncated.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The SPL doesn't need the CP15 reconfiguration, as that's what the
BootROM does for us already. Moreover, when the CP15 is reconfigured
and the code returns control to BootROM, the USB boot works no more.
Remove the code and allow [1] to work properly as well.
[1] http://git.bfuser.eu/?p=marex/mxsldr.git;a=summary
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The sys_proto.h functions (except the boot modes) are compatible with
i.MX233 and i.MX28 so we use 'mxs' prefix for its methods.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
The iomux header is included on sys_proto.h so to avoid SoC specific
header inclusion.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
This patch support exynos pwm backlight driver. It can control backlight
power and brightness by using pwm.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
To support display port in exynos fb driver, added dp_enabled variable
in vidinfo structure that set in board file.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch set supports exynos display port drivers.
DisplayPort is an industry standard device to accommodate the increasing board
adoption of digital display technology within the PC and consumer electronics.
The interface supports internal chip-to-chip and external box-to-box digital
display connections.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch add display port base address for EXYNOS5. In case of EXYNOS4,
use DEVICE_NOT_AVAILABLE macro because DP is not supported.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch supports exynos fimd driver for various exynos series different from
existing it supports only exynos4 chip.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
In general, The get_timer_masked function get the system time,
no the number of ticks. Such as the nand_wait_ready will use
get_timer_masked to delay the operations. And change the system
time to adopt to the CONFIG_SYS_HZ.
Signed-off-by: Hongbo Zhong <bocui107@gmail.com>
Tested-by: Jaehoon Chung<jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0.
It also corrects the gpio offset calculations.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add a structure for table-driven configuration mechanism such that no recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
CONFIG_STACKSIZE is not referenced anywhere except on AVR32, but present
in most ARM board config files.
IRQs are only enabled for 1 config, so remove the unused config options
for IRQ and FIQ stack size as well.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
This patch removes save_boot_params_default() and put the equivalent in start.S
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>
These flags were necessary when building tegra20 as a single binary
that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support
is split into a separate SPL, this is no longer necessary.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This fixes the SPL build to link with the SPL version of libgcc if
USE_PRIVATE_LIBGCC is set to "yes". Previously it was linking with
the libgcc from the normal u-boot build because it gets set in
PLATFORM_LIBS and passed down the to the SPL build.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Move warmboot_save_sdram_params() to later in the boot sequence. This
code relies on devicetree to get the address of the memory controller
and with upcoming changes for SPL boot it gets called early in the
boot process when devicetree is not initialized yet.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add target for tegra20 u-boot image. This is a concatenation of tegra
spl and normal u-boot binaries. For non-devicetree builds this is
named "u-boot-nodtb-tegra.bin" for devicetree builds is named
"u-boot-dtb-tegra.bin".
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for tegra20 arm7 boot processor. This processor is used
to power on the Cortex A9 and transfer control to it. In tegra this
processor is an ARM7TDMI not an ARM720T, but since we don't use cache
it was easier to just reuse the ARM720T code as the processors are
otherwise identical except for cache and MMU.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Update MAKEALL to handle the optional SPL CPU field that was added to
boards.cfg. This impacts the cases in MAKEALL that have to match
against CPU type (field 3). In these cases use ':' as a field
separator to split the u-boot CPU from the SPL CPU.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds some cleanup to mkconfig related to SPL support. Bash
specific script has been replaced with awk for better shell
compatibility. config.mk generation is done through a subshell and
single redirect to improve readability.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change the mkdir commands for the object directories to be
unconditional. This fixes an issue when building for SPL where
SRCTREE and OBJTREE are the same, but $(obj) is under SPLTREE.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA.
The meaning of the config options is now:
CONFIG_TEGRA - Any tegra chip
CONFIG_TEGRA20 - A tegra20 family chip
CONFIG_TEGRA30 - A tegra30 family chip (not added yet)
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Raspberry Pi model B uses the BCM2835 SoC, has 256MB of RAM,
contains an SMSC 9512 USB LAN/Hub chip, and various IO connectors.
For more details, see http://www.raspberrypi.org/.
Various portions (cache enable, MACH_TYPE setup, RAM size limit, stack
relocation to top of RAM) extracted from work by:
Oleksandr Tymoshenko <gonzo@bluezbox.com>.
GPIO driver enablement by Vikram Narayanan <vikram186@gmail.com>.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Tom Rini <trini@ti.com>
Note that this affects all users of the ARM1176 CPU that enable
CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
tnetv107x.
Cc: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
All usage of config_cmd_default.h uses <> for the include statement.
Update the README to do the same, rather than using "".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Following ARM's reference manuel for initializing the cache - the
kernel won't boot otherwise.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Some CPU (i.e u8500) need more cache management before launching
the Linux kernel.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Configuration in vexpress and u8500.v1 is different from what
is needed in u8500.v2. As such, card configuration specifics need
to reside in the board file rather than the driver.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
Register mapping has changed on power control chip between
the first and second revision.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multiple u8500-based boards.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
LAN and GBF need to be powered explicitely, doing so with
interface to AB8500 companion chip.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
This is to allow the prcmu functions to be used by multiple
u8500-based processors.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
We can safely use the same reset code written in C for both Davinci and
C6X platforms. In addition the C version of the code is marginally
smaller on Davinci.
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Orjan Friberg wrote at [1]:
"For the beagleboard, ecc.size is not explicitly set when doing 'nandecc
sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's
set to 256 bytes.
When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when
changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly
the format has changed."
No patch has been submitted and the issue was still present. This patch
adds the mentioned solution. Tested on a tam3517 board.
[1] http://lists.denx.de/pipermail/u-boot/2012-February/119002.html
cc: Orjan Friberg <of@flatfrog.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
change the behaviour of switch initialization:
- rename "pwl" to "lan" in hwconfig parameter
"lan" = port 1 with phy addr 2
"lmn" = port 2 with phy addr 3
- if we have a valid switch config file in flash, do not
evaluate the settings in the hwconfig "lan" or "lmn"
subcommand.
- if we have no valid switch config file in flash, start
the switch with default values, if we have a "lan" or
a "lmn" hwconfig subcommand. If no "lan" or "lmn" is
found in hwconfig, do nothing with the switch.
Signed-off-by: Heiko Schocher <hs@denx.de>
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.
During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.
Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.
Move the usb header for da8xx platforms under arch-davinci.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Make sure that when we setup the stack before calling s_init() we have
the stack have 8-byte alignment for ABI compliance.
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms. As part of this we change some of the macros that are used
to be more clear. Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we
should have been doing this initially and do now.
Cc: Sricharan R <r.sricharan@ti.com>
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value
Signed-off-by: Tom Rini <trini@ti.com>
The AM335x GP EVM can have one of 8 different profiles selected. Each
profile has a different set of peripherals and requires different pinmux
configurations that conflict with other profiles. i2c1 is an example of
a conflicted mux currently.
Signed-off-by: Tom Rini <trini@ti.com>
Fix build failure due the move of mx28 code to 'mxs' SoC.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
This gets us rid of duplication of the same file.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The DMA didn't work properly because the DMA descriptor wasn't
properly cleaned after it was used once. Also, the DMA_ENABLE bit
was enabled/disabled too late.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable
but this wasn't clear on code so a comment has been added to clarify
it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
The mx28 prefix has been added to the initialization data and function
so it is clear by which SoC it is used as i.MX233 will have a specific
one. While on that, we also change it to static.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
This adds support for Bluegiga APX4 Development Kit. It is built around
Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC,
RTC and USB. APX4 has only one ethernet port.
Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Cc: Stefano Babic <sbabic@denx.de>
The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
The DMA transfers happen only if the transfered data are larger
than 512 bytes. Otherwise PIO is used. This is a small speed
optimization.
The DMA transfer doesn't work if unaligned transfer is requested
due to the limitation of the DMA controller. This has to be fixed
by introducing generic bounce buffer. Therefore the DMA feature
is now disabled by default.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
This adds support for the AT91SAM9G20 boards by taskit GmbH.
Both boards, Stamp9G20 and PortuxG20, are integrated in one
file. PortuxG20 is basically a SBC built around the Stamp9G20.
Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.deve@googlemail.com>
The grasshopper board is a avr32 based device and belongs therefore to the avr32
section.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Beaglebone uses SMSC PHY which works incorrectly with generic PHY
driver so enable SMSC PHY driver to fix networking problems on
Beaglebone.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the
LPDDR memory consist on two dies of 256MiB.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...]
ARM frequency = 300 MHz
DSP frequency = -536870913 MHz
DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Hadli, Manjunath <manjunath.hadli@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
- Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.
Signed-off-by: Tom Rini <trini@ti.com>
- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
config_ddr with.
- Both of the above require filling in the header structure early, move
it into the data section.
Signed-off-by: Tom Rini <trini@ti.com>
The intention has always been (and boards are to support) an i2c EEPROM
that will identify what hardware they are, allowing a single binary to
support multiple boards. As such, remove the 'evm.c' file as there is
nothing EVM centric in it currently, only SoC peripheral configuration.
Signed-off-by: Tom Rini <trini@ti.com>
In order to support DDR3 as well as DDR2, we need to perform the same
init sequence, but with different values. So change config_ddr() to
toggle setting pointers/etc for what DDR2 wants, and then calling.
Signed-off-by: Tom Rini <trini@ti.com>
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.
Signed-off-by: Tom Rini <trini@ti.com>
The various ratio1 fields are not documented in any of the documentation
I can find. Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.
Signed-off-by: Tom Rini <trini@ti.com>
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation). Rather than defining a struct and setting the
value repeatedly, just pass in the value.
Signed-off-by: Tom Rini <trini@ti.com>
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.
Signed-off-by: Tom Rini <trini@ti.com>
A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.
Signed-off-by: Tom Rini <trini@ti.com>
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
we're operating in the normal mode where EMIF/PHY clock is controlled
by the PHY.
Signed-off-by: Tom Rini <trini@ti.com>
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value. This call can be delayed
slightly to the point where we know which type of memory we have.
Signed-off-by: Tom Rini <trini@ti.com>
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()). For now, pass in
the value of DDR2.
Signed-off-by: Tom Rini <trini@ti.com>
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const. This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.
Signed-off-by: Tom Rini <trini@ti.com>
With the previous bugfix we now don't need to set two different REF_CTRL
values and instead set the final value.
Signed-off-by: Tom Rini <trini@ti.com>
When we change SDRAM_CONFIG this triggers a refresh based on all of the
parameters that we have programmed so we must do this last.
Signed-off-by: Tom Rini <trini@ti.com>
We do not need to check for EMIF_GCLK and L3_GCLK being active. This
was a hold-over from bringup and no longer required.
Signed-off-by: Tom Rini <trini@ti.com>
- Add default commands
- Add HUSH parser
- Make environment, malloc areas larger
- Add ATAGS and OF_LIBFDT
- Add defaults to boot ramdisk and MMC, use uEnv.txt
Signed-off-by: Tom Rini <trini@ti.com>
This patch adds SPL support for IGEP-based boards.
Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
IGEP-based boards can have two different flash memories, a OneNAND or a
NAND device. Add a configuration option for to choose which memory to use.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
This patch adds board-specific initialization for CPSW on
TI AM335X based boards. Tested on BeagleBone.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split board-specific part into separate patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Read the on-board EEPROM during startup to detect the version
of the board we are running on (as for now only BeagleBone vs
EVM detection is supported).
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This patch adds pin mux settings for CPSW switch found on
TI AM335X based boards (MII and RGMII modes).
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split pinmux into separate patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split init out of original patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
CPSW is an on-chip ethernet switch that is found on various SoCs from Texas
Instruments. This patch adds a simple driver (based on the Linux driver) for
this hardware module.
This patch also adds support to clean and flush dcache during packet send
and receive.
Changes by Sandhya: Added support to clean and flush dcache during packet
send/receive and added timeouts.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
[Ilya: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This reverts commit 5347560f5427bcdd48a563b62180481606ac8044,
which was applied only to get release 2012.07 functional on as
many ARM targets as possible despite mis-aligned accesses.
omap2plus_defconfig now has built-in compile support for EXT4 enabled
by default now. So, we can use EXT4 as the default root file system
type for MMC.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
An OMAP specific serial driver was merged on the Linux kenel a long
time ago. So, it makes sense to default the console name to OMAP
ttyO instead of the generic ttyS naming.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
This patch adds support for direct NOR boot mode on
da850/omap-l138. Added da850evm_direct_nor entry in
boards.cfg to allow to build targets.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
Though Commit id a3f88293dd (da850evm:
setup the NAND flash timings) has configured the AEMIF timings, they
are not exactly in sync with the timings used in Linux. Linux is
configuring the timing register as 0x08222204, where as currently it
configured to 0x00100084 in U-Boot. This issue was found out when
support for NAND SPL is added in U-Boot. Without this patch U-Boot
does not come up with SPL.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
configuration file to enable this feature.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
On Logic PD Rev.3 DA850/OMAP-L138 EVM, NOR and MMC/SD cannot
work together. This patch enables the MMC/SD support only
when NOR support is disabled. NOR Flash identification works
even without this patch, but erase and write will have issues.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When
GP0[11] is low, the SD0 interface will not work, but NOR
flash will. When GP0[11] is high, SD0 will work but NOR
flash will not.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
This patch uses the code in omap-common to support gpio modules 1-3
on am33xx based boards.
It adds base address and register definitions, enables clocks to the
modules, and enables building the common gpio code for CONFIG_AM33XX
as well as CONFIG_OMAP
Signed-off-by: Steve Sakoman <steve@sakoman.com>
UART_RESET, UART_CLK_RUNNING_MASK, and UART_SMART_IDLE_EN
are defined inn evm.c but not used. Also removes unnecessary
include of serial.h
PHYS_DRAM_1_SIZE is defined in am335x_evm.h but never used.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Fix the comment to reflect the actual function call time.
Change the printf message to look nicer in the context it might be printed.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Parameters used for configuring certain SoC peripherals are parsed
from the cfg file and appended as part of the ais image's header. The
u-boot-spl.ais generated is flashed separately to the nand, so do not
delete the file after generation of u-boot.ais.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Various devices like EEPROMs require 2-byte address support to
be properly accessed. This patch adds this support for OMAP2/3/4
I2C controller driver.
I've tested it with EEPROM (16 bit address) and TPS65217 chip
(8 bit address) on TI Beaglebone board.
Unfortunately I don't have access to any compatible hardware
with 16bit data register so I can't test if those #ifdef
clauses really work.
CC: Tom Rini <trini@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Remove old o2dnt board without OF support. New support for this board
is added by the previous patch, O2I configuration.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add common code for o2dnt and o2dnt2 based boards and add different
board configuration files for O2D, O2I, O2DNT2, O2D300, O2MNT and
O3DNT boards.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add pci_mpc5xxx_init() prototype to the header file, so board .c files
do not need to add extern pci_mpc5xxx_init() declaration.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 'master' of git://git.denx.de/u-boot-sh:
sh: tmu: Removed arch/sh/include/asm/clk.h
sh: tmu: Changed switch statement to shift operation
sh: tmu: Changed TMU driver using array of structures
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: Add support for S25FL256S
sf: winbond: fix page_size
sf: stmicro: add support for N25Q128A
sf: stmicro: add support N25Q128 parts
sf: stmicro: support JEDEC standard two-byte signature
sf: winbond: add W25Q32
cmd_spi: remove superfluous semicolon
Signed-off-by: Wolfgang Denk <wd@denx.de>
asm/clk.h was included get_peripheral_clk_rate function. But this
is not used from anywhere.
This removed asm/clk.h, and deleted include line from arch/sh/lib/time.c
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Calculation of the bit position using switch statement can substitute
shift operation using ffs.
And removed unsed macro and variable.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This changed into access using array of structure from access to the register
using the definition of the register by macro.
And removed white space.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Import ashldr3, ashrdi3 and lshrdi3 to squash possible libgcc fp mismatch,
resulting in the following warning:
mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_lshrdi3.o) uses hard float, u-boot uses soft float
mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_ashldi3.o) uses hard float, u-boot uses soft float
Imported from Linux (linux-next 20120723) as of commit:
commit 72fbfb260197a52c2bc2583f3e8f15d261d0f924
Author: Ralf Baechle <ralf@linux-mips.org>
Date: Wed Jun 7 13:25:37 2006 +0100
[MIPS] Fix optimization for size build.
It took a while longer than on other architectures but gcc has finally
started to strike us as well ...
This also fixes the damage by 6edfba1b33c701108717f4e036320fc39abe1912.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
[<daniel.schwierzeck@gmail.com>: removed USE_PRIVATE_LIBGCC = yes]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The lb60 board accesses the clkgr register, which is 32bit via
16bit IO ops. This causes malfunction. Fix this.
qi_lb60.c: In function ‘cpm_init’:
qi_lb60.c:72:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
qi_lb60.c:84:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel <zpxu@ingenic.cn>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
The timer code contains more halfword writes which trigger gcc errors.
The registers are again 32bit, yet written by 16bit writes, fix this:
timer.c: In function ‘reset_timer_masked’:
timer.c:37:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c: In function ‘get_timer_masked’:
timer.c:43:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c: In function ‘timer_init’:
timer.c:86:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c:88:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c:89:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c:90:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel <zpxu@ingenic.cn>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
Write the TSCR register via 32bit write instead of 16bit one.
The register is 32bit wide and bit 16 is being set, triggering
gcc overflow error and making the code broken.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel <zpxu@ingenic.cn>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
Commit 8b5a02640a ("Makefile: cosmetic:
optimize usage of LIBS-y") broke the build of boards that have a board
vendor "common" directory, by introducing a space between "LIBS-" and
"y".
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Commit a4ed3b6 "sf: inline data constants" modified winbond.c's page_size
from 256 to 4096. This prevents either/both of "sf write" writing the
correct data, or "sf read" from reading the correct data back.
This allows U-Boot running on Compulab Tegra to upgrade itself.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 54652991
Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips
fixes a problem for Numonyx P33/P30 flashes for 256-Mbit, but this leads
to problems for smaller versions of this chip e.g. the 32Mbit version
with deviceid 0x16 on mgcoge. So move the code for this work around to
an own function and check previously manufacturer id and device id to
not break other flashes which don't need this work around.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Stefan Roese <sr@denx.de>
cc: Philippe De Muyter <phdm@macqel.be>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Erasing flash sectors protected with persistent protection bit (PPB)
mechanism on Spansion flash chips doesn't work. Add sector protection
status checking and sector lock and unlock commands to fix this.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Add '-ansi' to DTS_CPPFLAGS to avoid unwanted expansion of dts content
that matches some predefined macros.
Example: A number of PowerPC related *.dts files in the kernel define a
property named 'linux,network-index' which (w/o '-ansi') is expanded to
'1,network-index' by the preprocessor because of '#define linux 1.'
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Support for DS1388 is added by extending the DS1337 driver. DS1388 is
similar to DS1337. The time registers are offset by 1 (due to support
for hundreds of seconds), and there is no century bit.
The configuration and trickle charge registers are also different.
Tested on hardware with Freescale P2010 and DS1388.
Signed-off-by: Kenth Eriksson <kenth.eriksson@transmode.com>
Make sure that $(LDSCRIPT) is not empty before calling process_lds
with 'cat $(LDSCRIPT)' else cat will block waiting for input from
stdin.
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
This patch makes sure that we always use the GNU ld. U-Boot uses certain
construct e.g. OVERLAY which are not implemented in gold therefore it
always needs GNU ld for linking.
It works well if default linker in toolchain is GNU ld but in some
cases we can have gold to be the default linker and also ship GNU ld
but not as default in such cases its called $(PREFIX)ld.bfd, with this
patch we make sure that if $(PREFIX)ld.bfd exists than we use that for
our ld.
This way it does not matter what the default ld is.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Include arch specific gpio.h instead of asm-generic/gpio.h
because several architectures (Microblaze, Blackfin, Nios2, OpenRISC)
define gpio functions in header file.
asm-generic/gpio.h can be included in arch specific gpio.h
(For example: ARM)
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Simon Glass <sjg@chromium.org>
The top Makefile and the SPL Makefile have lines like those:
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),mx5)
LIBS += $(CPUDIR)/imx-common/libimx-common.o
endif
This should be done in the arch/CPU/SoC specific sub-makefiles to
keep the top Makefiles clean. This patch also allows adding of new
arch/CPU/SoC specific libraries in the future without touching
the top Makefiles.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Fixes the build-time warning:
board.c: At top level:
board.c:106: warning: 'pmu_init' defined but not used
This makes the ifdef logic at the call site match the logic at the
function definition.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Fixes the build-time warning:
board.c: In function 'board_init_r':
board.c:304: warning: unused variable 's'
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Nothing is using this, so punt it from the gd. Seems to just be a copy
& paste wart from the initial port.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Adds support for Numonyx's N25Q128 SPI flash. These devices
are used on (among others) Avnet Spartan-6 LX9 micro-evaluation
boards. Tested with "sf" commands and CONFIG_ENV_IS_IN_SPI_FLASH.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
There are more than the M25Pxx serial flashs that can be
used with the stmicro driver, for example: the M25PXxx or
N25Qxx serie. All these chips have burned in the original
stmicro manufacture id 0x20 together with a standard
two-byte signature.
In preperation to support all these chips the stmicro driver
have to decode the full two-byte signature.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
SMDK EVT1 has a different Winbond part, added its part details
to the SPI flash table.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
U-Boot port is based on sources forked from GRUB-0.97 by Sun in 2004,
which can be found here:
http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/grub/grub-0.97/stage2/zfs-include/zfs.h
Released by Sun for GRUB under the license:
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
GRUB official releases include ZFS in version:
ftp://alpha.gnu.org/gnu/grub/grub-1.99~rc1.tar.gz
And patched against GRUB Bazaar repository for ashift fixes (4KB HDDs)
more conveniently found at github:
e7b6ef3ac3
Signed-off-by: Jorgen Lundman <lundman@lundman.net>
This patch updates the yaffs2 in u-boot to correspond to
git://www.aleph1.co.uk/yaffs2
commit id 9ee5d0643e559568dbe62215f76e0a7bd5a63d93
Signed-off-by: Charles Manning <cdhmanning@gmail.com>
When reset code is in flash, the jump instructions emitted by the
compiler are relative instead of absolute jumps.
A fix to the reset code to make correct jumps to the beginning of
code relocated to RAM have also been added.
Signed-off-by: Julius Baxter <juliusbaxter@gmail.com>
When CONFIG_ZERO_BOOTDELAY_CHECK is not defined, bootdelay==0
prevents the check for console input (as stated in README.autoboot).
This must also work in CONFIG_AUTOBOOT_KEYED mode.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Add support for specifying a differnt CPU for main u-boot and SPL
u-boot builds. This is done by adding an optional SPL CPU after the
main CPU in boards.cfg as follows:
normal_cpu:spl_cpu
This this case CPU will be set to "normal_cpu" during the main u-boot
build and "spl_cpu" during the SPL build.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.
Chage protoype declaration as static.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type
u8/u16/u32.
Although 'unsigned' for in_be32 and in_le32 is correct. But to make return type
uniform across the file changed to u32
Similarly, parameter passed to out_8, out_be16, out_le16 ,out_be32 & out_le32
should not be 'int'.Change it to type u8/u16/u32.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
In addition to the error message also display the error code. I had the
problem that my malloc memory was not enough (ENOMEM), and if u-boot
had displayed the error code immediately that would have saved me some
debugging.
Signed-off-by: Bernhard Walle <walle@corscience.de>
Use ubifs_err instead of printf.
Add "errno=%d" in output as suggested by Albert Aribaud.
Signed-off-by: Thomas Weber <weber@corscience.de>
Since run_command() and run_command_list() are important and a little
confusing, add some basic tests to check that the behaviour is correct.
Note: I am not sure that this should be committed, nor where it should go
in the source tree. Comments welcome.
To run the unit tests use the ut_cmd command available in sandbox:
make sandbox_config
make
./u-boot -c ut_cmd
(To test both hush and built-in parsers, you need to manually change
CONFIG_SYS_HUSH_PARSER in include/configs/sandbox.h and build/run again)
Signed-off-by: Simon Glass <sjg@chromium.org>
Any environment variable can hold commands to be executed by the 'run'
command. The environment variables preboot, bootcmd and menucmd have
special code for triggering execution in certain circumstances.
We adjust these calls to use run_command_list() instead of run_command().
This change permits these variables to have embedded newlines so that
they work the same as the 'source' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
This new function runs a list of commands separated by semicolon or newline.
We move this out of cmd_source so that it can be used by other code. The
PXE code also uses the new function.
Suggested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Simon Glass <sjg@chromium.org>
In file included from arch/arm/lib/board.c:43:0:
include/malloc.h:490:5: warning: "HAVE_MMAP" is not defined [-Wundef]
include/malloc.h:590:5: warning: "HAVE_USR_INCLUDE_MALLOC_H" is not defined [-Wundef]
include/malloc.h:757:5: warning: "HAVE_MMAP" is not defined [-Wundef]
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
All the global flag defines are the same across all arches. So unify them
in one place, and add a simple way for arches to extend for their needs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If we build everything correctly with multiple builds, and an
ERR directory had been previously created, we failed to report
that everything was fine because grep failed to find anything
in the ERR directory. Use grep -r, which doesn't complain if
there are no input files.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Tom Rini <trini@ti.com>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
powerpc/mpc85xx: Ignore E bit for BSC9130/1
powerpc/sgmii: To support PHY link state auto detect in SGMII mode
powerpc/85xx: improve definition of BR_PHYS_ADDR macro
powerpc/p2041: configure the CPLD lane_mux according to RCW
powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined
powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
powerpc/p1022ds: add support for SPI and SD boot
Signed-off-by: Wolfgang Denk <wd@denx.de>
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for. The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
PHYs on SGMII riser card are used in SGMII mode with different external
IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type
under ethernet node should be updated. Otherwise the PHY interrupt can not
be handled therefor PHY link state change can not be auto detected.
For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed
but it's still be kept to guarantee the sgmii mode could work with old
device tree.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro
definition, so callers had to supply their own parenthesis.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.
Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.
Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
ENV location compile logic is wrong, and when CONFIG_SYS_NO_FLASH is defined
and non-NOR u-boot is building, it will cause compile error. Also, add
CONFIG_SYS_FLASH_USE_BUFFER_WRITE for p2041, which will improve NOR flash
write performance.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation. Early commit eb672e92
works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM
mode before switching to indirect mode.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Renesas SH and R-Mobile set up device using PFC.
This provide the framework. Most codes were brought from linux kernel.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Even if using CPU is SH-4A, the previous code always put "SH4".
This patch fixes it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*"
(sha1: edffa63d3d)
renamed tegra2_spi.c to tegra_spi.c
and the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze"
(sha1: d978780b2e)
has wrongly resolved confict.
This patch fix it.
Signed-off-by: Michal Simek <monstr@monstr.eu>
This fix prevents env_import() CRC to fail when CONFIG_ENV_SIZE
is not equal to 4096 bytes
It also prevents mtd->read and mtd->write to be incomplete when
the environment is larger than 4096 bytes.
Signed-off-by: David du Colombier <0intro@gmail.com>
The HW guys suggested to change these two values. And these values are
now identical to the values we use on mgcoge.
PSDMR_WRC was set to 1C as it should lead to better performance.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
mgcoge2ne was an intermediate step towards mgcoge3ne. One difference is the
smaller SDRAM on mgcoge2ne (128MB). To support both boards with the same
u-boot we use here the SDRAM detection.
This patch enables SDRAM detection between 256MB and 128MB.
So in addition to the existing 256MB geometry:
4 chips x 8M (13 rows, 10 cols) x 16 bit x 4 banks
we can now also have 128MB geometry:
4 chips x 4M (13 rows, 9 cols) x 16 bit x 4 banks
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
This patch adds SDRAM detection feature to km82xx boards.
To enable this feature, define CONFIG_SYS_SDRAM_LIST as the initializer
for an array of struct sdram_conf_s.
These structs will expose the bitfields within registers PSDMR and OR1 which
have to be different between configurations; common bitfields will be
defined, as usual, within CONFIG_SYS_PSDMR and CONFIG_SYS_OR1.
If CONFIG_SYS_SDRAM_LIST is not defined, then the usual behavior is retained.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
The only file including km82xx-common.h is km82xx.h.
So there is no need to have it as a separate file.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need
to keep them as separate .h config files.
Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h
file.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* 'master' of git://git.denx.de/u-boot-i2c:
km/common: remove printfs for i2c deblocking code
CONFIG: SMDK5250: I2C: Enable I2C
I2C: Add support for Multi channel
I2C: Modify the I2C driver for EXYNOS5
I2C: Move struct s3c24x0_i2c to a common place.
EXYNOS: PINMUX: Add pinmux support for I2C
EXYNOS5: define EXYNOS5_I2C_SPACING
EXYNOS: Add I2C base address.
EXYNOS: CLK: Add i2c clock
mx6qsabrelite: add i2c multi-bus support
imx-common: add i2c.c for bus recovery support
i.mx53: add definition for I2C3_BASE_ADDR
i.mx: iomux-v3.c: move to imx-common directory
i.mx: iomux-v3.h: move to imx-common include directory
iomux-v3: remove include of mx6x_pins.h
mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS support
mxc_i2c: add bus recovery support
mxc_i2c: prep work for multiple busses support
mxc_i2c: add i2c_regs argument to i2c_imx_stop
mxc_i2c: add retries
mxc_i2c: check for arbitration lost
mxc_i2c: change slave addr if conflicts with destination.
mxc_i2c: don't disable controller after every transaction
mxc_i2c: place i2c_reset code inline
mxc_i2c: place imx_start code inline
mxc_i2c: remove redundant read
mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state
mxc_i2c.c: code i2c_probe as a 0 length i2c_write
mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write
mxc_i2c: create i2c_init_transfer
mxc_i2c: clear i2sr before waiting for bit
mxc_i2c: create tx_byte function
mxc_i2c: remove ifdef of CONFIG_HARD_I2C
mxc_i2c: fix i2c_imx_stop
i2c: deblock i2c bus also if accessed before realocation
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-microblaze:
microblaze: Wire up SPI driver
spi: microblaze: Adds driver for Xilinx SPI controller
microblaze: intc: Clear interrupt code
microblaze: Call serial multi initialization
microblaze: Move __udelay implementation
microblaze: Remove extern from board.c
microblaze: Wire up dts configuration
fdt: Add board specific dts inclusion
microblaze: Move individual board linker scripts to common script in cpu tree.
microblaze: Add gpio.h
microblaze: Add missing undefs for UBI and UBIFS
microblaze: Expand and correct configuration comments
microblaze: Enable ubi support
microblaze: Avoid compile error on systems without cfi flash
microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION
Conflicts:
drivers/spi/Makefile
Signed-off-by: Wolfgang Denk <wd@denx.de>
This code will also be used before reallocation and during this time we
are not allowed to do these printings.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
This patch modifies the S3C I2C driver to suppport EXYNOS5.
The cahnges made to driver are as follows:
- I2C base address is passed as a parameter to many
functions to avoid multiple #ifdef
- Channel initialisation is moved to a commom funation
as it is required by i2c_init.
- Hardcoding for I2CCON_ACKGEN removed.
- Replaced printf with debug.
- Checkpatch issues resolved.
- Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c
to avoid repeated setting of gpio lines, as it have multi bus support.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch defined EXYNOS5_I2C_SPACING used to calculate I2C channel
base address.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add support for calling a function that will toggle the
SCL line to return the bus to idle condition.
The actual toggling function is added in a later patch.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
This helps in a multiple bus master environment which
is why I also added a wait for bus idle.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Not using udelay gives a more accurate timeout. The current implementation of udelay
in imx-common does not seem to wait at all for a udelay(1).
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
----
V2: Added WATCHDOG_RESET as suggested by Marek Vasut
add error message when stop fails
mxc_i2c: code i2c_probe as a 0 length i2c_write
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Let's clear the sr register before waiting for
bit to be set, instead of clearing it after
hardware sets it. No real operational difference here,
but allows combining of i2c_imx_trx_complete and
i2c_imx_bus_busy in later patches.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
This is always selected when CONFIG_I2C_MXC is
selected, so it adds no value.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Instead of clearing 2 bits, all the other
bits were set because '|=' was used instead
of '&='.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
If we switch to a different i2c bus in changing the mux config for the
i2c mux, we have to be sure to deblock the bus also before realocation.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Depending on XILINX_SPI_FLASH_BASEADDR enable SPI flash
and environment in SPI flash.
Expected values from xparameters.h are:
- XILINX_SPI_FLASH_BASEADDR
- XILINX_SPI_FLASH_MAX_FREQ
- XILINX_SPI_FLASH_CS
Signed-off-by: Stephan Linz <linz@li-pro.net>
Acked-by: Michal Simek <monstr@monstr.eu>
This is an improved version of the driver patch original
submitted by Graeme Smecher <graeme.smecher@mail.mcgill.ca>
The changes are:
- remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
use CONFIG_SYS_SPI_BASE from config.h instead
- add extensive register struct definitions
- remove offset calculation for register access and
use the new register struct instead
- move default SPI controller configuration from
spi_setup_slave() to spi_claim_bus()
- add spi_set_speed()
- insert SPI controller deactivation in spi_release_bus()
- protect while loops in spi_xfer() with counter / timeouts
- support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP
Come from:
http://patchwork.ozlabs.org/patch/71797/
Signed-off-by: Stephan Linz <linz@li-pro.net>
Tested-by: Michal Simek <monstr@monstr.eu>
* 'next' of git://git.denx.de/u-boot:
MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
doc: cleanup - move board READMEs into respective board directories
net: sh_eth: add support for SH7757's GETHER
net: sh_eth: modify the definitions of regsiter
net: sh_eth: add SH_ETH_TYPE_ condition
net: sh_eth: clean up for the SH7757's code
net: fec_mxc: Fix MDC for xMII
net: fec_mxc: Fix setting of RCR for xMII
net: nfs: make NFS_TIMEOUT configurable
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <wd@denx.de>
Hawkboard was using the wrong nand_read_page version for SPL image.
As a side effect, the u-boot image loaded by the SPL from nand
was getting corrupted.
Enable CONFIG_SYS_NAND_HW_ECC_OOBFIRST to select the correct nand_read_page
algorithm for SPL.
Signed-off-by: Linu Cherian <linucherian@gmail.com>
Acked-by: Sughosh Ganu <urwithsughosh@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
cpu.c: In function ‘check_CPU’:
cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Subject slightly changed.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Tested on TQM855MDCBAB7-T66.102 (MPC855T at 66 MHz) and
TQM860LDB0A3-T50.202 (MPC860T at 50MHz).
Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
make would spit out a message like
Generating /tmp/build/include/generated/asm-offsets.h
even when running with option "-s". Fix this.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix some remains of the renaming of inca-swap-bytes introduced in
commit 60b74bde92
MIPS: INCA-IP: rename inca-swap-bytes host tool
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
NetConsole may call NetSendUDPPacket before NetLoop is called. This
will cause the source MAC address (NetOurEther) to be wrong. Instead
of only changing it in NetLoop, move it to NetLoopInit so that it is
also updated when net_init() is called (especially by nc_start()).
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Michael Walle <michael@walle.cc>
Acked-by: Michael Walle <michael@walle.cc>
SH7757 has 2 ETHERs and 2 GETHERs. This patch supports the SH7757's
GETHER. If CONFIG_SH_ETHER_USE_GETHER is defined using SH7757,
the driver handles the GETHER.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
At the moment, the driver supports the following CPUs:
- GETHER (Gigabit Ethernet) : SH7763, SH7734
- ETHER (Fast Ethernet) : SH7724, SH7757
And the driver had the following "#if":
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
- Those are for GETHER
#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
- This is for ETHER
So, for clean up the code, this patch adds SH_ETH_TYPE_GETHER and
SH_ETH_TYPE_ETHER. And then, the patch modifies the above "#if".
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
This fixes:
cmd_bc3450.c:55:0: warning: "CONFIG_SYS_CPU" redefined [enabled by default]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
* 'master' of git://git.denx.de/u-boot-arm:
ARM1136: Fix cache range checks
mx6: Make pad name macro consistent with the datasheet
mx28: Fix elftosb source link in README.mx28_common
doc: README.mx28_common: Add missing entry into Contents
Signed-off-by: Wolfgang Denk <wd@denx.de>
An empty flush_dcache_range() was added into MPC83xx and MPC85xx to
work with drivers shared with other architecture. However, it is
compiled only if USB is set, but it is required for other drivers
(FSL_ESDHC), too.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Andy Fleming <afleming@gmail.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Marek Vasut <marex@denx.de>
CC: Wolfgang Denk <wd@denx.de>
Added MPC83xx version.
Signed-off-by: Wolfgang Denk <wd@denx.de>
bad_cache_range actually returned true if the range was OK, but it was used
according to its name, which resulted in all valid dcache range invalidate/flush
operations being dropped. Hence, most DMA transfers resulted in garbage data.
This patch renames this function according to what it does, and it fixes the
interpretation of its return value by other functions. The chosen naming is the
same as for ARM926EJ-S in order to be consistent.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Stefano Babic <sbabic@denx.de>
Use the same name as defined in the datasheet.
DSP_CLK -> DISP_CLK
Signed-off-by: Ashok Kumar Reddy Kourla <ashokkourla2000@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
commit 419ea2d84 (mx28: Split the README into a common part and a m28 specific part)
missed an entry in the Contents section that was part of the original file.
Add the missing entry for completeness.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
* 'master' of git://git.denx.de/u-boot-arm:
ARM: lib: Remove CONFIG_ARCH_CPU_INIT dependency
ARM: OMAP4: PANDA: Add rest of the USB module pads to essentials
arm: armv7: add compile option -mno-unaligned-access if available
arm: Fix to mistake clean the memory space
Signed-off-by: Wolfgang Denk <wd@denx.de>
Remove this as including it on global scale breaks a lot of things.
This was reported by:
Matthew McClintock <B29882@freescale.com>
Fix found by:
Tom Rini <trini@ti.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
- dcache_flush_rang -> flush_dcache_rang
- icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range
Signed-off-by: Macpaul Lin <macpaul@gmail.com>
Create a weak-aliased arch_cpu_init, so that we can get rid of CONFIG_ARCH_CPU_INIT
and always call arch_cpu_init.
This way we do not need to define CONFIG_ARCH_CPU_INIT in every board file, since
arch_cpu_init() is supposed to handle common CPU level code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
In commit 1a89a217f5 we moved most of the
required pads and mux data for USB to the essential list so that later
on we could NOT enable anything that wasn't essential unless otherwise
configured. This was however missing a few pandaboard-specific parts
which left for example USB ethernet non-functional.
Tested this on OMAP4430 ES2.2, OMAP4460 ES1.1 PANDA boards.
(Reworded by Tom Rini to be more precise about what the problem was)
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Tested-by: Tom Rini <trini@ti.com>
Recent compiler generates unaligned memory access in armv7 default.
But current U-Boot does not allow unaligned memory access, so it causes
data abort exception.
This patch add compile option "-mno-unaligned-access" if it is available.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Gary Thomas <gary@mlbassoc.com>
In currently, when __bss_start is equal to __bss_end__,
The bss loop will clear all the things in memory space.
But just only when __bss_end__ greater than __bss_start__,
we do the clear bss section operation.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* 'master' of git://git.denx.de/u-boot-usb:
usb_storage: fix ehci driver max transfer size
smsc95xx: align buffers to cache line size
ehci-hcd: change debug() to printf() in case of errors
usb: check return value of submit_{control, bulk}_msg
usb: pass cache-aligned buffer to usb_get_descriptor()
ehci-hcd: fix external buffer cache handling
ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
ehci-hcd: program asynclistaddr before every transfer
common.h: Introduce DEFINE_CACHE_ALIGN_BUFFER
ehci-omap: Do not call dcache_off from omap_ehci_hcd_init
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: inline useless id defines
sf: drop unused/duplicate command defines
Signed-off-by: Wolfgang Denk <wd@denx.de>
We have a header file specifically for mingw cruft, so keep it there
to avoid crap spreading into the main tools. This lets our devs just
worry about *nix systems.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
In an effort to unify the spi flash drivers further, drop all the
unused and/or duplicate command defines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so
mii_speed has to be set for all these interfaces, and not only for MII.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
At least on i.MX25, the RMII mode did not work, which is fixed by this patch.
The MII_MODE bit of the FEC RCR register means xMII, i.e. 'not 7-wire', so set
it accordingly.
According to the xMII and 7-wire (aka GPSI) standards, full duplex should be
available on xMII, but not on 7-wire, so set FCE accordingly. The FEC may
support full duplex for 7-wire too, but the reference manual does not say that,
so avoid an invalid assumption. Actually, the choice between half and full
duplex also depends on the endpoint/switch/repeater configuration, so a config
option could be added for that, but there has been no need for it so far.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Now that common code doesn't declare these as volatile, we don't need to
either anymore. This fixes the build warning:
bfin_mac.c: In function 'bfin_EMAC_recv':
bfin_mac.c:193:23: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The commit 5dd95cf93d 'usb_storage:
Fix EHCI "out of buffer pointers" with CD-ROM' introduce a bug in
usb_storage as it wrongly assumes that every transfer can use
4096 bytes per qt_buffer. This is wrong if the start address of
the data is not page aligned to 4096 bytes and leads to 'EHCI
timed out on TD' messages because of 'out of buffer pointers'
in ehci_td_buffer function.
The bug appears during load of a fragmented file and
read from or write to an unaligned memory address.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Return values of submit_{control,bulk}_msg() functions
should be checked to detect possible error.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
usb_get_descriptor passes it's buffer argument directly to
usb_control_msg() so it has to be properly aligned/padded.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Buffer coming from upper layers should be cacheline aligned/padded
to perform safe cache operations. For now we don't do bounce
buffering so getting unaligned buffer is an upper layer error.
We can't check if the buffer is properly padded with current
interface so just assume it is (consider changing with in the
future). The following changes are done:
1. Remove useless length alignment check. We get actual transfer
length not the size of the underlying buffer so it's perfectly
valid for it to be unaligned.
2. Move flush_dcache_range() out of while loop or it will
flush too much.
3. Don't try to fix buffer address before calling invalidate:
if it's unaligned it's an error anyway so let cache subsystem
cry about that.
4. Fix end buffer address to be cacheline aligned assuming upper
layer reserved enough space. This is potentially dangerous
operation so upper layers should be careful about that.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here
as we are not allowed to have tests inside of align(...).
Signed-off-by: Tom Rini <trini@ti.com>
[marek.vasut]: introduce some crazy macro voodoo
Signed-off-by: Marek Vasut <marex@denx.de>
[ilya.yanok]: moved external buffer fixes to separate patch,
we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN
for qh_list, qh and qtd structures to make sure they are proper aligned
for both controller and cache operations.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Move or_asynclistaddr programming to ehci_submit_async()
function to make sure queue head is properly programmed
before every transfer. This solves the problem with changing
qh address.
Also remove unneeded qh_list->qh_link reprogramming at the
end of transfer.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This is the out-of-function-scope counterpart of
ALLOC_CACHE_ALIGN_BUFFER.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
[ilya.yanok]: added missing <linux/compiler.h> include and
{DEFINE,ALLOC}_ALIGN_BUFFER macros allowing explicit alignment
specification.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* 'next' of git://git.denx.de/u-boot-video:
ipu_common: Add ldb_clk for use in parenting the pixel clock
ipu_common: Do not hardcode the ipu_clk frequency
ipu_common: Rename MXC_CCM_BASE
ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
ipu_common: Only apply the erratum to MX51
video: Rename CONFIG_VIDEO_MX5
mx6: Allow mx6 to access the IPUv3 registers
common lcd: minor coding style changes
Signed-off-by: Wolfgang Denk <wd@denx.de>
As suggested by Graeme Russ, move gd and bd data structrures
to BSS instead of calculating the locations around the stack
and heap.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Mike Frysinger <vapier@gentoo.org>
For FSL low-end processors (VVN2.2), in order to detect the SD card,
we should enable PEREN, HCKEN and IPGEN to enable the clock.
Otherwise, after booting the u-boot, and then inserting the SD card,
the SD card can't be detected.
For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used.
And when accessing to these reserved bit, no any impact happened.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Use the function 'mmc_send_status' to check the card status.
only when the card is ready, driver can send the next erase command
to the card, otherwise, the erase will failed:
=> mmc erase 0 1
MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK
=> mmc erase 0 2
MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed
1 blocks erase: ERROR
=> mmc erase 0 4
MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed
1 blocks erase: ERROR
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This code adds call to mmc_init(), for partition related commands (e.g.
fatls, fatinfo etc.).
It is safe to call mmc_init() multiple times since mmc->has_init flag
prevents from multiple initialization.
The FAT related code calls get_dev high level method and then uses
elements from mmc->block_dev, which is uninitialized until the mmc_init
(and thereof mmc_startup) is called.
This problem appears on boards, which don't use mmc as the default
place for envs
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
NFS_TIMEOUT is constant value defined in net/nfs.c. But sometimes it needs to adjust.
This patch enables to override NFS_TIMEOUT by defining CONFIG_NFS_TIMEOUT in a board specific config file.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* 'next' of git://git.denx.de/u-boot-net:
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-i2c:
mx28evk: Add I2C support
mxs-i2c: Fix internal address byte order
mxc_i2c: remove setting speed at each start
mx6qsabrelite: add i2c support
mxc_i2c: specify i2c base address in config file
Signed-off-by: Wolfgang Denk <wd@denx.de>
If the net driver has setup a valid ethernet address and an ethernet
address is not set in the environment already, then set the environment
variables from the net driver setting.
This enables pxe booting on boards which don't set ethaddr env variable.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
This commit is an add-on to f6c4191f. There are a few registers where
consecutive writes to the same location should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers:
Registers 0-3 All bits
Registers 6-7 All bits
Register 10 All bits
Register 11 All bits except for 5-6.
Registers 16-47 All bits
Register 48 All bits except for 18-16, 14.
Register 448 Bit 4.
Register 459 Bits 0-3.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Matthew Gerlach <mgerlach@altera.com>
Acked-by: Amit Virdi <amit.virdi@st.com>
Micrel accidentally used the same part number
for the KS8721 and KSZ9021. So, both cannot be
in the same build of u-boot. Add a config option
to handle this.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Nobuhiro Iwamamatsu <nobuhiro.iwamatsu.yj@renesas.com> (sh_eth part)
Acked-by: Stephan Linz <linz@li-pro.net> (Xilinx part, xilinx_axi_emac and xilinx_ll_temac)
Reviewed-by: Marek Vasut <marex@denx.de> (FEC part)
phy_startup() calls the PHY driver's startup function, but it ignores the
return code from that function, and so it never returns any failures.
Signed-off-by: Timur Tabi <timur@freescale.com>
The block argument for store_block can be -1 when the tftp sequence
number rolls over (i.e TftpBlock == 0), so the first argument to
store_block has to be of type 'int' instead of 'unsigned'.
In our environment (gcc 4.4.5 mips toolchain), this causes incorrect
'offset' to be generated for storing the block, and the tftp block
with number 0 will be written elsewhere, resulting in a bad block in
the downloaded file and a memory corruption.
Signed-off-by: Jayachandran Chandrasekharan Nair <jayachandranc@netlogicmicro.com>
Add I2C support.
Tested by placing a 24LC16 EEPROM into the U50 slot which comes empty from factory.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory.
These devices require that the high byte of the internal address has to be
written first.
The mxs_i2c driver currently writes the address' low byte first.
The following patch fixes the byte order of the internal address that should
be written to the I2C device.
Signed-off-by: Torsten Fleischer <to-fleischer@t-online.de>
CC: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Other then being very weird, this code was also wrong.
For example, say I set speed to 100K. I'll read back the speed
as 85937. But the speed is really 85937.5, so we I reset
the speed to 85937, I'll get 73660.7. After a couple of transactions
my speed is now exactly 68750 so it will remain there.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The clean up patch missed an &, so we end up passing an int rather than
a pointer to the sprintf function.
arp.c: In function 'ArpReceive':
arp.c:197: warning: format '%p' expects type 'void *', but argument 3 has type 'int'
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed.
Therefore SH7757 and SH7724 can not build. This revise this probelem.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Clear and prepare for device-tree driven configuration.
Remove CONFIG_SYS_INTC_0 definition
Use dynamic allocation instead of static.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
Move __udelay to the timer code because of unification.
And clean coding style because of checkpatch.pl.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
The registers accessed inside clk_ipu_enable/disable are not present on MX6,
so make sure they only run on MX51 and MX53.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The following erratum :
"ENGcm08316
IPU: Clarification regarding the bypass mode registers setup for
display and camera interfaces"
only applies to mx51, so restrict its usage for this SoC only.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
- enable OF control and embedded OF
- set default device tree file name to 'microblaze'
- add CPP to dtc proxy: board/xilinx/dts/microblaze.dts
- add an empty but processable dts for microblaze-generic
Signed-off-by: Stephan Linz <linz@li-pro.net>
Some architectures, for example Microblaze, doesn't need a
splitted device tree because every Microblaze hw design is
different. The individuell Microblaze device tree will be
auto generated by FPGA design tools and could be used directly
with dtc.
The auto generated dts for Microblaze can not processed by CPP.
Unfortunately that is the default procedure in U-Boot to merge
a splitted device tree (substitution of ARCH_CPU_DTS).
Microblaze will never use the ARCH_CPU_DTS substitution and we
introduce the new board specific substitution variable BOARD_DTS
that points into vendor/board/dts subdir with the file name
of CONFIG_DEFAULT_DEVICE_TREE. The common dts file in vendor/dts
subdir (defined by CONFIG_DEFAULT_DEVICE_TREE) contain a single
include line that can processed by CPP:
/include/ BOARD_DTS
Signed-off-by: Stephan Linz <linz@li-pro.net>
Tested-by: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
- fix CONFIG_SYS_MALLOC_BASE from 0x11FB_F000 to 0x13EF_F000
- add new size calculation for CONFIG_SYS_MONITOR_LEN
and CONFIG_SYS_MALLOC_LEN derived from SIZE
- change CONFIG_SYS_MONITOR_BASE and CONFIG_SYS_MALLOC_BASE
calculation to a symbolic equation with the corresponding
_LEN definitions
- add a "CFI flash memory layout - Example" comment
Signed-off-by: Stephan Linz <linz@li-pro.net>
Increase malloc area for UBI to >= 512k -- foreseeing of UBIFS
set to 768k. To save memory in flash (CONFIG_SYS_MONITOR_LEN)
the UBIFS is disabled by default.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Use XILINX_FLASH_START to set/unset FLASH and RAMENV.
Error:
board.c: In function 'board_init':
board.c:134: error: 'XILINX_FLASH_START' undeclared (first use in this function)
board.c:134: error: (Each undeclared identifier is reported only once
board.c:134: error: for each function it appears in.)
Signed-off-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Michal Simek <monstr@monstr.eu>
CONFIG_SYS_FLASH_PROTECTION is defined twice. The second one
is outside the flash configuration context and we can remove
it safely.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Note: because 4-byte addressing is not supported yet,
at the moment only the first 16MiB of the device are available.
Signed-off-by: Jérôme Carretero <cJ@zougloub.eu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
SPI flash operations inadvertently stretching beyond the flash size will
result in a wraparound. This may be particularly dangerous when burning
u-boot, because the flash contents will be corrupted rendering the board
unusable, without any warning being issued.
So add a consistency checking so not to overflow past the flash size.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The only two drivers to write the status register do it in the same
way, so unify the implementations. This also makes the block unlock
logic the same.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The local sst enable/disable write funcs don't really add anything
over the common API, so just inline the common calls directly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Analysis of the flash drivers shows that they all use 0x20 if the erase
size is 4KiB, or 0xd8 if it's larger. So with this info in hand, we can
unify all the erase functionality in one place.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
I imagine much of these constants are due to copy & pasting previous
drivers rather than an actual reflection of the hardware layout. At
any rate, inline the info that we don't care about externally as it
shrinks things nicely.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The bf527-ezkit boards are getting too big to fit into their reserved
flash space, so we need to use a lzma compressed logo.
Since the video driver code is very similar, add lzma compressed support
to all of the Blackfin video drivers.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-02-03 20:44:54 -05:00
1180 changed files with 65462 additions and 27690 deletions
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