leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

Browse Source
This commit is contained in:
Tom Rini 2012-09-18 14:56:31 -07:00
commit 49b3962d20
3 changed files with 93 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
board/freescale/mpc8308rdb/mpc8308rdb.c
View File

@ -24,18 +24,56 @@
#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
#include <spi.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The following are used to control the SPI chip selects for the SPI command.
*/
#ifdef CONFIG_MPC8XXX_SPI
#define SPI_CS_MASK 0x00400000
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/* active low */
clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/* inactive high */
setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
}
#endif /* CONFIG_MPC8XXX_SPI */
#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(bd_t *bd)
{
return fsl_esdhc_mmc_init(bd);
}
#endif
static u8 read_board_info(void)
{
u8 val8;
@ -109,6 +147,25 @@ void pci_init_board(void)
*/
int misc_init_r(void)
{
#ifdef CONFIG_MPC8XXX_SPI
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
sysconf83xx_t *sysconf = &immr->sysconf;
/*
* Set proper bits in SICRH to allow SPI on header J8
*
* NOTE: this breaks the TSEC2 interface, attached to the Vitesse
* switch. The pinmux configuration does not have a fine enough
* granularity to support both simultaneously.
*/
clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
puts("WARNING: SPI enabled, TSEC2 support is broken\n");
/* Set header J8 SPI chip select output, disabled */
setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
#endif
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
@ -124,6 +181,7 @@ void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
}
#endif

4
drivers/spi/mpc8xxx_spi.c
View File

@ -124,6 +124,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
* len > 16 0
*/
spi->mode &= ~SPI_MODE_EN;
if (bitlen <= 16) {
if (bitlen <= 4)
spi->mode = (spi->mode & 0xff0fffff) |
@ -138,6 +140,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
dout += 4;
}
spi->mode |= SPI_MODE_EN;
spi->tx = tmpdout; /* Write the data out */
debug("*** spi_xfer: ... %08x written\n", tmpdout);

31
include/configs/MPC8308RDB.h
View File

@ -37,6 +37,24 @@
#define CONFIG_MISC_INIT_R
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1
#define CONFIG_MMC 1
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_USE_PIO
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
/*
* On-board devices
*
@ -340,6 +358,19 @@
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* SPI on header J8
*
* WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
* due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
*/
#ifdef CONFIG_MPC8XXX_SPI
#define CONFIG_CMD_SPI
#define CONFIG_USE_SPIFLASH
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#endif
/*
* Board info - revision and where boot from