da850evm: setup the NAND flash timings
The default NAND flash timings are very conservative. This patch assigns the timings reccomended in the recent linux kernel patch [1] from Sekhar Nori. The speedup, as reported in that patch, is 5.3x for reads. [1] http://www.spinics.net/lists/arm-kernel/msg100278.html Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
parent
756d1fe7ac
commit
a3f88293dd
@ -24,6 +24,7 @@
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/io.h>
|
||||
#include "../common/misc.h"
|
||||
#include "common.h"
|
||||
@ -98,6 +99,23 @@ int board_init(void)
|
||||
irq_init();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_NAND_DAVINCI
|
||||
/*
|
||||
* NAND CS setup - cycle counts based on da850evm NAND timings in the
|
||||
* Linux kernel @ 25MHz EMIFA
|
||||
*/
|
||||
writel((DAVINCI_ABCR_WSETUP(0) |
|
||||
DAVINCI_ABCR_WSTROBE(0) |
|
||||
DAVINCI_ABCR_WHOLD(0) |
|
||||
DAVINCI_ABCR_RSETUP(0) |
|
||||
DAVINCI_ABCR_RSTROBE(1) |
|
||||
DAVINCI_ABCR_RHOLD(0) |
|
||||
DAVINCI_ABCR_TA(0) |
|
||||
DAVINCI_ABCR_ASIZE_8BIT),
|
||||
&davinci_emif_regs->ab2cr); /* CS3 */
|
||||
#endif
|
||||
|
||||
/* arch number of the board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user