snowball: Moving to ux500.v2 addess scheme for PRCMU access
Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
This commit is contained in:
Mathieu J. Poirier
Albert ARIBAUD
parent
81637e26b3
commit
101a769d75
@ -36,9 +36,10 @@
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#include <asm/arch/prcmu.h>
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/* CPU mailbox registers */
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#define PRCM_MBOX_CPU_VAL (U8500_PRCMU_BASE + 0x0fc)
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#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100)
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#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104)
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#define PRCMU_I2C_WRITE(slave) \
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(((slave) << 1) | I2CWRITE | (1 << 6))
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#define PRCMU_I2C_READ(slave) \
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(((slave) << 1) | I2CREAD | (1 << 6))
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#define I2C_MBOX_BIT (1 << 5)
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@ -50,26 +51,39 @@ static int prcmu_is_ready(void)
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return ready;
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}
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static int _wait_for_req_complete(int num)
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static int wait_for_i2c_mbx_rdy(void)
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{
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int timeout = 1000;
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int timeout = 10000;
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/* checking any already on-going transaction */
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while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout)
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if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) {
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printf("prcmu: warning i2c mailbox was not acked\n");
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/* clear mailbox 5 ack irq */
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writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
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}
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/* check any already on-going transaction */
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while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout)
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timeout--;
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timeout = 1000;
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if (timeout == 0)
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return -1;
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return 0;
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}
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static int wait_for_i2c_req_done(void)
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{
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int timeout = 10000;
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/* Set an interrupt to XP70 */
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writel(1 << num, PRCM_MBOX_CPU_SET);
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writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET);
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while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout)
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/* wait for mailbox 5 (i2c) ack */
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while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout)
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timeout--;
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if (!timeout) {
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printf("PRCMU operation timed out\n");
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if (timeout == 0)
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return -1;
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}
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return 0;
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}
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@ -84,6 +98,7 @@ int prcmu_i2c_read(u8 reg, u16 slave)
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{
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uint8_t i2c_status;
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uint8_t i2c_val;
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int ret;
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if (!prcmu_is_ready())
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return -1;
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@ -91,13 +106,23 @@ int prcmu_i2c_read(u8 reg, u16 slave)
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debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
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reg, slave);
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ret = wait_for_i2c_mbx_rdy();
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if (ret) {
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printf("prcmu_i2c_read: mailbox became not ready\n");
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return ret;
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}
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/* prepare the data for mailbox 5 */
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writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG);
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writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
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writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
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writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
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writeb(0, PRCM_REQ_MB5_I2CVAL);
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_wait_for_req_complete(REQ_MB5);
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ret = wait_for_i2c_req_done();
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if (ret) {
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printf("prcmu_i2c_read: mailbox request timed out\n");
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return ret;
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}
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/* retrieve values */
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debug("ack-mb5:transfer status = %x\n",
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@ -109,16 +134,14 @@ int prcmu_i2c_read(u8 reg, u16 slave)
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i2c_status = readb(PRCM_ACK_MB5_STATUS);
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i2c_val = readb(PRCM_ACK_MB5_VAL);
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/* clear mailbox 5 ack irq */
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writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
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if (i2c_status == I2C_RD_OK)
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return i2c_val;
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else {
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printf("prcmu_i2c_read:read return status= %d\n",
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i2c_status);
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return -1;
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}
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printf("prcmu_i2c_read:read return status= %d\n", i2c_status);
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return -1;
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}
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/**
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@ -131,6 +154,7 @@ int prcmu_i2c_read(u8 reg, u16 slave)
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int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
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{
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uint8_t i2c_status;
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int ret;
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if (!prcmu_is_ready())
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return -1;
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@ -138,14 +162,23 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
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debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
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reg, slave);
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ret = wait_for_i2c_mbx_rdy();
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if (ret) {
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printf("prcmu_i2c_write: mailbox became not ready\n");
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return ret;
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}
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/* prepare the data for mailbox 5 */
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writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG);
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writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
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writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
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writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
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writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
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debug("\ncpu_is_u8500v11\n");
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_wait_for_req_complete(REQ_MB5);
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ret = wait_for_i2c_req_done();
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if (ret) {
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printf("prcmu_i2c_write: mailbox request timed out\n");
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return ret;
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}
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/* retrieve values */
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debug("ack-mb5:transfer status = %x\n",
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@ -157,12 +190,14 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
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i2c_status = readb(PRCM_ACK_MB5_STATUS);
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debug("\ni2c_status = %x\n", i2c_status);
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/* clear mailbox 5 ack irq */
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writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
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if (i2c_status == I2C_WR_OK)
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return 0;
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else {
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printf("ape-i2c: i2c_status : 0x%x\n", i2c_status);
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return -1;
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}
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printf("%s: i2c_status : 0x%x\n", __func__, i2c_status);
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return -1;
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}
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void u8500_prcmu_enable(u32 *reg)
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@ -62,7 +62,7 @@
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/* Per4 */
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#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
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#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
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#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x06800)
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/* Per3 */
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#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
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@ -28,6 +28,7 @@
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#define I2CWRITE 0
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#define PRCMU_BASE U8500_PRCMU_BASE
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#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE
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#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
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#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
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#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
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@ -38,12 +39,15 @@
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#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
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#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
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#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
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#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC)
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#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100)
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#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
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#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494)
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#define PRCM_TCR (PRCMU_BASE + 0x1C8)
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#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44)
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#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4)
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#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC)
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#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44)
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#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4)
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#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC)
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/* Mailbox 5 Requests */
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#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
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#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
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