am33xx: Add support for TI AM335x StarterKit EVM
- Board requires gpio0 #7 to be set to power DDR3. - Board uses DDR3, add a way to determine which DDR type to call config_ddr with. - Both of the above require filling in the header structure early, move it into the data section. Signed-off-by: Tom Rini <trini@ti.com>
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@ -29,6 +29,7 @@
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#include <asm/io.h>
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#include <asm/omap_common.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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@ -52,6 +53,9 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
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#define MII_MODE_ENABLE 0x0
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#define RGMII_MODE_ENABLE 0xA
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/* GPIO that controls power to DDR on EVM-SK */
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#define GPIO_DDR_VTT_EN 7
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/*
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@ -72,13 +76,18 @@ struct am335x_baseboard_id {
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char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
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};
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static struct am335x_baseboard_id header;
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static struct am335x_baseboard_id __attribute__((section (".data"))) header;
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static inline int board_is_bone(void)
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{
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return !strncmp(header.name, "A335BONE", NAME_LEN);
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}
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static inline int board_is_evm_sk(void)
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{
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return !strncmp("A335X_SK", header.name, NAME_LEN);
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}
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/*
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* Read header information from EEPROM into global structure.
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*/
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@ -144,6 +153,18 @@ static void init_timer(void)
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}
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#endif
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/*
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* Determine what type of DDR we have.
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*/
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static short inline board_memory_type(void)
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{
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/* The following boards are known to use DDR3. */
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if (board_is_evm_sk())
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return EMIF_REG_SDRAM_TYPE_DDR3;
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return EMIF_REG_SDRAM_TYPE_DDR2;
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}
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/*
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* early system init of muxing and clocks.
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*/
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@ -185,7 +206,23 @@ void s_init(void)
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preloader_console_init();
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config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
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/* Initalize the board header */
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (read_eeprom() < 0)
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puts("Could not get board ID.\n");
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if (board_is_evm_sk()) {
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/*
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* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
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* This is safe enough to do on older revs.
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*/
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enable_gpio0_7_pin_mux();
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gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
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gpio_direction_output(GPIO_DDR_VTT_EN, 1);
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}
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config_ddr(board_memory_type());
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#endif
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/* Enable MMC0 */
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@ -18,6 +18,7 @@
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extern void enable_uart0_pin_mux(void);
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extern void enable_mmc0_pin_mux(void);
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extern void enable_gpio0_7_pin_mux(void);
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extern void enable_i2c0_pin_mux(void);
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extern void enable_mii1_pin_mux(void);
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extern void enable_rgmii1_pin_mux(void);
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@ -288,6 +288,11 @@ static struct module_pin_mux i2c1_pin_mux[] = {
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{-1},
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};
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static struct module_pin_mux gpio0_7_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
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{-1},
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};
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static struct module_pin_mux rgmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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@ -370,3 +375,8 @@ void enable_mii1_pin_mux(void)
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{
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configure_module_pin_mux(mii1_pin_mux);
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}
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void enable_gpio0_7_pin_mux(void)
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{
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configure_module_pin_mux(gpio0_7_pin_mux);
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}
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