There are uint8_t, uint32_t types in regs-common.h, so include
linux/types.h.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Change mxs_set_lcdclk prototype to add a new parameter
base_addr. There are two LCD interfaces for i.MX6SX,
we may support LCDIF1 or LCDIF2.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
1. add basic psci support for imx7 chip.
2. support cpu_on and cpu_off.
3. switch to non-secure mode when boot linux kernel.
4. set csu allow accessing all peripherial register in non-secure mode.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
The code such as PSCI in section named secure is bundled with
u-boot image, and when bootm, the code will be copied to their
runtime address same to compliation/linking address -
CONFIG_ARMV7_SECURE_BASE.
When compile the PSCI code and link it into the u-boot image,
there will be relocation entries in .rel.dyn section for PSCI.
Actually, we do not needs these relocation entries.
If still keep the relocation entries in .rel.dyn section,
r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid
address which may not support read/write for one SoC.
102 /* relative fix: increase location by offset */
103 add r0, r0, r4
104 ldr r1, [r0]
105 add r1, r1, r4
106 str r1, [r0]
So discard them to avoid touching the relocation entry in
arch/arm/lib/relocate.S.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
p2371-2180 is the engineering board name for the Jetson TX1 developer
kit. Update Kconfig description and help text to make this obvious to
everyone.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Rename GPU functions to less generic names to avoid potential name
collisions.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enable the GPU node in the system-wide ft_system_setup() hook instead of
the board-specific ft_board_hook(). This allows us to enable GPU per SoC
generation instead of per-board as we did initially.
Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There is no justification for this function, especially in exported
form.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add code to detect timeouts when waiting for HW events such as PLL
lock done. Any errors are logged and trigger an error return code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the tables defining which pads and mux options exist in the Tegra210
XUSB padctl hardware.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This change simply deletes code from the Tegra210 XUSB padctl driver that
is already present in the common XUSB padctl code. Since all the arrays
in tegra210_socdata are empty, this update may leave the Tegra210 XUSB
padctl driver non-functional at run-time. However, (a) this driver is not
used yet so no regression can be observed and (b) the next commit will
immediately fix this up.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There are some differences between the Tegra124 and Tegra210 XUSB padctl
code. So far, the common XUSB padctl code only supports Tegra124. Add
some parameters etc. so that it can work for both chips.
This also allows moving Tegra124's process_nodes() into the common file;
something that would have requires edits during the move if done in the
previous commit.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A fair amount of the XUSB padctl driver will be common between Tegra124
and Tegra210. To avoid cut/paste between the two chips, create a new
file that will contain the common code, and convert the Tegra124 code to
use it. This change doesn't move every last piece of code that can/will be
shared, but rather concentrates on moving code that can be moved with zero
changes, so there are no other diffs mixed in.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This file defines pr_fmt(), so the individual error() calls don't need to
include the prefix in their format strings. Doing so results in duplicate
text in any error messages. Remove the duplication.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A future patch will soon move some of the XUSB padctl code into a common
file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file
to avoid conflicting with that, or being confusing.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
p2371-2180 has two PCI ports; a regular x4 slot and a x1 M.2 slot. This
patch adds the relevant DT to enable the PCI controller and configure
the XUSB padctl pin muxing, and code to turn on the PCI power and enable
PCI features in U-Boot. I have only tested the x4 slot.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra210's PCI controller is largely identical to Tegra124, and hence
shares the same binding. However, it has a unique compatible value due
to the existence of at least one new HW bug that would prevent any driver
for a previous HW version from operating correctly.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Implement the procedure that the TRM mandates to initialize PLLREFE and
PLLE. This makes the PLL actually lock.
Note that this section of the TRM is being cleaned up to remove some
confusion. The set of register accesses in this patch should be final,
although the step numbers/descriptions might still change.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add 10m50 devboard support. It is based on the Golden Hardware
Reference Design (GHRD), available at,
http://rocketboards.org/foswiki/view/Documentation/
AlteraMAX1010M50RevCDevelopmentKitLinuxSetup
Though we supported only one nios2-generic board in the past. Now,
with the removal of the nios2-generic board dir, adding new nios2
boards to u-boot is easier than before. It should be helpful to
add those boards supported in Linux mainline. There are only two
such nios2 boards, the 3c120 devboard and 10m50 devboard. The
nios2-generic is actually 3c120, and should restore the name. The
10m50 is this one.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
The latest Linux can directly handle SMP operations for UniPhier SoCs
without any help of U-boot. Drop the relevant code from U-boot.
See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier:
rework SMP operations to use trampoline code") in Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This makes USB3.0 available on new SoCs/boards.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The IRQ is not used in U-Boot, but this would be useful to sync
device trees between Linux and U-Boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This sets up a fine-grained page table, which is a requirement for
noncached_init() to operate correctly.
MMU setup code currently exists in a number of places:
- A version in the core ARMv8 support code that sets up page tables that
use very large block sizes that CONFIG_SYS_NONCACHED_MEMORY doesn't
support.
- Enhanced versions for fsl-lsch3 and zynmq that set up finer grained
page tables.
Ideally, rather than duplicating the MMU setup code yet again this patch
would instead consolidate all the different routines into the core ARMv8
code so that it supported all use-cases. However, this will require
significant effort since there appear to be a number of discrepancies[1]
between different versions of the code, and between the defines/values by
some copies of the MMU setup code use and the architectural MMU
documentation. Some reverse engineering will be required to determine the
intent of the current code.
[1] For example, in the core ARMv8 MMU setup code, three defines named
TCR_EL[123]_IPS_BITS exist, but only one of them sets the IPS field and
the others set a different field (T1SZ) in the page tables. As far as I
can tell so far, there should be no need to set different values per
exception level nor to modify the T1SZ field at all, since TTBR1 shouldn't
be enabled anyway. Another example is inconsistent values for *_VA_BITS
between the current core ARMv8 MMU setup code and the various SoC-
specific MMU setup code. Another example is that asm/armv8/mmu.h's value
for SECTION_SHIFT doesn't match asm/system.h's MMU_SECTION_SHIFT;
research is needed to determine which code relies on which of those
values and why, and whether fixing the incorrect value will cause any
regression.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
In order for noncached_init() to operate correctly, SoCs must set up a
custom page table with fine-grained (2MiB) sections, which can be
configured from noncached_init().
This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c
by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There
are some other reasons for the duplication there though, such as enabling
icache early, and enabling dcaching earlier with a different configuration.
This change makes mmu_setup() a weak implementation, so that the MMU setup
code can be replaced without having to duplicate other code that calls it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The implementation of noncached_init() uses define MMU_SECTION_SIZE.
Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that
doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which
relies on something having set up translation tables with 2MB block size.
The core ARMv8 MMU setup code does not do this by default, but currently
relies on SoC specific MMU setup code. Be aware of this before enabling
this feature on your platform!
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Old sector number is not being cleared from FLASH_CR register. For example
when first erased sector was 001 and then you want to erase sector 010,
sector 011 gets erased instead.
This patch clears old sector number from FLASH_CR register before a new
one is written.
Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
flash_lock call is inside a for loop, so after the first iteration flash
is locked and no more sectors can be erased.
Move flash_lock out of the loop.
Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
In 522b021 we dropped 'PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4)' lines in
the mpc85xx linker scripts as this is not required and breaks newer
binutils. This commit cleans up the rest of the powerpc linker scripts.
Signed-off-by: Tom Rini <trini@konsulko.com>
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one. This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.
Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Revert commit 7a2c1b13 which dropped OpenRD boards.
Assume maintainership of OpenRD.
Remove OpenRD from scrapyard.
Switch OpenRD to generic board.
Switch to Thumb build.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Kirkwood files cpu.c and cache.c cannot build in Thumb state;
force them in ARM state even under CONFIG_SYS_THUMB_BUILD.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.
This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
This patch fixes compile warnings like this:
warning: format '%lu' expects argument of type 'long unsigned int',
but argument 5 has type 'size_t'
In C99 standard you can use %zu modifier to print size_t values.
Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile
error looking like this:
arch/arm/lib/semihosting.c: In function 'smh_read':
{standard input}: Assembler messages:
{standard input}:34: Error: invalid swi expression
{standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0
scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed
The source of the problem is "svc #0x123456" instruction. This instruction
can not be encoded using Thumb2 instruction set used by ARMv7M CPUs.
ARM documentation suggests using "bkpt #0xAB" instruction instead [1].
This patch fixes compile errors and adds support for semihosting for
STM32F429 or any other ARMv7M target.
This change was sested on STM32F429-DISCOVERY board using OpenOCD and
"smhload" u-boot command.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html
Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
In binutils-2.25, the _GLOBAL_OFFSET_TABLE_ symbols defined by PROVIDE in
u-boot.lds overrides the linker built-in symbols
(https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff;
h=b893397a4b1316610f49819344817715e4305de9),
so the linker is treating _GLOBAL_OFFSET_TABLE_ as a definition into the
.reloc section.
To align with the change of binutils-2.25, the _GLOBAL_OFFSET_TABLE_ symbol
should not be defined in sections, and the symbols in linker generated .got
section should be used(https://sourceware.org/ml/binutils/2008-09/
msg00122.html)
Fixed the following build errors with binutils-2.25:
| powerpc-poky-linux-gnuspe-ld.bfd: _GLOBAL_OFFSET_TABLE_ not defined in
linker created .got
Signed-off-by: Zhenhua Luo <zhenhua.luo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
A number of headers define functions as "extern inline" which is
causing problems with gcc5. The reason is that starting with
version 5.1, gcc defaults to the standard C99 semantics for the
inline keyword.
Under the traditional GNU inline semantics, an "extern inline"
function would never create an external definition, the same
as inline *without* extern in C99. In C99, and "extern inline"
definition is simply an external definition with an inline hint.
In short, the meanings of inline with and without extern are
swapped between GNU and C99.
The upshot is that all these definitions in header files create
an external definition wherever those headers are included,
resulting in multiple definition errors at link time.
Changing all these functions to "static inline" fixes the problem
since this works as desired in all gcc versions. Although the
semantics are slightly different (a static inline definition may
result in an actual function being emitted), it works as intended
in practice.
This patch also removes extern prototype declarations for the
changed functions where they existed.
Signed-off-by: Mans Rullgard <mans@mansr.com>
This patch fix compilation error:
drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for
‘zynq_sdhci_init’
int zynq_sdhci_init(phys_addr_t regbase)
^
In file included from drivers/mmc/zynq_sdhci.c:14:0:
./arch/arm/include/asm/arch/sys_proto.h:16:5: note: previous declaration
of ‘zynq_sdhci_init’ was here
int zynq_sdhci_init(unsigned long regbase);
^
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The move to 'generic board' as well as changes in the generic
bootm code broke the boot of FIT uImage's. Especially uImage's
with additional initramfs images or FDT's do not work anymore.
Refactor the bootm code to work again with the generic bootm code.
Always relocate ramdisk and FDT in step 'bootm prep' because the
generic bootm code does this only for legacy uImage's.
Move the step 'bootm cmdline' to 'bootm prep' because the Linux
kernel parameters rd_start and rd_size have to be initialized after
the relocation of the ramdisk.
Furthermore support the step 'bootm fake'.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As the generic board runs in cached mode, it should not use
"stwio" which bypass the cache.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Chin Liang See <clsee@altera.com>
Remove CONFIG_SYS_INIT_SP macro, as the initial stack is set to
below the u-boot code.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Chin Liang See <clsee@altera.com>
As virt_to_phys() is used a lot in DMA transfer, change it
to use physaddr_mask in global data. This will save an "if"
statement and get a little faster.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Remove the useless parenthesis in asm/io.h as suggested
by Marek.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Remove __ilog2_u64 and ffs4 from powerpc bitops to align with the
kernel implementation.
Use the generic __ffs64 instead of a custom powerpc implementation.
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Use the is_power_of_2() definition from log2.h to align with the
kernel implementation.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Use the generic bitops and also add custom __ffs() implementation
as per the kernel.
Also align the ffs() implementation with the kernel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
With a working QSPI calibration, the SCLK can now run up to 100MHz
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox <adrian at humboldt dot co dot uk>
Signed-off-by: Andy Fleming <afleming@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Remove zc70x target which was one setting for zc702 and zc706.
Currently zc702 and zc706 are separated.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Update this driver to use driver model and change all users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
SPI requires DM and OF that's why enable DM for ZynqMP
and start to use configuration based on embedded OF.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
We need to mark some device tree nodes so that they are available before
relocation. This enables driver model to find these automatically. In the
case of SPL it ensures that these nodes will be retained in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move to using device tree control in SPL so that we can use the same driver
code in both SPL and U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for the debug UART to assist with early debugging. Enable it
for Zybo as an example.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move to the new way of starting up SPL. Clearing of BSS and calling
board_init_r() is now handled by crt0.S.
Also tidy up the header include order.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia
Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC)
Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO
V3.0 specification. It is compliant with the SD Host Controller Standard
V3.0 specification.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Some peripherals may need a second clock source that may be different
from the system clock. This second clock is the generated clock (GCK)
and is managed by the PMC via PMC_PCR.
For simplicity, the clock source of the GCK is fixed to PLLA_CLK.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Provide the specific addresses for the Chip ID and Chip ID Extension
registers, instead of the offset, which make it use on other chips.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing
for PLL ratio.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
qe-tdm is muxed with diu, if hwconfig setted as qe-tdm,
assign muxed pins to qe-tdm, then delete diu node from
device tree.
Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch will fix these checkpatch issues.
ERROR: Macros with complex values should be enclosed in parentheses
+#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+ || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
ERROR: space prohibited before that ',' (ctx:WxW)
+ writel(val , &drex0->concontrol);
^
ERROR: space prohibited before that ',' (ctx:WxW)
+ writel(val , &drex1->concontrol);
^
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
There are 8 pins for SD card in Exynos, but the MUX was configured
only for 7, since the one was used for card detection.
This caused the pin's pull wrong configuration.
This commit fixes this and the card detect can work properly,
after call this function.
Tested-on: Odroid U3 and Odroid X2.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit adds implementation of Sandbox ADC device emulation.
The device provides:
- single and multi-channel conversion
- 4 channels with predefined conversion output data
- 16-bit resolution
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This ADC is required for Odroid's board revision detection.
The pre-reloc request is enabled, since board detection will
be done in one of early function call.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit adds common ADC node, which is disabled as default.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit adds driver for Exynos54xx ADC subsystem.
The driver is implemented using driver model, amd provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()
The basic parameters of ADC conversion, are:
- sample rate: 600KSPS
- output the data as average of 8 time conversion
ADC features:
- sample rate: 600KSPS
- resolution: 12-bit
- channels: 10 (analog multiplexer)
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The proper CPU ID for those Exynos variants is 0x5422,
but before the 0x5800 was set. This commit fix this back.
Changes:
- set cpu id to 0x5422 instead of 0x5800
- remove macro proid_is_exynos5800()
- add macro proid_is_exynos5422()
- change the calls to proid_is_exynos5800() with new macro
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This platform is based on Exynos5800 but the cpu id is 0x5422.
This doesn't fit the common Exynos SoC name convention, so now,
the CPU name is defined by device tree string, to be printed
properly.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The CPU name for Exynos was concatenated with cpu id,
but for new Exynos platforms, like Chromebook Peach Pi
based on Exynos5800, the name of SoC variant does not
include the real SoC cpu id (0x5422).
For such case, the CPU name should be defined in device tree.
This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
crt0.S do both memset the bss section and call board_init_r for us, so
remove them from board_init_f().
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add mx7 secure boot support, add helper macro IS_HAB_ENABLED_BIT
to get the corresponding bit mask per SoC (mx7 or mx6) to identify
if securue boot feature is enabled/disabled.
On authenticate_image only check for mmu enabled on mx6 SoC to
force pu_irom_mmu_enabled so ROM code can perform mmu cache flush
mx7 SoC ROM code does not have this issue as ROM enables cache support
based on fuse settings.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Add secure boot fuse helper struct to abstract the way
to find out secure boot settings per SoC iMX family
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework unified section macro select via Kconfig option
instead of macro definition in mx7_common header file.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target
platforms to resolve corresponding HAB_RVT_BASE base address,
the RVT table contains pointers to the HAB API functions in
ROM code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework secure boot support for imx6, move existing hab support
for imx6 into imx-common for SoC reuse.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Move common chip revision id's to main cpu header file
mx25 generic include cpu header for chip revision
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
We can reuse common functions in lib/time.c, but not reimplement
functions in imx-common/time.c.
Only keep timer_init ,get_tbclk and implement timer_read_counter in
imx-common/time.c.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043ARDB Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled
in SD boot for QSPI. This patch will add fdt support for
this rule.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Pointer 'reg' returned from call to function 'fdt_getprop' may be
NULL, will be passed to function and may be dereferenced there by
passing argument 1 to function 'of_read_number'. So check pointer
'reg' first.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enabled zynq qspi controller node for microzed board,
verified the same on spansion spi-nor flash.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
We have finished Generic Board conversion for ARM and PowerPC, i.e.
all the boards have been converted except OpenRISC, SuperH, SPARC,
which have not supported Generic Board framework yet.
Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro
defines in include/configs/*.h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We should not init the console this early since it precludes using driver
model for the UART, since it is not set up at the start of board_init_f().
See the README for more information. The debug UART does not have this
restriction. If we want to do early init with the console on it can be done
in spl_board_init().
Move the preloader_console_init() call from board_init_f() to board_init_r().
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
This C function should be used to do the early memory layout and init. This
is beyond my powers, so just add a TODO for the maintainer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.
Drop the unneeded code and adjust the hooks in board_f.c to cope.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.
Drop the unneeded code and adjust the hooks in board_f.c to cope.
Tested on LS2085ARDB and LS2085AQDS (armv8 SoC).
Tested-by: York Sun <yorksun@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
As the virtual address and physical address mapping of nios2 with
MMU are different. Add a check of MMU, and fix the mapping.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Ley Foon Tan <lftan@altera.com>
Convert cache flush to use dm cpu data.
The original cache flush functions are written in assembly
and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult
to convert to use cache configuration in dm cpu data which is
extracted from device tree.
The cacheflush.c of Linux nios2 arch uses cpuinfo structure,
which is very close to our dm cpu data. So we copy and modify
it to arch/nios2/lib/cache.c to replace the old cache.S.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Set default icache and dcache configuration for start.S.
We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE...
configuration macros. As we are just barely starting from
reset, there is no luxury of device tree.
We will set some maximum cache configuration so that it will
work for most configurations. This is used only in this
start.S. The speed penalty is only once here.
After start up, during board initialization, cpu information
will be extracted from device tree. Then cache flush operations
will have correct cache configurations.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Convert ioremap() to use io_region_base in dm cpu global data.
Also remove three unused io functions, which have style issue
and are replaced by macros already.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Remove asm/psr.h, which is not used.
Also clean up asm/sections.h and unaligned.h.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
Convert altera sysid to driver model with misc uclass.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert nios2 cpu to driver model. The cpu parameters are
extracted from device tree and saved to global data structure.
We will use them to replace the custom_fpga.h .
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert altera_pio to driver model.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These macros can be used to clear and set multiple bits
in a register using a single call.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>
Convert altera_jtag_uart to driver model.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add ioremap() to map physical address to uncached virtual
address. We need this to convert the reg address from the
device tree.
The order of headers inclusion in interrupts.c is changed
because common.h will include board header that contains
IO_REGION_BASE.
In the future, the IO_REGION_BASE should be decided from
the device tree.
tree
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
We will need CONFIG_SYS_MALLOC_F_LEN to use serial uclass.
So we shall undefine CONFIG_SYS_GENERIC_GLOBAL_DATA, and
call board_init_f_mem() to allocates early malloc() memory
with size of CONFIG_SYS_MALLOC_F_LEN in board_f.c.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
There is a weak version_string[] at common/cmd_version.c .
Remove the one in start.S.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
The dly_clks() in start.S is no use after switching to
generic timer. Remove it.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Move the timer code from interrupts.c into timer.c . Eliminate the
installation of timer interrupt handler, which is no longer used.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Zap almost all of the ad-hoc timer code from interrupts.c and
use the code in lib/time.c instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
This patch adds device tree control of U-Boot to nios2 boards.
The example dts is taken from Linux kernel.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Since commit 44c6e6591c
"rename _end to __bss_end__" , the _end was removed.
But we need it now for separated device tree control,
ie, CONFIG_OF_SEPARATE .
The _end is used by fdtdec_setup() to find the blob.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since we don't use gp for small data with option "-G0",
we use gp as global data pointer. The _gp location is
not needed.
The ALIGN(16) was for gp only. It is removed, so that we
can get correct address of dtb in u-boot-dtb.bin image.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
As we will use u-boot-dtb.bin, the code relocation range
should be adjusted to accommodate the additional dtb.
It might be overkilled to look into dtb header to find the
dtb size, so we will simply use CONFIG_SYS_MONITOR_LEN.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
As dtb in u-boot-dtb.bin overlapped the BSS section,
we should delay the clearing of BSS until dtb is relocated
in board_init_f().
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Enable this in the Kconfig so that nios2 boards can use device
tree to configure U-Boot.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Import various DT files for am57xx-beagle-x15 from
Linux Kernel v4.2
Add config file for this board, enable DM, DM_GPIO,
DM_SERIAL and DM_MMC.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Import various DT files for am437x-sk-evm from Linux Kernel v4.2
Add config file for this board, enable DM, DM_GPIO, DM_SERIAL
and DM_MMC.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Import various DT files for am4372, an43xx pinctrl and
am437x-gp-evm from Linux Kernel v4.2
Add config file for this board, enable DM, DM_GPIO, DM_SERIAL
and DM_MMC.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Existing driver gets the actual omap hammc base address + 0x100
bytes as the first 0x100 bytes is not used by the driver. But
with DM conversion the base address from DT is different, to
accommodate the offset adding res0[0x100] to struct hsmmc.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Import various DT files for dra7-evm from Linux Kernel v4.2
Add config file for this board, enable DM and DM_GPIO
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add MMC support for k2g
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
In K2G, Ethernet doesn't support SGMII instead it support RGMII,
adding support to the driver to connect to RGMII phy.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Phy mode is a board property and it can be different between
multiple board and ports, so it should not be hardcoded in
driver to one specific mode. So adding a field in eth_priv_t
structure to pass phy mode to driver.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
update K2G nav rx queue number
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add clock information for Galileo
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Keystone dts files assumes that LPAE is enabled and top level root
node uses 64bit addresses. This breaks the keystone boot with
CONFIG_OF_CONTROL enabled. So do not use 64 bit addresse in U-Boot DT.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Import various generic dts files from Linux kernel so that
all keystone2 platforms can be DT in U-boot.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
With CONFIG_DM_SERIAL is enabled NS16550_init() cannot be
called directly. Driver probe should be taking care of this.
So call this function only when DM_SERIAL is not enabled.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Introduce dummy devices for sandbox remoteproc device and enable it by
default
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since there is a common function to grab the serial number from the die id bits,
it makes sense have one to parse that serial number and feed it to the serial
ATAG.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap_die_id_display to display the full die id.
There is no need to store it in an environment variable, that no boot script
is using anyway.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we have a common prototype to grab the omap die id, functions to figure
out a serial number and usb ethernet address can use it directly.
Those also get an omap_die_id prefix for better consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap5 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap4 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This replaces the previous get_dieid definition with omap_die_id, that matches
the common omap_die_id definition.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces a common definition for omap_die_id, that aims at providing a
common interface for accessing omap platform's die id bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
Type 6. This patch adds support for it as a coreboot payload.
On board SATA and SPI are functional. On board Ethernet isn't functional
but since it's optional and ties up a PCIe x4 that is otherwise brought
out, this isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This works correctly now, so enable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Dropped malloc() and adjusted commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code takes about 450ms without the MRC cache and about 27ms with the
cache. Add a debug timer so that this time can be displayed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present a missing $ causes this code to hang when using the MRC cache/
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for the debug UART on link. This is useful for early debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If the debug UART is enabled, get it ready for use at the earliest possible
opportunity. This is not actually very early, but until we have a stack it
is difficult to make it work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten
by the ap_init() function address. Correct it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we have added MRC cache on quark support codes,
enable it on Intel Galileo board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Using existing mrccache library to implement mrc cache support
for Intel Quark.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
"type" and "wipe-value" are never used by the mrccache codes.
Remove them to avoid confusion. This also removes the alignment
comment in the panther dts file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
With MRC cache enabled, when typing 'reset' in the U-Boot shell,
BayTrail FSP initialization hangs at "Configuring Memory Start":
Setting BootMode to 0
Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
About to call MrcInit();
BayleyBay Platform Type
CurrentMrcData.BootMode = 4
Taking Fastboot path!
Configuring Memory Start...
Changing reset_cpu() to do a full system reset fixes this issue.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).
Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
fsp_init() call has a parameter nvs_buf which is used by FSP as the
MRC cache but currently is blindly set to NULL. Retreive the MRC
cache from SPI flash and pass it to fsp_init() call. After the call,
save FSP produced MRC cache to SPI flash too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently struct fmap_entry is used to describe a mrc region.
However this structure contains some other fields that are not
related to mrc cache and causes confusion. Besides, it does not
include a base address field to store SPI flash's base address.
Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to
calculate the SPI flash base address, which unfortunately is
not 100% correct as CONFIG_ROM_SIZE may not match the whole
SPI flash size.
Define a new struct mrc_region and use it instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Remove the call to custom mrc cache APIs, and use the ones
provided in the mrccache lib.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This adds mrccache_reserve(), mrccache_get_region() and
mrccache_save() APIs to the mrccache codes. They are ported
from the ivybridge implementation, but with some changes.
For example, in the mrccache_reserve(), ivybridge version
only reserves the pure MRC data, which causes additional
malloc() when saving the cache as the save API needs some
meta data. Now we change it to save the whole MRC date plus
the meta data to elinimate the need for the malloc() later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix some nits, improve some comments and reorder some codes
a little bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
For the cache record to write in mrccache_update(), we should
perform a sanity test to see if it is a valid one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
mrccache implementation can be common for all boards. Move it
from ivybridge cpu directory to the common lib directory.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
It would be helpful to have a command to show FSP header. So far
it only supports FSP header which conforms to FSP spec 1.0.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduce a new fsp command and make the existing hob command a
sub-command to fsp for future extension. Also move cmd_hob.c to
the dedicated fsp sub-directory in arch/x86/lib.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
When examining a HOB, it's useful to see which GUID this HOB
belongs to. Add GUID output in the hob command to aid this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Compact hob command output, especially by making hob type string a
little bit shorter so that we can leave room for future extension.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
System Management BIOS (SMBIOS) is a specification for how
motherboard and system vendors present management information
about their products in a standard format by extending the BIOS
interface on Intel architecture systems. As of today the latest
spec is 3.0 and can be downloaded from DMTF website. This commit
adds a simple and minimum required implementation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
install_e820_map() has nothing to do with zimage related codes.
Move it to a dedicated place.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
Add a Kconfig option to disable the Integrated Graphics Device (IGD)
so that it does not show in the PCI configuration space as a VGA
disaplay controller. This gives a chance for U-Boot to run PCI/PCIe
based graphics card's VGA BIOS and use that for the graphics console.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch enables DM_SERIAL for all ARCH_MVEBU boards (AXP & A38x).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds driver model support for some Marvell MVEBU SoC's. Including
Armada XP and 38x. All 3 currently mainlined boards are converted. DM is now
selected automatically for MVEBU platforms.
With this DM support now available for MVEBU, hardcoding the base addresses
and other information is not necessary any more. Probing should be done
by using the values provided via the device tree now instead. For this
the driver also need to be converted to DM. Patches for some of the drivers
will follow.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
These will be needed by the upcoming DM (driver model) support for
the Armada XP / 38x SoC's. This will provide DT based probing.
The dts files are copied 1:1 from the Linux kernel release v4.2.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the MVEBU SPL with the correct SPL design as well as reduces
the stack utilisation slightly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
When running on the AXP I sometimes noticed a strange behavior. As some
characters are not echoed on the U-Boot prompt. Not disabling the
lowlevel_init code, especially calling cpu_init_cp15() in the main
U-Boot seems to solve this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables the use of the kwboot tool, to boot mainline U-Boot
on the Marvell Armada XP/38x SoC's. This is done by returning to the
SoC's BootROM after SPL has initialized the SDRAM. We need to make sure
to not reconfigure the internal register space and MBARs. Otherwise
the BootROM will not be able to continue after SPL jumps back to it.
To use this feature, please don't forget to change the BOOT_FROM line
in your board specfic kwbimage.cfg file this way:
BOOT_FROM uart
Tested on these Marvell eval boards:
DB-MV784MP-GP - Armada XP
DB-88F6820-GP - Armada 38x
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.
The DT is identical to the DT submitted to the upstream kernel.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Linux had a number of changes to the AXP209 DTSI. Sync ours.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add the latest kernel changes to the sun5i family DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
So far, even if CONFIG_MMC was not enabled the board code was trying to use
the MMC-related functions, resulting in linker errors.
Protect those calls by an ifdef.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features
1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver,
stereo headphone jack and hdmi video output.
The dts changes are identical to the dts files submitted upstream.
A few notes on the use if dldo and aldo regulators. DLDO1 is used
for Vdd for the ethernet phy, ALDO2 is used for AVdd for the ethernet
phy. ALDO1 is used to power the sdio wifi module.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Stop prefixing the axp functions for setting voltages, etc. with the
model number, there ever is only one pmic driver built into u-boot,
this allows simplifying the callers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We now have generic q8_a?3_defconfig files for Q8 formfactor tablets with
an A13 / A23 / A33 SoC, there is no need for these PCB variant specific
defconfig-s and they only serve to confuse the user.
Note that in case of the forfun_q88db_defconfig and TZX-Q8-713B7_defconfig
for A13 based Q8 tablets there is not even a dts file for these in the
upstream kernel, which is all the more reason to remove them.
The generic q8_a?3_defconfig files have been tested on an Et_q8_v1_6,
Ippo_q8h_v1_2_a33_1024x600, Ippo_q8h_v1_2 and TZX-Q8-713B7 tablet, and the
forfun_q88db_defconfig is identical to q8_a13_tablet_defconfig.
This leaves only the Ippo_q8h_v5 untested with the new generic defconfigs
but there is no reason to assume that it will not work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a
Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes,
and .data from 0x54c to 0x144 bytes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Tom Rini <trini@konsulko.com>
Select CONFIG_SPL_STACK_R for sunxi boards, this gives us much more
room on the stack once we've the DRAM running.
Besides being a good change to have on itself, this also paves the
way for switching to using malloc_simple in the SPL which cuts of
close to 4KiB of the SPL size.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
